16 MEG x 4 FPM DRAM DRAM MT4LC16M4A7, MT4LC16M4T8 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT (Top View) • Single +3.3V ±0.3V power supply • Industry-standard x4 pinout, timing, functions, and packages • 13 row, 11 column addresses (A7) 12 row, 12 column addresses (T8) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • FAST-PAGE-MODE (FPM) access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention OPTIONS 32-Pin SOJ VCC DQ0 DQ1 NC NC NC NC WE# RAS# A0 A1 A2 A3 A4 A5 VCC MARKING • Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows T8 A7 • Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) DJ TG • Timing 50ns access 60ns access -5 -6 • Refresh Rates Standard Refresh Self Refresh (128ms period) VCC VSS DQ0 DQ3 DQ1 DQ2 NC NC NC NC NC NC NC WE# CAS# RAS# OE# A0 A12/NC** A1 A11 A2 A10 A3 A9 A4 A5 A8 VCC A7 A6 VSS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS DQ3 DQ2 NC NC NC CAS# OE# A12/NC** A11 A10 A9 A8 A7 A6 VSS 16 MEG x 4 FPM DRAM PART NUMBERS PART NUMBER MT4LC16M4A7DJ-x MT4LC16M4A7DJ-x S MT4LC16M4A7TG-x MT4LC16M4A7TG-x S MT4LC16M4T8DJ-x MT4LC16M4T8DJ-x S MT4LC16M4T8TG-x MT4LC16M4T8TG-x S None S* REFRESH ADDRESSING PACKAGE REFRESH 8K 8K 8K 8K 4K 4K 4K 4K SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP Standard Self Standard Self Standard Self Standard Self x = speed GENERAL DESCRIPTION *Contact factory for availability The 16 Meg x 4 DRAMs are high-speed CMOS, dynamic random-access memory devices contain-ing 67,108,864 bits organized in a x4 configuration. The MT4LC16M4A7 and MT4LC16M4T8 are functionally organized as 16,777,216 locations containing four bits each. The 16,777,216 memory locations are arranged in 8,192 rows by 2,048 columns for the MT4LC16M4A7 or 4,096 rows by 4,096 columns for the MT4LC16M4T8. During READ or WRITE cycles, each location is uniquely Part Number Example: MT4LC16M4A7DJ KEY TIMING PARAMETERS tRC tRAC tPC tAA tCAC 90ns 110ns 50ns 60ns 30ns 35ns 25ns 30ns 13ns 15ns 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 **A12 on A7 version and NC on T8 version NOTE: 1. The 16 Meg x 4 FPM DRAM base number differentiates the offerings in one place— MT4LC16M4A7. The fifth field distinguishes various options: A7 designates an 8K refresh and T8 designates a 4K refresh for FPM DRAMs. 2. The # symbol indicates signal is active LOW. SPEED -5 -6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-Pin TSOP 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FUNCTIONAL BLOCK DIAGRAM MT4LC16M4A7 (13 row addresses) WE# CAS# 4 DATA-IN BUFFER CONTROL LOGIC DATA-OUT BUFFER NO. 2 CLOCK GENERATOR DQ0 DQ1 DQ2 DQ3 4 4 OE# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 11 COLUMNADDRESS BUFFER(11) COLUMN DECODER 11 4 2,048 REFRESH CONTROLLER SENSE AMPLIFIERS I/O GATING 2,048 ROWADDRESS BUFFERS (13) 13 8,192 8,192 ROW SELECT 13 ROW DECODER 13 COMPLEMENT SELECT REFRESH COUNTER 8,192 x 2,048 x 4 MEMORY ARRAY NO. 1 CLOCK GENERATOR RAS# VDD VSS FUNCTIONAL BLOCK DIAGRAM MT4LC16M4T8 (12 row addresses) WE# CAS# 4 DATA-IN BUFFER CONTROL LOGIC DATA-OUT BUFFER NO. 2 CLOCK GENERATOR DQ0 DQ1 DQ2 DQ3 4 4 OE# RAS# 12 COLUMNADDRESS BUFFER(12) COLUMN DECODER 12 4,096 REFRESH CONTROLLER 4,096 12 12 4,096 NO. 1 CLOCK GENERATOR 4,096 ROW SELECT 12 COMPLEMENT SELECT REFRESH COUNTER ROWADDRESS BUFFERS (12) 4 SENSE AMPLIFIERS I/O GATING ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 4,096 x 4,096 x 4 MEMORY ARRAY VDD VSS 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM GENERAL DESCRIPTION (continued) addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address by CAS#. Both devices provide FAST-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row. The MT4LC16M4A7 and MT4LC16M4T8 must be refreshed periodically in order to retain stored data. whereas the MT4LC16M4T8 refreshes one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. The CBR refresh will invoke the internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method only one row is refreshed at a time; so for the MT4LC16M4A7, 8,192 RAS#-ONLY REFRESH cycles must be executed every 64ms to cover all rows. Some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows for an extended refresh period of 128ms, or 31.25µs per row for a 4K refresh and 15.625µs per row for an 8K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes RAS#-ONLY or burst CBR refresh sequence, all rows must be refreshed within the average internal refresh rate prior to the resumption of normal operation. FAST PAGE MODE ACCESS Each location in the DRAM is uniquely addressable as mentioned in the General Description. The data for each location is accessed via the four I/O pins (DQ0DQ3). The WE# signal must be activated to execute a WRITE operation; otherwise, a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary. FAST-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation. DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all 8,192 rows (A7) or all 4,096 rows (T8) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC16M4A7 internally refreshes two rows for every CBR cycle, 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 STANDBY Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Relative to VSS ................ -1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS ..................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0°C to +70°C Storage Temperature (plastic) ............ -55°C to +150°C Power Dissipation ................................................... 1W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VCC 3 3.6 V INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC VIH 2 VCC + 0.3 V 26 INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 26 II -2 2 µA OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4 – V OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 V IOZ -5 5 µA INPUT LEAKAGE CURRENT: Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); All other pins not under test = 0V OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V); DQ is disabled and in High-Z state 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION 4K 8K REFRESH REFRESH UNITS NOTES SYMBOL SPEED ICC1 ALL 1 1 mA ICC2 ALL 500 500 µA OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC3 -5 -6 170 160 130 120 mA 25 OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) ICC4 -5 -6 100 90 100 90 mA 25 REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) ICC5 -5 -6 170 160 130 120 mA 22 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) ICC6 -5 -6 170 160 130 120 mA 4, 7 ICC7 ALL 400 400 µA 4, 7 ICC8 ALL 400 400 µA 4, 7 STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# VCC - 0.2V, DQs may be left open, other inputs: VIN VCC - 0.2V or VIN ≤ 0.2V) REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM CAPACITANCE (Note: 2) PARAMETER SYMBOL MAX UNITS Input Capacitance: Address pins CI 1 5 pF Input Capacitance: RAS#, CAS#, WE#, OE# CI 2 7 pF Input/Output Capacitance: DQ CIO 7 pF UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES ns ns 17, 23 AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time (FAST PAGE MODE) Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH MIN tOFF 3 0 -6 MAX 25 40 0 0 48 MIN 45 0 0 55 13 8 13 15 15 3 8 10,000 15 10 15 15 15 3 10 30 5 50 5 36 13 8 0 3 13 13 13 tORD tPC tRAC 35 5 60 5 40 15 10 0 3 13 3 0 13 6 15 15 15 35 85 50 tRAD 10,000 15 30 76 tPRWC MAX 30 60 15 ns ns ns ns 18 4 13 4 18 19 19 23, 24 20 24 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period Refresh period (4,096 cycles) “S” version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 -5 SYMBOL tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 8 50 50 100 90 18 0 0 -6 MAX 10,000 125,000 MIN 10 60 60 100 110 20 0 0 64 128 30 0 90 0 13 131 73 13 2 8 40 0 8 10 10 7 50 MAX 10,000 125,000 64 128 40 0 105 0 15 155 85 15 2 10 45 0 10 10 10 50 UNITS ns ns ns µs ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 23 14 16 22 4 16 18 18 4, 23 4, 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM NOTES 18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD, and tCWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. The values shown were calculated for reference allowing 10ns for the external latching of read data and application of write data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 22. RAS#-ONLY REFRESH requires that all 8,192 rows of the MT4LC16M4A7 or all 4,096 rows of the MT4LC16M4T8 be refreshed at least once every 64ms. CBR REFRESH for either device requires that at least 4,096 cycles be completed every 64ms. 23. The DQs open during READ cycles once tOD or tOFF occur. If CAS# goes HIGH before OE#, the DQs will open regardless of the state of OE#. If CAS# stays LOW while OE# is brought HIGH, the DQs will open. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open. 25. Column address changed once each cycle. 26. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC = +3.3V; f = 1 MHz. 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# = VIH, data output is High-Z. 11. If CAS# = VIL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. 13. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. 14. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. 15. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM READ CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tRCD tCRP CAS# tRRH tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH COLUMN ROW tRCH tRCS WE# V IH V IL tAA tRAC tOFF tCAC tCLZ V DQ V IOH IOL OPEN OPEN VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR tCAS tCLZ 40 45 0 0 0 0 13 8 13 tCSH 3 5 50 tOD 3 tCRP tOE 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 MIN 25 tCAC tCAH -6 MAX 10,000 10 15 -5 MAX UNITS 30 ns ns tOFF tRAD 15 ns ns ns tRC 10,000 ns ns ns ns ns tRCH ns ns tRRH 3 5 60 13 13 3 15 15 SYMBOL MAX MIN MAX UNITS 3 13 50 3 15 60 ns ns 10,000 ns ns ns tRAC tRAH tRAS tRCD tRCS tRP tRSH 9 -6 MIN 13 8 50 10,000 15 10 60 90 18 110 20 ns ns 0 0 30 0 0 40 ns ns ns 0 13 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CAS# tRCD tCAS V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDS V DQ V IOH IOL tDH VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDS tRAD 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 MIN -6 MAX MIN -5 MAX UNITS SYMBOL 40 0 45 0 ns ns tRAH 0 8 13 0 10 15 ns ns ns tRC 10,000 10,000 tRAS tRCD tRP 5 50 5 60 ns ns tRSH 13 8 15 10 ns ns tWCH 0 13 0 15 ns ns tWCS tRWL tWCR tWP 10 MIN 8 50 -6 MAX MIN MAX UNITS 10,000 10 60 10,000 ns ns 90 18 30 110 20 40 ns ns ns 13 13 15 15 ns ns 8 40 10 45 ns ns 0 8 0 10 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS RAS# V IH V IL tCRP CAS# tCSH tRSH tCAS tRCD V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC tCAH ROW COLUMN tRCS WE# ROW tRWD tCWD tCWL tRWL tAWD tWP V IH V IL tAA tRAC tCAC tDS tCLZ V DQ V IOH IOL VALID D OUT OPEN tOE OE# tDH VALID D IN tOD OPEN tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD MIN 40 45 0 0 0 0 ns ns tOEH ns ns ns tRAD ns ns tRCD 48 8 tCAS 13 3 MAX 30 55 13 tCAH tCRP MIN -5 UNITS ns ns tCAC tCLZ -6 MAX 25 15 10 10,000 15 3 10,000 SYMBOL tOD tOE tRAH tRAS tRCS 5 60 ns ns tRP 40 15 10 ns ns ns tRWC tDH 36 13 8 tDS 0 0 ns tWP tCWD tCWL 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 tRSH tRWD tRWL 11 -6 MAX 13 13 13 tRAC 5 50 tCSH MIN 3 MIN 3 UNITS ns ns 60 ns ns 10,000 ns ns ns 15 50 13 8 50 MAX 15 15 10,000 15 10 60 18 0 20 0 ns ns 30 13 40 15 ns ns 131 73 13 155 85 15 ns ns ns 8 10 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE READ CYCLE tRASP tRP V IH V IL RAS# tCSH tCRP tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR tASC ROW tCAH tASC COLUMN tRCS tCAH COLUMN tCAH COLUMN tRCS tRCH tRCH ROW tRCS tRRH tRCH V IH V IL WE# tAA tRAC tAA tCPA tCAC tOFF tCLZ DQ tASC V IOH V IOL tOFF tCLZ tCAC tOFF tCLZ VALID DATA tOD OPEN tOE OE# tCAC tAA tCPA tOE VALID DATA tOD tOE VALID DATA tOD OPEN V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR 40 0 0 8 tCAS 13 3 8 tCPA 5 tCSH 50 3 tOD 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 UNITS 30 ns ns ns ns 15 10 10,000 15 3 10 30 tCRP -5 MAX 45 0 0 13 tCAH tCP MIN 25 tCAC tCLZ -6 MAX 10,000 35 5 13 60 3 15 SYMBOL tOE tOFF tPC tRAC ns ns tRAD ns ns ns tRASP ns ns tRCS ns ns tRRH tRAH tRCD tRCH tRP tRSH 12 MIN 3 30 -6 MAX 13 13 MIN 3 35 50 13 8 50 18 0 MAX 15 15 60 15 10 125,000 60 20 0 UNITS ns ns ns ns ns ns 125,000 ns ns ns 0 30 0 40 ns ns 0 13 0 15 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE EARLY WRITE CYCLE tRP tRASP RAS# V IH V IL tCSH tCRP CAS# tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH tASC COLUMN tCAH COLUMN tCWL tWCH tWCS tWCS tWCS tWP ROW tCWL tWCH tWP V IH V IL tWCR tDH tDS V DQ V IOH IOL OE# tCAH COLUMN tCWL tWCH tWP WE# tASC tDS VALID DATA tDH tDS VALID DATA tRWL tDH VALID DATA V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDS tPC 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 MIN 40 0 0 8 13 -6 MAX 10,000 MIN 45 0 0 10 15 -5 MAX 10,000 UNITS ns SYMBOL tRAD -6 MAX MIN 125,000 15 10 60 MAX UNITS 125,000 ns ns ns tRASP 13 8 50 tRCD 18 20 ns tRP 30 13 13 40 15 15 ns ns ns 8 40 10 45 ns ns 0 8 0 10 ns ns ns ns ns ns tRAH 8 5 10 5 ns ns tRSH 50 13 8 60 15 10 ns ns ns tWCH 0 30 0 35 ns ns tWP tRWL tWCR tWCS 13 MIN Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP tRP V IH V IL RAS# tCSH tCRP tRCD tPC tPRWC tCAS NOTE 1 tCP tCAS tRSH tCP tCAS tCP V IH V IL CAS# tAR tRAD tRAH tASR V IH V IL ADDR tASC ROW tCAH tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRWD tRCS tCWL tWP tAWD tCWD tWP tAWD tCWD V IH V IL WE# tAA tAA tRAC tDH tCAC tCLZ V IOH V IOL tAA tDH tCPA tDS DQ tRWL tCWL tCWL tWP tAWD tCWD tCAC tCLZ VALID D OUT OPEN tDS tCAC tCLZ VALID DIN VALID D OUT tOD VALID D IN VALID D OUT tOD tOE OE# tDH tCPA tDS VALID D IN OPEN tOD tOE tOE tOEH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR tAWD 40 0 0 48 8 tCAS 13 3 8 tCPA -5 MAX UNITS 30 ns 45 0 0 55 13 tCAH tCP MIN 25 tCAC tCLZ -6 MAX 15 10 10,000 15 3 10 10,000 SYMBOL tOD ns ns ns ns tOE ns ns tRAC tRAD 13 ns ns ns tRAH 8 50 18 tPC tPRWC tRASP tRCD 5 ns ns tRCS 5 tCSH 50 36 60 40 ns ns tRSH 13 8 0 15 10 0 ns ns ns tRWL tCWD tCWL tDH tDS 35 tRP tRWD tWP -6 MAX 13 MIN 3 13 tOEH tCRP 30 MIN 3 13 30 76 MAX 15 UNITS ns 15 ns ns ns ns 60 ns ns 15 35 85 50 15 125,000 10 60 20 125,000 ns ns ns 0 30 0 40 ns ns 13 73 15 85 ns ns 13 8 15 10 ns ns NOTE: 1. tPC is for LATE WRITE only. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP RAS# t RP V IH V IL t RSH t CSH t CRP CAS# t PC t RCD t CAS t CP t CAS t CP V IH V IL t AR t RAD t ASR ADDR V IH V IL ROW tASC t CAH t ASC t RAH COLUMN t CAH ROW COLUMN t CWL t RWL t WP t RCS t WCS WE# V IH V IL t CAC NOTE 1 t OFF t DS t CLZ DQ t WCH V OH V OL VALID DATA OPEN t DH VALID DATA t AA t RAC DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 40 0 0 tCAC 8 tCAS 13 3 8 tCP tCRP tCSH tCWL tDH tDS MIN -5 MAX 30 45 0 0 13 tCAH tCLZ -6 MAX 25 15 10 10,000 15 3 10 10,000 UNITS ns SYMBOL tOFF MIN 3 ns ns ns tPC tRAD 13 ns ns tRAH 8 50 ns ns ns tRCD 30 tRAC tRASP tRCS tRP 5 50 5 60 ns ns tRSH 13 8 0 15 10 0 ns ns ns tWCH tRWL tWCS tWP -6 MAX 13 MIN 3 MAX 15 UNITS ns 60 ns ns ns 35 50 15 125,000 10 60 125,000 ns ns 18 0 30 20 0 40 ns ns ns 13 13 15 15 ns ns 8 0 8 10 0 10 ns ns ns NOTE: 1. Do not drive input data prior to output data going High-Z. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS RAS# tRP V IH V IL tRPC tCRP CAS# V IH V IL tASR ADDR tRAH V IH V IL ROW ROW V DQ V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP RAS# tRAS tRP NOTE 1 tRAS V IH V IL tRPC tCP CAS# V IH V IL DQ V OH V OL tCSR tCHR OPEN tWRP WE# tRPC tCHR tCSR tWRH tWRP tWRH V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH MIN -6 MAX MIN -5 MAX UNITS SYMBOL tRAS tRC 0 15 0 15 ns ns 8 5 10 5 ns ns tRP 5 8 5 10 ns ns tWRH tRPC tWRP MIN 50 90 -6 MAX 10,000 MIN 60 110 MAX 10,000 UNITS ns ns 30 0 40 0 ns ns 10 10 10 10 ns ns NOTE: 1. End of CBR REFRESH cycle. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW) tRAS RAS# tRAS V IH V IL tCRP CAS# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tOFF tCAC tCLZ V DQ V IOH IOL OPEN VALID DATA OPEN tOD tOE OE# V IH V IL tORD DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN -6 MIN -5 40 45 UNITS ns ns 0 0 0 0 ns ns tORD tRAD tCAC MAX 25 MIN tOE tOFF 3 0 tRAC 3 5 ns ns tRCD tCRP 3 5 tRP 50 18 30 tOD 3 ns tRSH 13 13 3 15 MIN tRAH tRAS 13 3 0 50 10 15 tCLZ -6 MAX 13 8 15 tCHR 15 SYMBOL ns ns ns tCAH 13 MAX 30 13 8 MAX UNITS 15 ns 15 ns ns ns 60 15 10 10,000 60 20 40 ns ns 10,000 15 ns ns ns ns NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) RAS# V IH V IL (( )) tRPC tCSR tRPS NOTE 2 tRPC (( )) tCP CAS# NOTE 1 tRASS tRP (( )) tCP tCHD (( )) (( )) V IH V IL V DQ V OH OL (( )) tWRP OPEN tWRP tWRH tWRH (( )) (( )) V WE# V IH IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tCHD tCP tCSR tRASS tRP MIN 15 8 5 100 30 -6 MAX MIN 15 10 5 100 40 -5 MAX UNITS ns ns ns µs ns SYMBOL tRPC tRPS tWRH tWRP MIN 0 90 10 10 -6 MAX MIN 0 105 10 10 MAX UNITS ns ns ns ns NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed, if RAS#-only or burst CBR refresh is used. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM 32-PIN PLASTIC SOJ (400 mil) .829 (21.05) .823 (20.90) .750[19.05] (TYP) .050[1.27] (TYP) .445 (11.31) .435 (11.05) .405 (10.29) .399 (10.13) .145 (3.68) .132 (3.35) PIN #1 INDEX .095 (2.42) .080 (2.03) .037 [0.95] MAX DAMBAR PROTRUSION .032 (0.82) .026 (0.67) .024 [0.61] .030 [0.76] MIN SEATING PLANE .020 (0.51) .015 (0.38) R .040 (1.02) .030 (0.77) .380 (9.65) .360 (9.14) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM 32-PIN PLASTIC TSOP (400 mil) 20.96 ±0.08 SEE DETAIL A 1.27 TYP 0.95 11.76 ±0.10 10.16 ±0.08 PIN 1 ID 0.43 +0.07 -0.13 0.15 +0.03 -0.02 0.25 0.10 1.20 MAX GAGE PLANE 0.10 +0.10 -0.05 0.80 TYP 0.50 ±0.10 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc.