Integrated Circuit Systems, Inc. ICS85311 Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer GENERAL DESCRIPTION FEATURES The ICS85311 is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V ECL/ HiPerClockS™ LVPECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.T h e ICS85311 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and partto-part skew characteristics make the ICS85311 ideal for those clock distribution applications demanding well defined performance and repeatability. • 2 differential 2.5V/3.3V LVPECL / ECL outputs ,&6 • 1 CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency up to 1GHz • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 15ps (maximum) • Part-to-part skew: 100ps (maximum) • Propagation delay: 1.4ns (maximum) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT Q0 nQ0 Q0 nQ0 Q1 nQ1 Q1 nQ1 1 2 3 4 8 7 6 5 Vcc CLK nCLK VEE ICS85311 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View ICS85311AM www.icst.com/products/hiperclocks.html 1 REV. A JUNE 29, 2001 ICS85311 Integrated Circuit Systems, Inc. Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power Negative supply pin. Connect to ground. 6 nCLK Input 7 CLK Input 8 VCC Power Pullup Description Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Positive supply pin. Connect to 2.5v or 3.3V. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ICS85311AM Test Conditions Minimum Typical CLK, nCLK www.icst.com/products/hiperclocks.html 2 Maximum Units 4 pF REV. A JUNE 29, 2001 ICS85311 Integrated Circuit Systems, Inc. Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI 4.6V -0.5V to VCC + 0.5V Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VCC + 0.5V 112°C/W -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 25 mA TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units CLK VCC = VIN = 3.465V Test Conditions Minimum Typical 150 µA nCLK VCC = VIN = 3.465V 5 µA CLK VCC = 3.465V, VIN = 0V -5 µA nCLK VCC = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltag for CLK, nCLK is VCC + 0.3V. 1.3 V VCC - 0.85 V TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current ICS85311AM Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 25 mA www.icst.com/products/hiperclocks.html 3 REV. A JUNE 29, 2001 ICS85311 Integrated Circuit Systems, Inc. Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units CLK VCC = VIN = 2.625V Test Conditions Minimum Typical 150 µA nCLK VCC = VIN = 2.625V 5 µA CLK VCC = 2.625V, VIN = 0V -5 µA nCLK VCC = 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltag for CLK, nCLK is VCC + 0.3V. 1.3 V VCC - 0.85 V Maximum Units TABLE 3E. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.65 0.9 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4F. AC CHARACTERISTICS, VCC = 3.3V±5%, VCC = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum ƒ≤ 1GHz 0.9 Typical fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 100 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 52 % odc Output Duty Cycle 48 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS85311AM www.icst.com/products/hiperclocks.html 4 1 GHz 1.4 ns 15 ps REV. A JUNE 29, 2001 Integrated Circuit Systems, Inc. ICS85311 Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer PARAMETER MEASUREMENT INFORMATION VCC SCOPE Qx LVPECL VCC = 2.0V nQx VEE = -1.3V ± 0.135V FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT VCC SCOPE Qx LVPECL VCC = 2.0V nQx VEE = -0.5V ± 0.125V FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT ICS85311AM www.icst.com/products/hiperclocks.html 5 REV. A JUNE 29, 2001 ICS85311 Integrated Circuit Systems, Inc. Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer V CC CLK V Cross Points PP V CMR nCLK VEE FIGURE 2 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 3 - OUTPUT SKEW Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 4 - PART-TO-PART SKEW ICS85311AM www.icst.com/products/hiperclocks.html 6 REV. A JUNE 29, 2001 ICS85311 Integrated Circuit Systems, Inc. Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 5 - INPUT AND OUTPUT RISE AND F FALL TIME CLK nCLK Q0 - Q1 nQ0 - nQ1 t PD FIGURE 6 - PROPAGATION DELAY CLK, Qx nCLK, nQx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD ICS85311AM www.icst.com/products/hiperclocks.html 7 REV. A JUNE 29, 2001 Integrated Circuit Systems, Inc. ICS85311 Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC VCC CLK_IN R1 1K R1 1K + CLK_IN V_REF V_REF + - C1 0.1uF C1 0.1uF R2 1K R2 1K FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT ICS85311AM www.icst.com/products/hiperclocks.html 8 REV. A JUNE 29, 2001 Integrated Circuit Systems, Inc. ICS85311 Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85311. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation of the ICS85311 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core) = VCC * IEE = 3.465V * 25mA = 86.6mW Power (outputs) = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 x 30.2mW = 60.4mW Total Power (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. In order to determine if the junction temperature is below 125°C, the appropriate junction-to-ambient thermal resistance θJA must be used in conjunction with the total power dissipation. Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per the table below: Tj = θJA * Pd_total + TA where Pd_total is the total power dissipation of the device and TA is the ambient temperature. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.147W * 103.3°C/W = 85.2°C. This is well below the limit of 125°C. This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply voltage, air flow, and the type of board (single layer or multi-layer). Thermal Resistance q for 8-pin SOIC, Forced Convection JA q by Velocity (Linear Feet per Minute) JA 0 153.3°C/W 112.7°C/W Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 200 128.5°C/W 103.3°C/W 500 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS85311AM www.icst.com/products/hiperclocks.html 9 REV. A JUNE 29, 2001 ICS85311 Integrated Circuit Systems, Inc. Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 9. VCC Q1 VOUT RL 50 VCC - 2V Figure 9 - LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V Pd_L = [(V OH_MAX OL_MAX • (V - 2V))/R ]*(V - V CC L CC (V - 2V))/R ]*(V - V CC L For logic high , V OUT =V CC OH_MAX OH_MAX ) OL_MAX =V CC 1.0V Using V = 3.465, this results in V CC • OH_MAX For logic low , V OUT =V OL_MAX = 2.465V = V 1.7V CC Using V = 3.465, this results in V CC ) OL_MAX = 1.765V Pd_H = [(2.465V - (3.465V - 2V))/50 Ω]*(3.465V - 2.465V) = 20.0mW Pd_L = [(1.765V - (3.465V - 2V))/50 Ω]*(3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW ICS85311AM www.icst.com/products/hiperclocks.html 10 REV. A JUNE 29, 2001 Integrated Circuit Systems, Inc. ICS85311 Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE q by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 153.3°C/W 112.7°C/W 200 128.5°C/W 103.3°C/W 500 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85311 is: 225 ICS85311AM www.icst.com/products/hiperclocks.html 11 REV. A JUNE 29, 2001 ICS85311 Integrated Circuit Systems, Inc. Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer PACKAGE OUTLINE - M SUFFIX N C 8 5 1 4 L H E hx45˚ D A2 α A A1 e B SEATING PLANE .10 (.004) TABLE 6. PACKAGE DIMENSIONS SYMBOL Millimeters Inches MINIMUN MAXIMUM MINIMUN MAXIMUM A 1.35 1.75 0.532 0.0688 A1 0.10 0.25 0.0040 0.0098 A2 1.25 1.50 0.0492 0.0590 B 0.33 0.51 0.013 0.020 N 8 C 0.19 0.25 0.0075 0.0098 D 4.80 5.00 0.1890 0.1968 E 3.80 4.00 0.1497 0.1574 e H 1.27 BASIC 0.050 BASIC 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 α 0° 8° 0° 8° Reference Document: JEDEC Publication 95, MS-012 ICS85311AM www.icst.com/products/hiperclocks.html 12 REV. A JUNE 29, 2001 Integrated Circuit Systems, Inc. ICS85311 Low Skew, 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS85311AM ICS85311AM 8 lead SOIC 96 per tube 0°C to 70°C ICS85311AMT ICS85311AM 8 lead SOIC on Tape and Reel 2500 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS85311AM www.icst.com/products/hiperclocks.html 13 REV. A JUNE 29, 2001