Freescale MC33910G5AC/R2 Lin system basis chip with high side driver Datasheet

Freescale Semiconductor
Advance Information
Document Number: MC33910
Rev. 5.0, 12/2008
LIN System Basis Chip with High
Side Drivers
33910
The 33910 is a Serial Peripheral Interface (SPI) controlled System
Basis Chip (SBC), combining many frequently used functions in an
MCU based system, plus a Local Interconnect Network (LIN)
transceiver. The 33910 has a 5.0 V, 50 mA low dropout regulator with
full protection and reporting features. The device provides full SPI
readable diagnostics and a selectable timing watchdog for detecting
errant operation. The LIN Protocol Specification 2.0 and 2.1 compliant
LIN transceiver has waveshaping circuitry that can be disabled for
higher data rates.
Two 50 mA high side switches with optional pulse-width modulated
(PWM) are implemented to drive small loads. One high voltage input is
available for use in contact monitoring, or as external wake-up input.
This input can be used as high voltage Analog Input. The voltage on
this pin is divided by a selectable ratio and available via an analog
multiplexer.
The 33910 has three main operating modes: Normal (all functions
available), Sleep (VDD off, wake-up via LIN, wake-up inputs (L1), cyclic
sense and forced wake-up), and Stop (VDD on with limited current
capability, wake-up via CS, LIN bus, wake-up inputs, cyclic sense,
forced wake-up and external reset).
The 33910 is compatible with LIN Protocol Specification 2.0, 2.1, and
SAEJ2602-2.
SYSTEM BASIS CHIP WITH LIN
2ND GENERATION
AC SUFFIX (Pb-FREE)
98ASH70029A
32-PIN LQFP
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
•
Device
Full-duplex SPI interface at frequencies up to 4.0 MHz
LIN transceiver capable of up to 100 kbps with wave shaping
MC33910G5AC/R2
Two 50 mA high side switches
One high voltage analog/logic Input
MC34910G5AC/R2
Configurable window watchdog
5.0 V low drop regulator with fault detection and low voltage reset (LVR) circuitry
Switched/protected 5.0 V output (used for Hall sensors)
Pb-free packaging designated by suffix code AC
33910
VBAT
VSENSE
HS1
VS1
VS2
L1
VDD
MCU
MOSI
MISO
SCLK
CS
RXD
TXD
IRQ
RST
LGND
PGND
AGND
PWMIN
ADOUT0
LIN
LIN INTERFACE
HVDD
HS2
WDCONF
Figure 1. 33910 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
Temperature
Range (TA)
Package
- 40°C to 125°C
32-LQFP
-40°C to 85°C
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. This specification support the following products
Temperature
Generation
Specification
MC33910AC
Device
- 40 to 125°C
2.5
Rev. 5.0(1)
MC34910G5AC
- 40 to 85°C
2.5
Rev. 5.0(1)
Notes
1. Changes to Rev. 5 include:
- Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 Ω test conditions) performance to achieve +/-6 kV min on the LIN
pin
- Immunity against ISO7637 pulse 3b
- Reduce EMC emission level on LIN
- Improve EMC immunity against RF – target new specification including 3x68 pF
- Comply with J2602 conformance test
Table 2. This specification does not support the following products
Device
Temperature
Generation
Specification
MC33910BAC/R2
- 40 to 125°C
2.0
Rev 1.0 to 4.0(2)
MC34910BAC/R2
- 40 to 85°C
2.0
Rev 1.0 to 4.0(2)
Notes
2. For device specifications, refer to the documentation archive history. The current specification does not cover these products.
33910
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Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
RST IRQ
INTERRUPT CONTROL
MODULE
LVI, HVI,
ALL OT (VDD, HS, LIN, SD)
VS1
INTERNAL BUS
VS2
VDD
AGND
VOLTAGE REGULATOR
PGND
RESET CONTROL
MODULE
LVR, WD, EXT µC
5.0 V OUTPUT
MODULE
WINDOW
WATCHDOG
MODULE
HVDD
VS2
HIGH SIDE
CONTROL
MODULE
PWMIN
VS2
HS1
MISO
HS2
SCLK
SPI
&
CONTROL
ANALOG MULTIPLEXER
MOSI
CS
ADOUT0
WAKE-UP MODULE
VSENSE
CHIP TEMPERATURE
SENSE MODULE
L1
ANALOG INPUT
MODULE
DIGITAL INPUT MODULE
RXD
TXD
VBAT
SENSE MODULE
LIN PHYSICAL
LAYER
LIN
LGND
WDCONF
Figure 2. 33910 Simplified Internal Block Diagram
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
AGND
VDD
HVDD
VSENSE
NC*
VS1
VS2
HS1
32
31
30
29
28
27
26
25
PIN CONNECTIONS
RXD
1
24
HS2
TXD
2
23
L1
MISO
3
22
NC*
MOSI
4
21
NC*
SCLK
5
20
NC*
CS
6
19
NC*
ADOUT0
7
18
PGND
PWMIN
8
17
NC*
11
12
13
14
15
16
NC*
WDCONF
LIN
LGND
NC*
NC*
RST
10
9
IRQ
* Special Configuration Recommended /
Mandatory for Marked NC Pins
Figure 3. 33910 Pin Connections
Table 3. 33910 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.
Pin
Pin Name
Formal Name
Definition
1
RXD
Receiver Output
This pin is the receiver output of the LIN interface which reports the state of
the bus voltage to the MCU interface.
2
TXD
Transmitter Input
This pin is the transmitter input of the LIN interface which controls the state of
the bus output.
3
MISO
SPI Output
SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the
high-impedance state.
4
MOSI
SPI Input
SPI (Serial Peripheral Interface) data input.
5
SCLK
SPI Clock
SPI (Serial Peripheral Interface) clock Input.
6
CS
SPI Chip Select
7
ADOUT0
Analog Output Pin 0
8
PWMIN
PWM Input
9
RST
Internal Reset I/O
Bidirectional Reset I/O pin - driven low when any internal reset source is
asserted. RST is active low.
10
IRQ
Internal Interrupt
Output
Interrupt output pin, indicating wake-up events from Stop Mode or events from
Normal and Normal request modes. IRQ is active low.
SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
Analog Multiplexer Output.
High Side Pulse Width Modulation Input.
33910
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 3. 33910 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.
Pin
Pin Name
Formal Name
Definition
11, 15-17, 1922, 28
NC
12
WDCONF
Watchdog
Configuration Pin
13
LIN
LIN Bus
14
LGND
LIN Ground Pin
This pin is the device LIN ground connection. It is internally connected to the
PGND pin.
18
PGND
Power Ground Pin
This pin is the device low side ground connection. It is internally connected to
the LGND pin.
23
L1
Wake-up Input
24
HS2
25
HS1
26
VS2
27
VS1
29
No connect
This input pin is for configuration of the watchdog period and allows the
disabling of the watchdog.
This pin represents the single-wire bus transmitter and receiver.
This pin is the wake-up capable digital input(3). In addition, L1 input can be
sensed analog via the analog multiplexer.
High Side Outputs
High side switch outputs.
Power Supply Pin
These pins are device battery level power supply pins. VS2 is supplying the
HSx drivers while VS1 supplies the remaining blocks.(4)
VSENSE
Voltage Sense Pin
Battery voltage sense input.(5)
30
HVDD
Hall Sensor Supply
Output
+5.0 V switchable supply output pin.(6)
31
VDD
Voltage Regulator
Output
+5.0 V main voltage regulator output pin.(7)
32
AGND
Analog Ground Pin
This pin is the device analog ground connection.
Notes
3. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.
4. Reverse battery protection series diodes must be used externally to protect the internal circuitry.
5. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery
connections. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.
6. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.
7. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 4. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Normal Operation (DC)
VSUP(SS)
-0.3 to 27
Transient Conditions (load dump)
VSUP(PK)
-0.3 to 40
VDD
-0.3 to 5.5
VIN
-0.3 to VDD +0.3
VIN(IRQ)
-0.3 to 11
VHS
- 0.3 to VSUP +0.3
Normal Operation with a series 33k resistor (DC)
VL1DC
-18 to 40
Transient input voltage with external component (according to ISO7637-2)
(See Figure 5, page 19)
VL1TR
±100
VVSENSE
-27 to 40
Normal Operation (DC)
VBUSDC
-18 to 40
Transient input voltage with external component (according to ISO7637-2)
(See Figure 4, page 19)
VBUSTR
-150 to 100
IVDD
Internally Limited
Unit
ELECTRICAL RATINGS
Supply Voltage at VS1 and VS2
Supply Voltage at VDD
Input / Output Pins Voltage
V
(8)
CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD, HVDD
Interrupt Pin (IRQ)(9)
HS1 and HS2 Pin Voltage (DC)
V
L1 Pin Voltage
VSENSE Pin Voltage (DC)
V
V
LIN Pin Voltage
VDD Output Current
V
V
V
A
Notes
8. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.
9. Extended voltage range for programming purpose only.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 4. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
ESD Capability
Unit
V
AECQ100
Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω)
± 8.0k
LIN Pin
VESD1-1
L1
VESD1-2
± 6.0k
all other Pins
VESD1-3
±2000
Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)
VESD2-1
± 750
All other Pins (Pins 2-7, 10-15, 18-23, 26-31)
VESD2-2
± 500
LIN pin with 220 pF
VESD3-1
± 20k
LIN pin without capacitor
VESD3-2
± 11k
VS1/VS2 (100 nF to ground)
VESD3-3
>± 12k
L1 input (33 kΩ serial resistor)
VESD3-4
±6000
LIN pin with 220 pF and without capacitor
VESD4-1
± 8000
VS1/VS2 (100 nF to ground)
VESD4-2
± 8000
L1 input (33 kΩ serial resistor)
VESD4-3
± 8000
Charge Device Model - JESD22/C101 (CZAP = 4.0 pF)
According to LIN Conformance Test Specification / LIN EMC Test
Specification, August 2004 (CZAP = 150 pF, RZAP = 330 Ω)
Contact Discharge, Unpowered
According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω)
Unpowered
THERMAL RATINGS
Operating Ambient Temperature (10)
°C
TA
33910
-40 to 125
34910
-40 to 85
TJ
-40 to 150
°C
Storage Temperature
TSTG
-55 to 150
°C
Thermal Resistance, Junction to Ambient
RθJA
Operating Junction Temperature
°C/W
Natural Convection, Single Layer board (1s)(10), (11)
85
Natural Convection, Four Layer board (2s2p)(10), (12)
56
Thermal Resistance, Junction to Case(13)
Peak Package Reflow Temperature During Reflow(14), (15)
RθJC
23
°C/W
TPPRT
Note 15
°C
Notes
10.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
11.
12.
13.
14.
Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and
enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
15.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP
5.5
–
18
V
Functional Operating Voltage(16)
VSUPOP
–
–
27
V
Load Dump
VSUPLD
–
–
40
V
IRUN
–
4.5
10
mA
SUPPLY VOLTAGE RANGE (VS1, VS2)
Nominal Operating Voltage
SUPPLY CURRENT RANGE (VSUP = 13.5 V)
Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(17)
Stop Mode, VDD ON with IOUT = 100 µA, LIN Recessive State
(19) (20)
,
(17), (18),
ISTOP
µA
5.5 V < VSUP < 12 V
–
47
VSUP = 13.5 V
–
62
90
13.5 V < VSUP < 18 V
–
180
400
5.5 V < VSUP < 12 V
–
27
35
VSUP = 13.5 V
–
33
48
13.5 V ≤ VSUP < 18 V
–
160
300
ICYCLIC
–
10
–
Threshold (measured on VS1)(21)
VBATFAIL
1.5
3.0
3.9
Hysteresis (measured on VS1)(21)
VBATFAIL_HYS
–
0.9
–
Threshold (measured on VS1)
VSUV
5.55
6.0
6.6
Hysteresis (measured on VS1)
VSUV_HYS
–
0.2
–
Threshold (measured on VS1)
VSOV
19.25
20.5
Hysteresis (measured on VS1)
VSOV_HYS
18
–
1.0
–
Sleep Mode, VDD OFF, LIN Recessive State(17), (19)
Cyclic Sense Supply Current Adder(21)
80
ISLEEP
µA
µA
SUPPLY UNDER/OVER-VOLTAGE DETECTIONS
Power-On Reset (BATFAIL)(22)
V
VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
V
VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
V
Notes
16. Device is fully functional. All features are operating.
17. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.
18.
Total IDD current (including loads) below 100 µA.
19.
Stop and Sleep Modes current will increase if VSUP exceeds13.5 V.
20.
21.
22.
This parameter is guaranteed after 90 ms.
This parameter is guaranteed by process monitoring but not production tested.
The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.
33910
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
(23)
VOLTAGE REGULATOR
Symbol
Min
Typ
Max
4.75
5.00
5.25
60
110
200
–
0.1
0.25
Unit
(VDD)
Normal Mode Output Voltage
VDDRUN
1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V
Normal Mode Output Current Limitation
IVDDRUN
Dropout Voltage(24)
VDDDROP
IVDD = 50 mA
Stop Mode Output Voltage
V
V
VDDSTOP
IVDD < 5.0 mA
mA
V
4.75
5.0
5.25
IVDDSTOP
6.0
13
36
Normal Mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA
LRRUN
–
–
25
Stop Mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA
LRSTOP
–
–
25
Normal Mode, 1.0 mA < IVDD < 50 mA
LDRUN
–
–
80
Stop Mode, 0.1 mA < IVDD < 5.0 mA
LDSTOP
–
–
50
90
115
140
TPRE_HYS
–
13
–
°C
TSD
150
170
190
°C
TSD_HYS
–
13
–
°C
-2.0
–
2.0
20
35
50
Stop Mode Output Current Limitation
Line Regulation
mV
Load Regulation
Over-temperature Prewarning
mA
mV
(Junction)(25)
TPRE
Interrupt generated, VDDOT Bit Set
Over-temperature Prewarning Hysteresis(25)
Over-temperature Shutdown Temperature
(Junction)(25)
(25)
Over-temperature Shutdown Hysteresis
°C
HALL SENSOR SUPPLY OUTPUT(26) (HVDD)
VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100%
HVDDACC
IHVDD = 15 mA
Current Limitation
Dropout Voltage
IHVDD
HVDDDROP
IHVDD = 15 mA; IVDD = 5.0 mA
Line Regulation
–
160
300
–
–
40
mV
LDHVDD
1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA
mA
mV
LRHVDD
IHVDD = 5.0 mA; IVDD = 5.0 mA
Load Regulation
%
mV
–
–
20
Notes
23. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.
24. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).
25. This parameter is guaranteed by process monitoring but not production tested.
26. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VRSTTH
4.3
4.5
4.7
V
0.0
–
0.9
-150
-250
-350
1.5
–
8.0
RST INPUT/OUTPUT PIN (RST)
VDD Low Voltage Reset Threshold
Low-state Output Voltage
VOL
IOUT = 1.5 mA; 3.5 V ≤ VSUP ≤ 27 V
High-state Output Current (0 V < VOUT < 3.5 V)
IOH
Pull-down Current Limitation (internally limited)
IPD_MAX
VOUT = VDD
V
µA
mA
Low-state Input Voltage
VIL
-0.3
–
0.3 x VDD
V
High-state Input Voltage
VIH
0.7 x VDD
–
VDD +0.3
V
MISO SPI OUTPUT PIN (MISO)
Low-state Output Voltage
VOL
IOUT = 1.5 mA
High-state Output Voltage
0.0
–
1.0
VDD -0.9
–
VDD
-10
–
10
VOH
IOUT = -250 µA
Tri-state Leakage Current
V
V
ITRIMISO
0 V ≤ VMISO ≤ VDD
µA
SPI INPUT PINS (MOSI, SCLK, CS)
Low-state Input Voltage
VIL
-0.3
–
0.3 x VDD
V
High-state Input Voltage
VIH
0.7 x VDD
–
VDD +0.3
V
MOSI, SCLK Input Current
IIN
-10
–
10
10
20
30
0 V ≤ VIN ≤ VDD
CS Pull-up Current
µA
IPUCS
0 V < VIN < 3.5 V
µA
INTERRUPT OUTPUT PIN (IRQ)
Low-state Output Voltage
VOL
IOUT = 1.5 mA
High-state Output Voltage
0.0
–
0.8
VDD -0.8
–
VDD
–
–
2.0
VOH
IOUT = -250 µA
Leakage Current
V
V
IOUT
VDD ≤ VOUT ≤ 10 V
mA
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
Low-state Input Voltage
VIL
-0.3
–
0.3 x VDD
V
High-state Input Voltage
VIH
0.7 x VDD
–
VDD +0.3
V
Pull-up current
0 V < VIN < 3.5 V
IPUPWMIN
µA
10
20
30
33910
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
TJ = 25°C, ILOAD = 50 mA; VSUP > 9.0 V
–
–
7.0
TJ = 150°C, ILOAD = 50 mA; VSUP > 9.0 V(27)
–
–
10
TJ = 150°C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(27)
–
–
14
60
90
250
–
5.0
7.5
–
–
10
Unit
HIGH SIDE OUTPUTS HS1 AND HS2 PINS (HS1, HS2)
Output Drain-to-Source On Resistance
Output Current Limitation(28)
ILIMHSX
0 V < VOUT < VSUP - 2.0 V
Open Load Current Detection(29)
Leakage Current
IOLHSX
mA
ILEAK
-0.2 V < VHSX < VS2 + 0.2 V
Short-circuit Detection Threshold(30)
Shutdown(31), (32)
Over-temperature Shutdown
Hysteresis(32)
mA
µA
VTHSC
5.5 V < VSUP < 27 V
Over-temperature
Ω
RDS(ON)
V
VSUP -2.0
–
–
THSSD
140
160
180
°C
THSSD_HYS
–
10
–
°C
2.0
2.5
3.0
3.0
3.5
4.0
L1 INPUT PIN (L1)
Low Detection Threshold(33)
VTHL
5.5 V < VSUP < 27 V
High Detection Threshold(33)
VTHH
5.5 V < VSUP < 27 V
Hysteresis(33)
V
V
VHYS
5.5 V < VSUP < 27 V
V
0.4
0.8
1.4
-10
–
10
800
1300
2000
L1DS (L1 Divider Select) = 0
0.95
1.0
1.05
L1DS (L1 Divider Select) = 1
3.42
3.6
3.78
-80
6.0
80
-22
2.0
22
L1DS (L1 Divider Select) = 0
96
100
104
L1DS (L1 Divider Select) = 1
96
100
104
Input
Current(34)
IIN
-0.2 V < VIN < VS1
Analog Input Impedance(35)
Analog Input Divider Ratio (RATIOL1 = VL1 / VADOUT0)
Analog Output offset Ratio
L1DS (L1 Divider Select) = 0
RL1IN
kΩ
RATIOL1
VRATIOL1OFFSET
L1DS (L1 Divider Select) = 1
Analog Inputs Matching
µA
mV
L1MATCHING
%
Notes
27. This parameter is production tested up to TA = 125°C, and guaranteed by process monitoring up to TJ = 150°C.
28.
29.
30.
31.
32.
33.
34.
35.
When over-current occurs, the corresponding high side stays ON with limited current capability and the HSxCL flag is set in the HSSR.
When open load occurs, the flag (HSxOP) is set in the HSSR.
HS automatically shutdown if HSOT occurs or if the HVSE flag is enabled and an over-voltage occurs.
When over-temperature shutdown occurs, both high sides are turned off. All flags in HSSR are set.
Guaranteed by characterization but not production tested
If L1 pin is unused it must be connected to ground.
Analog multiplexer input disconnected from L1 input pin.
Analog multiplexer input connected to L1 input pin.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
REXT
20
–
200
kΩ
WDACC
-15
–
15
%
TA = -40°C
2.0
-
2.8
TA = 25°C
2.8
3.0
3.6
TA = 125°C
3.6
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
(36)
External Resistor Range
Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)(37)
ANALOG MULTIPLEXER
Temperature Sense Analog Output Voltage
Temperature Sense Analog Output Voltage per characterization
VADOUT0_TEMP
(38)
V
4.6
VADOUT0_25
3.1
3.15
3.2
V
STTOV
9.0
10.5
12
mV/K
STTOV_3T
9.9
10.2
10.5
mV/K
5.0
5.25
5.5
5.15
5.25
5.35
TA = 25°C
Internal Chip Temperature Sense Gain
Internal Chip Temperature Sense Gain per characterization at 3
temperatures(38) See Figure 16, Temperature Sense Gain
VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0)
RATIOVSENSE
5.5 V < VSUP < 27 V
VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per
characterization(38)
RATIOVSENSECZ
5.5 <Vsup< 27 V
VSENSE Output Related Offset
VSENSE Output Related Offset per characterization(38)
OFFSETVSENSE
mV
-30
-10
30
-30
-12.6
0
VDD -0.35
–
VDD
0.0
–
0.35
0.0
–
0.8
VDD -0.8
–
VDD
OFFSETVSENSE
_CZ
mV
ANALOG OUTPUT (ADOUT0)
Maximum Output Voltage
VOUT_MAX
-5.0 mA < IO < 5.0 mA
Minimum Output Voltage
V
VOUT_MIN
-5.0 mA < IO < 5.0 mA
V
RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)
Low-state Output Voltage
VOL
IOUT = 1.5 mA
High-state Output Voltage
IOUT = -250 µA
V
VOH
V
Notes
36. For VSUP 4.7 to 18 V
37.
Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)
38.
These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed
by production test.
33910
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Low-state Input Voltage
VIL
-0.3
–
0.3 x VDD
V
High-state Input Voltage
VIH
0.7 x VDD
–
VDD +0.3
V
IPUIN
10
20
30
µA
TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)
Pin Pull-up Current, 0 V < VIN < 3.5 V
LIN PHYSICAL LAYER WITH J2602 FEATURE ENABLED (BIT DIS_J2602 = 0)
LIN Under Voltage threshold
VTH_UNDER_
Positive and Negative threshold (VTHP, VTHN)
Hysteresis (VTHP - VTHN)
LIN PHYSICAL LAYER, TRANSCEIVER
VOLTAGE
V
5.0
VJ2602_DEG
6.0
400
mV
(LIN)(39)
Operating Voltage Range
VBAT
8.0
18
V
Supply Voltage Range
VSUP
7.0
18
V
VSUP_NON_OP
-0.3
40
V
Voltage Range within which the device is not destroyed
Current Limitation for Driver Dominant State
IBUS_LIM
Driver ON, VBUS = 18 V
Input Leakage Current at the receiver
Receiver Dominant State
Receiver Recessive State
Receiver Threshold Center
–
–
–
–
20
-1.0
–
1.0
mA
µA
–
–
100
–
–
0.4
0.6
–
–
0.475
0.5
0.525
–
–
0.175
VBUSDOM
VSUP
VBUSREC
VSUP
VBUS_CNT
VSUP
VHYS
(VTH_REC - VTH_DOM)
mA
µA
IBUSNO_BAT
(VTH_DOM + VTH_REC)/2
Receiver Threshold Hysteresis
-1.0
IBUS_NO_GND
GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V
VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V(41)
200
IBUS_PAS_REC
Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT
Control unit disconnected from ground(40)
90
IBUS_PAS_DOM
Driver off; VBUS = 0 V; VBAT = 12 V
Leakage Output Current to GND
mA
40
VSUP
Voltage Drop at the serial Diode in pull-up path
VSERDIODE
0.4
1.0
V
VBAT_SHIFT
VSHIFT_BAT
0
10%
VBAT
GND_SHIFT
VSHIFT_GND
0
10%
VBAT
Notes
39. Parameters guaranteed for 7.0 V ≤ VSUP ≤ 18 V.
40.
41.
Loss of local ground must not affect communication in the residual network.
Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
LIN PHYSICAL LAYER, TRANSCEIVER (LIN) (CONTINUED)
Symbol
Min
Typ
Max
Unit
5.3
5.8
V
(39)
LIN Wake-up threshold from Stop or Sleep Mode(42)
VBUSWU
LIN Pull-up Resistor to VSUP
RSLAVE
20
30
60
kΩ
TLINSD
140
160
180
°C
TLINSD_HYS
–
10
–
°C
Over-temperature Shutdown
(43)
Over-temperature Shutdown Hysteresis
Notes
42. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale
does not guarantee this parameter during the product's life time.
43. When over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.
33910
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI Operating Frequency
f SPIOP
–
–
4.0
MHz
SCLK Clock Period
SPI INTERFACE TIMING (SEE Figure 13, PAGE 22)
tPSCLK
250
–
N/A
ns
SCLK Clock High Time(44)
tWSCLKH
110
–
N/A
ns
SCLK Clock Low Time(44)
tWSCLKL
110
–
N/A
ns
Falling Edge of CS to Rising Edge of SCLK(44)
tLEAD
100
–
N/A
ns
Falling Edge of SCLK to CS Rising Edge(44)
tLAG
100
–
N/A
ns
MOSI to Falling Edge of SCLK(44)
tSISU
40
–
N/A
ns
Falling Edge of SCLK to MOSI(44)
tSIH
40
–
N/A
ns
MISO Rise Time(44)
tRSO
–
40
–
CL = 220 pF
MISO Fall Time(44)
tFSO
CL = 220 pF
Time from Falling or Rising Edges of
ns
ns
–
40
–
CS to:(44)
ns
- MISO Low-impedance
tSOEN
0.0
–
50
- MISO High-impedance
tSODIS
0.0
–
50
Time from Rising Edge of SCLK to MISO Data Valid(44)
tVALID
0.0
–
75
t RST
0.65
1.0
1.35
ms
t RSTDF
350
480
900
ns
8.5
10
11.5
0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100 pF
ns
RST OUTPUT PIN
Reset Low-level Duration After VDD High (see Figure 12, page 22)
Reset Deglitch Filter Time
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period(45)
External Resistor REXT = 20 kΩ (1%)
t PWD
ms
External Resistor REXT = 200 kΩ (1%)
79
94
108
Without External Resistor REXT (WDCONF Pin Open)
110
150
205
Notes
44. This parameter is guaranteed by process monitoring but not production tested.
45. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
t WUF
8.0
20
38
μs
–
–
5.0
t NR TOUT
110
150
205
ms
TON
130
200
270
µs
+35
%
L1 INPUT
L1 Filter Time Deglitcher(46)
STATE MACHINE TIMING
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation(46)
Normal Request Mode Timeout (see Figure 12, page 22)
Cyclic Sense ON Time from Stop and Sleep Mode(47)
Cyclic Sense Accuracy(46)
Delay Between SPI Command and HS Turn On(48)
-35
–
–
10
μs
t S-OFF
9.0 V < VSUP < 27 V
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode)(46)
μs
t S-ON
9.0 V < VSUP < 27 V
Delay Between SPI Command and HS Turn Off(48)
μs
t STOP
–
–
10
–
–
10
μs
t SNR2N
μs
Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST HIGH
t WUCS
9.0
15
80
First Accepted SPI Command
t WUSPI
90
—
N/A
t 2CS
4.0
—
—
35
50
70
Minimum Time Between Rising and Falling Edge on the CS
μs
J2602 DEGLITCHER
VSUP Deglitcher(49)
(DIS_J2602 = 0)
μs
tJ2602_DEG
Notes
46. This parameter is guaranteed by process monitoring but not production tested.
47. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale
does not guarantee this parameter during the product's life time.
48. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.
49. This parameter has not been monitoring during operating life test.
33910
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC ACCORDING TO LIN PHYSICAL
LAYER SPECIFICATION(50), (51)
Duty Cycle 1:
D1
THREC(MAX) = 0.744 * VSUP
THDOM(MAX) = 0.581 * VSUP
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V
Duty Cycle 2:
0.396
—
—
—
—
0.581
D2
THREC(MIN) = 0.422 * VSUP
THDOM(MIN) = 0.284 * VSUP
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER
SPECIFICATION(50), (52)
Duty Cycle 3:
D3
THREC(MAX) = 0.778 * VSUP
THDOM(MAX) = 0.616 * VSUP
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V
Duty Cycle 4:
0.417
—
—
—
—
0.590
D4
THREC(MIN) = 0.389 * VSUP
THDOM(MIN) = 0.251 * VSUP
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V
Notes
50. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal
threshold defined at each parameter. See Figure 6, page 20.
51. See Figure 7, page 20.
52. See Figure 8, page 20.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SRFAST
—
20
—
V / μs
t REC_PD
—
4.2
6.0
t REC_SYM
- 2.0
—
2.0
t PROPWL
42
70
95
t WAKE_SLEEP
—
—
1500
t WAKE_STOP
9.0
27
35
t TXDDOM
0.65
1.0
1.35
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS
(53)
Propagation Delay and Symmetry(54)
μs
Propagation Delay of Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF)
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
Bus Wake-Up Deglitcher (Sleep and Stop
Modes)(55)(59) (56)
μs
Bus Wake-Up Event Reported
From Sleep Mode
(57)
From Stop Mode(58)
TXD Permanent Dominant State Delay
μs
s
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
PWMIN pin(59)
Max. frequency to drive HS output pins
fPWMIN
kHz
10
Notes
53. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 6, page 20.
54. See Figure 9, page 21
55. See Figure 10, page 21 for Sleep and Figure 11, page 21 for Stop Mode.
56. This parameter is tested on automatic tester but has not been monitoring during operating life test.
57. The measurement is done with 1.0 µF capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V.
See Figure 10, page 21. The delay depends of the load and capacitor on VDD.
58.
59.
In Stop Mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11,
page 21.
This parameter is guaranteed by process monitoring but not production tested.
33910
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
33910
1.0 nF
LIN
TRANSIENT PULSE
GENERATOR
(NOTE)
GND
PGND LGND
AGND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 4. Test Circuit for Transient Test Pulses (LIN)
33910
Transient Pulse
Generator
(Note)
1.0 nF
L1
10 kΩ
GND
PGND LGND AGND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.
Figure 5. Test Circuit for Transient Test Pulses (L1)
VSUP
R0
TXD
LIN
RXD
C0
R0 AND C0 COMBINATIONS:
• 1.0 KΩ and 1.0 nF
• 660 Ω and 6.8 nF
• 500 Ω and 10 nF
Figure 6. Test Circuit for LIN Timing Measurements
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
tBIT
tBIT
tBUS_DOM(MAX)
VLIN_REC
THREC(MAX)
74.4% VSUP
THDOM(MAX)
58.1% VSUP
tBUS_REC(MIN)
Thresholds of
receiving node 1
LIN
THREC(MIN)
THDOM(MIN)
Thresholds of
receiving node 2
42.2% VSUP
28.4% VSUP
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD
Output of receiving Node 1
tREC_PDF(1)
tREC_PDR(1)
RXD
Output of receiving Node 2
tREC_PDF(2)
tREC_PDR(2)
Figure 7. LIN Timing Measurements for Normal Slew Rate
TXD
tBIT
tBIT
tBUS_DOM(MAX)
VLIN_REC
THREC(MAX)
77.8% VSUP
THDOM(MAX)
61.6% VSUP
tBUS_REC(MIN)
Thresholds of
receiving node 1
LIN
THREC(MIN)
THDOM(MIN)
Thresholds of
receiving node 2
38.9% VSUP
25.1% VSUP
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD
Output of receiving Node 1
tREC_PDF(1)
tREC_PDR(1)
RXD
Output of receiving Node 2
tREC_PDR(2)
tREC_PDF(2)
Figure 8. LIN Timing Measurements for Slow Slew Rate
33910
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VLIN_REC
VBUSREC
0.6% VSUP
VBUSDOM
0.4% VSUP
VSUP
LIN BUS SIGNAL
RXD
tREC_PDF
tREC_PDR
Figure 9. LIN Receiver Timing
VLIN_REC
LIN
5.0 V
VBUSWU
DOMINANT LEVEL
3.0 V
VDD
tPROPWL
tWAKE_SLEEP
Figure 10. LIN Wake-Up Sleep Mode Timing
VLIN_REC
LIN
5.0 V
VBUSWU
DOMINANT LEVEL
IRQ
tPROPWL
tWAKE_STOP
Figure 11. LIN Wake-up Stop Mode Timing
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VSUP
VDD
RST
tNRTOUT
tRST
Figure 12. Power On Reset and Normal Request Timeout Timing
tPSCLK
CS
tWSCLKH
tLEAD
tLAG
SCLK
tWSCLKL
tSISU
MOSI
UNDEFINED
D0
tSIH
DON’T CARE
D7
DON’T CARE
tVALID
tSODIS
tSOEN
MISO
D0
DON’T CARE
D7
Figure 13. SPI Timing Characteristics
33910
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33910 was designed and developed as a highly
integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
33910 is well suited to perform keypad applications via the
LIN bus.
Power switches are provided on the device configured as
high side outputs. Other ports are also provided, which
include a Hall Sensor port supply, and one wake-up capable
pin. An internal voltage regulator provides power to a MCU
device.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables this device
to be compatible with 3-wire bus systems, where one wire is
used for communication, one for battery, and one for ground.
FUNCTIONAL PIN DESCRIPTION
See Figure 1, 33910 Simplified Application Diagram,
page 1, for a graphic representation of the various pins
referred to in the following paragraphs. Also, see the pin
diagram on page 4 for a description of the pin locations in the
package.
MASTER OUT SLAVE IN PIN (MOSI)
RECEIVER OUTPUT PIN (RXD)
The MISO pin sends data to an SPI-enabled MCU. It is a
digital tri-state output used to shift serial data to the
microcontroller. Data on this output pin changes on the
positive edge of the SCLK. When CS is High, this pin will
remain in the high-impedance state.
The RXD pin is a digital output. It is the receiver output of
the LIN interface and reports the state of the bus voltage:
RXD Low when LIN bus is dominant, RXD High when LIN bus
is recessive.
TRANSMITTER INPUT PIN (TXD)
The TXD pin is a digital input. It is the transmitter input of
the LIN interface and controls the state of the bus output
(dominant when TXD is Low, recessive when TXD is High).
This pin has an internal pull-up to force recessive state in
case the input is left floating.
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is
compliant to the LIN bus specification 2.0, 2.1, and SAE
J2602-2.
The LIN interface is only active during Normal Mode. See
Table 7, Operating Modes Overview.
The MOSI digital pin receives SPI data from the MCU. This
data input is sampled on the negative edge of SCLK.
MASTER IN SLAVE OUT PIN (MISO)
CHIP SELECT PIN (CS)
CS is an active low digital input. It must remain low during
a valid SPI communication and allow for several devices to
be connected in the same SPI bus without contention. A
rising edge on CS signals the end of the transmission and the
moment the data shifted in is latched. A valid transmission
must consist of 8 bits only.
While in STOP Mode, a low-to-high level transition on this
pin will generate a wake-up condition for the 33910.
ANALOG MULTIPLEXER PIN (ADOUT0)
The ADOUT0 pin can be configured via the SPI to allow
the MCU A/D converter to read the several inputs of the
Analog Multiplexer, including the VSENSE and L1 input
voltages, and the internal junction temperature.
SERIAL DATA CLOCK PIN (SCLK)
PWM INPUT CONTROL PIN (PWMIN)
The SCLK pin is the SPI clock input. MISO data changes
on the positive transition of the SCLK. MOSI is sampled on
the negative edge of the SCLK.
This digital input can control the high sides drivers in
Normal Request and Normal Mode.
To enable PWM control, the MCU must perform a write
operation to the High Side Control Register (HSCR).
This pin has an internal 20 μA current pull-up.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
RESET PIN (RST)
This bidirectional pin is used to reset the MCU in case the
33910 detects a reset condition, or to inform the 33910 that
the MCU has just been reset. After release of the RST pin,
Normal Request Mode is entered.
The RST pin is an active low filtered input and output
formed by a weak pull-up and a switchable pull-down
structure which allows this pin to be shorted either to VDD or
to GND during software development, without the risk of
destroying the driver.
INTERRUPT PIN (IRQ)
The IRQ pin is a digital output used to signal events or
faults to the MCU while in Normal and Normal Request Mode
or to signal a wake-up from Stop Mode. This active low output
will transition to high only after the interrupt is acknowledged
by a SPI read of the respective status bits.
WATCHDOG CONFIGURATION PIN (WDCONF)
The WDCONF pin is the configuration pin for the internal
watchdog. A resistor can be connected to this pin to configure
the window watchdog period. When connected directly to
ground, the watchdog will be disabled. When this pin is left
open, the watchdog period is fixed to its lower precision
internal default value (150 ms typical).
GROUND CONNECTION PINS (AGND, PGND,
LGND)
The AGND, PGND and LGND pins are the Analog and
Power ground pins.
The AGND pin is the ground reference of the voltage
regulator module.
The PGND and LGND pins are used for high current load
return as in the LIN interface pin.
Note: PGND, AGND and LGND pins must be connected
together.
DIGITAL/ANALOG PIN (L1)
The L1 pin is multi purpose input. It can be used as a digital
input, which can be sampled by reading the SPI and used for
wake-up when 33910 is in low power mode or used as analog
input for the analog multiplexer. When used to sense voltage
outside the module, a 33 kohm series resistor must be used
on the input.
When used as wake-up input L1 can be configured to
operate in cyclic-sense mode. In this mode one or both of the
high side switches are configured to be periodically turned on
and sample the wake-up input. If a state change is detected
between two cycles a wake-up is initiated. The 33910 can
also wake-up from Stop or Sleep by a simple state change on
L1.
When used as analog input, the voltage present on the L1
pin is scaled down by an selectable internal voltage divider
and can be routed to the ADOUT0 output through the analog
multiplexer.
Note: If L1 input is selected in the analog multiplexer, it will
be disabled as digital input and remains disabled in low
power mode. No wake-up feature is available in that
condition.
When the L1 input is not selected in the analog
multiplexer, the voltage divider is disconnected from that
input.
HIGH SIDE OUTPUT PINS (HS1 AND HS2)
These two high side switches are able to drive loads such
as relays or lamps. Their structures are connected to the VS2
supply pin. The pins are short-circuit protected and both
outputs are also protected against overheating.
HS1 and HS2 are controlled by SPI and can respond to a
signal applied to the PWMIN input pin.
HS1 and HS2 outputs can also be used during low-power
mode for the cyclic-sense of the wake inputs.
POWER SUPPLY PINS (VS1 AND VS2)
Those are the battery level voltage supply pins. In an
application, VS1 and VS2 pins must be protected against
reverse battery connection and negative transient voltages
with external components. These pins sustain standard
automotive voltage conditions such as a load dump at 40 V.
The high side switches (HS1 and HS2) are supplied by the
VS2 pin. All other internal blocks are supplied by the VS1 pin.
33910
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VOLTAGE SENSE PIN (VSENSE)
This input can be connected directly to the battery line. It
is protected against battery reverse connection. The voltage
present in this input is scaled down by an internal voltage
divider, and can be routed to the ADOUT0 output pin and
used by the MCU to read the battery voltage.
The ESD structure on this pin allows for excursion up to
+40 V and down to -27 V, allowing this pin to be connected
directly to the battery line. It is strongly recommended to
connect a 10 kohm resistor in series with this pin for
protection purposes.
The HVDD pin needs to be connected to an external
capacitor to stabilize the regulated output voltage.
+5V MAIN REGULATOR OUTPUT PIN (VDD)
An external capacitor has to be placed on the VDD pin to
stabilize the regulated output voltage. The VDD pin is
intended to supply a microcontroller. The pin is current limited
against shorts to GND and over-temperature protected.
During Stop Mode, the voltage regulator does not operate
with its full drive capabilities and the output current is limited.
During Sleep Mode, the regulator output is completely shut
down.
HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)
This pin provides a switchable supply for external hall
sensors. While in Normal Mode, this current limited output
can be controlled through the SPI.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
INTRODUCTION
The 33910 offers three main operating modes: Normal
(Run), Stop, and Sleep (Low Power). In Normal Mode, the
device is active and is operating under normal application
conditions. The Stop and Sleep Modes are low power modes
with wake-up capabilities.
In Stop Mode, the voltage regulator still supplies the MCU
with VDD (limited current capability), while in Sleep Mode the
voltage regulator is turned off (VDD = 0 V).
Wake-up from Stop Mode is initiated by a wake-up
interrupt. Wake-up from Sleep Mode is done by a reset and
the voltage regulator is turned back on.
The selection of the different modes is controlled by the
MOD1:2 bits in the Mode Control Register (MCR).
Figure 14 describes how transitions are done between the
different operating modes. Table 7, 28, gives an overview of
the operating modes.
RESET MODE
The 33910 enters the Reset Mode after a power up. In this
mode, the RST pin is low for 1.0 ms (typical value). After this
delay, it enters the Normal Request Mode and the RST pin is
driven high.
The Reset Mode is entered if a reset condition occurs (VDD
low, watchdog trigger fail, after wake-up from Sleep Mode,
Normal Request Mode timeout occurs).
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the
device after the Reset Mode, or after a wake-up from Stop
Mode.
In Normal Request Mode, the VDD regulator is ON, the
RESET pin is High, and the LIN is operating in RX Only
Mode.
As soon as the device enters in the Normal Request Mode
an internal timer is started for 150 ms (typical value). During
these 150 ms, the MCU must configure the Timing Control
Register (TIMCR) and the Mode Control Register (MCR) with
MOD2 and MOD1 bits set = 0, to enter the Normal Mode. If
within the 150 ms timeout, the MCU does not command the
33910 to Normal Mode, it will enter in Reset Mode. If the
WDCONF pin is grounded in order to disable the watchdog
function, it goes directly in Normal Mode after the Reset
Mode.
NORMAL MODE
In Normal Mode, all 33910 functions are active and can be
controlled by the SPI interface and the PWMIN pin.
The VDD regulator is ON and delivers its full current
capability.
If an external resistor is connected between the WDCONF
pin and the Ground, the window watchdog function will be
enabled.
The wake-up input (L1) can be read as digital input or have
its voltage routed through the analog-multiplexer.
The LIN interface has slew rate and timing compatible with
the LIN protocol specification 2.0, 2.1 and SAEJ2602. The
LIN bus can transmit and receive information.
The high side switches are active and have PWM
capability according to the SPI configuration.
The interrupts are generated to report failures for VSUP
over/under-voltage, thermal shutdown, or thermal shutdown
prewarning on the main regulator.
SLEEP MODE
The Sleep Mode is a low power mode. From Normal
Mode, the device enters into Sleep Mode by sending one SPI
command through the Mode Control Register (MCR), or (VDD
low > 150 ms) with VSUV = 0. When in Reset Mode, a VDD
under-voltage condition with no VSUP under-voltage (VSUV =
0) will send the device to Sleep Mode. All blocks are in their
lowest power consumption condition. Only some wake-up
sources (wake-up input with or without cyclic sense, forced
wake-up and LIN receiver) are active. The 5.0 V regulator is
OFF. The internal low-power oscillator may be active if the IC
is configured for cyclic-sense. In this condition, one of the
high side switches is turned on periodically and the wake-up
input is sampled.
Wake-up from Sleep Mode is similar to a power-up. The
device goes in Reset Mode except that the SPI will report the
wake-up source and the BATFAIL flag is not set.
STOP MODE
The Stop Mode is the second low power mode, but in this
case the 5.0 V regulator is ON with limited current drive
capability. The application MCU is always supplied while the
33910 is operating in Stop Mode.
The device can enter into Stop Mode only by sending the
SPI command. When the application is in this mode, it can
wake-up from the 33910 side (for example: cyclic sense,
force wake-up, LIN bus, wake inputs) or the MCU side (CS,
RST pins). Wake-up from Stop Mode will transition the 33910
to Normal Request Mode and generates an interrupt except
if the wake-up event is a low to high transition on the CS pin
or comes from the RST pin.
33910
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Normal Request
Timeout
Expired
(t NRTOUT
)
Normal Request
timeout
expired (NR
TOUT)
VVDD
Low
DD Low
VDD High and
Normal
Request
VVDDLow
Low
DD
VVDD
LOW (>t NRTOUT
) expired) Expired
DD Low (>NRTOUT
andand
VSUV
=0
VSUV
=0
Wake-up
Wake-Up (Reset)
(Reset)
Sleep
Command
SLEEP
Command
Sleep
Stop
STOPCommand
Command
Normal
WD
Failed
WD
failed
Wake-up
(Interrupt)
Wake-Up Interrupt
Reset
Reset
Delay
(t Delay
VDD
High and
Reset
RST) expired
RST) (tExpired
WD
Disabled
WD disabled
Power Up
WDtrigger
Trigger
WD
Power
Down
Stop
VDD
VDD Low
Low
Legend
WD: Watchdog
Notes:
WD Disabled:
Watchdog disabled (WDCONF pin connected to GND)
WD
- meansisWatchdog
WD Trigger:
Watchdog
triggered by SPI command
WD
means or
Watchdog
disabled
(WDCONF
terminal connected to GND)
WD Failed: No disabled
watchdog- trigger
trigger occurs
in closed
window
WD
trigger
–
means
Watchdog
is triggered by SPI command
Stop Command: Stop command
sent via SPI
WD failed
– means
no Watchdog
trigger or trigger occurs in closed window
Sleep Command:
Sleep
command
sent via SPI
STOP
Command
meanschange,
STOP command
sent via SPI
Wake-up from
Stop
Mode: L1- state
LIN bus wake-up,
Periodic wake-up, CS rising edge wake-up or RST wake-up.
SLEEP
Command
means
SLEEP
command
send Periodic
via SPI wake-up.
Wake-up from
Sleep
Mode: L1 -state
change,
LIN
bus wake-up,
Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge
Figure 14. Operating Modes and Transitions
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Table 7. Operating Modes Overview
Function
VDD
Reset Mode Normal Request Mode
Normal
Mode
Stop Mode
Sleep Mode
Full
Full
Full
Stop
-
-
SPI(60)
SPI
-
-
HSx
-
SPI/PWM(61)
SPI/PWM
Note(62)
Note(63)
Analog Mux
-
SPI
SPI
-
-
L1
-
Input
Input
Wake-up
Wake-up
LIN
-
Rx-Only
HVDD
Watchdog
-
150 ms (typ.) timeout
Voltage
Monitoring
VSUP/VDD
VSUP/VDD
Notes
60.
61.
62.
63.
64.
Full/Rx-Only Rx-Only/Wake-up
On
(64)
/Off
VSUP/VDD
Wake-up
-
-
VDD
-
Operation can be enabled/controlled by the SPI.
Operation can be controlled by the PWMIN input.
HSx switches can be configured for cyclic sense operation in Stop Mode.
HSx switches can be configured for cyclic sense operation in Sleep Mode.
Windowing operation when enabled by an external resistor.
INTERRUPTS
Low-voltage Interrupt:
Interrupts are used to signal a microcontroller that a
peripheral needs to be serviced. The interrupts which can be
generated, change according to the operating mode. While in
Normal and Normal Request Modes, the 33910 signals
through interrupts special conditions which may require a
MCU software action. Interrupts are not generated until all
pending wake-up sources are read in the Interrupt Source
Register (ISR).
While in Stop Mode, interrupts are used to signal wake-up
events. Sleep Mode does not use interrupts. Wake-up is
performed by powering-up the MCU. In Normal and Normal
Request Mode the wake-up source can be read by SPI.
The interrupts are signaled to the MCU by a low logic level
of the IRQ pin, which will remain low until the interrupt is
acknowledged by a SPI read command of the ISR register.
The IRQ pin will then be driven high.
Interrupts are only asserted while in Normal, Normal
Request and Stop Mode. Interrupts are not generated while
the RST pin is low.
The following is a list of the interrupt sources in Normal and
Normal Request Modes. Some of these can be masked by
writing to the SPI - Interrupt Mask Register (IMR).
Signals when the supply line (VS1) voltage drops below
the VSUV threshold (VSUV).
High-voltage Interrupt:
Signals when the supply line (VS1) voltage increases
above the VSOV threshold (VSOV).
Over-temperature Prewarning:
Signals when the 33910 temperature has reached the preshutdown warning threshold. It is used to warn the MCU that
an over-temperature shutdown in the main 5.0 V regulator is
imminent.
LIN Over-temperature Shutdown / TXD Stuck At
Dominant / RXD Short-circuit:
These signal fault conditions within the LIN interface will
cause the LIN driver to be disabled. In order to restart the
operation, the fault must be removed and TXD must go
recessive.
High Side Over-temperature Shutdown:
Signals a shutdown in the high side outputs.
33910
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
RESET
To reset a MCU the 33910 drives the RST pin low for the
time the reset condition lasts.
After the reset source is removed, the state machine will
drive the RST output low for at least 1.0 ms (typical value)
before driving it high.
In the 33910, four main reset sources exist:
5.0 V Regulator Low-voltage-Reset (VRSTTH)
The 5.0 V regulator output VDD is continuously monitored
against brown outs. If the supply monitor detects that the
voltage at the VDD pin has dropped below the reset threshold
VRSTTH the 33910 will issue a reset. In case of overtemperature, the voltage regulator will be disabled and the
voltage monitoring will issue a VDDOT Flag independently of
the VDD voltage.
Window Watchdog Overflow
If the watchdog counter is not properly serviced while its
window is open, the 33910 will detect an MCU software runaway and will reset the microcontroller.
Wake-up From Sleep Mode
During Sleep Mode, the 5V regulator is not active, hence
all wake-up requests from Sleep Mode require a power-up/
reset sequence.
In order to select and activate direct wake-up from L1
input, the Wake-up Control Register (WUCR) must be
configured with appropriate L1WE input enabled or disabled.
The wake-up input’s state is read through the Wake-up
Status Register (WUSR).
L1 input is also used to perform cyclic-sense wake-up.
Note: Selecting an L1 input in the analog multiplexer
before entering low power mode will disable the wake-up
capability of the L1 input
Wake-up from Wake-up input (L1) with cyclic sense timer
enabled
The SBCLIN can wake-up at the end of a cyclic sense
period if on the wake-up input line (L1) a state change occurs.
One or both HSx switch can be activated in Sleep or Stop
Modes from an internal timer. Cyclic sense and force wakeup are exclusive. If cyclic sense is enabled, the force wakeup can not be enabled.
In order to select and activate the cyclic sense wake-up
from the L1 input, before entering in low power modes (Stop
or Sleep Modes), the following SPI set-up has to be
performed:
In WUCR: select the L1 input to WU-enable.
In HSCR: enable the desired HSx.
• In TIMCR: select the CS/WD bit and determine the
cyclic sense period with CYSTx bits.
• Perform Goto Sleep/Stop command.
External Reset
The 33910 has a bidirectional reset pin which drives the
device to a safe state (same as Reset Mode) for as long as
this pin is held low. The RST pin must be held low long
enough to pass the internal glitch filter and get recognized by
the internal reset circuit. This functionality is also active in
Stop Mode.
After the RST pin is released, there is no extra t RST to be
considered.
WAKE-UP CAPABILITIES
Once entered into one of the low-power modes (Sleep or
Stop) only wake-up sources can bring the device into Normal
Mode operation.
In Stop Mode, a wake-up is signaled to the MCU as an
interrupt, while in Sleep Mode the wake-up is performed by
activating the 5.0 V regulator and resetting the MCU. In both
cases the MCU can detect the wake-up source by accessing
the SPI registers and reading the Interrupt Source Register.
There is no specific SPI register bit to signal a CS wake-up or
external reset. If necessary this condition is detected by
excluding all other possible wake-up sources.
Wake-up from Wake-up input (L1) with cyclic sense
disabled
Forced Wake-up
The 33910 can wake-up automatically after a
predetermined time spent in Sleep or Stop Mode. Cyclic
sense and Forced wake-up are exclusive. If Forced wake-up
is enabled, the Cyclic Sense can not be enabled.
To determine the wake-up period, the following SPI set-up
has to be sent before entering in low power modes:
• In TIMCR: select the CS/WD bit and determine the low
power mode period with CYSTx bits.
• In HSCR: all HSx bits must be disabled.
CS Wake-up
While in Stop Mode, a rising edge on the CS will cause a
wake-up. The CS wake-up does not generate an interrupt,
and is not reported on SPI.
LIN Wake-up
While in the low-power mode, the 33910 monitors the
activity on the LIN bus. A dominant pulse larger than t PROPWL
followed by a dominant to recessive transition will cause a
LIN wake-up. This behavior protects the system from a short
to ground bus condition. The bit RXONLY = 1 from LINCR
Register disables the LIN wake-up from Stop Mode.
The wake-up line is dedicated to sense state changes of
external switch and wake-up the MCU (in Sleep or Stop
Mode).
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
RST Wake-up
While in Stop Mode, the 33910 can wake-up when the
RST pin is held low long enough to pass the internal glitch
filter. Then, the 33910 will change to Normal Request or
Normal Modes depending on the WDCONF pin
configuration. The RST wake-up does not generate an
interrupt and is not reported via SPI.
From Stop Mode, the following wake-up events can be
configured:
• Wake-up from L1 input without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• CS wake-up
• LIN wake-up
• RST wake-up
From Sleep Mode, the following wake-up events can be
configured:
• Wake-up from L1 input without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• LIN wake-up
WINDOW WATCHDOG
The 33910 includes a configurable window watchdog
which is active in Normal Mode. The watchdog can be
configured by an external resistor connected to the WDCONF
pin. The resistor is used to achieve higher precision in the
timebase used for the watchdog.
SPI clears are performed by writing through the SPI in the
MOD bits of the Mode Control Register (MCR).
During the first half of the SPI timeout, watchdog clears are
not allowed, but after the first half of the SPI timeout window,
the clear operation opens. If a clear operation is performed
outside the window, the 33910 will reset the MCU, in the
same way as when the watchdog overflows.
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WD TIMING X 50%
WINDOW OPEN
FOR WATCHDOG
CLEAR
WD TIMING X 50%
WD PERIOD (tPWD)
WD TIMING SELECTED BY RESISTOR
ON WDCONF PIN
Figure 15. Window Watchdog Operation
To disable the watchdog function in Normal Mode the user
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request Mode. The WDOFF bit
in the Watchdog Status Register (WDSR) will be set. This
condition is only detected during Reset Mode.
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150 ms (typ.) and signals the faulty condition
through the Watchdog Status Register (WDSR).
The watchdog timebase can be further divided by a
prescaler which can be configured by the Timing Control
Register (TIMCR). During Normal Request Mode, the
window watchdog is not active but there is a 150 ms (typ.)
timeout for leaving the Normal Request Mode. In case of a
timeout, the 33910 will enter into Reset Mode, resetting the
microcontroller before entering again into Normal Request
Mode.
FAULTS DETECTION MANAGEMENT
The 33910 has the capability to detect faults like an over
or under-voltage on VS1, TxD in permanent Dominant State,
Over-temperature on HS, LIN. It is able to take corrective
actions accordingly. Most of faults are monitoring through
SPI and the Interrupt pin. The microcontroller can also take
actions.
The following table summarizes all fault sources the
device is able to detect with associated conditions. The status
for a device recovery and the SPI or pins monitoring are also
described.
33910
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Table 8. Fault Detection Management Conditions
MONITORING(66)
BLOCK
FAULT
BATTERY FAIL
VSUP OVERVOLTAGE
Power Supply
MODE
All modes
FALLOUT
VSUP<3.0 V (typ)
then power-up
VSUP > 19.25 V (typ)
Normal, Normal
Request
VSUP UNDERVOLTAGE
VDD UNDERVOLTAGE
CONDITION
In Normal mode, HS
shutdown if bit
HVSE=1 (reg MCR)
VSUP < 6.0 V (typ)
All except Sleep
VDD < 4.5 V (typ)
RECOVERY
REG (FLAG,
BIT)
INTERRUPT
Condition gone
VSR (BATFAIL, 0)
-
Condition gone, to
re-enable HS write to
HSCR registers
VSR (VSOV,3)
-
(67)
VSR (VSUV,2)
Reset (65)
IRQ low +
ISR (0101)
IRQ low + ISR
(0101)
-
-
Condition gone
VDD OVER-TEMP
PREWARNING
VDD OVERTEMPERATURE
All except Low
Power modes
RXD PIN SHORT
CIRCUIT
LIN
TXD PIN
PERMANENT
DOMINANT
Normal, Normal
Request
VDD shutdown,
Reset then Sleep
RXD pin shorted to
GND or 5 V
LIN trans shutdown
TXD pin low for more
than 1s (typ)
Temperature >
160°C (typ)
HIGH SIDE DRIVERS
OVERTEMPERATURE
Temperature >
160°C (typ)
HS2 OPEN-LOAD
DETECTION
-
Temperature >
170°C (typ)
LIN DRIVER OVERTEMPERATURE
HS1 OPEN-LOAD
DETECTION
High Side
Temperature >
115°C (typ)
LIN transmitter
shutdown
VSR (VDDOT,1)
IRQ low + ISR
(0101)
-
-
LINSR,
(RXSHORT,3)
LIN transmitter reenabled once the
condition is gone and
TXD is high
LINSR (TXDOM,2)
IRQ low + ISR
(0100)(67)
LINSR (LINOT,1)
Both HS thermal
shutdown
Condition gone, to
re-enable HS write to
HSCR reg
All flags in HSSR
are set
IRQ low + ISR
(0010) (67)
HSSR (HS1OP,1)
Normal, Normal
Request
Current through HSx
< 5.0 mA (typ)
HSSR (HS2OP,3)
Condition gone
HS1 OVERCURRENT
HS2 OVERCURRENT
NORMAL REQUEST
TIME-OUT EXPIRED
Watchdog
Notes
65.
66.
67.
Normal Request
Current through HSx
tends to rise above
the current limit
60 mA (min)
HSx on with limited
current capability
60 mA (min)
The MCU did not
command the device
to Normal mode
within the 150 ms
timeout after reset
Reset
HSSR (HS1CL,0)
HSSR (HS2CL,2)
-
WATCHDOG
TIMEOUT
Normal
WD timeout or WD
clear within the
window closed
Reset
-
WATCHDOG ERROR
Normal
WDCONF pin is
floating
WD internal lower
precision timebase
150 ms (typ)
WDSR (WDTO, 3)
Connect WDCONF
to a resistor or to
GND
WDSR (WDERR, 2)
When in Reset mode a VDD under-voltage condition combined with no VSUP under-voltage (VSUV=0) will send the device to Sleep mode.
Registers to be read when back in Normal Request or Normal Mode depending on the fault. Interrupts only generated in Normal, Normal Request and Stop modes
Unless masked, If masked IRQ remains high and the ISR flags are not set.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
TEMPERATURE SENSE GAIN
The analog multiplexer can be configured via SPI to allow
the ADOUT0 pin to deliver the internal junction temperature
of the device.
The graph below illustrates the internal chip temp sense
obtained per characterization at 3 temperatures with 3
different lots and 30 samples.
Temperature Sense Analog Output Voltage
5
4.5
Vadout0 (V)
4
3.5
3
2.5
2
-50
0
50
100
150
Temperature (°C)
Figure 16. Temperature Sense Gain
HIGH SIDE OUTPUT PINS HS1 AND HS2
These outputs are two high side drivers intended to drive
small resistive loads or LEDs incorporating the following
features:
• PWM capability (software maskable)
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• High-voltage shutdown (software maskable)
• Cyclic sense
The high side switches are controlled by the bits HS1:2 in
the High Side Control Register (HSCR).
PWM Capability (direct access)
Each high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
If both the bits HS1 and PWMHS1 are set in the High Side
Control Register (HSCR), then the HS1 driver is turned on if
the PWMIN pin is high and turned of if the PWMIN pin is low.
This applies to HS2 configuring HS2 and PWMHS2 bits.
33910
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Interrupt
Control
Module
VDD
VDD
PWMIN
High-Side Interrupt
High Voltage Shutdown
HVSE
PWMHSx
VS2
MOD1:2
on/off
HSx
Control
HSxOP
Status
HSxCL
High Side Driver
charge pump
open load detection
current limitation
over-temperture shutdown (interrupt maskable)
high voltage shutdown (maskable)
Cyclic Sense
HSx
Wakeup
Module
Figure 17. High Side Drivers HS1 and HS2
Open Load Detection
Each high side driver signals an open load condition if the
current through the high side is below the open load current
threshold.
The open load condition is indicated with the bits HS1OP
and HS2OP in the High Side Status Register (HSSR).
Current Limitation
Each high side driver has an output current limitation. In
combination with the over-temperature shutdown the highside drivers are protected against over-current and shortcircuit failures.
When the driver operates in the current limitation area, it is
indicated with the bits HS1CL and HS2CL in the HSSR.
Note: If the driver is operating in current limitation mode,
excessive power might be dissipated.
Over-temperature Protection (HS Interrupt)
Both high side drivers are protected against overtemperature. In case of an over-temperature condition both
high side drivers are shut down and the event is latched in the
Interrupt Control Module. The shutdown is indicated as HS
Interrupt in the Interrupt Source Register (ISR).
A thermal shutdown of the high side drivers is indicated by
setting all HSxOP and HSxCL bits simultaneously.
If the bit HSM is set in the Interrupt Mask Register (IMR),
then an interrupt (IRQ) is generated.
A write to the High Side Control Register (HSCR), when
the over-temperature condition is gone, will re-enable the
high side drivers.
High-voltage Shutdown
In case of a high voltage condition and if the high voltage
shutdown is enabled (bit HVSE in the Mode Control Register
(MCR) is set both high side drivers are shut down.
A write to the High Side Control Register (HSCR), when
the high voltage condition is gone, will re-enable the high side
drivers.
Sleep And Stop Mode
The high side drivers can be enabled to operate in Sleep
and Stop Mode for cyclic sensing. Also see Table 7,
Operating Modes Overview.
LIN PHYSICAL LAYER
The LIN bus pin provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification
and has the following features:
• LIN physical layer 2.0, 2.1 and SAEJ2602 compliant
• Slew rate selection
• Over-temperature shutdown
• Advanced diagnostics
The LIN driver is a low side MOSFET with thermal
shutdown. An internal pull-up resistor with a serial diode
structure is integrated, so no external pull-up components are
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
required for the application in a slave node. The fall time from
dominant to recessive and the rise time from recessive to
dominant is controlled. The symmetry between both slopes is
guaranteed.
LIN Pin
The LIN pin offers a high susceptibility immunity level from
external disturbance, guaranteeing communication during
external disturbance.
WAKE-UP
MODULE
LIN
Wake-up
MOD1:2
LSR0:1
VS1
J2602
LIN DRIVER
RXONLY
Slope and Slew Rate Control
RXSHORT
Over-temperature Shutdown (interrupt maskable)
TXDOM
LINOT
30 K
LIN
TXD
SLOPE
CONTROL
WAKE-UP
FILTER
LGND
RXD
RECEIVER
Figure 18. LIN Interface
Slew Rate Selection
The slew rate can be selected for optimized operation at
10.4 and 20 kBit/s as well as a fast baud rate for test and
programming. The slew rate can be adapted with the bits
LSR1:0 in the LIN Control Register (LINCR). The initial slew
rate is optimized for 20 kBit/s.
J2602 Conformance
To be compliant with the SAE J2602-2 specification, the
J2602 feature has to be enabled in the LINCR Register (bit
DIS_J2602 sets to 0). The LIN transmitter is disabled in case
of a VSUP under-voltage condition occurs and TXD is in
Recessive State: the LIN bus goes in Recessive State and
RXD goes high. The LIN transmitter is not disabled if TXD is
in Dominant State. A deglitcher on VSUP (tJ2602_DEG) is
implemented to avoid false switching.
If the (DIS_J2602) bit is set to 1, the J2602 feature is
disabled and the communication TXD-LIN-RXD works for
VSUP down to 4.6 V (typical value) and then the
communication is interrupted.
The (DIS_J2602) bit is set per default to 0.
Over-temperature Shutdown (LIN Interrupt)
The output low side FET is protected against overtemperature conditions. In case of an over-temperature
condition, the transmitter will be shut down and the LINOT bit
in the LIN Status Register (LINSR) is set.
If the LINM bit is set in the Interrupt Mask Register (IMR),
an Interrupt IRQ will be generated.
The transmitter is automatically re-enabled once the
condition is gone and TXD is high.
RXD Short-circuit Detection (LIN Interrupt)
The LIN transceiver has a short-circuit detection for the
RXD output pin. If the device transmits and in case of a shortcircuit condition, either 5.0 V or Ground, the RXSHORT bit in
33910
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
the LIN Status Register (LINSR) is set and the transmitter is
shut down.
If the LINM bit is set in the Interrupt Mask Register (IMR),
an Interrupt IRQ will be generated.
The transmitter is automatically re-enabled once the
condition is gone (transition on RXD) and TXD is high.
A read of the LIN Status Register (LINSR) without the RXD
pin short-circuit condition will clear the bit RXSHORT.
TXD Dominant Detection (LIN Interrupt)
The LIN transceiver monitors the TXD input pin to detect a
stuck in dominant (0 V) condition. In case of a stuck condition
(TXD pin 0 V for more than 1 second (typ.)), the transmitter is
shut down and the TXDOM bit in the LIN Status Register
(LINSR) is set.
If the LINM bit is set in the IMR, an Interrupt IRQ will be
generated.
The transmitter is automatically re-enabled once TXD is
high.
A read of the LIN Status Register (LINSR) with the TXD pin
at 5.0 V will clear the bit TXDOM.
LIN Receiver Operation Only
While in Normal Mode, the activation of the RXONLY bit
disables the LIN TXD driver. In case of a LIN error condition,
this bit is automatically set. If Stop mode is selected with this
bit set, the LIN wake-up functionality is disabled and the RXD
pin will reflect the state of the LIN bus.
STOP Mode And Wake-up Feature
During Stop Mode operation, the transmitter of the
physical layer is disabled. The receiver is still active and able
to detect wake-up events on the LIN bus line.
A dominant level longer than TPROPWL followed by a rising
edge will generate a wake-up interrupt, and will be reported
in the Interrupt Source Register (ISR). Also see Figure 11,
page 21.
SLEEP Mode And Wake-up Feature
During Sleep Mode operation, the transmitter of the
physical layer is disabled. The receiver must be active to
detect wake-up events on the LIN bus line.
A dominant level longer than TPROPWL followed by a rising
edge will generate a system wake-up (Reset), and will be
reported in the Interrupt Source Register (ISR). Also see
Figure 10, page 21.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
33910 SPI INTERFACE AND CONFIGURATION
• MISO — Master-in Slave-out
• SCLK— Serial Clock
A complete data transfer via the SPI consists of 1 byte.
The master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 4 system
status bits (VMS,LINS,HSS,n.d.) + 4 bits of status information
(S3:S0).
The serial peripheral interface creates the communication
link between a microcontroller (master) and the 33910.
The interface consists of four pins (see Figure 19):
• CS — Chip Select
• MOSI — Master-out Slave-in
CS
Register Write Data
MOSI
A3
A2
A1
A0
C3
C2
C1
C0
S1
S0
Register Read Data
MISO
VMS LINS HSS
-
S3
S2
SCLK
Read Data Latch
Rising: 33910 changes MISO/
MCU changes MOSI
Write Data Latch
Falling: 33910 samples MOSI/
MCU samples MISO
Figure 19. SPI Protocol
During the inactive phase of the CS (HIGH), the new data
The rising edge of the Chip Select CS indicates the end of
transfer is prepared.
the transfer and latches the write data (MOSI) into the
register. The CS high forces MISO to the high-impedance
The falling edge of the CS indicates the start of a new data
state.
transfer and puts the MISO in the low-impedance state and
Register reset values are described along with the reset
latches the analog status data (Register read data).
condition.
Reset condition is the condition causing the bit to
With the rising edge of the SPI clock (SCLK), the data is
be set to its reset value. The main reset conditions are:
moved to MISO/MOSI pins. With the falling edge of the SPI
- Power-On Reset (POR): the level at which the logic is
clock (SCLK), the data is sampled by the receiver.
reset
and BATFAIL flag sets.
The data transfer is only valid if exactly 8 sample clock
- Reset Mode
edges are present during the active (low) phase of CS.
- Reset done by the RST pin (ext_reset)
33910
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
SPI REGISTER OVERVIEW
Table 9. System Status Register
BIT
Adress(A3:A0)
$0 - $F
Register Name / Read / Write Information
SYSSR - System Status Register
R
7
6
5
4
VMS
LINS
HSS
-
Table 10 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.
Table 10. SPI Register Overview
BIT
Adress(A3:A0)
Register Name / Read / Write Information
3
2
1
0
MCR - Mode Control Register
W
HVSE
0
MOD2
MOD1
VSR - Voltage Status Register
R
VSOV
VSUV
VDDOT
BATFAIL
VSR - Voltage Status Register
R
VSOV
VSUV
VDDOT
BATFAIL
WUCR - Wake-up Control Register
W
0
0
0
L1WE
WUSR - Wake-up Status Register
R
-
-
-
L1
WUSR - Wake-up Status Register
R
-
-
-
L1
LINCR - LIN Control Register
W
DIS_J2602
RXONLY
LSR1
LSR0
LINSR - LIN Status Register
R
RXSHORT
TXDOM
LINOT
0
LINSR - LIN Status Register
R
RXSHORT
TXDOM
LINOT
0
HSCR - High Side Control Register
W
PWMHS2
PWMHS1
HS2
HS1
HSSR - High Side Status Register
R
HS2OP
HS2CL
HS1OP
HS1CL
HSSR - High Side Status Register
R
HS2OP
HS2CL
HS1OP
HS1CL
WD2
WD1
WD0
TIMCR - Timing Control Register
W
CS/WD
CYST2
CYST1
CYST0
$0
$1
$2
$3
$4
$5
$6
$7
$A
WDSR - Watchdog Status Register
R
WDTO
WDERR
WDOFF
WDWO
$B
WDSR - Watchdog Status Register
R
WDTO
WDERR
WDOFF
WDWO
$C
AMUXCR - Analog Multiplexer Control Register
W
L1DS
MX2
MX1
MX0
$D
CFR - Configuration Register
W
HVDD
CYSX8
0
0
IMR - Interrupt Mask Register
W
HSM
0
LINM
VMM
ISR - Interrupt Source Register
R
ISR3
ISR2
ISR1
ISR0
ISR - Interrupt Source Register
R
ISR3
ISR2
ISR1
ISR0
$E
$F
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
REGISTER DEFINITIONS
HS1CL
System Status Register - SYSSR
HS1OP
The System Status Register (SYSSR) is always
transferred with every SPI transmission and gives a quick
system status overview. It summarizes the status of the
Voltage Monitor Status (VMS), LIN Status (LINS) and High
Side Status (HSS).
Table 11. System Status Register
Read
HS2OP
Figure 22. High Side Status
Mode Control Register - MCR
S7
S6
S5
S4
VMS
LINS
HSS
-
The Mode Control Register (MCR) allows switching
between the operation modes and to configure the 33910.
Writing the MCR will return the VSR.
Table 12. Mode Control Register - $0
VMS - Voltage Monitor Status
This read-only bit indicates that one or more bits in the
VSR are set.
1 = Voltage Monitor bit set
0 = None
BATFAIL
VDDOT
VSUV
HSS
HS2CL
VMS
VSOV
Figure 20. Voltage Monitor Status
LINS - LIN Status
This read-only bit indicates that one or more bits in the
LINSR are set.
1 = LIN Status bit set
0 = None
C3
C2
C1
C0
Write
HVSE
0
MOD2
MOD1
Reset
Value
1
0
-
-
Reset
Condition
POR
POR
-
-
HVSE - High-Voltage Shutdown Enable
This write-only bit enables/disables automatic shutdown of
the high side drivers during a high-voltage VSOV condition.
1 = automatic shutdown enabled
0 = automatic shutdown disabled
MOD2, MOD1 - Mode Control Bits
These write-only bits select the operating mode and allow
clearing the watchdog in accordance with Table 10 Mode
Control Bits.
Table 13. Mode Control Bits
LINOT
TXDOM
LINS
RXSHORT
Figure 21. LIN Status
HSS - High Side Switch Status
This read-only bit indicates that one or more bits in the
HSSR are set.
1 = High Side Status bit set
0 = None
MOD2
MOD1
Description
0
0
Normal Mode
0
1
Stop Mode
1
0
Sleep Mode
1
1
Normal Mode + Watchdog Clear
Voltage Status Register - VSR
Returns the status of the several voltage monitors. This
register is also returned when writing to the Mode Control
Register (MCR).
Table 14. Voltage Status Register - $0/$1
Read
S3
S2
S1
S0
VSOV
VSUV
VDDOT
BATFAIL
33910
38
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
VSOV - VSUP Over-voltage
This read-only bit indicates an over-voltage condition on
the VS1 pin.
1 = Over-voltage condition.
0 = Normal condition.
VSUV - VSUP Under-voltage
This read-only bit indicates an under-voltage condition on
the VS1 pin.
1 = Under-voltage condition.
0 = Normal condition.
VDDOT - Main Voltage Regulator Over-temperature
Warning
This read-only bit indicates that the main voltage regulator
temperature reached the Over-temperature Prewarning
Threshold.
1 = Over-temperature Prewarning
0 = Normal
BATFAIL - Battery Fail Flag.
This read-only bit is set during power-up and indicates that
the 33910 had a Power-On-Reset (POR).
Any access to the MCR or VSR will clear the BATFAIL flag.
1 = POR Reset has occurred
0 = POR Reset has not occurred
Wake-Up Control Register - WUCR
This register is used to control the digital wake-up input.
Writing the WUCR will return the Wake-Up Status Register
(WUSR).
Table 15. Wake-Up Control Register - $2
C3
C2
C1
C0
Write
0
0
0
L1WE
Reset
Value
1
1
1
1
Reset
Condition
POR, Reset Mode or ext_reset
L1WE - Wake-up Input Enable
This write-only bit enables/disables the L1 input. In Stop
and Sleep Mode the L1WE bit activates the L1 input for wakeup. If the L1 input is selected on the analog multiplexer, the
L1WE is masked to 0.
1 = Wake-up Input enabled.
0 = Wake-up Input disabled.
Wake-up Status Register - WUSR
This register is used to monitor the digital wake-up input
and is also returned when writing to the WUCR.
Table 16. Wake-up Status Register - $2/$3
Read
S3
S2
S1
S0
-
-
-
L1
L1 - Wake-up input 1
This read-only bit indicates the status of the L1 input. If the
L1 input is not enabled, then the Wake-up status will return 0.
After a wake-up from Stop or Sleep Mode this bit also
allows to verify the L1 input has caused the wake-up, by first
reading the Interrupt Status Register (ISR) and then reading
the WUSR. The source of the wake-up is only reported on the
first WUCR or WUSR access.
1 = L1 pin high, or L1 is the source of the wake-up.
0 = L1 pin low, disabled or selected as an analog input.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LIN Control Register - LINCR
This register controls the LIN physical interface block.
Writing the LIN Control Register (LINCR) returns the LIN
Status Register (LINSR).
Table 17. LIN Control Register - $4
C3
C2
C1
C0
Write
DIS_J2602
RXONLY
LSR1
LSR0
Reset
Value
0
0
0
0
Reset
Condition
POR
POR, Reset
Mode, ext_reset
or LIN failure
gone*
Table 18. LIN Slew Rate Control
LSR1
LSR0
Description
0
0
Normal Slew Rate (up to 20 kb/s)
0
1
Slow Slew Rate (up to 10 kb/s)
1
0
Fast Slew Rate (up to 100 kb/s)
1
1
Reserved
LIN Status Register - LINSR
This register returns the status of the LIN physical
interface block and is also returned when writing to the
LINCR.
POR
* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set,
the flag resets automatically when the failure is gone.
Table 19. LIN Status Register - $4/$5
Read
S3
S2
S1
S0
RXSHORT
TXDOM
LINOT
0
J2602 - LIN Dominant Voltage Select
RXSHORT - RXD Pin Short-circuit
This write-only bit controls the J2602 circuitry. If the
circuitry is enabled (bit sets to 0), the TXD-LIN-RXD
communication works down to the battery under-voltage
condition is detected. Below, the bus is in recessive state. If
the circuitry is disabled (bit sets to 1), the communication
TXD-LIN-RXD works down to 4.6 V (typical value).
0 = Enabled J2602 feature.
1 = Disabled J2602 feature.
This read-only bit indicates a short-circuit condition on the
RXD pin (shorted either to 5.0 V or to Ground). The shortcircuit delay must be a worst case of 8.0 µs to be detected
and to shut down the driver. To clear this bit, it must be read
after the condition is gone (transition detected on RXD pin).
The LIN driver is automatically re-enabled once the condition
is gone and TXD is high.
1 = RXD short-circuit condition.
0 = None.
RXONLY - LIN Receiver Operation Only
TXDOM - TXD Permanent Dominant
This write-only bit controls the behavior of the LIN
transmitter.
In Normal Mode, the activation of the RXONLY bit disables
the LIN transmitter. In case of a LIN error condition, this bit is
automatically set.
In Stop Mode this bit disables the LIN wake-up
functionality, and the RXD pin will reflect the state of the LIN
bus.
1 = only LIN receiver active (Normal Mode) or LIN wakeup disabled (Stop Mode).
0 = LIN fully enabled.
This read-only bit signals the detection of a TXD pin stuck
at dominant (Ground) condition and the resultant shutdown in
the LIN transmitter. This condition is detected after the TXD
pin remains in dominant state for more than 1 second (typical
value).
To clear this bit, it must be read after TXD has gone high.
The LIN driver is automatically re-enabled once TXD goes
High.
1 = TXD stuck at dominant fault detected.
0 = None.
LSRx - LIN Slew-Rate
LINOT - LIN Driver Over-temperature
This write-only bit controls the LIN driver slew-rate in
accordance with Table 18.
This read-only bit signals that the LIN transceiver was
shutdown due to over-temperature. The transmitter is
automatically re-enabled after the over-temperature
condition is gone and TXD is high. The LINOT bit is cleared
after SPI read once the condition is gone.
1 = LIN over-temperature shutdown
0 = None
33910
40
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
High Side Control Register - HSCR
Timing Control Register - TIMCR
This register controls the operation of the high side drivers.
Writing to this register returns the High Side Status Register
(HSSR).
This register allows to configure the watchdog, the cyclic
sense and Forced Wake-up periods. Writing to the Timing
Control Register (TIMCR) will also return the Watchdog
Status Register (WDSR).
Table 20. High Side Control Register - $6
C3
C2
C1
C0
Write
PWMHS2
PWMHS1
HS2
HS1
Reset
Value
0
0
0
0
Table 22. Timing Control Register - $A
C3
Reset
Condition
Write
POR, Reset Mode, ext_reset, HSx
over-temp or (VSOV & HVSE)
POR
PWMHSx - PWM Input Control Enable.
This write-only bit enables/disables the PWMIN input pin
to control the respective high side switch. The corresponding
high side switch must be enabled (HSx bit).
1 = PWMIN input controls HSx output.
0 = HSx is controlled only by SPI.
HSx - HSx Switch Control.
This write-only bit enables/disables the corresponding
high side switch.
1 = HSx switch on.
0 = HSx switch off.
C2
C1
C0
WD2
WD1
WD0
CYST2
CYST1
CYST0
0
0
0
CS/WD
Reset
Value
-
Reset
Condition
-
POR
CS/WD - Cyclic Sense or Watchdog prescaler select
This write-only bit selects which prescaler is being written
to, the Cyclic Sense/Forced Wake-up prescaler or the
Watchdog prescaler.
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select
WDx - Watchdog Prescaler
High Side Status Register - HSSR
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table . This configuration is valid only if
windowing watchdog is active.
This register returns the status of the high side switches
and is also returned when writing to the HSCR.
Table 23. Watchdog Prescaler
WD2
WD1
WD0
Prescaler Divider
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
6
High Side thermal shutdown
1
0
0
8
A thermal shutdown of the high side drivers is indicated by
setting all HSxOP and HSxCL bits simultaneously.
1
0
1
10
1
1
0
12
HSxOP - High Side Switch Open-Load Detection
1
1
1
14
Table 21. High Side Status Register - $6/$7
Read
S3
S2
S1
S0
HS2OP
HS2CL
HS1OP
HS1CL
This read-only bit signals that the high side switches are
conducting current below a certain threshold indicating
possible load disconnection.
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal
HSxCL - High Side Current Limitation
This read-only bit indicates that the respective high side
switch is operating in current limitation mode.
1 = HSx in current limitation (or thermal shutdown)
0 = Normal
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 43).
This option is only active if one of the high side switches is
enabled when entering in Stop or Sleep Mode. Otherwise, a
timed wake-up is performed after the period shown in Table .
Table 24. Cyclic Sense and Force Wake-up Interval
CYSX8(68)
CYST2
CYST1
CYST0
Interval
X
0
0
0
No cyclic sense(69)
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Table 24. Cyclic Sense and Force Wake-up Interval
(68)
CYSX8
timeouts are disabled and the device automatically enters
Normal Mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
1 = Watchdog is disabled
0 = Watchdog is enabled
CYST2
CYST1
CYST0
Interval
0
0
0
1
20 ms
0
0
1
0
40 ms
0
0
1
1
60 ms
0
1
0
0
80 ms
WDWO - Watchdog Window Open
0
1
0
1
100 ms
0
1
1
0
120 ms
0
1
1
1
140 ms
1
0
0
1
160 ms
This read-only bit signals when the watchdog window is
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
1 = Watchdog window open
0 = Watchdog window closed
1
0
1
0
320 ms
1
0
1
1
480 ms
Analog Multiplexer Control Register - MUXCR
1
1
0
0
640 ms
1
1
0
1
800 ms
This register controls the analog multiplexer and selects
the divider ration for the L1 input divider.
1
1
1
0
960 ms
1
1
1
1
1120 ms
Table 26. Analog Multiplexer Control Register -$C
Notes
68. bit CYSX8 is located in Configuration Register (CFR)
69. No Cyclic Sense and no Force Wake-up available.
Watchdog Status Register - WDSR
This register returns the Watchdog status information and
is also returned when writing to the TIMCR.
Table 25. Watchdog Status Register - $A/$B
Read
S3
S2
S1
S0
WDTO
WDERR
WDOFF
WDWO
WDTO - Watchdog Timeout
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
Any access to this register or the Timing Control Register
(TIMCR) will clear the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None
WDERR - Watchdog Error
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The Windowing function is
disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
WDOFF - Watchdog Off
This read-only bit signals that the watchdog pin connected
to Ground and therefore disabled. In this case watchdog
C3
C2
C1
C0
Write
L1DS
MX2
MX1
MX0
Reset
Value
1
0
0
0
Reset
Condition
POR
POR, Reset Mode or ext_reset
L1DS - L1 Analog Input Divider Select
This write-only bit selects the resistor divider for the L1
analog input. Voltage is internally clamped to VDD.
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
MXx - Analog Multiplexer Input Select
These write-only bits selects which analog input is
multiplexed to the ADOUT0 pin according to Table .
When disabled or when in Stop or Sleep Mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Table 27. Analog Multiplexer Channel Select
MX2
MX1
MX0
Meaning
0
0
0
Disabled
0
0
1
Reserved
0
1
0
Die Temperature Sensor
0
1
1
VSENSE input
1
0
0
L1 input
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
33910
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Configuration Register - CFR
HSM - High Side Interrupt Mask
This register controls the Hall Sensor Supply enable/
disable and the cyclic sense timing multiplier.
This write-only bit enables/disables interrupts generated in
the high side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
Table 28. Configuration Register - $D
C3
C2
C1
C0
Write
HVDD
CYSX8
0
0
Reset
Value
0
0
0
0
Reset
Condition
POR, Reset
Mode or
ext_reset
POR
POR
POR
LINM - LIN Interrupts Mask
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
HVDD - Hall Sensor Supply Enable
This write-only bit enables/disables the state of the hall
sensor supply.
1 = HVDD on
0 = HVDD off
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the VSUP over-voltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled
Interrupt Source Register - ISR
CYSX8 - Cyclic Sense Timing x 8.
This write-only bit influences the cyclic sense and Forced
Wake-up period as shown in Table .
1 = Multiplier enabled
0 = None
Interrupt Mask Register - IMR
This register allows masking of some of the interrupt
sources. No interrupt will be generated to the MCU and no
flag will be set in the ISR register. The 5.0V Regulator overtemperature prewarning interrupt and Under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
Writing to the IMR will return the ISR.
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
This register is also returned when writing to the Interrupt
Mask Register (IMR).
Table 30. Interrupt Source Register - $E/$F
Read
S3
S2
S1
S0
ISR3
ISR2
ISR1
ISR0
ISRx - Interrupt Source Register
Table 29. Interrupt Mask Register - $E
C3
C2
C1
C0
Write
HSM
0
LINM
VMM
Reset
Value
1
1
1
1
Reset
Condition
These read-only bits indicate the interrupt source following
Table . If no interrupt is pending then all bits are 0.
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
POR
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Table 31. Interrupt Sources
Interrupt Source
ISR3 ISR2 ISR1 ISR0
Priority
none maskable
maskable
0
0
0
0
no interrupt
no interrupt
none
0
0
0
1
L1 Wake-up from Stop and Sleep Mode
-
highest
0
0
1
0
-
HS Interrupt (Over-temperature)
0
0
1
1
-
Reserved
0
1
0
0
LIN Wake-up
LIN Interrupt (RXSHORT, TXDOM, LIN OT)
0
1
0
1
Voltage Monitor Interrupt
Voltage Monitor Interrupt
(Low Voltage and VDD over-temperature)
(High Voltage)
Forced Wake-up
-
0
1
1
0
lowest
33910
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATION
TYPICAL APPLICATION
The 33910 can be configured in several applications. The figure below shows the 33910 in the typical Slave Node Application.
V
BAT
VS2
VS1
D1
C2
C1
Interrupt
Control Module
LVI, HVI, HTI, OCI
IRQ
C4
Internal Bus
VDD
C3
Voltage Regulator
C5
AGND
5V Output Module
VDD
HVDD
Hall Sensor Supply
Reset
Control Module
LVR, HVR, HTR, WD,
RST
IRQ
RST
TIMER
Window
Watchdog Module
PWMIN
R1
High Side Control
Module
HS2
MISO
MOSI
Chip Temp Sense Module
SCLK
Analog Multiplexer
SPI
&
CONTROL
SPI
CS
MCU
HS1
VSENSE
VBAT Sense Module
R2
L1
Analog Input Module
A/D
ADOUT0
Wake Up Module
Digital Input Module
RXD
LIN Physical Layer
SCI
LIN
LIN
TXD
C6
WDCONF
LGND
AGND
PGND
A/D
R7
Typical Component Values:
C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 220 pF
R1 = 10 kΩ; R2 = 20 kΩ-200 kΩ
Recommended Configuration of the not Connected Pins (NC):
Pin 15, 16, 17, 19, 20, 21, 22 = GND
Pin 11 = open (floating)
Pin 28 = this pin is not internally connected and may be used for PCB routing optimization.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under
Available Documentation column select Packaging Information.
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33910
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACKAGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTATION,
PACKAGE DIMENSIONS (Continued)
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
REVISION HISTORY
REVISION HISTORY
Revision
Date
Description of Changes
1.0
5/2007
•
Initial Release
2.0
9/2007
•
•
•
•
•
Several textual corrections
Page 11: “Analog Output offset Ratio” changed to “Analog Output offset” +/-22mV
Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5
Page 12: Common mode input impedance corrected to 75kΩ
Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release
3.0
9/2007
•
Revision number incremented at engineering request.
4.0
2/2008
•
Changed Functional Block Diagram on page 24.
5.0
11/2008
•
•
•
Datasheet updated according to the Pass1.2 silicon version electrical parameters
Add Maximum Rating on IBUS_NO_GND parameter
Added L1, Temperature Sense Analog Output Voltage per characterization(38), Internal Chip
Temperature Sense Gain per characterization at 3 temperatures(38) See Figure 16, Temperature Sense
Gain, VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(38), and
VSENSE Output Related Offset per characterization(38) parameters
Added Temperature Sense Gain section
Minor corrections to ESD Capability, (20), Cyclic Sense ON Time from Stop and Sleep Mode(47), Lin Bus
Pin (LIN), Serial Data Clock Pin (SCLK), Master Out Slave In Pin (MOSI), Master In Slave Out Pin
(MISO), Digital/analog Pin (L1), Normal Request Mode, Sleep Mode, LIN Over-temperature Shutdown
/ TXD Stuck At Dominant / RXD Short-circuit:, Fault Detection Management Conditions, Lin Physical
Layer, LIN Interface, Over-temperature Shutdown (LIN Interrupt), LIN Receiver Operation Only, SPI
Protocol, L1 - Wake-up input 1, LIN Control Register - LINCR, and RXSHORT - RXD Pin Short-circuit
Updated Freescale form and style
•
•
•
33910
48
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC33910
Rev. 5.0
12/2008
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