LM741QML www.ti.com SNOSAN4A – AUGUST 2005 – REVISED MARCH 2013 LM741QML Operational Amplifier Check for Samples: LM741QML FEATURES DESCRIPTION 1 The amplifier offers many features which make their application nearly foolproof: overload protection on the input and output, no latch-up when the common mode range is exceeded, as well as freedom from oscillations 2 The LM741 is a general purpose operational amplifier which features improved performance over industry standards such as the LM709. They are direct, plugin replacements for the 709C, LM201, MC1439 and 748 in most applications. Connection Diagrams Figure 1. Metal Can Package See Package Number LMC0008C Figure 2. Dual-In-Line Package See Package Number NAB0008A Figure 3. Ceramic Flatpak and SOIC Package See Package Number NAD0010A & NAC0010A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM741QML SNOSAN4A – AUGUST 2005 – REVISED MARCH 2013 www.ti.com Schematic Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM741QML LM741QML www.ti.com SNOSAN4A – AUGUST 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage ±22V Power Dissipation (2) 500 mW Differential Input Voltage ±30V Input Voltage (3) ±15V Output Short Circuit Duration Continuous Operating Temperature Range −55°C ≤ TA ≤ +125°C Storage Temperature Range −65°C ≤ TA ≤ +150°C Junction Temperature (TJ) 150°C Lead Temperature (Soldering, 10 Seconds) Thermal Resistance 300°C θJA Metal Can (Still Air) 167°C/W Metal Can (500LF / Min Air Flow) 100°C/W CERDIP (Still Air) TBD CERDIP (500LF / Min Air Flow) θJC 228°C/W CERPACK (500LF / Min Air Flow) 154°C/W Ceramic SOIC (Still Air) 228°C/W Ceramic SOIC (500LF / Min Air Flow) 154°C/W Metal Can 44°C/W CERDIP CERPACK Ceramic SOIC Package Weight (typical) (2) (3) (4) TBD 27°C/W 27°C/W Metal Can 1000mg CERDIP 1100mg CERPACK 260mg Ceramic SOIC 225mg ESD Tolerance (4) (1) TBD CERPACK (Still Air) 400V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage. Human body model, 1.5 kΩ in series with 100 pF. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM741QML 3 LM741QML SNOSAN4A – AUGUST 2005 – REVISED MARCH 2013 www.ti.com Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp °C 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 Electrical Characteristics DC Parameters The following conditions apply to all the following parameters, unless otherwise specified. DC: VCC = ±15V, VCM = 0V Symbol VIO Parameter Input Offset Voltage Conditions VCM = -12V VCM = 12V +VCC = ± 5V Notes Max Unit -5.0 5.0 mV 1 -6.0 6.0 mV 2, 3 -5.0 5.0 mV 1 -6.0 6.0 mV 2, 3 -5.0 5.0 mV 1 -6.0 6.0 mV 2, 3 -5.0 5.0 mV 1 6.0 mV 2, 3 -6.0 mV 1, 2, 3 mV 1, 2, 3 -6.0 -VIO Adj Offset Null +VIO Adj Offset Null IIO Input Offset Current 6.0 VCM = -12V VCM = 12V VCC = ± 5V ±IIB Input Bias Current VCM = -12V VCM = 12V VCC = ± 5V 4 Submit Documentation Feedback Subgroup Min -200 200 nA 1 -500 500 nA 2, 3 -200 200 nA 1 -500 500 nA 2, 3 -200 200 nA 1 -500 500 nA 2, 3 -200 200 nA 1 -500 500 nA 2, 3 0.0 500 nA 1 0.0 1500 nA 2, 3 0.0 500 nA 1 0.0 1500 nA 2, 3 0.0 500 nA 1 0.0 1500 nA 2, 3 0.0 500 mA 1 0.0 1500 nA 2, 3 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM741QML LM741QML www.ti.com SNOSAN4A – AUGUST 2005 – REVISED MARCH 2013 Electrical Characteristics DC Parameters (continued) The following conditions apply to all the following parameters, unless otherwise specified. DC: VCC = ±15V, VCM = 0V Symbol ICC Parameter Conditions Notes Min Power Supply Current +AVS Open Loop Voltage Gain RL = 2KΩ, VO = 0 to 10V Open Loop Voltage Gain RL = 2KΩ, VO = 0 to −10V Unit Subgroup 2.8 mA 1 2.5 mA 2 3.5 mA 3 See (1) 50 V/mV 1 (1) 25 V/mV 2, 3 See (1) 50 V/mV 1 See (1) 25 V/mV 2, 3 See −AVS Max +PSRR Power Supply Rejection Ratio +VCC = 15V to 5V, -VCC = -15V 77 dB 1, 2, 3 -PSRR Power Supply Rejection Ratio -VCC = -15V to -5V, +VCC = +15V 77 dB 1, 2, 3 CMRR Common Mode Rejection Ratio -12V ≤ VCM ≤ 12V 70 dB 1, 2, 3 +IOS Output Short Circuit Current 1,2 -IOS Output Short Circuit Current +VOpp Output Voltage Swing -VOpp RI Output Voltage Swing -5.0 mA -50 -5.0 mA 3 5.0 45 mA 1,2 5.0 50 mA 3 RL = 10KΩ 12 V 1, 2, 3 RL = 2KΩ 10 V 1, 2, 3 VCC = ± 20V, RL = 10KΩ 16 V 1, 2, 3 VCC = ± 20V, RL = 2KΩ 15 V 1, 2, 3 RL = 10KΩ -12 V 1, 2, 3 RL = 2KΩ -10 V 1, 2, 3 VCC = ± 20V, RL = 10KΩ -16 V 1, 2, 3 VCC = ± 20V, RL = 2KΩ -15 V 1, 2, 3 0.3 MΩ 1 (3) ±12 V 1, 2, 3 ±2.0 V 1, 2, 3 Unit Subgroup See (2) Input Resistance VI Input Voltage Range VCC = ± 15V See VO Output Voltage Swing VCC = ± 5V See (2) (1) (2) (3) -45 Datalog reading in K = V/mV Specified parameter, not tested. Ensured by CMRR, IIB, IIO, VIO Electrical Characteristics AC Parameters The following conditions apply to all the following parameters, unless otherwise specified. AC: VCC = ±15V, VCM = 0V Symbol Parameter Conditions Notes Min Max +SR Slew Rate VI = -5V to 5V, AV = 1, RL = 2KΩ 0.2 V/µS 7 -SR Slew Rate VI = 5V to -5V, AV =1, RL = 2KΩ 0.2 V/µS 7 tR Rise Time RL = 2KΩ, AV = 1, CL = 100pF µS 7 OS Overshoot RL = 2KΩ, AV = 1, CL = 100pF % 7 GBW Gain Bandwidth VI = 50mVRMS, ƒ = 20KHz, RL = 2KΩ KHz - 1.0 30 250 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM741QML 5 LM741QML SNOSAN4A – AUGUST 2005 – REVISED MARCH 2013 www.ti.com Typical Application Figure 4. Offset Nulling Circuit 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM741QML LM741QML www.ti.com SNOSAN4A – AUGUST 2005 – REVISED MARCH 2013 REVISION HISTORY Date Released Revision Section Originator Changes 08/22/05 A New Release to the corporate format L. Lytle 1 MDS datasheet converted into one corporate datasheet format. Since drift is not performed on 883 product, the table was removed. MNLM741-X Rev 1A0 will be archived. 03/26/13 A All - Changed layout of National Data Sheet to TI format. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM741QML 7 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM741 MD8 ACTIVE DIESALE Y 0 400 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM741H/883 ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM741H/883 Q ACO LM741H/883 Q >T LM741J/883 ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM741J /883 Q ACO /883 Q >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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