LTC1289
3 Volt Single Chip 12-Bit
Data Acquisition System
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DESCRIPTIO
FEATURES
■
■
■
■
■
Single Supply 3.3V or ±3.3V Operation
Software Programmable Features
Unipolar/Bipolar Conversions
4 Differential/8 Single-Ended Inputs
Variable Data Word Length
Power Shutdown
Built-In Sample and Hold
Direct 4-Wire Interface to Most MPU Serial Ports
and all MPU Parallel Ports
25kHz Maximum Throughput Rate
The LTC1289 is a 3V data acquisition component which
contains a serial I/O successive approximation A/D converter. The device specifications are guaranteed at a
supply voltage of 2.7V. It uses LTCMOSTM switched capacitor technology to perform a 12-bit unipolar, or 11-bit
plus sign bipolar A/D conversion. The 8 channel input
multiplexer can be configured for either single-ended or
differential inputs (or combinations thereof). An on-chip
sample and hold is included for all single-ended input
channels. When the LTC1289 is idle it can be powered
down in applications where low power consumption is
desired.
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KEY SPECIFICATIO S
■
■
■
■
The serial I/O is designed to be compatible with industry
standard full duplex serial interfaces. It allows either MSBor LSB- first data and automatically provides 2’s complement output coding in the bipolar mode. The output data
word can be programmed for a length of 8, 12 or 16 bits.
This allows easy interface to shift registers and a variety of
processors.
Minimum Guaranteed Supply Voltage ............... 2.7V
Resolution ...................................................... 12 Bits
Fast Conversion Time .............. 26µs Max Over Temp
Low Supply Currents ...................................... 1.0mA
LTCMOS TM is a trademark of Linear Technology Corporation
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TYPICAL APPLICATI
Single Cell 3V 12-Bit Data Acquisition System
+3V
–
CH0
VCC
CH1
ACLK
CH2
SCLK
1/4 LTC1079
CH3
DIN
+
CH4 LTC1289 DOUT
CH5
CS
10Ω
10µF
–3V
FOR OVERVOLTAGE PROTECTION ON
ONLY ONE CHANNEL LIMIT THE INPUT
CURRENT TO 15mA. FOR MORE THAN
ONE CHANNEL LIMIT THE INPUT
CURRENT TO 7mA PER CHANNEL AND
28mA FOR ALL CHANNELS.
CONVERSION RESULTS ARE NOT VALID
WHEN THE SELECTED OR ANY OTHER
CHANNEL IS OVERVOLTAGED (VIN < V –
or VIN > VCC).
CH6
REF+
CH7
REF –
COM
V–
DGND
AGND
+
22µF
TANTALUM
3V
LITHIUM
10k
V+
BOOST
TO AND
FROM
MPU
1N4148
CAP+
+
10µF
GND
CAP –
+
OSC
LTC1044
LV
VOUT
–3V
LT1004-1.2
22µF
+
1N4148
0.1µF
22µF
1N5817
LTC1289 TA01
1
LTC1289
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AXI U
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ABSOLUTE
RATI GS (Notes 1 and 2)
Supply Voltage VCC to GND or V – ........................... 12V
Negative Supply Voltage (V –) .................... – 6V to GND
Voltage
Analog and Reference Inputs (V –) – 0.3V to VCC + 0.3V
Digital Inputs ......................................... – 0.3V to 12V
Digital Outputs............................ – 0.3V to VCC + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1289BI, LTC1289CI ..................... – 40°C TO 85°C
LTC1289BC, LTC1289CC ......................... 0°C to 70°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
CH0
1
20 VCC
CH1
2
19 ACLK
CH2
3
CH3
4
17 DIN
CH4
5
16 DOUT
CH5
6
CH6
7
14 REF+
CH7
8
13 REF –
COM
9
12 V –
18 SCLK
15 CS
DGND 10
J PACKAGE
20-LEAD CERAMIC DIP
ORDER PART
NUMBER
11 AGND
LTC1289BIJ
LTC1289CIJ
LTC1289BIN
LTC1289CIN
LTC1289BCJ
LTC1289CCJ
LTC1289BCN
LTC1289CCN
ORDER PART
NUMBER
TOP VIEW
CH0
1
20 VCC
CH1
2
19 ACLK
CH2
3
18 SCLK
CH3
4
17 DIN
CH4
5
16 DOUT
CH5
6
15 CS
CH6
7
14 REF+
CH7
8
13 REF –
COM
9
12 V –
DGND 10
N PACKAGE
20-LEAD PLASTIC DIP
LTC1289BCS
LTC1289CCS
11 AGND
S PACKAGE
20-LEAD PLASTIC SOL
1289 PO01
LTC1289 PO02
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CO VERTER A D ULTIPLEXER CHARACTERISTICS (Note 3)
PARAMETER
CONDITIONS
Offset Error
VCC = 2.7V
(Note 4)
●
Linearity Error (INL)
VCC = 2.7V
(Notes 4 and 5)
Gain Error
VCC = 2.7V
(Note 4)
Minimum Resolution for
Which No Missing Codes are
Guaranteed
Analog and REF Input Range
(Note 7)
On Channel Leakage Current
(Note 8)
On Channel = 3V
Off Channel = 0V
On Channel = 0V
Off Channel = 3V
Off Channel Leakage Current
(Note 8)
2
On Channel = 3V
Off Channel = 0V
On Channel = 0V
Off Channel = 3V
MIN
LTC1289B
TYP
MAX
LTC1289C
TYP
MAX
UNITS
±1.5
±1.5
LSB
●
±0.5
±0.5
LSB
●
±0.5
±1.0
LSB
●
12
12
BITS
(V –) – 0.05V to VCC + 0.05V
MIN
(V –) – 0.05V to VCC + 0.05V
V
●
±1
±1
µA
●
±1
±1
µA
●
±1
±1
µA
●
±1
±1
µA
LTC1289
AC CHARACTERISTICS (Note 3)
LTC1289B
LTC1289C
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
fSCLK
Shift Clock Frequency
(Note 6)
0
1.0
MHz
fACLK
A/D Clock Frequency
(Note 6)
(Note 10)
2.0
MHz
tACC
Delay time from CS↓ to DOUT Data Valid
(Note 9)
2
ACLK
Cycles
tSMPL
Analog Input Sample Time
See Operating Sequence
7
SCLK
Cycles
tCONV
Conversion Time
See Operating Sequence
52
ACLK
Cycles
tCYC
Total Cycle Time
See Operating Sequence (Note 6)
tdDO
Delay Time, SCLK↓ to DOUT Data Valid
See Test Circuits
●
200
350
ns
tdis
Delay Time, CS↑ to DOUT Hi-Z
See Test Circuits
●
70
150
ns
ten
Delay Time, 2nd ACLK↓ to DOUT Enabled
See Test Circuits
●
130
250
ns
thCS
Hold Time, CS After Last SCLK↓
(Note 6)
0
ns
thDI
Hold Time, DIN After SCLK↑
(Note 6)
50
ns
thDO
Time Output Data Remains Valid After SCLK↓
tf
DOUT Fall Time
See Test Circuits
●
40
100
ns
tr
DOUT Rise Time
See Test Circuits
●
40
100
ns
tsuDI
Setup Time, DIN Stable Before SCLK↑
(Note 6 and 9)
tsuCS
Setup Time, CS↓ Before Clocking in
First Address Bit
(Note 6 and 9)
tWHCS
CS High Time During Conversion
(Note 6)
CIN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
Digital Inputs
12 SCLK +
56 ACLK
UNITS
Cycles
50
50
ns
ns
2 ACLK Cycles
+ 180ns
52
ACLK
Cycles
100
5
5
pF
pF
pF
3
LTC1289
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DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3)
LTC1289B
LTC1289C
MIN
TYP
MAX
SYMBOL
PARAMETER
VIH
High Level Input Voltage
VCC = 3.6V
●
VIL
Low Level Input Voltage
VCC = 3.0V
●
0.45
V
IIH
High Level Input Current
VIN = VCC
●
2.5
µA
IIL
Low Level Input Current
VIN = 0V
●
– 2.5
µA
VOH
High Level Output Voltage
VCC = 3.0V
IO = 20µA
IO = 400µA
●
VCC = 3.0V
IO = 20µA
IO = 400µA
●
●
●
VOL
Low Level Output Voltage
CONDITIONS
2.1
UNITS
V
V
2.7
2.90
2.85
V
0.05
0.10
0.3
High Z Output Leakage
VOUT = VCC, CS High
VOUT = 0V, CS High
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VCC
9
mA
ICC
Positive Supply Current
CS High
CS High, Power Shutdown, ACLK Off
●
●
1.5
1.0
5
10
mA
µA
IREF
Reference Current
VREF = 2.5V
●
10
50
µA
I–
Negative Supply Current
CS High
●
1
50
µA
The ● denotes specifications which apply over the operating temperature
range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impared.
Note 2: All voltage values are with respect to ground with DGND, AGND
and REF –wired together (unless otherwise noted).
Note 3: VCC = 3V, VREF+ = 2.5V, VREF– = 0V, V – = 0V for unipolar mode
and – 3V for bipolar mode, ACLK = 2.0MHz unless otherwise specified.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096.
For example, when VREF = 2.5V, 1LSB(bipolar) = 2(2.5)/4096 = 1.22mV.
V – = – 2.7V for bipolar mode.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Recommended operating conditions.
Note 7: Two on-chip diodes are tied to each analog input which will
conduct for analog voltages one diode drop below GND or one diode drop
above VCC. Be careful during testing at low VCC levels, as high level analog
4
3
–3
µA
µA
IOZ
inputs can cause this input diode to conduct, especially at elevated
temperature, and cause errors for inputs near full scale. This spec allows
50mV forward bias of either diode. This means that as long as the analog
input does not exceed the supply voltage by more than 50mV, the output
code will be correct.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: To minimize errors caused by noise at the chip select input, the
internal circuitry waits for two ACLK falling edges after a chip select falling
edge is detected before responding to control input signals. Therefore, no
attempt should be made to clock an address in or data out until the
minimum chip select set-up time has elasped. See Typical Peformance
Characteristics curves for additional information (tsuCS vs VCC).
Note 10: Increased leakage currents at elevated temperatures cause the
S/H to droop, therefore it's recommended that fACLK ≥ 125kHz at 85°C and
fACLK ≥ 15kHz at 25°C.
LTC1289
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
2.8
0.9
1.9
ACLK = 2MHz
TA = 25°C
ACLK = 2MHz
VCC = 3V
1.8
SUPPLY CURRENT (mA)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.7
1.6
1.5
1.4
1.3
–40 –25 –10
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
5 20 35 50 65
TEMPERATURE (°C)
LTC1289 TPC01
VOS = 0.250mV
0.5
0.4
VOS = 0.125mV
0.3
0.2
80
0.3
VCC = 3V
0.20
0.15
0.10
0.05
0
–0.10
–0.15
0.1
–0.20
0.5
2.5
1.0
1.5
2.0
REFERENCE VOLTAGE (V)
3.0
–0.25
0
0.5
1.5
2.0
2.5
1.0
REFERENCE VOLTAGE (V)
LTC1289 TPC04
0.4
0.3
0.2
0.1
LTC1289 TPC05
Change in Linearity vs
Temperature
LTC1289 • TPC06
Maximum ACLK Frequency vs
Source Resistance
Change in Gain vs Temperature
3
0.5
0.5
MAGNITUDE OF GAIN CHANGE (LSB)
VCC = 3V
VREF = 2.5V
ACLK = 2MHz
0.3
0.2
0.1
0
20
–60 –40 –20 0
40 60 80 100
AMBIENT TEMPERATURE (°C)
LTC1289 TPC07
VCC = 3V
VREF = 2.5V
ACLK = 2MHz
0
20
–60 –40 –20 0
40 60 80 100
AMBIENT TEMPERATURE (°C)
3.0
0.4
VCC = 3V
VREF = 2.5V
ACLK = 2MHz
MAXIMUM ACLK FREQUENCY* (MHz)
0
3.0
Change in Offset vs Temperature
–0.05
0.2
2.5
2.0
1.5
1.0
REFERENCE VOLTAGE (V)
0.5
MAGNITUDE OF OFFSET CHANGE (LSB)
CHANGE IN GAIN (LSB = 1/4096 × VREF)
0.4
0.5
LTC1289 TPC03
0.25
VCC = 3V
0.4
0
Change in Gain vs Reference
Voltage
0.5
0
0
95
LTC 1289 • TPC02
Change in Linearity vs Reference
Voltage
CHANGE IN LINEARITY (LSB = 1/4096 × VREF)
0.7
0.6
0.1
1.0
0.8
MAGNITUDE OF LINEARITY CHANGE (LSB)
VCC = 3V
0.8
OFFSET (LSB = 1/4096 × VREF)
2.6
SUPPLY CURRENT (mA)
Unadjusted Offset Voltage vs
Reference Voltage
Supply Current vs Temperature
0.3
0.2
0.1
0
20
40 60 80 100
–60 –40 –20 0
AMBIENT TEMPERATURE (°C)
LTC1289 TPC08
VCC = 3V
VREF = 2.5V
TA = 25°C
2
VIN
RSOURCE –
+ INPUT
– INPUT
1
0
100
1k
10 k
100k
RSOURCE (Ω)
LTC1289 TPC09
* MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK FREQUENCY AT WHICH A 0.1LSB SHIFT
IN THE ERROR AT ANY CODE TRANSITION FROM ITS 2MHZ VALUE IS FIRST DETECTED.
5
LTC1289
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TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Filter Resistor vs
Cycle Time
100
1k
100
RFILTER
+
VIN
CFILTER ≥ 1µF
10
–
100
1000
VIN
10
RSOURCE+
10000
1.6
+
1k
Input Channel Leakage Current
vs Temperature
Noise Error vs Reference Voltage
8
6
4
200
400
600
800
ACLK FREQUENCY (kHZ)
1.0
900
LTC1289 NOISE = 200µVp-p
GUARANTEED
PEAK-TO-PEAK NOISE ERROR (LSB)
INPUT CHANNEL LEAKAGE CURRENT (nA)
10
800
700
600
500
400
300
200
ON CHANNEL
OFF CHANNEL
100
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE (°C)
1000
100
LTC1289 TPC12
1000
12
0.6
LTC1289 TPC11
Supply Current (Power Shutdown)
vs ACLK
14
0.8
0
–60 –40 –20 0 20 40 60 80
AMBIENT TEMPERATURE (°C)
10k
LTC1289 TPC10
VCC = 3V
CMOS LOGIC SWINGS
1.0
0.2
CYCLE TIME (µs)
16
1.4
1.2
0.4
RSOURCE+ (Ω)
18
ACLK OFF DURING
POWER SHUTDOWN
1.8
–
1
100
1
10
2.0
VREF = 2.5V
VCC = 3V
TA = 25°C
0V TO 2.5V INPUT STEP
SUPPLY CURRENT (µA)
S & H AQUISITION TIME TO 0.02% (µs)
MAXIMUM RFILTER** (Ω)
10k
SUPPLY CURRENT (µA)
Supply Current (Power Shutdown)
vs Temperature
Sample and Hold Acquisition
Time vs Source Resistance
LTC1289 • TPC14
LTC1298 TPC13
0.8
0.6
0.4
0.2
0
0
0.5
1.5
2.0
2.5
1.0
REFERENCE VOLTAGE (V)
3.0
LTC1289 • TPC15
Power Consumption with Power
Shutdown vs fSAMPLE
tsuCS vs Supply Voltage
10000
300
VCC = 3V
VREF = 2.5V
ACLK = 2MHz
CMOS LOGIC SWINGS
THREE CONVERSIONS/CYCLE
TA = 25°C
250
1000
ICC (µA)
2ACLK + ns
200
150
100
100
10
50
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
LTC1289 TPC16
6
1
1
10
100
1000
10000
fSAMPLE (Hz)
LTC1289 TPC17
** MAXIMUM RFILTER REPRESENTS THE FILTER
RESISTOR VALUE AT WHICH A 0.1LSB CHANGE
IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER
= 0 IS FIRST DETECTED.
LTC1289
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#
PIN
FUNCTION
DESCRIPTION
1–8
9
CH0 – CH7
COM
Analog Inputs
Common
10
11
12
13,14
15
16
17
18
19
20
DGND
AGND
V–
REF –, REF +
CS
DOUT
DIN
SCLK
ACLK
VCC
Digital Ground
Analog Ground
Negative Supply
Reference Inputs
Chip Select Input
Digital Data Output
Digital Input
Shift Clock
A/D Conversion Clock
Positive Supply
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single-ended inputs. It must be free of noise and
is usually tied to the analog ground plane.
This is the ground for the internal logic. Tie to the ground plane.
AGND should be tied directly to the analog ground plane.
Tie V – to the most negative potential in the circuit. (Ground in single supply applications.)
The reference inputs must be kept free of noise with respect to AGND.
A logic low on this input enables data transfer.
The A/D conversion result is shifted out of this output.
The A/D configuration word is shifted into this input.
This clock synchronizes the serial data transfer.
This clock controls the A/D conversion process.
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
BLOCK DIAGRAM
VCC
DIN
18
20
INPUT
SHIFT
REGISTER
17
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
OUTPUT
SHIFT
REGISTER
16
SCLK
DOUT
1
SAMPLE
AND
HOLD
2
3
COMP
4
5
ANALOG
INPUT MUX
12-BIT
SAR
6
12-BIT
CAPACITIVE
DAC
7
8
9
19
10
11
DGND
AGND
12
V–
13
REF –
14
REF+
CONTROL
AND
TIMING
15
ACLK
CS
LTC1289 BD
7
LTC1289
TEST CIRCUITS
On and Off Channel Leakage Current
Voltage Waveforms for DOUT Delay Time, tdDO
3V
ION
A
SCLK
ON CHANNEL
0.45V
tdDO
IOFF
A
2.1V
DOUT
OFF
CHANNELS
0.6V
LTC1289 TC03
POLARITY
LTC1283 TC01
Load Circuit for tdDO, tr and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr,tf
1.5V
2.1V
DOUT
3k
DOUT
0.6V
TEST POINT
tr
tf
100pF
LTC1289 TC04
LTC1289 TC02
Load Circuit for tdis and ten
TEST POINT
3V tdis WAVEFORM 2, ten
3k
DOUT
tdis WAVEFORM 1
100pF
LTC1289 TC05
Voltage Waveforms for ten and tdis
1
2
ACLK
2.1V
CS
DOUT
WAVEFORM 1
(SEE NOTE 1)
2.1V
ten
DOUT
WAVEFORM 2
(SEE NOTE 2)
90%
tdis
0.6V
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH CONDITIONS SUCH THAT THE OUTPUT IS HIGH
UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT
IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1289 TC06
8
LTC1289
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APPLICATI
S I FOR ATIO
The LTC1289 is a data acquisition component which
contains the following functional blocks:
previous conversion is output on the DOUT line. At the end
of the data exchange the requested conversion begins and
CS should be brought high. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion is
delayed by one CS cycle from the input word requesting it.
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample and hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIN
DIN WORD 1
DOUT
DOUT WORD 0
DIGITAL CONSIDERATIONS
DATA
TRANSFER
DIN WORD 2
DIN WORD 3
DOUT WORD 1
tCONV
A/D
CONVERSION
DOUT WORD 2
tCONV
A/D
CONVERSION
DATA
TRANSFER
Serial Interface
LTC1289 AI01
The LTC1289 communicates with microprocessors and
other external circuitry via a synchronous, full duplex, four
wire serial interface (see Operating Sequence). The shift
clock (SCLK) synchronizes the data transfer with each bit
being transmitted on the falling SCLK edge and captured
on the rising SCLK edge in both transmitting and receiving
systems. The data is transmitted and received simultaneously (full duplex).
Input Data Word
The LTC1289 8-bit data word is clocked into the DIN input
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the DIN pin are then ignored
until the next CS cycle. The eight bits of the input word are
defined as follows:
UNIPOLAR/
BIPOLAR
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the DIN input which configures the LTC1289 for
the next conversion. Simultaneously, the result of the
SGL/
DIFF
ODD/
SIGN
SELECT
1
SELECT
0
UNI
WORD
LENGTH
MSBF
WL1
MSB-FIRST/
LSB-FIRST
MUX ADDRESS
WL0
LTC1289 AI02
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
tCYC
1
2
3
4
5
6
7
8
9
SCLK
10
11
12
DON'T CARE
tSMPL
tCONV
CS
DIN
DON'T CARE
B11 B10 B9
DOUT
SHIFT CONFIGURATION
WORD IN
(SB)
B8
B7 B6
B5
B4
B3
B2
B1
B0
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
LTC1289 AI03
9
LTC1289
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APPLICATI
S I FOR ATIO
MUX Address
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs
in the selected row of Table 1. Note that in differential
mode (SGL/DIFF = 0) measurements are limited to four
adjacent input pairs with either polarity. In single-ended
mode, all input channels are measured with respect to
COM.
Table 1. Multiplexer Channel Selection
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
DIFFERENTIAL CHANNEL SELECTION
0
1
+
–
2
3
+
–
4
+
5
6
–
+
–
0,1
{
2,3
{
4,5
{
6,7
{
–
+
–
+
–
+
–
4 Differential
CHANNEL
7
+
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
8 Single-Ended
CHANNEL
0
1
2
3
4
5
6
7
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
SINGLE-ENDED CHANNEL SELECTION
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
Combinations of Differential and Single-Ended
CHANNEL
+
+
+
+
+
+
+
+
0,1
{
+
–
2,3
{
–
+
+
+
+
+
4
5
6
7
COM (–)
COM (–)
Changing the MUX Assignment “On the Fly”
4,5
{
6,7
{
+
–
+
–
COM (UNUSED)
1ST CONVERSION
5,4
{
–
+
6
7
{
+
+
COM (–)
2ND CONVERSION
LTC1289 AIF01
Figure 1. Examples of Multiplexer Options on the LTC1289
10
COM
–
–
–
–
–
–
–
–
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Unipolar/Bipolar (UNI)
The fifth input bit (UNI) determines whether the conversion will be unipolar or bipolar. When UNI is a logical one,
a unipolar conversion will be performed on the selected
input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for
each conversion type are shown in the figures below.
Unipolar Transfer Curve (UNI = 1)
Unipolar Output Code (UNI = 1)
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 2.5V)
111111111111
OUTPUT CODE
111111111111
111111111110
•
•
•
000000000001
000000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
2.4994V
2.4988V
•
•
•
0.0006V
0V
•
•
•
111111111110
000000000001
000000000000
VREF
VREF – 1LSB
VREF – 2LSB
1LSB
0V
LTC1289 AI04a
VIN
LTC1289 AI04b
Bipolar Output Code (UNI = 0)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 2.5V)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 2.5V)
011111111111
011111111110
•
•
•
000000000001
000000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
2.4988V
2.4976V
•
•
•
0.0012V
0V
111111111111
111111111110
•
•
•
100000000001
100000000000
–1LSB
–2LSB
•
•
•
–(VREF) + 1LSB
– (VREF)
–0.0012V
–0.0024V
•
•
•
–2.4988V
–2.5000V
LTC1289 AI05a
Bipolar Transfer Curve (UNI = 0)
011111111111
011111111110
1LSB
–VREF + 1LSB
–VREF
•
•
•
000000000001
000000000000
VIN
100000000001
VREF
–1LSB
–2LSB
•
•
•
VREF – 1LSB
111111111110
VREF – 2LSB
111111111111
LTC1289 AI05b
100000000000
11
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The following discussion will demonstrate how the two
reference pins are to be used in conjunction with the
analog input multiplexer. In unipolar mode the input span
of the A/D is set by the difference in voltage on the REF+ pin
and the REF – pin. In the bipolar mode the input span is
twice the difference in voltage on the REF+ pin and the
REF– pin. In the unipolar mode the lower value of the input
span is set by the voltage on the COM pin for single-ended
inputs and by the voltage on the minus input pin for
differential inputs. For the bipolar mode of operation the
voltage on the COM pin or the minus input pin sets the
center of the input span.
The upper and lower value of the input span can now be
summarized in the following table:
INPUT
CONFIGURATION
Single-Ended
Differential
UNIPOLAR MODE
Example 3 (Diff.): IN – – 2V ≤ IN+ ≤ IN– + 2V.
MSB-First/LSB-First Format (MSBF)
The output data of the LTC1289 is programmed for MSBfirst or LSB-first sequence using the MSBF bit. For MSBfirst output data, the input word clocked to the LTC1289
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data the input
word clocked to the LTC1289 should always contain a zero
in the MSBF bit location. The MSBF bit affects only the
order of the output data word. The order of the input word
is unaffected by this bit.
–
BIPOLAR MODE
Lower Value IN
Upper Value (REF + – REF – ) + IN –
+
–
–(REF – REF ) + IN
(REF + – REF – ) + IN –
–
The following examples are for a single-ended input configuration.
Example 1: Let VCC = 3.3V, V – = 0V, REF + = 3V, REF – = 1V
and COM = 0V. Unipolar mode of operation. The resulting
input span is 0V ≤ IN + ≤ 2V.
Example 2: The same conditions as Example 1 except
COM = 1V. The resulting input span is 1V ≤ IN+ ≤ 3V. Note
if IN+ ≥ 3V the resulting DOUT word is all 1’s. If IN+ ≤ 1V then
the resulting DOUT word is all 0’s.
Example 3: Let VCC = 3.3V, V – = –3.3V, REF+ = 3V, REF –
= 1V and COM = 1V. Bipolar mode of operation. The
resulting input span is –1V ≤ IN+ ≤ 3V.
For differential input configurations with the same conditions as in the above three examples the resulting input
spans are as follows:
Example 1 (Diff.): IN – ≤ IN + ≤ IN – + 2V
OUTPUT FORMAT
LSB-First
MSB-First
MSBF
0
1
Lower Value COM
–(REF + – REF – ) + COM
Upper Value (REF + – REF – ) + COM (REF+ – REF – ) + COM
The reference voltages REF + and REF – can fall between
VCC and V –, but the difference (REF +– REF –) must be less
than or equal to VCC. The input voltages must be less than
or equal to VCC and greater than or equal to V –.
12
Example 2 (Diff.): IN – ≤ IN+ ≤ IN – + 2V
LTC1289 AI06
Word Length (WL1, WL0) and Power Shutdown
The last two bits of the input word (WL1 and WL0)
program the output data word length and the power
shutdown feature of the LTC1289. Word lengths of 8, 12
or 16 bits can be selected according to the following table.
WL1
0
0
1
1
WL0
0
1
0
1
OUTPUT WORD LENGTH
8 Bits
Power Shutdown
12 Bits
16 Bits
LTC1289 AI07
The WL1 and WL0 bits in a given DIN word control the
length of the present, not the next, DOUT word. WL1 and
WL0 are never “don’t cares” and must be set for the
correct DOUT word length even when a “dummy” DIN word
is sent. On any transfer cycle, the word length should be
made equal to the number of SCLK cycles sent by the
MPU. Power down will occur when WL1 = 0 and WL0 = 1
is selected. The previous result will be clocked out as a 10
bit word so a “dummy”conversion is required before
powering down the LTC1289. Conversions are resumed
once CS goes low or an SCLK is applied, if CS is already
low.
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8-Bit Word Length
tSMPL
tCONV
CS
SCLK
1
DOUT
MSB-FIRST
B11
B10
B9
B8
B7
B6
B5
B4
B1
B2
B3
B4
B5
B6
B7
THE LAST FOUR BITS
ARE TRUNCATED
(SB)
DOUT
LSB-FIRST
B0
12-Bit Word Length
tSMPL
tCONV
CS
10
1
SCLK
12
(SB)
DOUT
MSB-FIRST
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(SB)
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
16-Bit Word Length
tSMPL
tCONV
CS
SCLK
1
12
16
(SB)
DOUT
MSB-FIRST
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B0
FILL
ZEROS
(SB)
B11
*
* IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROS.
IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS.
*
*
LTC1289 AIF02
Figure 2. Data Output (DOUT) Timing with Different Word Lengths
13
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Deglitcher
CS Low During Conversion
A deglitching circuit has been added to the Chip Select
input of the LTC1289 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
one ACLK cycle. After a change of state on the CS input, the
LTC1289 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1289 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
DOUT line will become active with the first output bit. Then
the data transfer can begin as normal.
Low CS Recognized Internally
High CS Recognized Internally
ACLK
ACLK
CS
CS
Hi-Z
DOUT
DOUT
VALID OUTPUT
Hi-Z
VALID OUTPUT
LTC1289 AI08
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
LTC1289 AI08a
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK
DIN
DOUT
DON'T CARE
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1289 AIF03
Figure 3. CS High During Conversion
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK MUST
REMAIN LOW
SCLK
DIN
DOUT
DON'T CARE
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1289 AIF04
Figure 4. CS Low During Conversion
14
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Logic Levels
The logic level standards for this supply range have not been
well defined. What standards that do exist are not universally
accepted. The trip point on the logic inputs of the LTC1289 is
0.28 × VCC. This makes the logic inputs compatible with HC
type logic levels and processors that are specified at 3.3V.
The output DOUT is also compatible with the above standards. The following summarizes such levels.
VOH (no load)
VOL (no load)
VOH
VOL
VIH
VIL
VCC - 0.1V
0.1V
0.9 × VCC
0.1 × VCC
0.7 × VCC
0.2 × VCC
The LTC1289 can share 3-wire serial interface with other
peripheral components or other LTC1289s (See Figure 5).
In this case, the CS signals decide which LTC1289 is being
addressed by the MPU.
1. Grounding
The LTC1289 should be used with an analog ground plane
and single point grounding techniques.
Microprocessor Interfaces
The LTC1289 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats. If an MPU without a serial interface is
used, then four of the MPU’s parallel port lines can be
programmed to form the serial link to the LTC1289. Many
of the popular MPU's can operate with 3V supplies. For
example the MC68HC11 is an MPU with a serial format
(SPI). Likewise parallel MPU’s that have the 8051 type
architecture are also capable of operating at this voltage
1
Sharing the Serial Interface
ANALOG CONSIDERATIONS
The LTC1289 can be driven with 5V logic even when VCC
is at 3.3V. This is due to a unique input protection device
that is found on the LTC1289.
2
range. The code for these processors remains the same
and can be found in the LTC1290 datasheet or application
notes AN36A and AN36B.
Pin 11 (AGND) should be tied directly to this ground plane.
Pin 10 (DGND) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
Pin 20 (VCC) should be bypassed to the ground plane with a
22µF tantalum with leads as short as possible. Pin 12 (V –)
should be bypassed with a 0.1µF ceramic disk. For single
supply applications, V – can be tied to the ground plane.
It is also recommended that pin 13 (REF –) and pin 9 (COM)
be tied directly to the ground plane. All analog inputs should
be referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
0
OUTPUT PORT
SERIAL DATA
MPU
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1289s
3
3
3
3
CS
LTC1289
CS
LTC1289
CS
LTC1289
8 CHANNELS
8 CHANNELS
8 CHANNELS
LTC1289 AIF05
Figure 5. Several LTC1289s Sharing One 3-Wire Serial Interface
15
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Figure 6 shows an example of an ideal ground plane design
for a two-sided board. Of course, this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
tor. The noise and ripple is approximately 0.5mV. Figure 8b
shows the response of a lithium battery with a 10µF bypass
capacitor. The noise and ripple is kept below 0.5mV.
For good performance, VCC must be free of noise and ripple.
Any changes in the VCC voltage with respect to analog
ground during a conversion cycle can induce errors or
noise in the output code. VCC noise and ripple can be kept
below 0.5mV by bypassing the VCC pin directly to the analog
ground plane with a 22µF tantalum capacitor and leads as
short as possible. The lead from the device to the VCC
supply should also be kept to a minimum and the VCC
supply should have a low output impedance such as that
obtained from a voltage regulator (e.g., LT1117). Using a
battery to power the LTC1289 will help reduce the amount
of bypass capacitance required on the VCC pin. A battery
placed close to the device will only require 10µF to adequately bypass the supply pin. Figure 7 shows the effect of
poor VCC bypassing. Figure 8a shows the settling of a
LT1117 low dropout regulator with a 22µF bypass capaci-
VERTICAL: 0.5mV/DIV
2. Bypassing
HORIZONTAL: 10µs/DIV
Figure 7. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors.
5V/DIV
CS
VCC
VCC
0.5mV/DIV
0.1µF
22µF
TANTALUM
HORIZONTAL: 20µs/DIV
ANALOG
GROUND
PLANE
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
Figure 8a. LT1117 Regulator with 22µF Bypassing on VCC
5V/DIV
CS
V–
0.5mV/DIV
0.1µF
CERAMIC
DISK
VCC
LTC1289 AIF06
HORIZONTAL: 20µs/DIV
Figure 6. Example Ground Plane for the LTC1289
16
Figure 8b. Lithium Battery with 10µF Bypassing on VCC
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3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1289 have
capacitive switching input current spikes. These current
spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling
op amps drive the inputs, care must be taken to insure that
the transients caused by the current spikes settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1289 look like a 100pF
capacitor (CIN) is series with a 1500Ω resistor (RON) as
shown in Figure 9. This value for RON is for VCC = 2.7V.
With larger supply voltages RON will be reduced. For
example with VCC = 2.7V and V –= – 2.7V RON becomes
500Ω. CIN gets switched between the selected “+” and “–
” inputs once during each conversion cycle. Large external
source resistors and capacitances will slow the settling of
“+”
INPUT
RSOURCE +
LTC1289
VIN +
RSOURCE –
C1
4TH SCLK
RON = 1.5k
“–”
INPUT
LAST SCLK
CIN =
100pF
VIN –
C2
LTC1289 AIF09
Figure 9. Analog Input Equivalent Circuit
SAMPLE
MUX ADDRESS
SHIFTED IN
ACLK
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 10). The sample
phase starts at the 4th SCLK cycle and lasts until the falling
edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
depending on the selected word length). The voltage on
the “+” input must settle completely within this sample
time. Minimizing RSOURCE+ and C1 will improve the input
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 4µs, RSOURCE+ < 2k
and C1 < 20pF will provide adequate settling.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
RSOURCE– and C2 will improve settling time. If large “–”
input source resistance must be used, the time allowed for
HOLD
•••
CS
SCLK
“+” INPUT
MUST SETTLE
DURING THIS TIME
tSMPL
the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to
completely settle within the allotted time.
1
2
3
4
LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)
•••
•••
1
2
3
4
•••
1ST BIT TEST
“–” INPUT MUST SETTLE
DURING THIS TIME
“+” INPUT
“–” INPUT
1289 AIF10
Figure 10. “+” and “–” Input Settling Windows
17
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settling can be extended by using a slower ACLK frequency. At the maximum ACLK rate of 2MHz, RSOURCE– <
200Ω and C2 < 20pF will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommodate slower op amps. For single supply low voltage
applications the LT1006, LT1013 and LT1014 can be
made to settle well even with the minimum settling windows of 4µs (“+” input) and 2µs (“–” input) which occur
at the maximum clock rates (ACLK = 2MHz and SCLK =
1MHz). Figures 11 and 12 show examples of adequate and
poor op amp settling. The LT1077, LT1078 or LT1079 can
be used here to reduce power consumption. Placing an RC
network at the output of the op amps will improve the
settling response and also reduce the broadband noise.
rapidly (see typical curve of Input Channel Leakage Current vs Temperature).
Noise Coupling Into Inputs
High source resistance input signals (>500Ω) are more
sensitive to coupling from external sources. It is preferable to use channels near the center of the package (i.e.,
CH2-CH7) for signals which have the highest output
resistance because they are essentially shielded by the
VERTICAL: 5mV/DIV
APPLICATI
RC Input Filtering
Figure 11. Adequate Settling of Op Amps Driving Analog Input
VERTICAL: 5mV/DIV
It is possible to filter the inputs with an RC network as
shown in Figure 13. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 100pF × VIN /tCYC and is roughly
proportional to VIN. When running at the minimum cycle
time of 40µs, the input current equals 6.3µA at VIN = 2.5V.
In this case, a filter resistor of 10Ω will cause 0.1LSB of
full-scale error. If a larger filter resistor must be used,
errors can be eliminated by increasing the cycle time as
shown in the typical curve of Maximum Filter Resistor vs
Cycle Time.
HORIZONTAL: 500ns/DIV
HORIZONTAL: 20µs/DIV
Figure 12. Poor Op Amp Settling Can Cause A/D Errors
Input Leakage Current
RFILTER
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1µA (at 85°C) flowing through a
source resistance of 1kΩ will cause a voltage drop of 1mV
or 1.6LSB with VREF = 2.5V. This error will be much
reduced at lower temperatures because leakage drops
18
IIDC
“+”
VIN
CFILTER
LTC1289
“–”
LTC1289 AIF13
Figure 13. RC Input Filtering
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pins on the package ends (DGND and CH0). Grounding
any unused inputs (especially the end pin, CH0) will also
reduce outside coupling into high source resistances.
a 60Hz signal on the “–” input to generate a 1/4LSB error
(150µV) with the converter running at ACLK = 2MHz, its
peak value would have to be 15mV.
4. Sample and Hold
5. Reference Inputs
Single-Ended Inputs
The voltage between the reference inputs of the LTC1289
defines the voltage span of the A/D converter. The reference inputs will have transient capacitive switching currents due to the switched capacitor conversion technique
(see Figure 14). During each bit test of the conversion
(every 4 ACLK cycles), a capacitive current spike will be
generated on the reference pins by the A/D. These current
spikes settle quickly and do not cause a problem. However, if slow settling circuitry is used to drive the reference
inputs, care must be taken to insure that transients caused
by these current spikes settle completely during each bit
test of the conversion.
The LTC1289 provides a built-in sample and hold (S&H)
function for all signals acquired in the single-ended mode
(COM pin grounded). This sample and hold allows the
LTC1289 to convert rapidly varying signals (see typical
curve of S&H Acquisition Time vs Source Resistance). The
input voltage is sampled during the tSMPL time as shown
in Figure 10. The sampling interval begins after the fourth
MUX address bit is shifted in and continues during the
remainder of the data transfer. On the falling edge of the
final SCLK, the S&H goes into hold mode and the conversion begins. The voltage will be held on either the 8th, 12th
or 16th falling edge of the SCLK depending on the word
length selected.
Differential Inputs
With differential inputs or when the COM pin is not tied to
ground, the A/D no longer converts just a single voltage
but rather the difference between two voltages. In these
cases, the voltage on the selected “+” input is still sampled
and held and therefore may be rapidly time varing just as
in single ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise
and ripple throughout the conversion time. Otherwise, the
differencing operation may not be performed accurately.
The conversion time is 52 ACLK cycles. Therefore, a
change in the “–” input voltage during this interval can
cause conversion errors. For a sinusoidal voltage on the
“–” input this error would be:
VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 52
fACLK
When driving the reference inputs, two things should be
kept in mind:
1. Transients on the reference inputs caused by the
capacitive switching currents must settle completely
during each bit test (each 4 ACLK cycles). Figures 15
and 16 show examples of both adequate and poor
settling. Using a slower ACLK will allow more time for
the reference to settle. However, even at the maximum
ACLK rate of 2MHz most references and op amps can
be made to settle within the 2µs bit time. For example
an LT1019 used in the shunt mode with a 10µF bypass
capacitor will settle adequately. To minimize power an
LT1004-2.5 can be used with a 10µF bypass capacitor.
For lower value references the LT1004-1.2 with a 1µF
bypass capacitor can be used.
REF+
14
ROUT
VREF
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fACLK is the frequency of
the ACLK. In most cases VERROR will not be significant. For
REF –
13
LTC1289
EVERY 4 ACLK CYCLES
RON
8pF – 40pF
LTC1289 AIF14
Figure 14. Reference Input Equivalent Circuit
19
LTC1289
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APPLICATI
S I FOR ATIO
VERTICAL: 0.5mV/DIV
Offset with Reduced VREF
HORIZONTAL: 1µs/DIV
Figure 15. Adequate Reference Settling
The offset of the LTC1289 has a larger effect on the output
code when the A/D is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB is
reduced. The typical curve of Unadjusted Offset Error vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example, a
VOS of 0.1mV which is 0.2LSB with a 2.5V reference
becomes 0.4LSB with a 1.25V reference. If this offset is
unacceptable, it can be corrected digitally by the receiving
system or by offsetting the “–” input to the LTC1289.
Noise with Reduced VREF
VERTICAL: 0.5mV/DIV
The total input referred noise of the LTC1289 can be reduced
to approximately 200µV peak-to-peak using a ground plane,
good bypassing, good layout techniques and minimizing
noise on the reference inputs. This noise is insignificant with
a 2.5V reference but will become a larger fraction of an LSB
as the size of the LSB is reduced. The typical curve of Noise
Error vs Reference Voltage shows the LSB contribution of
this 200µV of noise.
HORIZONTAL: 1µs/DIV
Figure 16. Poor Reference Settling Can Cause A/D Errors
2. It is recommended that REF– input be tied directly to
the analog ground plane. If REF– is biased at a voltage
other than ground, the voltage must not change during
a conversion cycle. This voltage must also be free of
noise and ripple with respect to analog ground.
6. Reduced Reference Operation
The effective resolution of the LTC1289 can be increased by
reducing the input span of the converter. The LTC1289
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Linearity and Gain
Error vs Reference Voltage). However, care must be taken
when operating at low values of VREF because of the reduced
LSB step size and the resulting higher accuracy requirement
placed on the converter. The following factors must be
considered when operating at low VREF values:
1. Offset
2. Noise
20
For operation with a 2.5 reference, the 200µV noise is only
0.32LSB peak-to-peak. In this case, the LTC1289 noise will
contribute virtually no uncertainty to the output code. However, for reduced references, the noise may become a
significant fraction of an LSB and cause undesirable jitter in
the output code. For example, with a 1.25V reference, this
same 200µV noise is 0.64LSB peak-to-peak. This will reduce the range of input voltages over which a stable output
code can be achieved by 0.64LSB. In this case averaging
readings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, VREF, VIN or V –) will
add to the internal noise. The lower the reference voltage to
be used, the more critical it becomes to have a clean, noisefree setup.
LTC1289
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APPLICATI
S I FOR ATIO
7. LTC1289 AC Characteristics
Two commonly used figures of merit for specifying the
dynamic performance of the A/D’s in digital signal processing applications are the Signal-to-Noise Ratio (SNR)
and the “effective number of bits (ENOB).” SNR is defined
as the ratio of the RMS magnitude of the fundamental to
the RMS magnitude of all the nonfundamental signals up
to the Nyquist frequency (half the sampling frequency).
The theoretical maximum SNR for a sine wave input is
given by:
SNR = (6.02N + 1.76dB)
where N is the number of bits. Thus the SNR is a function
of the resolution of the A/D. For an ideal 12-bit A/D the SNR
is equal to 74dB. A Fast Fourier Transform(FFT) plot of the
output spectrum of the LTC1289 is shown in Figures 17a
and 17b. The input (fIN) frequencies are 1kHz and 12kHz
with the sampling frequency (fS) at 25kHz. The SNR
obtained from the plot are 72.92dB and 72.23dB.
Rewriting the SNR expression it is possible to obtain the
equivalent resolution based on the SNR measurement.
N = SNR – 1.76dB
6.02
This is the so-called effective number of bits (ENOB). For
the example shown in Figures 17a and 17b, N = 11.8 bits
and 11.7 bits, respectively. Figure 18 shows a plot of ENOB
as a function of input frequency. The curve shows the A/
D’s ENOB remain in the range of 11.8 to 11.7 for input
frequencies up to fS/2
12
0
FS = 25kHz
EFFECTIVE NUMBER OF BITS
–20
MAGNITUDE (dB)
–40
–60
–80
–100
11
10
9
8
7
–120
6
–140
0
2
4
8
6
10
FREQUENCY (kHz)
12
0
14
10
20
30
FREQUENCY (kHz)
LTC1289 • AIF18
LTC1289 F17a
Figure 18. LTC1289 ENOB vs Input Frequency
0
0
–20
–20
–40
–40
MAGNITUDE (dB)
MAGNITUDE (dB)
Figure 17a. fIN = 1kHz, fS = 25kHz, SNR = 72.92dB
–60
–80
50
40
–60
–80
–100
–100
–120
–120
–140
–140
0
2
4
8
6
10
FREQUENCY (kHz)
12
14
LTC1289 F17b
Figure 17b. fIN = 12kHz, fS = 25kHz, SNR = 72.23dB
0
2
4
8
6
10
FREQUENCY (kHz)
12
14
LTC1289 F19
Figure 19. fIN1 = 2.6kHz, fIN2 = 3.1kHz, fS = 25kHz
21
LTC1289
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APPLICATI
S I FOR ATIO
Figure 19 shows an FFT plot of the output spectrum for two
tones applied to the input of the A/D. Nonlinearities in the
A/D will cause distortion products at the sum and difference frequencies of the fundamentals and products of the
fundamentals. This is classically referred to as
intermodulation distortion (IMD).
8. Overvoltage Protection
Applying signals to the analog MUX that exceed the
positive or negative supply of the device will degrade the
accuracy of the A/D and possibly damage the device. For
example this condition would occur if a signal is applied to
the analog MUX before power is applied to the LTC1289.
Another example is the input source is operating from
different supplies of larger value than the LTC1289. These
conditions should be prevented either with proper supply
sequencing or by use of external circuitry to clamp or
current limit the input source. As shown in Figure 20, a
1kΩ resistor is enough to stand off ±15V (15mA for one
only channel). If more than one channel exceeds the
supplies than the following guidelines can be used. Limit
the current to 7mA per channel and 28mA for all channels.
This means four channels can handle 7mA of input current
each. Reducing the ACLK and SCLK frequencies from the
maximum of 2MHz and 1MHz, respectively (see Typical
Peformance Characteristics curves Maximum ACLK Frequency vs Source Resistance and Sample and Hold Acquisition Time vs Source Resistance) allows the use of larger
current limiting resistors. Use 1N4148 diode clamps from
the MUX inputs to VCC and V – if the value of the series
resistor will not allow the maximum clock speeds to be
used or if an unknown source is used to drive the LTC1289
MUX inputs.
How the various power supplies to the LTC1289 are
applied can also lead to overvoltage conditions. For single
supply operation (i.e., unipolar mode), if VCC and REF + are
not tied together, then VCC should be turned on first, then
REF +. If this sequence cannot be met, connecting a diode
from REF + to VCC is recommended (see Figure 21).
For dual supplies (bipolar mode) placing two Schottky
diodes from VCC and V – to ground (Figure 22) will prevent
power supply reversal from occuring when an input source
22
is applied to the analog MUX before power is applied to the
device. Power supply reversal occurs, for example, if the
input is pulled below V – then VCC will pull a diode drop
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above VCC then
V – will be pulled a diode drop above ground. If no inputs
are present on the MUX, the Schottky diodes are not
required if V – is applied first, then VCC.
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
VIN
1k
3.3V
VCC
CH0
22µF
LTC1289
V–
DGND
–3.3V
0.1µF
AGND
LTC1289 AIF20
Figure 20. Overvoltage Protection for MUX
VCC
20
3.3V
22µF
LTC1289
1N4148
REF+
14
VREF
LTC1289 AIF21
Figure 21.
3.3V
VCC
1N5817
22µF
1N5817
0.1µF
LTC1289
V–
DGND
AGND
–3.3V
LTC1289 AIF22
Figure 22. Power Supply Reversal
LTC1289
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TYPICAL APPLICATI
S
A “Quick Look” Circuit for the LTC1289
Users can get a quick look at the function and timing of the
LTC1289 by using the following simple circuit. REF + and
DIN are tied to VCC selecting a 3V input span, CH7 as a
single-ended input, unipolar mode, MSB-first format and
16-bit word length. ACLK is driven by an external clock and
SCLK is driven by one half the clock rate. CS is driven at
1/128 the clock rate by the 74HC393 and DOUT outputs the
data. All other pins are tied to a ground plane. The output
data from the DOUT pin can be viewed on an oscilloscope
which is set up to trigger on the falling edge of CS.
A “Quick Look” Circuit for the LTC1289
3.0V
22µF
f
A1
CLR1
CHO
VCC
CH1
ACLK
CH2
SCLK
CH3
DIN
CH4
DOUT
CH5
1QB 74HC393 2QA
f/2
1QC
2QB
1QD
2QC
GND
2QD
CS
CH6
REF +
CH7
REF –
COM
V–
f/128
LTC1289 TA02
CLOCK IN
2MHz MAX
AGND
DGND
0.1µF
A2
CLR2
{
VIN
LTC1289
1QA
VCC
TO
OSCILLOSCOPE
Scope Trace of LTC1289 “Quick Look” Circuit
Showing A/D Output of 010101010101 (555HEX)
ACLK
SCLK
CS
DOUT
DEGLITCHER
TIME
MSB
(B11)
LSB
(B0)
FILLS
ZEROES
VERTICAL: 5V/DIV
HORIZONTAL: 2µs/DIV
23
LTC1289
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TYPICAL APPLICATI
S
SNEAK-A-BITTM
The LTC1289’s unique ability to software select the polarity of the differential inputs and the output word length is
used to achieve one more bit of resolution. Using the
circuit below with two conversions and some software, a
2’s complement 12-bit + sign word is returned to memory
inside the MPU. The MC68HC05C4 was chosen as an
example, however, any processor that operates at 3.3V
could be used.
Two 12-bit unipolar conversions are performed: the first
over a 0V to 2.5V span and the second over a 0V to –2.5V
span (by reversing the polarity of the inputs). The sign of
the input is determined by which of the two spans contained it. Then the resulting number (ranging from –4095
to +4095 decimal) is converted to 2’s complement notation and stored in RAM.
SNEAK-A-BIT Circuit
22µF
OTHER CHANNELS
OR SNEAK-A-BIT
INPUTS
2MHz
ACLK
CHO
VCC
CH1
ACLK
CH2
SCLK
CH3
DIN
MOSI
DOUT
MISO
CH4
CH5
VIN
–2.5V TO +2.5V
+3.3V
LTC1289
1k
MC68HC05C4
SCLK
CO
CS
CH6
REF +
CH7
REF –
COM
V–
10µF
LT1019
–2.5
AGND
DGND
LTC1289 TA03
0.1µF
–3.3V
SNEAK-A-BIT
VIN
2.5V
VIN
2.5V
(+) CH6
1ST CONVERSION
4096 STEPS
(–) CH7
1ST CONVERSION
0V
0V
(–) CH6
SOFTWARE
0V
8191 STEPS
2ND CONVERSION
4096 STEPS
(+) CH7
–2.5V
–2.5V
2ND CONVERSION
LTC1289 TA04
SNEAK-A-BIT is a trademark of Linear Technology Corp.
24
LTC1289
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TYPICAL APPLICATI
S
SNEAK-A-BIT Code
SNEAK-A-BIT Code for the LTC1289 Using the MC68HC05C4
MNEMONIC
DOUT from LTC1289 in MC68HC05C4 RAM
READ +/–:
Sign
Location $77B12B11B10B9B8B7B6B5
LSB
Location $87B4B3B2B1B0filled with 0s
DIN words for LTC1289
MUX Addr.
MSBF
UNI
(ODD/SIGN)
Word
Length
DIN100111111
DIN201111111
DIN300111111
LTC1289 TA05
SNEAK-A-BIT Code for the LTC1289 Using the MC68HC05C4
MNEMONIC
LDA
STA
LDA
STA
BSET
JSR
#$50
$0A
#$FF
$06
0, $02
READ –/+
JSR READ +/–
JSR READ –/+
JSR CHK SIGN
READ – / + : LDA
JSR
LDA
STA
LDA
STA
RTS
#$3F
TRANSFER
$60
$71
$61
$72
DESCRIPTION
Configuration data for SPCR
Load configuration data into $0A
Configuration data for port C DDR
Load configuration data into port C DDR
Make sure CS is high
Dummy read configures LTC1289 for
next read
Read CH6 with respect to CH7
Read CH7 with respect to CH6
Determines which reading has valid
data, converts to 2's complement and
stores in RAM
Load DIN word for LTC1289 into ACC
Read LTC1289 routine
Load MSBs from LTC1289 in ACC
Store MSBs in $71
Load LSBs from LTC1289 in ACC
Store LSBs in $72
Return
LDA
JSR
LDA
STA
LDA
STA
RTS
TRANSFER: BCLR
STA
LOOP 1:
TST
BPL
LDA
STA
STA
LOOP 2:
TST
BPL
BSET
LDA
STA
RTS
CHK SIGN: LDA
ORA
BEQ
CLC
ROR
ROR
LDA
STA
LDA
STA
BRA
MINUS:
CLC
ROR
ROR
COM
COM
LDA
ADD
STA
CLRA
ADC
STA
STA
LDA
STA
END:
RTS
#$7F
TRANSFER
$60
$73
$61
$74
0, $02
$0C
$0B
LOOP 1
$0C
$0C
$60
$0B
LOOP 2
0, $02
$0C
$61
$73
$74
MINUS
$73
$74
$73
$77
$74
$87
END
$71
$72
$71
$72
$72
#$01
$72
$71
$71
$77
$72
$87
DESCRIPTION
Load DIN word for LTC1289 into ACC
Read LTC1289 routine
Load MSBs from LTC1289 into ACC
Store MSBs in $73
Load LSBs from LTC1289 into ACC
Store LSBs in $74
Return
CS goes low
Load DIN into SPI. Start transfer
Test status of SPIF
Loop to previous instruction if not done
Load contents of SPI data reg into ACC
Start next cycle
Store MSBs in $60
Test status of SPIF
Loop to previous instruction if not done
CS goes high
Load contents of SPI data reg into ACC
Store LSBs in $61
Return
Load MSBs of +/– read into ACC
Or ACC (MSBs) with LSBs of +/– read
If result is 0 goto minus
Clear carry
Rotate right $73 through carry
Rotate right $74 through carry
Load MSBs of +/– read into ACC
Store MSBs in RAM locations $77
Load LSBs of +/– read into ACC
Store LSBs in RAM location $87
Goto end of routine
Clear carry
Shift MSBs of –/+ read right
Shift LSBs of –/+ read right
1's complement of MSBs
1's complement of LSBs
Load LSBs into ACC
Add 1 to LSBs
Store ACC in $72
Clear ACC
Add with carry to MSBs. Result in ACC
Store ACC in $71
Store MSBs in RAM locations $77
Load LSBs in ACC
Store LSBs in RAM location $87
Return
25
LTC1289
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TYPICAL APPLICATI
S
Power Shutdown
For battery-powered applications it is desirable to keep
power dissipation at a minimum. The LTC1289 can be
powered down when not in use reducing the supply
current from a nominal value of 1mA to typically 1µA (with
ACLK turned off). See the Curve for Supply Current (Power
Shutdown) vs ACLK if ACLK cannot be turned off when the
LTC1289 is powered down. In this case the supply current
is proportional to the ACLK frequency and is independent
of temperature until it reaches the magnitude of the supply
current attained with ACLK turned off.
As an example of how to use this feature let’s add this to
the previous application, SNEAK-A-BIT. After the CHK
SIGN subroutine call insert the following:
JSR CHK SIGN
JSR SHUTDOWN
•
•
Determines which reading has valid
data, converts to 2’s complement
and stores in RAM
LTC1289 power shutdown routine
The actual subroutine is:
To place the device in power shutdown the word length
bits are set to WL1 = 0 and WL0 = 1. The LTC1289 is
powered up on the next request for conversion and it's
ready to digitize an input signal immediately.
Power Shutdown Timing Considerations
After power shutdown has been requested, the LTC1289
is powered up on the next request for a conversion. This
request can be initiated either by bringing CS low or by
starting the next cycle of SCLKs if CS is kept low (see
Figures 3 and 4). When the SCLK frequency is much
slower than the ACLK frequency a situation can arise
where the LTC1289 could power down and then prematurely power back up. Power shutdown begins at the
negative going edge of the 10th SCLK once it has been
requested. A dummy conversion is executed and the
LTC1289 waits for the next request for conversion. If the
SCLKs have not finished once the LTC1289 has finished its
dummy conversion, it will recognize the next remaining
SCLKs as a request to start a conversion and power up the
LTC1289 (see Figure 23). To prevent this, bring either CS
high at the 19th SCLK (Figure 24) or clock out only 10
SCLKs (Figure 25) when power shutdown is requested.
SHUTDOWN: LDA #$3D
Load DIN word for
LTC1289 into ACC
JSR TRANSFER Read LTC1289 routine
RTS
Return
CS
1
10
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
POWER UP
LTC1289 TAF23
Figure 23. Power Shutdown Timing Problem
CS
POWER UP
1
10
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
Figure 24. Power Shutdown Timing
26
LTC1289 TAF24
LTC1289
UO
TYPICAL APPLICATI
S
CS
POWER UP
1
10
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
LTC1289 TAF2
Figure 25. Power Shutdown Timing
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J Package
20-Lead Ceramic DIP
0.160
(4.064)
MAX
0.290 – 0.320
(7.366 – 8.128)
0.200
(5.080)
MAX
1.060
(26.924)
MAX
20
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.457)
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
10
0.220 – 0.310 0.025
(5.588 – 7.874) (0.635)
RAD TYP
0° – 15°
0.125
(3.175)
MIN
0.385 ± 0.025
(9.779 ± 0.635)
19
1
0.038 – 0.068
(0.965 – 1.727)
0.080
(2.032)
MAX
0.100 ± 0.010
(2.540 ± 0.254)
0.005
(0.127)
MIN
0.014 – 0.026
(0.356 – 0.660)
J20 0392
TJMAX
θJA
150°C
80°C/W
N Package
20-Lead Plastic DIP
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.025
0.325 –0.015
+0.635
8.255
–0.381
)
0.130 ± 0.005
(3.302 ± 0.127)
1.040
(26.416)
MAX
0.045 – 0.065
(1.143 – 1.651)
0.015
(0.381)
MIN
0.065
(1.651)
0.125
(3.175)
MIN
0.065 ± 0.015
(1.651 ± 0.381)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
0.260 ± 0.010
(6.604 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N20 0392
TJMAX
θJA
110°C
100°C/W
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
27
LTC1289
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S Package
20-Lead Plastic SOL
0.496 – 0.512
(12.598 – 13.005)
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029 × 45°
(0.254 – 0.737)
20
19
18
17
16
15
14
13
12
11
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
SEE NOTE
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.394 – 0.419
(10.007 – 10.643)
SEE NOTE
0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
1
2
3
4
5
6
7
8
9
10
SOL20 0392
28
Linear Technology Corporation
TJMAX
θJA
110°C
150°C/W
LT/GP 0392 10K REV 0
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1992