TI BQ24703RHDR Multichemistry battery charger controller and system power selector Datasheet

 SLUS553D − MAY 2003 − REVISED JULY 2005
FEATURES
D Dynamic Power Management, DPM
6
19
7
18
8
17
9
16
10
15
11
14
12
13
ACSET
VREF
ENABLE
BATSET
COMP
3
4
5
6
7
ACPRES
27
9
ACP
ACDET
26
10
NC
ACDRV
25
11
NC
BATDRV
24
12
BATP
NC
23
13
IBAT
VCC
22
14
NC
NC − No internal connection
SRN
20
ACN
15
5
8
16
21
28
SRP
4
ACSEL
17
22
GND
3
ACDRV
BATDRV
VCC
PWM
VHSP
ALARM
VS
GND
SRP
SRN
IBAT
BATP
18
23
VS
24
2
19
1
ALARM
ACDET
ACPRES
ACSEL
BATDEP
SRSET
ACSET
VREF
ENABLE
BATSET
COMP
ACN
ACP
bq24703
RHD PACKAGE
(BOTTOM VIEW)
SRSET
bq24702, bq24703
PW PACKAGE
(TOP VIEW)
2
D
20
D
VHSP
D
The bq24702/bq24703 uses a fixed frequency, pulse
width modulator (PWM) to accurately control battery
charge current and voltage. Charge current limits can
be programmed from a keyboard controller DAC or by
external resistor dividers from the precision 5-V, ±0.6%,
externally bypassed voltage reference (VREF),
supplied by the bq24702/bq24703.
BATDEP
D
D
The bq24702/bq24703 uses dynamic power
management (DPM) to minimize battery charge time by
maximizing use of available wall-adapter power. This is
achieved by dynamically adjusting the battery charge
current based on the total system (adapter) current.
1
D
The bq24702/bq24703 is a highly integrated battery
charge controller and selector tailored for notebook and
sub-notebook PC applications.
Minimizes Battery Charge Time
Integrated Selector Supports Battery
Conditioning and Smart Battery Learn Cycle
Zero Volt Operation
Selector Feedback Circuit Ensures
Break-Before-Make Transition
±0.4% Charge Voltage Accuracy, Suitable for
Charging Li-Ion Cells
±4% Charge Current Accuracy
300-kHz Integrated PWM Controller for
High-Efficiency Buck Regulation
Depleted Battery Detection and Indication to
Protect Battery From Over Discharge
20-µA Sleep Mode Current for Low Battery
Drain
24-Pin TSSOP Package and 5 mm × 5 mm
QFN package (bq24703 only)
21
D
D
DESCRIPTION
PWM
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$ % &'!!($ #% )'*&#$ +#$(,
!+'&$% &!" $ %)(&&#$% )(! $-( $(!"% (.#% %$!'"($%
%$#+#!+ /#!!#$0, !+'&$ )!&(%%1 +(% $ (&(%%#!*0 &*'+(
$(%$1 #** )#!#"($(!%,
Copyright  2003 − 2004, Texas Instruments Incorporated
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1
SLUS553D − MAY 2003 − REVISED JULY 2005
DESCRIPTION (continued)
The battery voltage limit can be programmed by using the internal 1.196-V, ±0.5% precision reference, making it
suitable for the critical charging demands of lithium-ion cells. Also, the bq24702/bq24703 provides an option to
override the precision reference and drive the error amplifier either directly from an external reference or from a
resistor divider off the 5 V supplied by the integrated circuit.
The selector function allows the manual selection of the system power source, battery or wall-adapter power. The
bq24702/bq24703 supports battery-conditioning and battery-learn cycles through the ACSEL function. The ACSEL
function allows manual selection of the battery or wall power as the main system power. It also provides autonomous
switching to the remaining source (battery or ac power) should the selected system power source terminate (refer
to Table 1 for the differences between the bq24702 and the bq24703). The bq24702/bq24703 also provides an alarm
function to indicate a depleted battery condition.
The bq24702/bq24703 PWM controller is ideally suited for operation in a buck converter for applications when the
wall-adapter voltage is greater than the battery voltage.
DISSIPATION RATINGS
MAXIMUM POWER DISSIPATION
(LOW K BOARD)
vs
FREE-AIR TEMPERATURE
1.60
Maximum Power Dissipation (Low K Board) − W
Maximum Power Dissipation (High K Board) − W
MAXIMUM POWER DISSIPATION
(HIGH K BOARD)
vs
FREE-AIR TEMPERATURE
MAX Pd (W) @ 500 LFM
1.40
MAX Pd (W) @ 250 LFM
1.20
MAX Pd (W) @ 150 LFM
MAX Pd (W) @ 0 LFM
1
0.80
0.60
0.40
θJA = 89.37 C/W @ 0 LFM,
θJA = 77.98 C/W @ 150 LFM,
θJA = 73.93 C/W @ 250 LFM,
θJA = 68.23 C/W @ 500 LFM
0.20
1.40
1.20
MAX Pd (W) @ 500 LFM
MAX Pd (W) @ 250 LFM
1
MAX Pd (W) @ 150 LFM
MAX Pd (W) @ 0 LFM
0.80
0.60
0.40
θJA = 150.17 C/W @ 0 LFM,
θJA = 110.95 C/W @ 150 LFM,
θJA = 99.81 C/W @ 250 LFM,
θJA = 86.03 C/W @ 500 LFM
0.20
0
0
25
50
70
TA − Free-Air Temperature − °C
85
25
50
70
85
TA − Free-Air Temperature − °C
† The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch, two layer board with 2 ounce copper traces on top of the board.
‡ The JEDEC high K (1s) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1 ounce internal power and ground
planes and 2 ounce copper traces on top and bottom of the board.
2
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SLUS553D − MAY 2003 − REVISED JULY 2005
Table 1. Available Options
CONDITION
−20°C ≤ TJ ≤ 125°C
SELECTOR OPERATION
bq24702PW
bq24703RHD
Battery as Power Source
Battery removal
Automatically selects ac + alarm
Automatically selects ac + alarm
Battery reinserted
Selection based on selector inputs
Adapter latched until adapter is removed or ac select
toggles.
AC removal
Automatically selects battery
Automatically selects battery
AC reinserted
Selection based on selector inputs
Selection based on selector inputs
Battery as power source
Sends ALARM signal
Automatically selects ac
Sends ALARM signal
AC as power source
Sends ALARM signal
Sends ALARM signal
Depleted battery condition
Depleted battery condition
AC as Power Source
Depleted Battery Condition
ALARM Signal Active
When selector input is not equal to selector
output (single pulse alarm)
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE
(unless otherwise noted)Ĕ}
Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Battery voltage range: SRP, SRN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Input voltage: ACN, ACP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Maximum source/sink current VHSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Maximum ramp rate for VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V/ µs
Maximum sink current ACPRES, COMP, ALARM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 mA
Maximum ramp rate for V(BAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V/ µs
Maximum source/sink current BATDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Maximum source/sink current ACDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Maximum source/sink current PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Maximum source/sink current pulsed ACDRV, (10-µs rise time, 10-µs fall time, 1-ms pulse width, single pulse) 50 mA
Maximum source current VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Maximum source current SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Maximum difference voltage SRP − SRN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals. Consult the Packaging section of
the data book for thermal limitations and considerations of the package.
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3
SLUS553D − MAY 2003 − REVISED JULY 2005
RECOMMENDED OPERATING CONDITIONS
(TA = TOPR) all voltages relative to Vss
MIN
MAX
Analog and PWM operation
7.0
28
Selector operation
4.5
28
Negative ac current sense, (ACN)
7.0
28
V
Positive ac current sense, (ACP)
7.0
28
V
Negative battery current sense, (SRN)
5
28
V
Positive battery current sense, (SRP)
5
28
V
AC or adapter power detection (ACDET)
0
5
V
AC power indicator (ACPRES)
0
5
V
AC adapter power select (ACSEL)
0
5
V
Depleted battery level (BATDEP)
0
5
V
Battery charge current programming voltage (SRSET)
0
2.5
V
Charge enable (ENABLE)
0
5
V
External override to an internal 0.5% precision reference (BATSET)
0
2.5
V
Inverting input to the PWM comparator (COMP)
0
5
V
Battery charge regulation voltage measurement input to the battery—voltage gm amplifier (BATP)
0
5
V
Battery current differential amplifier output (IBAT)
0
5
V
System load voltage input pin (VS)
0
2.5
V
Depleted battery alarm output (ALARM)
0
5
V
VHSP
VCC
V
Supply voltage, (VCC)
Gate drive output (PWM)
Battery power source select output (BATDRV)
AC or adapter power source selection output (ACDRV)
ACSET
Operating free-air temperature, TA
4
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UNIT
V
0
28
V
VHSP
VCC
V
0
2.5
V
−40
85
°C
SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 125°C, 7.0 VDC ≤ VCC ≤ 28 VDC, all voltages relative to Vss) (unless otherwise specified)
Quiescent Current
PARAMETER
IDD(OP)
IDD(SLEEP)
TEST CONDITIONS
Total chip operating current
ACPRES = High, EN = 0
Total battery sleep current, ac not present
ACPRES = Low
MIN
TYP
MAX
UNIT
1
1.6
6
mA
22
28
µA
logic interface dc characteristics
PARAMETER
VOL
VIL
Low-level output voltage (ACPRES, ALARM)
VIH
I(SINK1)
High-level input voltage (ACSEL, ENABLE)
I(SINK2)
Sink current (ALARM)
TEST CONDITIONS
MIN
TYP
IOL = 1 mA
Low-level input voltage (ACSEL, ENABLE)
Sink current (ACPRES)
MAX
0.4
V
0.6
V
1.8
VOL = 0.4
VOL = 0.4
UNIT
V
1.5
2
2.5
mA
1.5
2
2.5
mA
PWM Oscillator
PARAMETER
fOSC(PWM)
Oscillator frequency
MIN
TYP
MAX
0°C ≤ TJ ≤ 85°C
TEST CONDITIONS
260
300
340
−40°C ≤ TJ ≤ 125°C
240
300
350
Maximum duty cycle
3.8
V
Minimum duty cycle
0%
Input voltage for minimum dc (COMP)
Oscillator ramp voltage (peak-to-peak)
VIK(COMP)
Internal input clamp voltage
(tracks COMP voltage for maximum dc)
IS(COMP)
Internal source current (COMP)
kHz
100%
Input voltage for maximum dc (COMP)
V(RAMP)
UNIT
0.8
1.85
Error amplifier = OFF, V(COMP) = 1 V
2.15
2.30
3.8
4.5
70
110
140
µA
MIN
TYP
MAX
UNIT
V
Leakage Current
PARAMETER
TEST CONDITIONS
V(ACDET) = 5 V
V(SRSET) = 2.5 V
0.2
µA
0.2
µA
V(ACSET) = 2.5 V
V(BATDEP) = 5 V
0.2
µA
0.2
µA
V(VS) = 5 V
V(ALARM) = 5 V
0.2
µA
0.2
µA
V(ACSEL) = 5 V
V(ENABLE) = 5 V
0.2
µA
0.2
µA
V(ACPRES) = 5 V
V(BATP) = 5 V
0.2
µA
Leakage current, BATP
0.2
µA
Leakage current, BATSET
V(BATSET) = 2.5 V
0.2
µA
IL(ACDET)
IL(SRSET)
Leakage current, ACDET
IL(ACSET)
IL(BATDEP)
Leakage current, ACSET
IL(VS)
IL(ALARM)
Leakage current, VS
IL(ACSEL)
IL(ENABLE)
Leakage current, ACSEL
IL(ACPRES)
IL(BATP)
Leakage current, ACPRES
IL(BATSET)
Leakage current, SRSET
Leakage current, BATDEP
Leakage current, ALARM
Leakage current, ENABLE
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5
SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ TJ ≤ 125°C, 7.0 VDC ≤ VCC ≤ 28 VDC, all voltages relative to Vss) (unless otherwise specified)
Battery Current-Sense Amplifier
PARAMETER
gm
CMRR
TEST CONDITIONS
Transconductance gain
MIN
TYP
MAX
UNIT
75
120
175
mA/V
Common-mode rejection ratio
See Note 1
VICR
Common-mode input (SRP, SRN)
voltage range
VCC = SRN, SRP + 2 V
I(SINK)
Sink current (COMP)
COMP = 1 V,
(SRP − SRN) = 10 mV
0.5
Input bias current (SRP), See Note 2
V(SRP) = 16 V,
(SRP − SRN) = 100 mV
SRSET = 2.5 V,
VCC = 28
Input bias current accuracy
(ISRP − ISRN)
(SRP − SRN) = 100 mV, SRSET= 2.5 V,
VCC = 28 V, 0 ≤ TJ ≤ 125°C
IIB
V(SET)
Battery current programming voltage
(SRSET)
AV
Battery current set gain
90
5
30
V
1.5
2.5
mA
70
85
110
−3
0
3
µA
A
0
0.65 V ≤ SRSET ≤ 2.5 V, 8 V ≤ SRN ≤ 16 V,
See Note 3
dB
24
25
2.5
V
26
V/V
Total battery current-sense mid-scale
accuracy
SRSET = 1.25 V, TJ = 25°C, See Note 4
−5%
5%
SRSET = 1.25 V, See Note 4
−6%
6%
Total battery current-sense full-scale
accuracy
SRSET = 2.5 V, TJ = 25°C, See Note 4
−3%
3%
SRSET = 2.5 V, See Note 4
−4%
4%
NOTES: 1. Specified by design. Not production tested.
2 I(SRP) = I(SRN) = (V(SRSET) / 50 kΩ) + ((V(SRP) − V(SRN) / 3 kΩ)
example: If (V(SRSET) = 2.5 V) , (V(SRP) − V(SRN) = 100 mV) Then I(SRP) = I(SRN) = 83 µA
1
3. I
+ SRSET
BAT
A
R
V
SENSE
4. Total battery-current set is based on the measured value of (SRP−SRN) = ∆m, and the calculated value of (SRP−SRN) = ∆C, using
(Dm * Dc)
the measured gain, AV. Dc + SRSET , Total accuracy in % +
100, I (SRP) * I (SRN) + 0
Dc
A
V
6
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SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ TJ ≤ 125°C, 7.0 VDC ≤ VCC ≤ 28 VDC, all voltages relative to Vss) (unless otherwise specified)
Adapter Current-Sense Amplifier
PARAMETER
TEST CONDITIONS
gm
CMRR
Transconductance gain
VICR
I(SINK)
Common-mode input voltage range (ACP)
IIB
Common-mode rejection ratio
MIN
TYP
MAX
UNIT
75
130
175
mA/V
See Note 1
90
dB
Sink current (COMP)
COMP = 1 V, (ACP − ACN) = 10 mV
7.0
0.5
1.5
VCC
2.5
Input bias current (ACP, ACN)
ACP = ACN = 28 V,
VCC = 28 V, ACSET = 2.5 V
40
50
65
Input bias current accuracy ratio
(I(ACP), I(ACN))
ACP = ACN = 28 V, VCC = 28 V,
ACSET = 2.5 V, 0 ≤ TJ ≤ 125°C
−3
0
3
A
µA
V(SET)
AC current programming voltage (ACSET)
AV
AC current set gain
0.65 V ≤ ACSET ≤ 2.5 V, 12 V ≤ ACP ≤ 20 V,
See Note 5
ACSET = 1.25 V, TJ = 25°C, See Note 6
ACSET = 1.25 V, See Note 6
−5%
Total ac current-sense mid-scale accuracy
−6%
6%
ACSET = 2.5 V, TJ = 25°C, See Note 6
−3.5%
3.5%
−4%
4%
Total ac current-sense full-scale accuracy
0
ACSET = 2.5 V, See Note 6
V
mA
24.5
25.3
2.5
V
26.5
V/V
5%
Battery Voltage Error Amplifier
PARAMETER
TEST CONDITIONS
gm
CMRR
Transconductance gain
VICR
VIT
BATSET common-mode input voltage range
I(SINK)
Sink current COMP
V(FB)
NOTE:
Common-mode rejection ratio
MIN
TYP
MAX
UNIT
75
135
175
mA/V
See Note 1
Internal reference override input threshold voltage
dB
2.5
V
0.20
0.25
0.35
V
0.5
1.5
2.5
mA
TJ = 25°C
TJ = 0°C to 85°C
1.190
1.196
1.202
1.183
1.196
1.203
TJ = −40°C to 125°C
1.178
1.196
1.204
COMP = 1 V,
(BATP − BATSET) = 10 mV,
BATSET = 1.25 V
Error-amplifier precision reference voltage
90
1
V
1
+ ACSET
R
A
V
SENSE
6. Total ac-current set accuracy is based on the measured value of (ACP−ACN) = ∆c, using the measured gain, AV.
(Dm * Dc)
Dc + ACSET , Total accuracy in % +
100, I (ACP) * I (ACN) + 0
Dc
A
V
5. Calculation of the ac current: I
AC
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7
SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ TJ ≤ 125°C, 7.0 VDC ≤ VCC ≤ 28 VDC, all voltages relative to Vss) (unless otherwise specified)
Battery Current Output Amplifier
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
G(TR)
Transfer gain
(SRP − SRN) = 5 mV, See Note 7
20
V/V
VI(BAT)
Battery current readback output
voltage (IBAT)
(SRP − SRN) = 5 mV, SRP = 12 V,
VCC = 18 V,
TJ = 25°C
100
mV
Line rejection voltage
TJ = 25°C
10
mV/V
CM
Common-mode input range (SRP)
5
28
V
VO(IBAT)
Battery current output voltage range
(IBAT)
0
2.5
V
IS(O)
Output source current (IBAT)
9.4
mA
(SRP − SRN) = 100 mV
5
(SRP − SRN) = 50 mV, TJ = 25°C, See Note 7
Total battery current readback
full-scale accuracy
7.1
−3%
2.4%
(SRP − SRN) = 50 mV, 0°C ≤ TJ ≤ 85°C
−20%
20%
(SRP − SRN) = 100 mV, TJ = 25°C, See Note 7
−1.5%
1.2%
−6%
8.5%
(SRP − SRN) = 100 mV, 0°C < TJ < 85°C
5-V Voltage Reference
PARAMETER
Vref
Output voltage (VREF)
Line regulation
Load regulation
TEST CONDITIONS
MIN
TYP
MAX
TJ = 25°C
TJ = 0°C to 85°C
4.985
5
5.013
4.946
5
5.013
TJ = 40°C to 85°C
TJ = −40°C to 125°C
4.946
5
5.03
5
5.03
V
0.1
0.37
mV/V
4.926
ILOAD = 5 mA
1 mA ≤ ILOAD ≤ 5 mA
Output capacitor equivalent resistor
ESR
V
4
mV/mA
20
30
mA
2.2
10
µF
5
1000
mΩ
8
Capacitance
V
1.1
Short circuit current
5V REF output capacitor
UNIT
Half Supply Regulator
PARAMETER
V(HSP)
NOTE:
8
TEST CONDITIONS
I(SINK) = 20 mA, VCC = 18 V
I(SINK) = 1 mA, VCC = 7 V
V
IBAT
7. Battery readback transfer gain G
+
TR
(SRP * SRN)
Voltage regulation
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MIN
VCC − 11
TYP
VCC − 10.2
MAX
VCC − 8.5
1.5
UNIT
V
SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ TJ ≤ 125°C, 7.0 VDC ≤ VCC ≤ 28 VDC, all voltages relative to Vss) (unless otherwise specified)
MOSFET Gate Drive
PARAMETER
AC driver RDS(on) high
AC driver RDS(on) low
TEST CONDITIONS
MIN
TYP
VCC = 18 V, I(ACDRV) = 1 mA
VCC = 18 V, I(ACDRV) = 1 mA
MAX
UNIT
85
150
Ω
55
110
Ω
VCC = 18 V, I(BATDRV) = 1 mA
VCC = 18 V, I(BATDRV) = 1 mA
315
600
Ω
Battery driver RDS(on) low
70
115
Ω
tda
Time delay from ac driver off to battery
driver on
ACSEL 2.4 V ⇓ 0.2 V
1.2
2
µs
tdb
Time delay from battery driver off to ac
driver on
ACSEL 0.2 V ⇑ 2.4 V
2.4
3.3
µs
VOH
PWM driver high-level output voltage
IO = −10 mA, VCC = 18 V
IO = −50 mA, VCC = 18 V
Battery driver RDS(on) high
VCC −0.18
VCC −1.2
VCC −0.09
VCC −0.8
7
14
Ω
VHSP+0.1
VHSP+0.6
VHSP+0.4
VHSP+1.2
V
5
8.5
Ω
UNIT
PWM driver RDS(on) high
VOL
PWM driver low-level output voltage
IO = 10 mA, VCC = 18 V
IO = 50 mA, VCC = 18 V
V
PWM driver RDS(on) low
Selector
PARAMETER
V(ACPRES)
AC presence detect voltage
VIT(ACPRES)
td(ACPRES)
AC presence hysteresis
TEST CONDITIONS
−40°C to 85°C
MIN
TYP
MAX
1.194
1.246
1.286
1.208
1.246
1.285
V
1%
Deglitch delay for adapter insertion
µs
100
See Note 8
1.194
1.246
1.286
−40°C to 85°C
1.208
1.246
1.285
bq24702 only, See Note 8
0.869
1
1.144
−40°C to 85°C
0.880
1
1.118
1
2.5
3.5
µs
µs
V(BATDEP)
Battery depletion ALARM trip voltage
V(NOBAT)
No battery detect, switch to ACDRV
t(BATSEL)
Battery select time (ACSEL low to BATDRV low)
VS < BATP, 50% threshold,
ACSEL 2.4 V ⇓ 0.2 V
t(ACSEL)
V(VS)
AC select time (ACSEL high to ACDRV low)
ACSEL 0.2 V ⇑ 2.4 V
1
2.5
3.5
VS voltage to enable BATDRV
BATP = 1 V
0.98
1
1.02
VIT(VS)
VS voltage hysteresis
VS > BATP
20
35
85
MIN
TYP
MAX
VCC = 7 V, TJ = 125°C, IO = 100 mA
BATDEP increasing
5.3
8.7
0.743
0.794
0.840
BATDEP decreasing
0.570
0.62
0.656
V
V
V
mV
Zero Volt Operation
PARAMETER
rDS(on)
Static drain source on-state resistance
zero volt operation threshold
TEST CONDITIONS
UNIT
Ω
V
NOTES: 8. Total battery current readback accuracy is based on the measured value of VIBAT, VIBATm, and the calculated value of VIBAT,
VIBATc, using the measured value of the transfer gain, GTR.
V
*V
IBATc 100
V
+ (SRP * SRN) GTR Total Accuracy in % + IBATm
IBATc
V
IBATm
9. Refer to Table 1 to determine the logic operation of the bq24702 and the bq24703.
www.ti.com
9
10
www.ti.com
R10
Note1
Note 1: R8 Sets AC Adapter Current Limit
R10 Sets Charge Current
R12 Sets AC ADAPTER Current Limit
R23 Sets the Battery Depleted Threshold
R25 Sets the Charge Regulation Voltage
R28 Sets System Break Before Make
R19 = R21, Sets Zero Volt Charge Current
C11 Optional, See Application Notes
C12 For Value, See Application Notes
C8 Value Depends on R21 and R19, See Application Notes
D5, D6 Refer to the Application Section
17 GND
6 ACSET
BATP 13
VS 18
BATDRV 23
9 BATSET
BATSET
5 SRSET
2 ACPRES
ACPRES
PROCESSOR’S
POWER SUPPLY
COMP 10
SRN 15
4
8 ENABLE
BATDEP
7 VREF
14 IBAT
SRP 16
19 ALARM
bq24702
bq24703
R2100 kΩ
PWM 21
1 ACDET
C10
180pF
C7
4.7 µF
35 V
C5
4.7 µF
U3
SI4435DY
Connect to GND
to Disable
C4
150pF
R16
100 Ω
C6
D3 13 V
1 µF
16V
VHSP 20
VCC 22
12 ACP
11 ACN
24 ACDRV
D2
BAS16
ALARM
R8
Note1
R18
10 Ω
R29 30 kΩ
C12
Note1
35V
R15
100 Ω
U2
SI4435DY
3 ACSEL
C1
4.7 µ F
C3
1 µF
R13
100 Ω
R14
0.025
ACSEL
ENABLE
C13
1 nF
R12
Note1
R11
R6
100 kΩ Open
IBAT
AC Adapter
D1
MBRD640CTT4
R28
Note1
D5
Note 1
R19
Note1
D4
MBRD640CTT4
L1
33 µH
BAS16
R23
Note1
604 kΩ
R27
R25
Note1
R24
604 kΩ
C11 22 µ F
Note1
35 V
R22
604 kΩ
R26 100K
D9
D6
Note 1
C8
Note1
R21
Note1
R20
0.025 Ω
U4
SI4435DY
Battery Plus
SYSTEM
SLUS553D − MAY 2003 − REVISED JULY 2005
APPLICATION DIAGRAM
SLUS553D − MAY 2003 − REVISED JULY 2005
BLOCK DIAGRAM
VHSP
VCC
VREF
20
22
7
VREF
ACPRES
VHSP
REGULATOR
2
VOLTAGE
REFERENCE
ACPRES
ACPRES
HYST
ACDET
1
+
VCC
300 kHz
S
Q
R
Q
2V
VACPRES
OSC
PWM
LOGIC
HIGH−SIDE
DRIVE
LEVEL
SHIFT
21
PWM
13
BATP
+
VHSP
ACSEL
3
ENABLE
8
5V
100 µ A
BATDA
BATTERY
VOLTAGE
ERROR
AMPLIFIER
COMP
+
Zero Volt
Charging
VTBD
5V
10
ACP
12
ACN
11
ACSET
6
9
VCC
2kΩ
+
+
+
BATSET
0.25 V
VFB
ac
CURRENT
ERROR
AMPLIFIER
+
SRN
2 kΩ
+
BATTERY
CURRENT
ERROR
AMPLIFIER
25
kΩ
0.8 x VNOBAT
VBATDEP
BATDEP
4
DEPLETED
BATTERY
COMPARATOR
BATP
VS
ALARM
18
19
15
SRN
5
SRSET
24
ACDRV
23
BATDRV
17
GND
14
IBAT
VCC
+
25
kΩ
ADAPTER
SELECT
DRIVE
VHSP
2
ACPRES
ACSEL
1
ACDRV
BATTERY
SELECT
DRIVE
VCC
SRP
1 bq24702 ONLY
VCC
BATTERY SELECT
LOGIC
AND
ANTI−CROSS
CONDUCT
+
SWITCH TO
BATTERY
SRP
+
NO BATTERY
COMPARATOR
+
16
ACSEL
+
A=20
SRN
2 bq24703 ONLY
UDG−00137
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11
SLUS553D − MAY 2003 − REVISED JULY 2005
Terminal Functions
TERMINAL
12
I/O
DESCRIPTION
bq24702
(PW)
bq24703
(QFN)
ACDET
1
26
I
AC or adapter power detection
ACDRV
24
25
O
AC or adapter power source selection output
ACN
11
8
I
Negative differential input
ACP
12
9
I
Positive differential input
ACPRES
2
27
O
AC power indicator
ACSEL
3
28
I
AC adapter power select
ACSET
6
3
I
Adapter current programming voltage
ALARM
19
19
O
Alarm output
BATDEP
4
1
I
Depleted battery level
BATDRV
23
24
O
Battery power source select output
BATP
13
12
I
Battery charge regulation voltage measurement input to the battery-voltage gm amplifier
BATSET
9
6
I
External override to an internal precision reference
COMP
10
7
O
Inverting input to the PWM comparator
ENABLE
8
5
I
Charge enable
GND
17
17
O
Supply return and ground reference
IBAT
14
13
O
Battery current differential amplifier output
PWM
21
21
O
Gate drive output
SRN
15
15
I
Negative differential battery current sense amplifier input
SRP
16
16
I/O
Positive differential battery current sense amplifier input
SRSET
5
2
I
Battery charge current programming voltage
VCC
22
22
I
Operational supply voltage
VHSP
20
20
O
Voltage source to drive gates of the external MOSFETs
NAME
VREF
7
4
O
Precision 5-V reference
VS
18
18
I
System (load) voltage input pin
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SLUS553D − MAY 2003 − REVISED JULY 2005
Pin Assignments
ACDET: AC or adapter power detection. This input pin is used to determine the presence of the ac adapter.
When the voltage level on the ACDET pin is less than VACPRES, the bq24702/bq24703 is in sleep mode, the
PWM control is disabled, the BATDRV is driven low, and the ACDRV is driven high. This feature can be used
to automatically select battery as the system power source.
ACDRV: AC or adapter power source select output. This pin drives an external P-channel MOSFET used to
switch to the ac wall-adapter as the system power source. When the ACSEL pin is high while the voltage on
the ACDET pin is greater than VACPRES, the output ACDRV pin is driven low (VHSP). This pin is driven high (VCC)
when the ACDET is less than VACPRES.
ACN, ACP: Negative and positive differential inputs, respectively for ac-to-dc adapter current sense resistor.
ACPRES: This open-drain output pin is used to indicate the presence of ac power. A logic high indicates there
is a valid ac input. A low indicates the loss of ac power. ACPRES is high when the voltage level on the ACDET
pin is greater than VACPRES.
ACSEL: AC adapter power select. This input selects either the ac adapter or the battery as the power source.
A logic high selects ac power, while a logic low selects the battery.
ACSET: Adapter current programming voltage. This input sets the system current level at which dynamic power
management occurs. Adapter currents above this programmed level activate the dynamic power management
and proportionally reduce the available power to the battery.
ALARM: Depleted battery alarm output. This open-drain pin indicates that a depleted battery condition exists.
A pullup on ALARM goes high when the voltage on the BATDEP pin is below VACPRES. On the bq24702, the
ALARM output also activates when the selector inputs do not match the selector state.
BATDEP: Depleted battery level. A voltage divider network from the battery to BATDEP pin is used to set the
battery voltage level at which depletion is indicated by the ALARM pin. See ALARM pin for more details. A
battery depletion is detected when BATDEP is less than VACPRES. A no-battery condition is detected when the
battery voltage is < 80% of the depleted threshold. In a no-battery condition, the bq24702 automatically selects
ac as the input source. If ENABLE = 1, the PWM remains enabled.
BATDRV: Battery power source select output. This pin drives an external P-channel MOSFET used to switch
the battery as the system’s power source. When the voltage level on the ACDET pin is less than VACPRES, the
output of the BATDRV pin is driven low, GND. This pin is driven high (VCC) when ACSEL is high and ACDET
> VACPRES.
BATP: Battery charge regulation voltage measurement input to the battery-voltage gm amplifier. The voltage
on this pin is typically derived from a voltage divider network connected across the battery. In a voltage loop,
BATP is regulated to the VFB precision reference of the battery voltage gm amplifier.
BATSET: An external override to an internal precision reference. When BATSET is > 0.25 V, the voltage level
on the BATSET pin sets the voltage charge level. When BATSET ≤ 0.25 V, an internal VFB reference is
connected to the inverting input of the battery error amplifier. To ensure proper battery voltage regulation with
BATSET, BATSET must be > 1.0 V. Simply ground BATSET to use the internal reference.
COMP: The inverting input to the PWM comparator and output of the gm amplifiers. A type II compensation
network between COMP and GND is recommended.
ENABLE: Charge enable. A high on this input pin allows PWM control operation to enable charging while a low
on this pin disables and forces the PWM output to a high state. Battery charging is initiated by asserting a logic
1 on the ENABLE pin.
GND: Supply return and ground reference
IBAT: Battery current differential amplifier output. The output of this pin produces a voltage proportional to the
battery charge current. This voltage is suitable for driving an ADC input.
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13
SLUS553D − MAY 2003 − REVISED JULY 2005
PWM: Gate drive output pin drives the P-channel MOSFET for PWM control. The PWM control is active when
ACPRES, ACSEL, and ENABLE are high. PWM is driven low to VHSP and high to VCC.
SRN, SRP: Differential amplifier inputs for battery current sense. These pins feed back the battery charge
current for PWM control. SRN is tied to the battery terminal. SRP is the source pin for zero volt operation.
SRSET: Battery charge current programmed voltage. The level on this pin sets the battery charge current limit.
VCC: Operational supply voltage.
VHSP: The VHSP pin is connected to a 1-µF capacitor (close to the pin) to provide a stable voltage source to
drive the gates of the external MOSFETs. VHSP = VCC − 10 V for VCC > 10.5 V and VHSP = VCC − 0.5 V for
VCC <10.5 V. A 13-V Zener diode should be placed between VCC and VHSP to prevent MOSFET overstress
during start-up.
VREF: Bypassed precision voltage 5-V output. It can be used to set fixed levels on the inverting inputs of any
one of the three error amplifiers if desired. The tight tolerance is suitable for charging lithium-ion batteries.
VS: System (Load) voltage input pin. The voltage on this pin indicates the system voltage in order to insure a
break before make transition when changing from ac power to battery power. The battery is protected from an
over-voltage condition by disabling the P-channel MOSFET connected to the BATDRV pin if the voltage at VS
is greater than BATP. This function can be eliminated by grounding the VS pin.
14
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SLUS553D − MAY 2003 − REVISED JULY 2005
APPLICATION INFORMATION
Programming the Thresholds
The input-referenced thresholds for battery depleted, ac detection and charge voltage are defined by
dimensioning the external dividers connected to pins BATDEP, ACDET and BATP. This calculation is simple,
and consists of assuming that when the input voltage equals the desired threshold value the voltage at the
related pin is equal to the pin internal reference voltage:
Vinput = Vpin × (1 + Kres)
where:
Vinput = Target threshold, referenced to input signal
Vpin = Internal reference(1.196 V for BATP; 1.246 V for BATDEP, ACDET)
Kres = External resistive divider gain ( for instance: R24/R25 for BATP)
When using external dividers with high absolute value the input bias currents for those pins must be included
in the threshold calculation. On the bq24702/3 the input bias currents increase the actual value for the threshold
voltage, when compared to the values calculated using the internal references and divider gain only:
Vinput = Vpin × (1+Kres) + Vbias
The increase on the threshold voltage is given by:
Vbias = Rdiv × Ipin
where:
Vbias = Voltage increase due to pin bias current
Rdiv = External resistor value for resistor connected from pin to input voltage
Ipin = Maximum pin leakage current
The effect of IB can be reduced if the resistor values are decreased.
Dynamic Power Management
The dynamic power management (DPM) feature allows a cost effective choice of an ac wall-adapter that
accommodates 90% of the system’s operating-current requirements. It minimizes battery charge time by
allocating available power to charge the battery (i.e. IBAT = IADPT − ISYS). If the system plus battery charge
current exceeds the adapter current limit, as shown in Figure 1, the DPM feature reduces the battery charge
current to maintain an overall input current consumption within user defined power capability of the wall-adapter.
As the system’s current requirements decrease, additional current can be directed to the battery, thereby
increasing battery charge current and minimizing battery charge time.
The DPM feature is inherently designed into the PWM controller by inclusion of the three control loops,
battery-charge regulation voltage, battery-charge current, and adapter-charge current, refer to Figure 2. If any
of the three user programmed limits are reached, the corresponding control loop commands the PWM controller
to reduce duty cycle, thereby reducing the battery charge current.
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15
SLUS553D − MAY 2003 − REVISED JULY 2005
ADAPTER CURRENT LIMIT
ADAPTER CURRENT
SYSTEM CURRENT
BATTERY CHARGE CURRENT
NO
CHARGE
MAXIMUM
CHARGE CURRENT
DYNAMIC POWER
MANAGEMENT
MAXIMUM
CHARGE CURRENT
UDG−00113
Figure 1. Dynamic Power Management
ACDET Operation
The ACDET function senses the loss of adequate adapter power. If the voltage on ACDET drops below the
internal VACPRES reference voltage, a loss of ADAPTER power is declared and the bq24702/bq24703 switches
to battery power as the main system power. In addition, the bq24702/bq24703 shuts down its 5-V VREF and
enters a low power sleep mode.
Battery Charger Operation
The bq24702/bq24703 fixed-frequency, PWM controller is designed to provide closed-loop control of battery
charge-current (ICH) based on three parameters, battery-float voltage (VBAT), battery-charge current, and
adapter charge current (IADPT). The bq24702/bq24703 is designed primarily for control of a buck converter
using a high side P-channel MOSFET device (SW, refer to Figure 2).
The three control parameters are voltage programmable through resistor dividers from the bq24702/bq24703
precision 5-V reference, an external or internal precision reference, or directly via a DAC interface from a
keyboard controller.
Adapter and battery-charge current information is sensed and fed back to two transconductance (gm ) amplifiers
via low-value-sense resistors in series with the adapter and battery respectively. Battery voltage information is
sensed through an external resistor divider and fed back from the battery to a third gm amplifier.
Precharge Operation
The precharge operation must be performed using the PWM regulator. The host can set the precharge current
externally by monitoring the ALARM pin to detect a battery depleted condition and programming SRSET voltage
to obtain the desired precharge current level.
16
www.ti.com
SLUS553D − MAY 2003 − REVISED JULY 2005
Zero Volt Operating
The zero volt operation is intended to provide a low current path to close open packs and protect the system
in the event of a pack cell short-circuit condition or if a short is applied to the pack terminal. It is not designed
to precharge depleted packs, as it is disabled at voltages that are not within normal pack operating range for
precharge.
If the voltage at BATDEP pin is below the zero volt operation threshold , charge is enabled (EN=HI), and ac is
selected (ACSEL=HI) the bq24702/3 enters the zero volt operation mode. When the zero volt operation mode
is on, the internal PWM is disabled, and an internal power MOSFET connects SRP to VCC. The battery charge
current is limited by the filter resistor connected to SRP pin (R19). R19 must be dimensioned to withstand the
worst case power dissipation when in zero volt operation mode.
The zero volt operation mode is disabled when BATDEP is above the zero volt operation threshold, and the main
PWM loop is turned on if charge is enabled, regulating the current to the value set by SRSET voltage. To avoid
errors on the charge current both resistors on the SRP, SRN filter must have the same value. Note, however,
that R21 (connected to SRN) does not dissipate any power when in zero volt operation and can be of minimum
size.
PWM Operation
The three open collector gm amplifiers are tied to the COMP pin (refer to Figure 2), which is internally biased
up by a 100-µA constant current source. The voltage on the COMP pin is the control voltage (VC) for the PWM
comparator. The PWM comparator compares VC to the sawtooth ramp of the internally fixed 300-kHz oscillator
to provide duty cycle information for the PWM drive. The PWM drive is level-shifted to provide adequate gate
voltage levels for the external P-channel MOSFET. Refer to PWM selector switch gate drive section for gate
drive voltage levels.
Q1
SW
ISW
+
VADPT
D1
CLK
OSC
RAMP
ENABLE
S
Q
R
Q
LATCH OUT
VCC
LEVEL
SHIFT
5V
100 µA
VBAT
PWM COMPARATOR
PWM
DRIVE
21
PWM
VHSP
FROM ENABLE LOGIC
COMP
10
+
13
BATP
ZCOMP
ENABLE
BATTERY
VOLTAGE
+
1.25 V
BATTERY CHARGE
CURRENT
ADP CURRENT
gm
AMPLIFIERS
UDG−00114
Figure 2. PWM Controller Block Diagram
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17
SLUS553D − MAY 2003 − REVISED JULY 2005
Softstart
Softstart is provided to ensure an orderly start-up when the PWM is enabled. When the PWM controller is
disabled (ENABLE = Low), the 100-µA current source pullup is disabled and the COMP pin is actively pulled
down to GND. Disabling the 100-µA pullup reduces current drain when the PWM is disabled. When the
bq24702/bq24703 PWM is enabled (ENABLE = High), the COMP pin is released and the 100-µA pullup is
enabled (refer to Figure 2). The voltage on the COMP pin increases as the pullup charges the external
compensation network connected to the COMP pin. As the voltage on the COMP pin increases the PWM duty
cycle increases linearly as shown in Figure 3.
PERCENT DUTY CYCLE
vs
COMPENSATION VOLTAGE
100
90
Percent Duty Cycle − %
80
70
60
50
40
30
20
10
0
1.2
1.7
2.2
2.7
3.2
VCOMP − Compensation Voltage − V
Figure 3
As any one of the three controlling loops approaches the programmed limit, the gm amplifier begins to shunt
current away from the COMP pin. The rate of voltage rise on the COMP pin slows due to the decrease in total
current out of the pin, decreasing the rate of duty cycle increase. When the loop has reached the programmed
limit the gm amplifier shunts the entire bias current (100 µA) and the duty cycle remains fixed. If any of the control
parameters tries to exceed the programmed limit, the gm amplifier shunts additional current from the COMP pin,
further reducing the PWM duty cycle until the offending parameter is brought into check.
Setting the Battery Charge Regulation Voltage
The battery charge regulation voltage is programmed through the BATSET pin, if the internal precision
reference is not used. The BATSET input is a high-impedance input that is driven by either a keyboard controller
DAC or via a resistor divider from a precision reference (see Figure 4).
The battery voltage is fed back to the gm amplifier through a resistor divider network. The battery charge
regulation voltage can be defined as:
V
BATTERY
+
(R1 ) R2)
V
R2
BATSET V ) I
BATP
where IBATP = input bias current for pin BATP
18
www.ti.com
R1
(1)
SLUS553D − MAY 2003 − REVISED JULY 2005
The overall accuracy of the battery charge regulation voltage is a function of the bypassed 5-V reference voltage
tolerance as well as the tolerances on R1 and R2. The precision voltage reference has a 0.5% tolerance making
it suitable for the tight battery voltage requirements of Li-ion batteries. Tolerance resistors of 0.1% are
recommended for R1 and R2 as well as any resistors used to set BATSET.
The bq24702/bq24703 provides the capability of using an internal precision voltage reference through the use
of a multiplexing scheme, refer to Figure 4, on the BATSET pin. When BATSET voltage is less than 0.25 V, an
internal reference is switched in and the BATSET pin is switched out from the gm amplifier input. When the
BATSET voltage is greater than 0.25 V, the BATSET pin voltage is switched in to the input of the gm amplifier
and the voltage reference is switched out.
NOTE:The minimum recommended BATSET is 1.0 V, if BATSET is used to set the voltage loop.
VBAT
BATP
COMP
13
gm AMPLIFIER
10
+
BATSET
9
0.25 V
1.25 V
VBAT
(a) VBATSET < 0.25 V
R1
VREF = 5 V
COMP
BATP
13
gm AMPLIFIER
10
+
R2
9
BATSET
0.25 V
1.196 V
(b) VBATSET > 1 V
UDG−00116
Figure 4. Battery Error Amplifier Input Multiplexing Scheme
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19
SLUS553D − MAY 2003 − REVISED JULY 2005
Programming the Battery Charge Current
The battery charge current is programmed via a voltage on the SRSET pin. This voltage can be derived from
a resistor divider from the 5-V VREF or by means of an DAC. The voltage is converted to a current source that
is used to develop a voltage drop across an internal offset resistor at one input of the SR gm amplifier. The charge
current is then a function of this voltage drop and the sense resistor (RS), refer to Figure 5.
RS
COMP 10
SRP
2 kΩ
16
+
VREF
SRN
15
SRSET
5
+
25 kΩ
UDG−00117
Figure 5. Battery Charge Current Input Threshold Function
The battery charge current can be defined as:
I
V
+ SRSET
BAT
25 R
S
(2)
where VSRSET is the programming voltage on the SRSET pin. VSRSET maximum is 2.5 V.
Programming the Adapter Current
Like the battery charge current described previously, the adapter current is programmed via a voltage on the
ACSET pin. That voltage can either be from an external resistor divider from the 5-V VREF or from an external
DAC. The adapter current is defined as:
I
20
ADPT
+
V
ACSET
25 R
S2
(3)
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SLUS553D − MAY 2003 − REVISED JULY 2005
COMPONENT SELECTION
MOSFET Selection
MOSFET selection depends on several factors, namely, gate-source voltage, input voltage, and input current.
The MOSFET must be a P-channel device capable of handling at least 15-V gate-to-source with a drain-source
breakdown of VBV~ VIN+1 V. The average input current can be approximated by:
I
(avg) + D
IN
Ichg
A
D = Duty cycle
Ichg = Charge current
(4)
The RMS current through the MOSFET is defined as:
I
ǸD A
(RMS) + Ichg
IN
RMS
(5)
The rise/fall times for pin PWM for the selected MOSFET should be greater than 40 nsec.
Schottky Rectifier (Freewheeling)
The freewheeling Schottky rectifier must also be selected to withstand the input voltage, VIN. The average
current can be approximated from:
I
(avg) + Ichg
D1
(1 * D) A
(6)
Choosing an Inductance
Low inductance values result in a steep current ramp or slope. Steeper current slopes result in the converter
operating in the discontinuous mode at a higher power level. Steeper current slopes also result in higher output
ripple current, which may require a higher number or more expensive capacitors to filter the higher ripple current.
In addition, the higher ripple current results in an error in the sensed battery current particularly at lower charging
currents. It is recommended that the ripple current not exceed 20% to 30% of full scale dc current.
L+
D
ǒVIN * VBATǓ
F
Ichg Ripple
S
Ripple = % Ripple allowed (Ex.: 0,2 for 20% ripple)
(7)
Too large an inductor value results in the current waveform of Q1 and D1 in Figure 2 approximating a
squarewave with an almost flat current slope on the step. In this case, the inductor is usually much larger than
necessary, which may result in an efficiency loss (higher DCR) and an area penalty.
Selecting an Output Capacitor
For this application the output capacitor is used primarily to shunt the output ripple current away from the battery.
The output capacitor should be sized to handle the full output ripple current as defined as:
I c (RMS) +
ǒVIN * VBATǓ
F
S
L
D
A
RMS
(8)
www.ti.com
21
SLUS553D − MAY 2003 − REVISED JULY 2005
Selecting an Input Capacitor
The input capacitor is used to shunt the converter ripple current on the input lines. The capacitor(s) must have
a ripple current (RMS) rating of:
I
RMS
+
Ǹ[Ichg
(1–D)]
2
D ) [Ichg
D]
2
(1–D)
A
RMS
(9)
In addition to shunting the converter input ripple when the PWM is operating, the input capacitor also acts as
part of an LC filter, where the inductance component is defined by the ac adapter cable inductance and board
trace inductance from adapter connector to filter capacitor. Overshoot conditions can be observed at VCC line
during fast load transients when the adapter powers the load or when the adapter is hot-plugged .
Increasing the input capacitor value decreases the overshoot at VCC. Avoid overshoot voltages at VCC in excess
of the absolute maximum ratings for that pin.
Compensating the Loop
For the bq24702/bq24703 used as a buck converter, the best method of compensation is to use a Type II
compensation network from the output of the transconductance amplifiers (COMP pin) to ground (GND) as
shown in Figure 2. A Type II compensation adds a pole-zero pair and an additional pole at dc.
The Type II compensation network places a zero at
ǒ
F +1
Z
2
p
1
R
COMP
C
Z
Ǔ
Hz
(10)
and a pole at
F +1
P
2
ǒ
p
1
R
COMP
C
Ǔ
Hz
P
(11)
For this battery charger application the following component values: CZ = 4.7 µF, CP = 150 pF, and
RCOMP = 100 Ω, provides a closed loop response with more than sufficient phase margin, as long as the LC
pole [1/2 × PI × sqrt (l×c)] is set below 10 kHz. The SRP/SRN filter (R19, R21, C8) and ACP/ACN filter
(R13/R15/C3) are required to filter noise associated with the PWM switching. To avoid adding secondary poles
to the PWM closed loop system those filters should be set with cutoff frequencies higher than 1 kHz.
Selector Operation
The bq24702/bq24703 allows the host controller to manually select the battery as the system’s main power
source, without having to remove adapter power. This allows battery conditioning through smart battery learn
cycles. In addition, the bq24702/bq24703 supports autonomous supply selection during fault conditions on
either supply. The selector function uses low RDS(on) P-channel MOSFETs for reduced voltage drops and longer
battery run times.
NOTE: Selection of battery power whether manual or automatic results in the suspension of battery
charging.
22
www.ti.com
SLUS553D − MAY 2003 − REVISED JULY 2005
ADAPTER SELECT SWITCH
ADAPTER
INPUT
SYSTEM
LOAD
(bq24702)
PWM
BATTERY
CHARGER
BAT
ACDRV
(bq24702) 24
BATTERY
SELECTOR
BATDRV
CONTROL 23
BATTERY
SELECT
SWITCH
UDG−00119
Figure 6. Selector Control Switches
Autonomous Selection Operation
Adapter voltage information is sensed at the ACDET pin via a resistor divider from the adapter input. The voltage
on the ACDET pin is compared to an internally fixed threshold. An ACDET voltage less than the set threshold
is considered as a loss of adapter power regardless of the actual voltage at the adapter input. Information
concerning the status of adapter power is fed back to the host controller through ACPRES. The presence of
adapter power is indicated by ACPRES being set high. A loss of adapter power is indicated by ACPRES going
low regardless of which power source is powering the system. During a loss of adapter power, the
bq24702/bq24703 obtains operating power from the battery through the body diode of the P-channel battery
select MOSFET. Under a loss of adapter power, ACPRES (normally high) goes low, if adapter power is selected
to power the system, the bq24702/bq24703 automatically switches over to battery power by commanding
ACDRV high and BATDRV low. During the switch transition period, battery power is supplied to the load via the
body diode of the battery select P-channel MOSFET. When adapter power is restored, the bq24702/bq24703
configures the selector switches according to the state of signals; ACSEL, and ACPRES. If the ACSEL pin is
left high when ac power is restored, the bq24702/bq24703 automatically switches back to ac power. To remain
on battery power after ac power is restored, the ACSEL pin must be brought low.
Conversely, if the battery is removed while the system is running on battery power and adapter power is present,
the bq24702/bq24703 automatically switches over to adapter power by commanding BATDRV high and
ACDRV low.
NOTE: For the bq24702 any fault condition that results in the selector MOSFET switches not
matching their programmed states is indicated by the ALARM pin momentarily going high. Refer
to Battery Depletion Detection Section for more information on the ALARM discrete.
When switching between the ac adapter and battery the internal logic monitors the voltage at pins ACDRV and
BATDRV to implement a break-before-make function, with typical dead time on the order of 150 nsec.
The turnon times for the external ac/battery switches can be increased to minimize inrush peak currents; that
can be accomplished by adding external resistors in series with the MOSFET gates(R18 and R26). Note,
however, that adding those resistors effectively disables the internal break-before-make function for
ac/battery-switches, as the MOSFET gate voltages can not be monitored directly. If external resistors are added
to increase the rise/fall times for battery/ac switches the break-before-make has to be implemented with discrete
external components, to avoid shoot-through currents between ac adapter and battery pack. This functionality
can be implemented by adding diodes (D2/D9) that bypass the external resistors when turning off the external
FETs.
www.ti.com
23
SLUS553D − MAY 2003 − REVISED JULY 2005
Smart Learn Cycles When Adapter Power Is Present
Smart learn cycles can be conducted when adapter power is present by asserting and maintaining the ACSEL
pin low. The adapter power can be reselected at the end of the learn cycle by a setting ACSEL to a logic high,
provided that adapter power is present. Battery charging is suspended while selected as the system power
source.
NOTE: On the bq24703 the ac adapter is switched to the load when the battery voltage reaches
the battery depleted threshold; it can be used when the learn cycle does not require the battery
voltage to go below the battery depleted threshold. If the learn cycle algorithm requires the battery
voltage to go lower than the battery depleted voltage, the bq24702 should be used, as it does not
switch the ac adapter to load upon battery depleted detection.
System Break Before Make Function
When selecting the battery as the system primary power source, the adapter power select MOSFET turns off,
in a break-before-make fashion, before the battery select MOSFET turns on. To ensure that this happens under
all load conditions, the system voltage (load voltage) can be monitored through a resistor divider on the VS pin.
This function provides protection against switching over to battery power if the adapter selector switch were
shorted and adapter power present. Setting the VS resistive divider gain with the same gain selected for the
BATP resistive divider assures the battery switch is turned on only when the system voltage is equal or less than
the battery voltage. This function can be eliminated by grounding the VS pin.
The ACDET function senses the adapter voltage via a resistive divider (refer to application circuit).The divider
can be connected either to the anode of the input blocking diode (directly to the adapter supply) or to the cathode
of the input blocking diode (bq24702/3 VCC pin). When the divider is connected to the adapter supply, the
adapter power removal is immediately identified and the sleep mode is entered, disabling the
break-before-make function for system voltage (see section for system power switching) and coupling system
voltage to the battery line. In normal operation with a battery present, the battery low impedance prevents any
over-voltage conditions. However, if a pack is not present or the pack is open, the battery line voltage has a
transient equal to the adapter voltage. The bq24703 SRP/SRN pins are designed to withstand this over-voltage
condition, but avoid connection to the battery line of any external devices that are not rated to withstand the
adapter voltage.
Connecting the ACDET resistive divider input to the VCC node keeps the system break-before-make function
enabled until the voltage at pin VS is lower than the voltage at pin BATP. However, note that when using this
topology the VCC pin voltage can be held by capacitive loads at either the VCC or system (ac switch is on) nodes
when the ac adapter is removed. As the ACDET divider is connected to the VCC line there is a time delay from
ac adapter removal to ac adapter removal detection by the IC. This time is dependent on load conditions and
capacitive load values at VCC and system lines.
Battery Depletion Detection
The bq24702/bq24703 provides the host controller with a battery depletion discrete, the ALARM pin, to alert
the host when a depleted battery condition occurs. The battery depletion level is set by the voltage applied to
the BATDEP pin through a voltage divider network. The ALARM output asserts high and remains high as long
as the battery deplete condition exists, regardless of the power source selected.
For the bq24702, the host controller must take appropriate action during a battery deplete condition to select
the proper power source. The bq24702 remains on the selected power source. The bq24703, however,
automatically reverts over to adapter power, provided the adapter is present, during a deep discharge state. The
battery is considered as being in a deep discharge state when the battery voltage is less than (0.8 × depleted
level).
Feature sets for the bq24702 and bq24703 are detailed in Table 1.
24
www.ti.com
SLUS553D − MAY 2003 − REVISED JULY 2005
SELECTOR/ALARM TIMING EXAMPLE
The selector and ALARM timing example in Figure 7 illustrates the battery conditioning support.
NOTE: For manual selection of wall power as the main power source, both the ACPRES and
ACSEL signals must be a logic high.
ACPRES
ACSEL
ACDRV
BATDRV
ALARM
BATTERY
DEPLETE
CONDITION
bq24703 ONLY
UDG−00122
ACSEL
(ACPRES)
tBATSEL
ACDRV
tACSEL
BATDRV
BATDEP< 1 V
t
ACSEL
BATDRV
tBATSEL
ACDRV
UDG−00120
Figure 7. Battery Selector and ALARM Timing Diagram
www.ti.com
25
SLUS553D − MAY 2003 − REVISED JULY 2005
PWM SELECTOR SWITCH GATE DRIVE
Because the external P-channel MOSFETs (as well as the internal MOSFETs) have a maximum gate-source
voltage limitation of the input voltage, VCC, cannot be used directly to drive the MOSFET gate under all input
conditions. To provide safe MOSFET-gate-drive at input voltages of less than an intermediate gate drive voltage
rail was established (VSHP). Where VHSP = VCC − 10 V. This ensures adequate enhancement voltage across
all operating conditions.
An external zener diode (D3) connected between VCC and VHSP is required for transient protection; its
breakdown voltage should be above the maximum value for internal VHSP/VCC clamp voltage for all operating
conditions.
TRANSIENT CONDITIONS AT SYSTEM, OVER-VOLTAGE AT SYSTEM TERMINAL
Overshoot conditions can be observed at the system terminal due to fast load transients and inductive
characteristics of the system terminal to load connection. An overshoot at the system terminal can be directly
coupled to the VCC and VBAT nodes, depending on the switch mode of operation. If the capacitors at VBAT
and VCC can not reduce this overshoot to values below the absolute maximum ratings, it is recommended that
an additional capacitor is added to the system terminal to avoid damage to IC or external components due to
voltage overstress under those transient conditions.
AC ADAPTER COLLAPSING DUE TO TRANSIENT CONDITIONS
The ac adapter voltage collapses when the ac switch is on and a current load transient at the system exceeds
the adapter current limit protection. Under those conditions the ac switch is turned off when the ac adapter
voltage falls below the ac adapter detection threshold. If the system terminal to load impedance has an inductive
characteristic, a negative voltage spike can be generated at the system terminal and coupled into the battery
line via the battery switch backgate diode.
In normal operation, with a battery present, this is not an issue, as the low battery impedance holds the voltage
at battery line. However, if a battery is not present or the pack protector switches are open the negative spike
at the system terminal is directly coupled to the SRP/SRN pins via the R19/R21 resistors.
Avoid damage to the SRP/SRN pins if this transient condition happens in the application. If a negative voltage
spike happens at system terminal and R19/R21 limit the current sourced from the pin to less than −50 mA (Ipin
= Vsystem/R19), the pins SRP/SRN are not damaged and the external protection schottky diodes are not
required. However, if the current under those transient conditions exceeds −50 mA, external schottky diodes
must be added to clamp the voltage at pins SRP/SRN so they do not exceed the absolute maximum ratings
specified (−0.3 V).
IBAT AMPLIFIER
A filter with a cutoff frequency smaller than 10 kHz should be added to the IBAT output to remove switching
noise.
POWER DISSIPATION CALCULATION
During PWM operation, the power dissipated internally to the IC increases as the internal driver is switching the
PWM FET on/off. The power dissipation figures are dependent on the external FET used, and can be calculated
using the following equation:
Pd(max) = [IDDOP + Qg × Fs(max)] × VADAP
where:
Qg= Total gate charge for selected PWM MOSFET
IDDOP = Maximum quiescent current for IC
VADAP = Maximum adapter voltage
Fs(max) = Maximum PWM switching frequency
The maximum junction temperature for the IC must be limited to 125°C, under worst case conditions.
26
www.ti.com
SLUS553D − MAY 2003 − REVISED JULY 2005
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER REFERENCE
vs
JUNCTION TEMPERATURE
BYPASSED 5-V REFERENCE
vs
JUNCTION TEMPERATURE
5.1
1.215
5.08
1.21
VREF − 5 -V Reference − V
VFB − Error Amplifier Reference − V
VCC = 18 V
1.205
1.2
1.195
1.19
1.185
VCC = 18 V
5.06
5.04
5.02
5
4.98
4.96
4.94
1.18
4.92
1.175
−40
10
60
TJ − Junction Temperature − _C
4.9
−40
110 125
10
60
110 125
TJ − Junction Temperature − _C
Figure 8
Figure 9
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
TOTAL SLEEP CURRENT
vs
JUNCTION TEMPERATURE
335
26
VCC = 18 V
325
24
f − Oscillator Frequency − kHz
I SLEEP − Battery Sleep Current − µ A
VCC = 18 V
22
20
18
16
315
305
295
285
275
265
255
245
14
−40
10
60
TJ − Junction Temperature − _C
110 125
Figure 10
235
−40
10
60
110 125
TJ − Junction Temperature − _C
Figure 11
www.ti.com
27
SLUS553D − MAY 2003 − REVISED JULY 2005
BATTERY CURRENT SET ACCURACY
vs
BATTERY CURRENT SET VOLTAGE
AC CURRENT SET ACCURACY
vs
AC CURRENT SET VOLTAGE
20
25
SRSET Full Scale = 2.5 V
= Max Programmed Current
TJ = 25°C
AC Current Set Accuracy − %
Battery Current Set Accuracy − %
25
15
10
5
0
1 1.25 1.5 1.75 2 2.25 2.5
0.25 0.5 0.75
VSRSET − Battery Current Set Voltage − V
20
ACSET Full Scale = 2.5 V
= Max Programmed Current
TJ = 25°C
15
10
5
0
0.25 0.5
0.75 1
1.25 1.5 1.75 2
2.25 2.5
VACSET − AC Current Set Voltage − V
Figure 12
Figure 13
BOARD LAYOUT GUIDELINES
Recommended Board Layout
Follow these guidelines when implementing the board layout:
1. Do not place lines and components dedicated to battery/adapter voltage sensing (ACDET,BATDEP, VS),
voltage feedback loop (BATP, BATSET if external reference is used) and shunt voltage sensing
(SRP/SRN/ACP/ACN) close to lines that have signals with high dv/dt (PWM, BATDRV, ACDRV, VHSP) to
avoid noise coupling.
2. Add filter capacitors for SRP/SRN (C8) and ACP/ACN (C3) close to IC pins
3. Add Reference filter capacitor C1 close to IC pins
4. Use an isolated, clean ground for IC ground pin and resistive dividers used in voltage sensing; use an
isolated power ground for PWM filter cap and diode (C11/D4). Connect the grounds to the battery PACK−
and adapter GND.
5. Place C7 close to VCC pin.
6. Place input capacitor C12 close to PWM switch (U3) source and R14.
7. Position ac switch (U2) to minimize trace length from ac switch source to input capacitor C12.
8. Minimize inductance of trace connecting PWM pin and PWM external switch U3 gate
9. Maximize power dissipation planes connected to PWM switch
10. Maximize power dissipation planes connected to SRP resistor if steady state in zero volt mode is possible
11. Maximize power dissipation planes connected to D1
28
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24702PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ24702PWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ24702PWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ24702PWRG4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ24703PW
ACTIVE
TSSOP
PW
24
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ24703PWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ24703PWRG4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ24703RHDR
ACTIVE
QFN
RHD
28
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24703RHDRG4
ACTIVE
QFN
RHD
28
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
60
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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