SAMSUNG K1S16161CA

Preliminary
K1S16161CA
UtRAM
Document Title
1Mx16 bit Page Mode Uni-Transistor Random Access Memory
Revision History
Revision No. History
0.0
Draft Date
Initial Draft
Remark
December 12, 2003 Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
1M x 16 bit Page Mode Uni-Transistor CMOS RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
The K1S16161CA is fabricated by SAMSUNG′s advanced
CMOS technology using one transistor memory cell. The device
support 4 page mode operation, Industrial temperature range
and 48 ball Chip Scale Package for user flexibility of system
design. The device also supports deep power down mode for
low standby current.
Process Technology: CMOS
Organization: 1M x16 bit
Power Supply Voltage: 2.7~3.1V
Three State Outputs
Compatible with Low Power SRAM
• Support 4 page read mode
• Package Type: 48-FBGA-6.00x7.00
PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Speed
(tRC)
K1S16161CA-I
Industrial(-40~85°C)
2.7~3.1V
70ns
2
Operating
(ICC2, Max.)
PKG Type
80µA
35mA
48-FBGA-6.00x7.00
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
1
Power Dissipation
Standby
(ISB1, Max.)
3
4
5
6
Clk gen.
A
LB
OE
A0
A1
A2
CS2
B
I/O9
UB
A3
A4
CS1
I/O1
Vcc
Vss
Row
Addresses
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
Vss
I/O12
A17
A7
I/O4
Vcc
E
Vcc
I/O13
NC
A16
I/O5
Vss
I/O1~I/O8
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
A19
A12
A13
WE
I/O8
H
A18
A8
A9
A10
A11
NC
Row
select
Data
cont
Memory array
I/O Circuit
Column select
Data
cont
I/O9~I/O16
F
Precharge circuit.
Data
cont
Column Addresses
CS1
CS2
48-FBGA: Top View(Ball Down)
OE
Control Logic
WE
UB
Name
Function
CS1,CS2 Chip Select Inputs
Name
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O9~16)
LB
Lower Byte(I/O1~8)
NC
No Connection1)
A0~A19
Address Inputs
I/O1~I/O16 Data Inputs/Outputs
LB
Function
1) Reserved for future use
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min.=2.7V) for a minimum 200µs with CS1=high.or CS2=low.
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)
VCC
Min. 200µs
≈
VCC(Min)
≈
CS1
≈ ≈
CS2
Power Up Mode
Normal Operation
POWER UP(1)
1. After VCC reaches VCC(Min.), wait 200µs with CS1 high. Then the device gets into the normal operation.
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)
VCC
≈
CS2
≈ ≈
CS1
Min. 200µs
≈
VCC(Min)
Power Up Mode
Normal Operation
POWER UP(2)
1. After VCC reaches VCC(Min.), wait 200µs with CS2 low. Then the device gets into the normal operation.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
LB
UB
1)
1)
I/O1~8
I/O9~16
Mode
Power
H
X
X
X
X
X
High-Z
High-Z
Deselected
Standby
X1)
L
X1)
X1)
X1)
X1)
High-Z
High-Z
Deselected
Standby
X1)
X1)
X1)
X1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
L
X1)
High-Z
High-Z
Output Disabled
Active
1)
1)
1)
L
H
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X1)
L
L
L
Din
Din
Word Write
Active
1)
1. X means don′t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
Unit
VIN, VOUT
-0.2 to VCC+0.3V
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 3.6V
V
Power Dissipation
PD
1.0
W
TSTG
-65 to 150
°C
TA
-40 to 85
°C
Voltage on any pin relative to Vss
Storage temperature
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
PRODUCT LIST
Industrial Temperature Product(-40~85°C)
Part Name
Function
K1S16161CA-FI70
K1S16161CA-BI701)
48-FBGA, 70ns, 2.9V
48-FBGA, 70ns, 2.9V
1. Lead Free Product
RECOMMENDED DC OPERATING CONDITIONS1)
Symbol
Min
Typ
Max
Unit
Supply voltage
Item
Vcc
2.7
2.9
3.1
V
Ground
Vss
0
0
0
V
Input high voltage
VIH
2.2
-
Vcc+0.32)
V
Input low voltage
VIL
-
0.6
V
-0.2
3)
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.
3. Undershoot: -1.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Symbol
Test Condition
Min
Max
Unit
Input capacitance
Item
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ1)
Max
Unit
Input leakage current
ILI
VIN=Vss to Vcc
-1
-
1
µA
Output leakage current
ILO
CS=VIH, ZZ=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc
-1
-
1
µA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V,
ZZ≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
-
-
7
mA
ICC2
Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH,
VIN=VIL or VIH
-
35
mA
VOL
IOL=2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH=-1.0mA
2.4
-
-
V
Standby Current(CMOS)
ISB12)
CS≥Vcc-0.2V, ZZ≥Vcc-0.2V, Other inputs=Vss to Vcc
-
-
80
µA
Average operating current
Output low voltage
1. Typical values are tested at VCC=2.9V, TA=25°C and not guaranteed.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
AC OPERATING CONDITIONS
Dout
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load: CL=50pF
CL
1. Including scope and jig capacitance
AC CHARACTERISTICS(Vcc=2.7~3.1V, TA=-40 to 85°C)
Speed Bin
Parameter List
Symbol
Min
Read
Write
Units
70ns1)
Max
Read Cycle Time
tRC
70
-
ns
Address Access Time
tAA
-
70
ns
Chip Select to Output
tCO
-
70
ns
Output Enable to Valid Output
tOE
-
35
ns
UB, LB Access Time
tBA
-
70
ns
Chip Select to Low-Z Output
tLZ
10
-
ns
UB, LB Enable to Low-Z Output
tBLZ
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
ns
Chip Disable to High-Z Output
tHZ
0
25
ns
UB, LB Disable to High-Z Output
tBHZ
0
25
ns
Output Disable to High-Z Output
tOHZ
0
25
ns
Output Hold from Address Change
tOH
5
-
ns
Page Cycle
tPC
25
-
ns
Page Access Time
tPA
-
20
ns
Write Cycle Time
tWC
70
-
ns
Chip Select to End of Write
tCW
60
-
ns
Address Set-up Time
tAS
0
-
ns
Address Valid to End of Write
tAW
60
-
ns
UB, LB Valid to End of Write
tBW
60
-
ns
Write Pulse Width
tWP
551)
-
ns
Write Recovery Time
tWR
0
-
ns
Write to Output High-Z
tWHZ
0
25
ns
Data to Write Time Overlap
tDW
30
-
ns
Data Hold from Write Time
tDH
0
-
ns
End Write to Output Low-Z
tOW
5
-
ns
1. tWP(min) =70ns for continuous write operation over 50 times.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ
Data out
tOHZ
tLZ
High-Z
Data Valid
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
A20~A2
Valid
Address
A1~A0
Valid
Address
Valid
Address
tAA
Valid
Address
Valid
Address
tPC
CS1
CS2
tCO
OE
tPA
tOE
DQ15~DQ0
High Z
Data
Valid
tOHZ
Data
Valid
Data
Valid
Data
Valid
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW
tWR
CS1
CS2
tAW
tBW
UB, LB
tWP
WE
tAS
Data in
tDW
High-Z
tDH
tWHZ
Data out
High-Z
Data Valid
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tAS
tWR
tCW
CS1
tAW
CS2
tBW
UB, LB
tWP
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS
tWR
tCW
CS1
tAW
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
tWR
tCW
CS1
tAW
CS2
tBW
UB, LB
tAS
tWP
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
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Revision 0.0
December 2003
Preliminary
K1S16161CA
UtRAM
PACKAGE DIMENSION
Unit: millimeters
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
Bottom View
B
B1
B
6
5
4
3
2
1
A
#A1
B
C
C
C
C1
D
C1/2
E
F
G
H
B/2
Detail A
Side View
A
Y
0.55/Typ.
E1
E
0.35/Typ.
E2
D
C
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
1. Bump counts: 48(8 row x 6 column)
B1
-
3.75
-
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
C
7.90
8.00
8.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
-
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.10
Notes.
3. All tolerence are ±0.050 unless
specified beside figures.
4. Typ : Typical
5. Y is coplanarity: 0.10(Max)
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Revision 0.0
December 2003