MTD20N06V Power Field Effect Transistor N−Channel DPAK This device is a new technology designed to achieve an on−resistance area product about one−half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 V devices. This device is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 60 V 65 mW 20 A N−Channel D Features • On−resistance Area Product about One−half that of Standard G S MARKING DIAGRAM Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc Gate−to−Source Voltage − Continuos − Non−repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 25 Vdc Vpk ID ID 20 13 70 Adc PD 60 0.4 2.1 Watts W/°C Watts Operating and Storage Temperature Range TJ, Tstg −55 to 175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 Ω) EAS 200 mJ Thermal Resistance − Junction to Case − Junction to Ambient (Note 1) − Junction to Ambient (Note 2) RθJC RθJA RθJA 2.5 100 71.4 °C/W TL 260 °C Rating Drain Current − Continuous − Continuous @ 100°C − Single Pulse (tp ≤ 10 μs) Total Power Dissipation Derate above 25°C Total Power Dissipation @ 25°C (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds IDM 4 Drain 4 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Apk 1 2 YWW T20 N06V • • • • MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than Predecessors Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Surface Mount Package Available in 16 mm 13−inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number 3 DPAK CASE 369C (Surface Mount) Style 2 T20N06V Y WW 2 1 Drain 3 Gate Source = Device Code = Year = Work Week ORDERING INFORMATION Package Shipping† MTD20N06V DPAK 75 Units/Rail MTD20N06VT4 DPAK 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size. © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 5 1 Publication Order Number: MTD20N06V/D MTD20N06V ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 − − 69 − − − − − − 10 100 − − 100 2.0 − 2.8 5.0 4.0 − − 0.065 0.080 − − − − 2.0 1.9 gFS 6.0 8.0 − mhos pF OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Cpk ≥ 2.0) (3) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C μAdc nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) (Cpk ≥ 2.0) (3) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 10 Adc) (Cpk ≥ 2.0) (3) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 10 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C) VGS(th) RDS(on) VDS(on) Forward Transconductance (VDS = 6.0 Vdc, ID = 10 Adc) Vdc mV/°C Ohm Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 590 830 Coss − 180 250 Crss − 40 80 td(on) − 8.7 20 SWITCHING CHARACTERISTICS (2) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc, RG = 9.1 Ω) Fall Time Gate Charge (VDS = 48 Vdc, ID = 20 Adc, VGS = 10 Vdc) tr − 77 150 td(off) − 26 50 tf − 46 90 QT − 28 40 Q1 − 4.0 − Q2 − 9.0 − Q3 − 8.0 − − − 1.05 0.96 1.6 − trr − 60 − ta − 52 − tb − 8.0 − QRR − 0.172 − − − 3.5 4.5 − − − 7.5 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (1) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) Reverse Recovery Stored Charge VSD Vdc ns μC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS (1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. (3) Reflects typical values. Max limit − Typ Cpk = 3 x SIGMA http://onsemi.com 2 nH nH MTD20N06V TYPICAL ELECTRICAL CHARACTERISTICS 8V I D , DRAIN CURRENT (AMPS) 35 30 7V 25 20 6V 15 10 5V 5 4V 1 3 2 4 5 6 7 9 8 20 15 10 2 0.1 25°C 0.08 0.06 - 55°C 0.04 0.02 6 7 5 10 15 25 20 30 ID, DRAIN CURRENT (AMPS) 35 40 8 9 0.11 TJ = 25°C 0.1 0.09 0.08 VGS = 10 V 0.07 0.06 15 V 0.05 0.04 0 Figure 3. On−Resistance versus Drain Current and Temperature 10 5 20 30 15 25 ID, DRAIN CURRENT (AMPS) 35 40 Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.0 35 VGS = 0 V VGS = 10 V ID = 10 A 30 1.5 I DSS , LEAKAGE (nA) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 5 Figure 2. Transfer Characteristics TJ = 100°C 1.25 1 0.75 0.5 TJ = 125°C 25 20 15 10 100°C 5 0.25 0 -50 4 Figure 1. On−Region Characteristics 0.12 1.75 3 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VGS = 10 V 0 100°C 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.14 0 25°C 30 0 10 0.18 0.16 TJ = -55°C 5 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0 VDS ≥ 10 V 35 TJ = 25°C 0 R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 40 9V VGS = 10V I D , DRAIN CURRENT (AMPS) 40 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 0 175 0 Figure 5. On−Resistance Variation with Temperature 50 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 60 MTD20N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at Switching behavior is most easily modeled and predicted a voltage corresponding to the off−state condition when by recognizing that the power MOSFET is charge calculating td(on) and is read at a voltage corresponding to the controlled. The lengths of various switching intervals (Δt) on−state when calculating td(off). are determined by how fast the FET input capacitance can be charged by current from the generator. At high switching speeds, parasitic circuit elements The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths, charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also t = Q/IG(AV) complicates the mathematics. And finally, MOSFETs have During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified. times may be approximated by the following: The resistive switching time variation versus gate tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching tf = Q2 x RG/VGSP performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would where maintain a value of unity regardless of the switching speed. VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize RG = the gate drive resistance common inductance in the drain and gate circuit loops and and Q2 and VGSP are read from the gate charge curve. is believed readily achievable with board mounted components. Most power electronic loads are inductive; the During the turn−on and turn−off delay times, gate current is data in the figure is taken with a resistive load, which not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power values from the capacitance curves in a standard equation for MOSFETs may be safely operated into an inductive load; voltage change in an RC network. The equations are: however, snubbing reduces switching losses. td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1600 VDS = 0 V C, CAPACITANCE (pF) VGS = 0 V TJ = 25°C Ciss 1400 1200 Crss 1000 800 Ciss 600 400 Coss 200 0 Crss 10 0 5 VGS 5 10 15 20 25 VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 30 9 VGS QT 27 8 24 7 21 6 18 Q2 Q1 5 15 4 12 9 3 2 1 0 TJ = 25°C ID = 20 A Q3 VDS 0 5 10 15 20 25 6 3 0 30 1000 t, TIME (ns) 10 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) MTD20N06V TJ = 25°C ID = 20 A VDD = 30 V VGS = 10 V 100 tr tf td(off) 10 td(on) 1 1 10 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 1 DRAIN−TO−SOURCE DIODE CHARACTERISTICS 20 I S , SOURCE CURRENT (AMPS) 18 TJ = 25°C VGS = 0 V 16 14 12 10 8 6 4 2 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance The Forward Biased Safe Operating Area curves define dissipated in the transistor while in avalanche must be less the maximum simultaneous drain−to−source voltage and than the rated limit and adjusted for operating conditions drain current that a transistor can handle safely when it is differing from those specified. Although industry practice is forward biased. Curves are based upon maximum peak to rate in terms of energy, avalanche energy capability is not junction temperature and a case temperature (TC) of 25°C. a constant. The energy rating decreases non−linearly with an Peak repetitive pulsed power limits are determined by using increase of peak current in avalanche and peak junction the thermal response data in conjunction with the procedures temperature. discussed in AN569, “Transient Thermal Although many E−FETs can withstand the stress of Resistance−General Data and Its Use.” drain−to−source avalanche at currents up to rated pulsed Switching between the off−state and the on−state may current (IDM), the energy rating is specified at rated traverse any load line provided neither rated peak current continuous current (ID), in accordance with industry (IDM) nor rated voltage (VDSS) is exceeded and the custom. The energy rating must be derated for temperature transition time (tr,tf) do not exceed 10 μs. In addition the total as shown in the accompanying graph (Figure 12). Maximum power averaged over a complete switching cycle must not energy at currents below rated continuous ID can safely be exceed (TJ(MAX) − TC)/(RθJC). assumed to equal the values indicated. A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 5 MTD20N06V SAFE OPERATING AREA 200 VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 10 μs 10 100 μs 1 ms 10 ms dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT ID = 20 A 180 160 140 120 100 80 60 40 20 0 0.1 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 25 100 50 75 100 125 175 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 P(pk) 0.10 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RθJC(t) 1.0E+00 1.0E+01 MTD20N06V PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C−01 ISSUE D A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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