TI1 DLPR100 Dlpâ® configuration prom for dlpc100 Datasheet

DLPR100
www.ti.com
DLPS020 – DECEMBER 2009
®
DLP Configuration PROM for DLPC100
Check for Samples: DLPR100
FEATURES
1
•
•
•
•
•
Programmed for Use With the DLPC100 and DLP1700 (0.17 HVGA Chipset)
Data Transfer up to 150 M-Bits/Second
Single 2.7 to 3.6 V Supply
5 mA Active-Current, 1-μA Powerdown (Typ)
–40°C to 85°C Operating Temperature Range
DESCRIPTION
The DLPR100 is one of three components in the 0.17 HVGA chipset (see Block Diagram). Proper function and
operation of the DLPR100 requires that it be used in conjunction with the other components of the 0.17 HVGA
chipset. Refer to the 0.17 HVGA Chip-Set data sheet for further details (TI Literature Number DLPS017).
The serial flash device provides a storage solution for the DLPC100 device in the 0.17 HVGA chipset. The
device operates on a single 2.7 V to 3.6 V power supply with current consumption as low as 5 mA active and 1
µA for power-down. The DLPR100 supports the standard Serial Peripheral Interface (SPI). SPI clock frequencies
of up to 75 MHz are supported.
ORDERING INFORMATION
TA
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
DLPR100DWC
By Pin 1
CS
1
8
VCC
DO
2
7
HOLD
WP
3
6
CLK
GND
4
5
DIO
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NO.
NAME
1
CS
I
Chip select, active low. When CS is high, the device is deselected and DO pin is high
impedance.
2
DO
O
Data output. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
3
WP
I
Write protect input, active low. Disables writes to the status register when the Status Register
Protect (SRP) bit is set to a 1 state.
4
GND
–
Ground
5
DIO
I/O
6
CLK
I
Serial clock. Provides the timing clock for the serial input and output operation.
7
HOLD
I
Hold input, active low. Allows the device to be paused. When HOLD is brought low, while CS
is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will be
ignored. Device operation will resume when HOLD is brought high.
8
VCC
–
Power supply
Data input/output. Data is latched on the rising edge of the CLK input pin.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DLPR100
DLPS020 – DECEMBER 2009
www.ti.com
Related Documents
DOCUMENT
TI LITERATURE NUMBER
DLP 0.17 HVGA Chip-Set data sheet
DLPS017
DLPC100 Digital Controller data sheet
DLPS019
DLP1700 0.17 HVGA DMD data sheet
DLPS018
Block Diagram
24-bit RGB DATA
Digital Video
VSYNC
DVI
Receiver
HSYNC
2
I2C
5VDC
2
Control
I2C
MSP430
Voltage Control
Voltage
Regulator
Control
RED STROBE
DLPR100
Configuration
DLPC100
Illumination
Optics
GREEN STROBE
Projection
Optics
BLUE STROBE
LED
RED PWM
DLP1700
Driver
GREEN PWM
BLUE PWM
OSC
2
Mobile
SDR
Memory
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
DLPR100
www.ti.com
DLPS020 – DECEMBER 2009
1FFFFFh
•
1F00FFh
Block 31(64KB)
1FFFFFh
•
1F00FFh
•
•
•
•
00FFFFh
•
0000FFh
Block 0(64KB)
Beginning
page address
00FFFFh
•
0000FFh
Ending
page address
Figure 1. Memory Blocks of the DLPR100
Functional Description
The memory blocks of the DLPR100 are shown in Figure 1.
SPI Operation
The DLPR100 is accessed through an SPI compatible bus. Data input on the DIO pin is sampled on the rising
edge of the CLK. Data on the DO and DIO pins are clocked out on the falling edge of the CLK.
Write Protection
Upon power-up or at power-down the DLPR100 will maintain a reset condition while VCC is below the threshold
value of VWI. While reset, all operations are disabled and no instructions are recognized. During power-up and
after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time of
tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write
Status Register instructions. Note that the chip select pin (CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached. If needed a pull-up resistor on CScan be used to accomplish
this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a write operation will be
accepted. After completing a write operation the Write Enable Latch (WEL) is automatically cleared to a
write-disabled status of 0. Software controlled write protection is facilitated using the Write Status Register
instruction and setting the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored
except for the Released Power-down instruction.
Control and Status Registers
The Read Status Register instruction can be used to provide status on the availability of the Flash memory array,
if the device is write enabled/disabled, and the state of write protect. The Write Status Resister instruction can be
used to configure the device’s write protection feature.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
3
DLPR100
DLPS020 – DECEMBER 2009
www.ti.com
Status Register
Busy
Busy is a read only status register (S0) that is set to 1 state when the device is executing a write operation.
When write operation is completed the BUSY bit will be cleared to a 0 state indicating the device is ready for
further instructions.
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write disable state
occurs upon power-up.
Block Protect Bits (BP2, BP1, BP0)
Block Protect Bits are non-volatile read/write bits in the status register (S4,S3,S2) that provide Write Protection
control and status. Block Protect bits can be set using the Write Status Register instruction. The factory default
setting for the Block Protect bits is 0, none of the array protected. The Block Protect bits cannot be written to if
the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.
Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the block protect bits (BP2,BP1,BP0) protect from the Top (TB=0) or the
Bottom (TB=1) of the array. Factory default setting is TB=0. The TB bit cannot be written to if the Status Register
Protect (SRP) bit is set to 1 and Write Protect (/WP) pin is low.
Reserved Bits
Status register bit location S6 is reserved for the future use. Device will read 0 for this bit.
Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a read/write bit in status register (S7) that can be used in conjunction
with the Write Protect (WP) pin to disable writes to the status register. When the SRP bit is set to 0 state (factory
default) the WP pin has no control over Status Register. When the SRP bit is set to a 1 state, the Write Status
Register is locked out while the WP pin is low. When the WP pin is high the Write Status Register instruction is
allowed.
Table 1. Status Register Bit Locations
S7
S6
S5
S4
S3
S2
S1
S0
SRP
(R)
TB
BP2
BP1
BP0
WEL
BUSY
Table 2. Status Register Memory Protection
STATUS REGISTER
BP2
BP1
BP0
BLOCK(S)
ADDRESSES
DENSITY
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
1
31
1F0000h-1FFFFFh
64KB
Upper 1/32
0
0
1
0
30 thru 31
1E0000h-1FFFFFh
128KB
Upper 1/16
0
0
1
1
28 thru 31
1C0000h-1FFFFFh
256KB
Upper 1/8
0
1
0
0
24 thru 31
180000h-1FFFFFh
512KB
Upper 1/4
0
1
0
1
16 thru 31
100000h-1FFFFFh
1MB
Upper 1/2
1
0
0
1
0
000000h-00FFFFh
64KB
Lower 1/32
1
0
1
0
0 and 1
000000h-01FFFFh
128KB
Lower 1/16
1
0
1
1
0 thru 3
000000h-03FFFFh
256KB
Lower 1/8
1
1
0
0
0 thru 7
000000h-07FFFFh
512KB
Lower 1/4
1
1
0
1
0 thru 15
000000h-0FFFFFh
1MB
Lower 1/2
(1)
4
MEMORY PROTECTION
TB (1)
PORTION
x = don’t care
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
DLPR100
www.ti.com
DLPS020 – DECEMBER 2009
Table 2. Status Register Memory Protection (continued)
STATUS REGISTER
TB
x
(1)
MEMORY PROTECTION
BP2
BP1
BP0
BLOCK(S)
ADDRESSES
DENSITY
PORTION
1
1
X
0 thru 31
000000h-1FFFFFh
2MB
ALL
Instructions
The instruction set of the DLPR100 consists of fifteen basic instructions that are fully controlled through the SPI
bus. Instructions are initiated by the falling edge of the Chip Select (CS). The first byte of data clocked into the
DIO input provides the instruction code. Data on the DIO input is sampled on the rising edge of the clock with
most significant bit (MSB) first. Instructions are completed with the rising edge of CS.
Table 3. Manufacturer and Device Identification
MANUFACTURER ID
(M7-M0)
Winbond Serial Flash
EFH
DEVICE ID
(ID7-ID0)
INSTRUCTION
ABh, 90h
9Fh
W25X16A
14h
3015h
(ID15-ID0)
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
5
DLPR100
DLPS020 – DECEMBER 2009
www.ti.com
Table 4. Instruction Set (1)
INSTRUCTION
NAME
BYTE1
CODE
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
N-BYTES
Write Enable
06h
Write Disable
04h
Read Status Register
05h
Write Status Register
01h
S7–S0
Read Data
03h
A23–A16
A15–A8
A7–A0
(D7–D0)
(Nest byte)
Continuous
Fast Read
0Bh
A23–A16
A15–A8
A7–A0
dummy
(D7–D0)
(Nest byte)
continuous
Fast Read Dual Output
3Bh
A23–A16
A15–A8
A7–A0
dummy
I/O=(D6,D4,D2
,D0)
O=(D7,D5,D3,
D1)
(one byte per 4
clocks cont.)
(D7–D0)
(Nest byte)
Up to 256 bytes
(S7–S0) (1)
See
Page Program
02h
A23–A16
A15–A8
A7–A0
Block Erase (64KB)
D8h
A23–A16
A15–A8
A7–A0
Sector Erase (4KB)
20h
A23–A16
A15–A8
A7–A0
Chip Erase
C7h
Power-down
B9h
Release
Power-down/Device ID
ABh
dummy
dummy
dummy
(ID7–ID0) (3)
Manufacturer/Device
ID (4)
90h
dummy
dummy
00h
(M7–M0)
JEDEC ID
9Fh
(M7–M0)
Manufacturer
(ID15–ID8)
Memory Type
(ID7–ID0)
Capacity
(1)
(2)
(3)
(4)
(2)
(ID7–ID0)
Data bytes are shifted with Most significant Bit first. Byte fields with data in parenthesis indicate data being read from the device on the
DO pin.
The status register contents will repeat continuously until CS terminates the instruction
The Device ID will repeat continuously until CS terminates the instruction
See Manufacturer and Device ID table for Device ID information
DLPR100 instruction example using the Read data (03h) instruction is shown in Figure 2.
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the CSpin low and then shifting the instruction code “03h” followed by a 24-bit
address (A23–A0) into the DIO pin. The code and address bits are latched in the rising edge of the CLK pin.
After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at
the falling edge of the CLK with most significant bit (MSB) first. The address is automatically incremented to the
next higher address after each byte of data is shifted out allowing for a continuous stream of data. The entire
memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by
driving the CS high. If a Read Data instruction is issued while a write operation is in process the instruction is
ignored and will not have any effect on the current operation.
6
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
DLPR100
www.ti.com
DLPS020 – DECEMBER 2009
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
CLK
Instruction(03h)
24-bit address
DIO
Data Out 1
High impedance
DO
7
6
5
4
3
Data Out 1
2
1
0
7
Figure 2. Read Data Instruction Sequence Diagram
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
Supply voltage
VIO
Voltage applied to any pin
VIOT
Transient voltage on any pin
Tstg
Storage temperature
TLEAD
Lead temperature
VESD
(1)
(2)
(3)
CONDITIONS
MIN
MAX
–0.6
4.0
V
Relative to ground
–0.6
VCC + 0.4
V
<20 ns transient relative to ground
–2.0
VCC + 2.0
V
–65
150
°C
(2)
°C
2000
V
See
Electrostatic discharge voltage
Human Body Model
(3)
–2000
UNIT
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Compliant with JEDEC standards J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on
restrictions on hazardous substance (RoHS) 2002/95/EU.
JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
VCC
Supply voltage
TA
Ambient operating temperature
MIN
MAX
Fr = 50MHz, fR = 33 MHz
2.3
3.6
Fr = 75 MHz, fR = 33 MHz
2.7
3.6
Industrial
–40
85
MIN
MAX
UNIT
V
°C
POWER-UP TIMING AND WRITE INHIBIT THRESHOLD (1)
PARAMETER
UNIT
tVSL
VCC(min) to CS low
tPUW
Time delay before write instruction
1
10
ms
VWI
Write inhibit threshold voltage
1
2
V
(1)
10
µs
Parameters are characterized only
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
7
DLPR100
DLPS020 – DECEMBER 2009
www.ti.com
VCC
VCC(max)
Program, erase, and write functions ignored
CS must track VCC
VCC(min)
reset
state
tVSL
read instruction allowed
Device fully accessible
VWI
tPUW
time
Figure 3. Power-Up Timing and Voltage Levels
DC ELECTRICAL CHARACTERISTICS
PARAMETER
(1)
CIN
Input capacitance
Cout
Output capacitance (1)
ILI
CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 0 V
6
VOUT = 0 V
8
pF
Input leakage
±2
µA
ILO
I/O leakage
±2
µA
ICC1
Standby current
CS = VCC, VIN = GND or VCC
25
50
µA
ICC2
Power-down current
CS = VCC, VIN = GND or VCC
<1
10
µA
ICC3
Current read data/dual output
read (2)
C = 0.1 VCC/0.9 VCC DO =
open
5/6
7/8
mA
33 MHz
7/8
11/12
mA
50 MHz
9/10
13/15
mA
75 MHz
11/12
16/18
mA
1 MHz
pF
ICC4
Current page program
CS = VCC
20
25
mA
ICC5
Current Write Status Register
CS = VCC
10
18
mA
ICC6
Current sector/block erase
CS = VCC
20
25
mA
ICC7
Current chip erase
CS = VCC
20
25
mA
VIL
Low-level input voltage
–0.5
VCC x 0.3
V
VIH
High-level input voltage
VCC x 0.7
VCC + 0.4
V
VOL
Low-level output voltage
IOL = 1.6 mA
0.4
V
VOH
High-level output voltage
IOH = –100 µA
(1)
(2)
VCC - 0.7
V
Tested on sample basis and specified through design and characterization data TA= 25°C, VCC = 3.0 V
Checker board pattern
AC ELECTRICAL CHARACTERISTICS
VCC = 2.3 V to 3.6 V unless otherwise specified
MAX
UNIT
FR
SYMBOL
fC
Clock frequency for all instructions, except read data(03h) 2.3–3.6
V VCC
50
MHz
FR
fC
Clock frequency for all instructions, except read data(03h) 2.7–3.6
V VCC
75
MHz
Clock frequency read data(03h)
33
MHz
fR
8
ALT
DESCRIPTION
Submit Documentation Feedback
MIN
TYP
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
DLPR100
www.ti.com
DLPS020 – DECEMBER 2009
AC ELECTRICAL CHARACTERISTICS (continued)
VCC = 2.3 V to 3.6 V unless otherwise specified
SYMBOL
ALT
DESCRIPTION
MIN
tCLH, tCLL
Clock high, low time, for fast read(0Bh, 3Bh)/other instructions
except read data (03h) (1)
tCLH, tCLL
tCRLH, tCRLL
Clock high, low time, for all instructions 2.3 V-3.6 V VCC (1)
8
ns
Clock high, low time, for read data(03h) instructions (1)
8
ns
(2)
Clock rise time peak to peak
Clock fall time peak to peak (2)
tCHSL
UNIT
ns
tCHCL
tCSS
MAX
6/7
tCLCH
tSLCH
TYP
0.1
V/ns
0.1
V/ns
CS active setup time relative to CLK
5
ns
CS Not active Hold time relative to CLK
5
ns
tDVCH
tDSU
Data in setup time
2
ns
tCHDX
tDH
Data in hold time
5
ns
CS active hold time relative to CLK
5
ns
5
ns
50/100
ns
tCHSH
tSHCH
CS not active setup time relative to CLK
tSHSL
tCSH
CS deselect time (for array read->array read/erase or
program->Read Status Register)
tSHQZ
tDIS
Output disable time (3)
tCLQV
tV
Clock low to output valid 2.7–3.6 V/ 3.0–3.6 V/ 2.3-3.6V
tCLQX
tOH
Output hold time
0
ns
tHLCH
HOLD active setup time relative to CLK
5
ns
tCHHH
HOLD active Hold time relative to CLK
5
ns
tHHCH
HOLD Not active setup time relative to CLK
5
ns
tCHHL
HOLD Not active Hold time relative to CLK
5
ns
(3)
tHHQX
tLZ
HOLD to output low-Z
tHLQZ
tHZ
HOLD to output high-Z
tWHSL
(3)
Write protect setup time before CS low (4)
7
ns
7/6/9
ns
7
ns
12
ns
20
(4)
tSHWL
Write protect Hold time after CS high
tDP
CS high to power-down mode (3)
tRES1
CS high to standby mode without electronic signature Read (3)
ns
100
ns
(3)
3
µs
3
µs
tRES2
CS high to standby mode with electronic signature Read
1.8
µs
tW
Write Status Register time
10
15
ms
tBP1
Byte program time (first byte) (5)
30
50
µs
tBP2
Additional byte program time (after first byte) (5)
6
12
µs
tPP
Page program time
1.6
3
ms
tSE
Sector erase time (4KB)
120
200
ms
tBE
Block erase time (64KB)
0.32
1
s
tCE
Chip erase time
10
20
s
(1)
(2)
(3)
(4)
(5)
Clock high + clock low must be less than or equal to 1/fC.
Value ensured by design and/or characterization, not production tested.
Value ensured by design and/or characterization, not production tested.
Only applicable as a constraint for Write Status Register instruction when Sector Protect Bit is set to 1.
For multiple bytes after the first byte within a page, tBPN = tBP1 + tBP2 * N(typical) and tBPN = tBP1 + tBP2 * N(max), where N = number of
bytes programmed
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
9
DLPR100
DLPS020 – DECEMBER 2009
www.ti.com
Serial Output Timing
CS
tCH
tCL
CLK
tCLQV
tCLQV
tSHQZ
tCLQX
tCLQX
LSB Out
DO/DIO
tQLQH
tQHQL
Input Timing
tSHSL
CS
tCHSL
tSLCH
CLK
tDVCH
DIO
tSHCH
tCHDX
tCLCH
tCHCL
LSB In
MSB In
High impedance
DO
10
tCHSH
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
DLPR100
www.ti.com
DLPS020 – DECEMBER 2009
HOLD Timing
CS
tCHHH
tCHHL
tHLCH
tHHCH
CLK
tHLQZ
tHHQX
DIO
DO
HOLD
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
11
DLPR100
DLPS020 – DECEMBER 2009
www.ti.com
Table 5. Revision History
12
REVISION
SECTION(S)
COMMENT
*
All
Initial release
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DLPR100
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2011
PACKAGING INFORMATION
Orderable Device
DLPR100DWC
Status
(1)
ACTIVE
Package Type Package
Drawing
SOIC
DWC
Pins
Package Qty
8
1
Eco Plan
(2)
Pb-Free (RoHS)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
POST-PLATE Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and Automotive www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
www.ti.com/video
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated