A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Features and Benefits Description ▪ Customer programmable offset, sensitivity, sensitivity temperature coefficient, and polarity ▪ Programmability at end-of-line ▪ Ratiometric sensitivity, quiescent voltage output, and clamps for interfacing with application DAC ▪ Temperature-stable quiescent voltage output and sensitivity ▪ Precise recoverability after temperature cycling ▪ Output voltage clamps provide short circuit diagnostic capabilities ▪ Wide ambient temperature range: –40°C to 150°C ▪ Immune to mechanical stress ▪ Miniature package options New applications for linear output Hall effect sensing, such as displacement, angular position, and current measurement, require high accuracy in conjunction with small package size. The Allegro® A138x family of programmable linear Hall effect sensor ICs was designed specifically to achieve both goals. These temperature-stable devices are available in a miniature surface mount package (SOT23-W) and an ultramini throughhole single-in-line package. The accuracy of these devices is enhanced via programmability on the output pin for end-of-line optimization without the added complexity and cost of a fully programmable device. Packages: 3 pin SOT23W (suffix LH), and 3 pin SIP (suffix UA) These ratiometric Hall effect devices provide a voltage output that is proportional to the applied magnetic field. Both the quiescent voltage output and magnetic sensitivity are useradjustable. The quiescent voltage output can be set around 50% of the supply voltage, and the sensitivity adjusted between 2 mV/G and 9 mV/G over the device family. Programming selections also exist for output polarity and temperature compensation. The features of this linear family make it ideal for high accuracy requirements of automotive and industrial applications, and performance is guaranteed over an extended temperature range, –40°C to 150°C. Continued on the next page… Not to scale Functional Block Diagram V+ CBYPASS Amp Filter To all subcircuits Dynamic Offset Cancellation VCC Out Hall Drive Circuit Gain Gain Temperature Coefficient Trim Control GND A1381-DS, Rev. 9 Offset VOUT (Programming) A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Description (continued) Each BiCMOS monolithic circuit integrates a Hall element, temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the Hall element, a small-signal high-gain amplifier, a clamped low-impedance output stage, and a proprietary dynamic offset cancellation technique. The A138x devices are provided in a 3 pin ultramini single-in-line package (UA suffix), and a 3 pin surface mount SOT-23W package (LH suffix). Selection Guide Packing1 Part Number TA (°C) Package Internal Bandwidth (kHz) Sensitivity Range (mV/G) A1381ELHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 85 A1381EUA-T Bulk bag, 500 pieces/bag Through hole 12 6.00 to 9.00 A1381LLHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 150 A1381LUA-T Bulk bag, 500 pieces/bag Through hole A1382ELHLT-T2 Tape and reel, 3000 pieces/reel Surface mount A1382ELHLX-T2 Tape and reel, 10000 pieces/reel –40 to 85 Surface mount Bulk bag, 500 pieces/bag Through hole A1382EUA-T2 17 4.00 to 6.25 Surface mount A1382LLHLT-T2 Tape and reel, 3000 pieces/reel 2 A1382LLHLX-T Tape and reel, 10000 pieces/reel –40 to 150 Surface mount A1382LUA-T2 Bulk bag, 500 pieces/bag Through hole A1383ELHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 85 A1383EUA-T Bulk bag, 500 pieces/bag Through hole 21 2.75 to 4.25 A1383LLHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 150 A1383LUA-T Bulk bag, 500 pieces/bag Through hole A1384ELHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 85 A1384EUA-T Bulk bag, 500 pieces/bag Through hole 27 2.00 to 3.00 A1384LLHLT-T Tape and reel, 3000 pieces/reel Surface mount –40 to 150 A1384LUA-T Bulk bag, 500 pieces/bag Through hole 1Contact Allegro for additional packing options. 2Variants are in production but have been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change December 10, 2012. Deadline for receipt of LAST TIME BUY orders is May 31, 2013. Absolute Maximum Ratings Characteristic Forward Supply Voltage Reverse Supply Voltage Forward Output Voltage Reverse Output Voltage Output Source Current Output Sink Current Symbol VCC VRCC VOUT VROUT IOUT(SOURCE) IOUT(SINK) Operating Ambient Temperature TA Storage Temperature Maximum Junction Temperature Tstg TJ(max) Notes VOUT to GND VCC to VOUT Range E Range L Rating 8 –0.1 28 –0.1 2 10 –40 to 85 –40 to 150 –65 to 165 165 Units V V V V mA mA ºC ºC ºC ºC Pin-out Diagrams LH Package UA Package 3 1 2 1 2 Number Name Description LH UA 1 1 VCC Input power supply; use bypass capacitor to connect to ground 3 2 GND Ground 2 3 VOUT Output signal; also used for programming 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package OPERATING CHARACTERISTICS, valid over full operating temperature range, TA; CBYPASS= 0.1 μF, VCC = 5 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Units 4.5 5.0 5.5 V – 6.9 8 mA ELECTRICAL CHARACTERISTICS Supply Voltage VCC Supply Current ICC Power-On Time1 No load on VOUT A1381 TA = 25 °C, CBYPASS = open, CL (of test probe) = 10 pF, Sens = 7.5 mV/G – 32 – μs A1382 TA = 25 °C, CBYPASS = open, CL (of test probe) = 10 pF, Sens = 5.0 mV/G – 27 – μs A1383 TA = 25 °C, CBYPASS = open, CL (of test probe) = 10 pF, Sens = 3.125 mV/G – 23 – μs A1384 TA = 25 °C, CBYPASS = open, CL (of test probe) = 10 pF, Sens = 2.5 mV/G – 19 – μs tPO Delay to Clamp1 tCLP TA = 25°C, CL = 10 nF – 30 – μs Supply Zener Clamp Voltage VZ TA = 25°C, ICC = 11 mA 6 8.3 – V Internal Bandwidth Chopping Frequency2 BWi fC A1381 – 12 – kHz A1382 – 17 – kHz A1383 Small signal –3 dB – 21 – kHz A1384 – 27 – kHz TA = 25°C – 170 – kHz OUTPUT CHARACTERISTICS Noise (peak to peak) DC Output Resistance VN(p-p) A1381 TA=25°C; CL = 10 nF, Sens = 7.5 mV/G; no external filter – 34 – mV A1382 TA=25°C; CL = 10 nF, Sens = 5.0 mV/G; no external filter – 27 – mV A1383 TA=25°C; CL = 10 nF, Sens = 3.125 mV/G; no external filter – 20 – mV A1384 TA=25°C; CL = 10 nF, Sens = 2.5 mV/G; no external filter – 18 – mV A138x TA=25°C; Sens = 2.5 mV/G; external 2 kHz low pass filter with R = 1.69 kΩ, C = 47 nF – 4.7 – mV ROUT – <1 – Ω VOUT to VCC 4.7 – – kΩ Output Load Resistance RL VOUT to GND 4.7 – – kΩ Output Load Capacitance CL VOUT to GND – – 10 nF Phase Shift3 ∆Φ No load on VOUT, magnetic input signal frequency = 1 kHz, with 1 V(p-p) output signal – 3 – deg. Output Voltage VCLP(HIGH) TA = 25°C, B = 600 G, Sens = 5.0 mV/G, RL = 10 kΩ (VOUT to GND) 4.35 4.5 4.65 V VCLP(LOW) TA = 25°C, B = –600 G, Sens = 5.0 mV/G, RL = 10 kΩ (VCC to VOUT) 0.40 0.55 0.70 V – 175 – V/ms Clamp4 Output Slew Rate SR CL = 10 nF Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package OPERATING CHARACTERISTICS (continued), valid over full operating temperature range, TA; CBYPASS= 0.1 μF, VCC = 5 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Units – 2.1 – V PRE-PROGRAMMING TARGET5 Pre-Programming Quiescent Voltage Output VOUT(Q)init Pre-Programming Sensitivity Sensinit Pre-Programming Sensitivity Temperature Coefficient6 TCSensinit B = 0 G, TA = 25°C A1381 – 4.2 – mV/G A1382 – 2.9 – mV/G A1383 TA = 25°C – 2.1 – mV/G A1384 – 1.4 – mV/G TA = 150°C – –0.05 – %/°C 2.3 – 2.6 V – 6 – bit QUIESCENT VOLTAGE OUTPUT PROGRAMMING Guaranteed Quiescent Voltage Output Range4,7 VOUT(Q) B = 0 G, TA = 25°C Quiescent Voltage Output Programming Bits Average Quiescent Voltage Output Step Size8,9 StepVOUT(Q) TA = 25°C 8 11.5 15 mV Quiescent Voltage Output Programming Resolution10 ErrPGVOUT(Q) TA = 25°C – StepVOUT(Q) × ±0.5 – mV SENSITIVITY PROGRAMMING Guaranteed Sensitivity Range4,11 Sens A1381 6.00 – 9.00 mV/G A1382 4.00 – 6.25 mV/G A1383 TA = 25°C 2.75 – 4.25 mV/G A1384 2.00 – 3.00 mV/G – 6 – bit A1381 90 110 130 μV/G 55 75 95 μV/G Sensitivity Programming Bits Average Sensitivity Step Size8,9 StepSENS Sensitivity Programming Resolution10 A1382 A1383 TA = 25°C 35 55 75 μV/G A1384 28 35 42 μV/G ErrPGSENS TA = 25°C – StepSENS × ±0.5 – mV/G TCSens TA = 150°C 0.00 – 0.095 %/°C – 3 – bit SENSITIVITY TC PROGRAMMING Guaranteed Sensitivity Temperature Coefficient Range6 Sensitivity Temperature Coefficient Programming Bits Average Sensitivity Temperature Coefficient Step Size6 StepTCSENS TA = 150°C – 0.03 – %/°C Sensitivity Temperature Coefficient Programming Resolution6 ErrPGTCSENS TA = 150°C – StepTCSENS x ±0.5 – %/°C POL – 1 – bit LOCK – 1 – bit POLARITY PROGRAMMING Polarity Programming Bit12 LOCK BIT PROGRAMMING Overall Programming Lock Bit Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package OPERATING CHARACTERISTICS (continued), valid over full operating temperature range,TA; CBYPASS= 0.1 μF, VCC = 5 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Units LinERR – ±1.5 – % ERROR COMPONENTS Linearity Sensitivity Error Symmetry Sensitivity Error SymERR – ±1.5 – % Ratiometry Quiescent Voltage Output Error13 RatERRVOUT(Q) – ±1.5 – % Ratiometry Sensitivity Error13 RatERRSens – ±1.5 – % – ±1.5 – % – – ±60 mV – – ±50 mV – – ±40 mV – – ±40 mV – ±3 – % – ±2 – % Ratiometry Clamp Error14 RatERRCLP TA = 25°C DRIFT CHARACTERISTICS A1381 Quiescent Voltage Output Drift Through Temperature Range ∆VOUT(Q) A1382 A1383 TA = 150°C A1384 Sensitivity Drift Through Temperature Range15 ∆SensTC Sensitivity Drift Due to Package Hysteresis1 ∆SensPKG 1See TA = 25°C; after temperature cycling Characteristic Definitions section. 2f varies up to approximately ± 20% over the full C 3Unit of measure (phase degrees) in reference to operating ambient temperature range, TA, and process. the magnetic input signal. 4Sens, V OUT(Q), VCLP(LOW) , and VCLP(HIGH) scale with VCC due to ratiometry. 5Raw device characteristic values before any programming. 6Programmed at 150°C and calculated relative to 25°C. 7V OUT(Q)(max) is the value available with all programming fuses blown (maximum programming code set). The VOUT(Q) range is the total range from VOUT(Q)init up to and including VOUT(Q)(max). See Characteristic Definitions section. 8Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section. 9Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum specified value of StepVOUT(Q) , StepSENS , or StepTCSENS. 10Overall programming value accuracy. See Characteristic Definitions section. 11Sens(max) is the value available with all programming fuses blown (maximum programming code set). Sens range is the total range from Sens init up to and including Sens(max). See Characteristic Definitions section. 12Default polarity is for V OUT voltage to increase with a positive (south polarity) field applied to the branded face of the device. 13Percent change from actual value at V CC = 5 V, for a given temperature, over the guaranteed supply voltage operating range. 14Percent change from actual value at V CC = 5 V, TA = 25°C, over the guaranteed supply voltage operating range. 15Sensitivity drift from expected value at T after programming TC A SENS. See Characteristic Definitions section. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol RθJA Package Thermal Resistance Test Conditions* Value Units Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W Package LH, 2-layer PCB with 0.463 in.2 of copper area each side connected by thermal vias 110 ºC/W Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W *Additional thermal information available on Allegro website. Power Derating Curve 6 Maximum Allowable VCC (V) VCC(max) 5 1-layer PCB, Package LH (RQJA = 228 ºC/W) 1-layer PCB, Package UA (RQJA = 165 ºC/W) 2-layer PCB, Package LH (RQJA = 110 ºC/W) 4 3 VCC(min) 2 1 0 20 40 60 80 100 120 140 160 180 Temperature (ºC) Power Dissipation, PD (mW) Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 2l (R aye rP QJ C A = 11 B, P 0 º ac 1-la C/ ka W (R yer PC ) ge L QJA = B, P H 165 ack ºC/ a W) ge U A 1-lay er P (R CB, QJA = 228 Packag ºC/W e LH ) 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Characteristic Definitions Power-On Time When the supply is ramped to its operating Quiescent Voltage Output In the quiescent state (no significant voltage, the device requires a finite time to power its internal components before responding to an input magnetic field. Power-On Time, tPO , is defined as: the time it takes for the output voltage to settle within ±10% of its steady state value under an applied magnetic field, after the power supply has reached its minimum specified operating voltage, VCC(min), as shown in the following chart. magnetic field: B = 0 G), the output, VOUT(Q), has a constant ratio to the supply voltage, VCC, throughout the entire operating ranges of VCC and ambient temperature, TA. V VCC VCC(typ.) VOUT 90% VOUT Guaranteed Quiescent Voltage Output Range The quiescent voltage output, VOUT(Q), can be programmed around its nominal value of 2.5 V, within the guaranteed quiescent voltage range limits: VOUT(Q)(min) and VOUT(Q)(max). The available guaranteed programming range for VOUT(Q) falls within the distributions of the initial, VOUT(Q)init, and the maximum programming code for setting VOUT(Q), as shown in the following diagram. VOUT(Q)init(typ) VCC(min.) tPO t1 Guaranteed Output Programming Range, VOUT(Q) t2 t1= time at which power supply reaches minimum specified operating voltage t2= time at which output voltage settles within ±10% of its steady state value under an applied magnetic field 0 Distribution for VOUT(Q)init Distribution for Max Code VOUT(Q) VOUT(Q)(min) VOUT(Q)(max) +t Delay to Clamp A large magnetic input step may cause the Average Quiescent Voltage Output Step Size The average qui- clamp to overshoot its steady state value. The Delay to Clamp, tCLP , is defined as: the time it takes for the output voltage to settle within ±1% of its steady state value, after initially passing through its steady state voltage, as shown in the following chart. escent voltage output step size for a single device is determined using the following calculation: VOUT(Q)maxcode –VOUT(Q)init . StepVOUT(Q) = (1) 2n–1 Magnetic Input V where: n is the number of available programming bits in the trim range, 2n–1 is the value of the maximum programming code in the range, and VOUT(Q)maxcode is the quiescent voltage output at code 2n–1. VCLP(HIGH) VOUT tCLP t1 t2 Quiescent Voltage Output Programming Resolution The programming resolution for any device is half of its programming step size. Therefore, the typical programming resolution will be: t1= time at which output voltage initially reaches steady state clamp voltage t2= time at which output voltage settles to within 1% of steady state clamp voltage Note: Times apply to both high clamp (shown) and low clamp. 0 ErrPGVOUT(Q)(typ) = 0.5 × Step VOUT(Q)(typ) . (2) t Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Quiescent Voltage Output Drift Through Temperature Range Due to internal component tolerances and thermal considerations, the quiescent voltage output, VOUT(Q), may drift from its nominal value over the operating ambient temperature, TA. For purposes of specification, the Quiescent Voltage Output Drift Through Temperature Range, ∆VOUT(Q) (mV), is defined as: ∆VOUT(Q) = VOUT(Q)(TA) –VOUT(Q)(25°C) . (3) Sensitivity The presence of a south polarity magnetic field, perpendicular to the branded surface of the package face, increases the output voltage from its quiescent value toward the supply voltage rail (assuming that the polarity bit, POL, is in its initial state of logic 0). The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely, the application of a north polarity field decreases the output voltage from its quiescent value. This proportionality is specified as the magnetic sensitivity, Sens (mV/G), of the device, and it is defined as: Sens = VOUT(BPOS) – VOUT(BNEG) BPOS – BNEG , (4) where BPOS and BNEG are two magnetic fields with opposite polarities. Guaranteed Sensitivity Range The magnetic sensitivity, Sens, can be programmed around its nominal value, 2.5 to 7.5 mV/G depending on device type, within the sensitivity range limits: Sens(min) and Sens(max). Refer to the Guaranteed Quiescent Voltage Output Range section for a conceptual explanation of how value distributions and ranges are related. Average Sensitivity Step Size Refer to the Average Quiescent Voltage Output Step Size section for a conceptual explanation. Sensitivity Programming Resolution Refer to the Quiescent Voltage Output Programming Resolution section for a conceptual explanation. Sensitivity Temperature Coefficient Device sensitivity changes as temperature changes, with respect to its programmed sensitivity temperature coefficient, TCSENS. TCSENS is programmed at 150°C, and calculated relative to the nominal sensitivity program ming temperature of 25°C. TCSENS (%/°C) is defined as: ⎛SensT2 – SensT1 ⎞⎛ 1 ⎞ TCSens = ⎜⎜ × 100%⎟⎟ ⎜⎜T2–T1⎟⎟ Sens T1 ⎝ ⎠⎝ ⎠ , (5) where T1 is the nominal Sens programming temperature of 25°C, and T2 is the TCSENS programming temperature of 150°C. The ideal value of Sens over the full ambient temperature range, SensIDEAL(TA), is defined as: SensIDEAL(TA) = SensT1 [100% + TCSENS (TA –T1)] (6) Guaranteed Sensitivity Temperature Coefficient Range The magnetic sensitivity temperature coefficient can be programmed within its limits: TCSens(max) and TCSens(min). Refer to the Guaranteed Quiescent Voltage Output Range section for a conceptual explanation of how value distributions and ranges are related. Average Sensitivity Temperature Coefficient Step Size Refer to the Average Quiescent Voltage Output Step Size section for a conceptual explanation. Sensitivity Temperature Coefficient Programming Resolution Refer to the Quiescent Voltage Output Programming Resolution section for a conceptual explanation. Sensitivity Drift Through Temperature Range Second order sensitivity temperature coefficient effects cause the magnetic sensitivity, Sens, to drift from its ideal value over the operating ambient temperature range, TA. For purposes of specification, the sensitivity drift through temperature range, ∆SensTC, is defined as: SensTA – SensIDEAL(TA) ∆SensTC = × 100% . (7) SensIDEAL(TA) Sensitivity Drift Due to Package Hysteresis Package stress and relaxation can cause the device sensitivity at TA = 25°C to change during and after temperature cycling. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package For purposes of specification, the sensitivity drift due to package hysteresis, ∆SensPKG, is defined as: Sens(25°C)2 – Sens(25°C)1 ∆SensPKG = × 100% Sens(25°C)1 (8) , where Sens(25°C)1 is the programmed value of sensitivity at TA Symmetry error, SymERR (%), is measured and defined as: ⎛ SensBPOS SymERR = ⎜⎜1– ⎝ SensBNEG ⎞ ⎟⎟ × 100% ⎠ , (12) where SensBx is as defined in equation 10, and BPOS and BNEG = 25°C, and Sens(25°C)2 is the value of sensitivity at TA = 25°C, are positive and negative magnetic fields such that |BPOS| = |BNEG|. after temperature cycling TA up to 150°C, down to –40°C, and Ratiometry Error The A138x devices feature ratiometric output. back to up 25°C. This means that the quiescent voltage output, VOUT(Q) , magnetic Linearity Sensitivity Error The 138x family is designed to provide a linear output in response to a ramping applied magnetic field. Consider two magnetic fields, B1 and B2. Ideally, the sensitivity of a device is the same for both fields, for a given supply voltage and temperature. Linearity error is present when there is a the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same in the supply voltage relative to 5 V, and the measured change in Linearity Error is calculated separately for the positive (LinERRPOS) and negative (LinERRNEG ) applied magnetic fields. Linearity error (%) is measured and defined as: each characteristic. The ratiometric error in quiescent voltage output, RatERRVOUT(Q) ⎛ SensBPOS2 ⎞ ⎟⎟ × 100% LinERRPOS = ⎜⎜1– ⎝ SensBPOS1 ⎠ , ⎛ SensBNEG2⎞ ⎟⎟ × 100% LinERRNEG = ⎜⎜1– ⎝ SensBNEG1⎠ , (%), for a given supply voltage, VCC, is defined as: (9) ⎛ VOUT(Q)(VCC) / VOUT(Q)(5V) ⎞ ⎟⎟ × 100% RatERRVOUT(Q) = ⎜⎜1– VCC / 5 V ⎝ ⎠ . (13) The ratiometric error in magnetic sensitivity, RatERRSens (%), for where: |VOUT(Bx) – VOUT(Q)| Bx are proportional to the supply voltage, VCC. In other words, when percentage. Error is the difference between the measured change difference between the sensitivities measured at B1 and B2. SensBx = sensitivity, Sens, and clamp voltage, VCLP(HIGH) and VCLP(LOW), a given supply voltage, VCC, is defined as: (10) , and BPOSx and BNEGx are positive and negative magnetic fields, ⎛ Sens(VCC) / Sens(5V) ⎞ ⎟⎟ × 100% RatERRSens = ⎜⎜1– VCC / 5 V ⎝ ⎠ . (14) with respect to the quiescent voltage output such that The ratiometric error in the clamp voltages, RatERRCLP (%), for a |BPOS2| > |BPOS1| and |BNEG2| > |BNEG1|. Then: given supply voltage, VCC, is defined as: LinERR = max( |LinERRPOS | , |LinERRNEG | ) . (11) Symmetry Sensitivity Error The magnetic sensitivity of an A138x device is constant for any two applied magnetic fields of equal magnitude and opposite polarities. ⎛ VCLP(VCC) / VCLP(5V) ⎞ ⎟⎟ × 100% RatERRCLP = ⎜⎜1– VCC / 5 V ⎝ ⎠ . (15) where VCLP is either VCLP(HIGH) or VCLP(LOW). Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Typical Application Drawing V+ VCC VOUT CL CBYPASS GND Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall element. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented Allegro technique, namely Dynamic Quadrature Offset Cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. The chopper stabilization technique uses a 170 kHz high frequency clock. For the demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency (340 kHz). This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and Precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sampleand-hold circuits. Regulator Clock/Logic Amp Sample and Hold Hall Element Low-Pass Filter Concept of Chopper Stabilization Technique 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Programming Guidelines Overview Definition of Terms Programming is accomplished by sending a series of input voltage pulses serially through the VOUT pin of the device. A unique combination of different voltage level pulses controls the internal programming logic of the device to select a desired programmable parameter and change its value. There are two programming pulses, referred to as a high voltage pulse, VPH, consisting of a VP(LOW) –VP(HIGH) –VP(LOW) sequence and a mid voltage pulse, VPM, consisting of a VP(LOW) –VP(MID) –VP(LOW) sequence. Register. The section of the programming logic that controls the choice of programmable modes and parameters. The 138x features Try mode, Blow mode, and Lock mode: • In Try mode, the value of a single programmable parameter may be set and measured. The parameter value is stored temporarily, and resets after cycling the supply voltage. Note that other parameters cannot be accessed simultaneously in this mode. • In Blow mode, the value of a single programmable parameter may be permanently set by blowing solid-state fuses internal to the device. Additional parameters may be blown sequentially. • In Lock mode, a device-level fuse is blown, blocking the further programming of all parameters. The programming sequence is designed to help prevent the device from being programmed accidentally; for example, as a result of noise on the supply line. Although any programmable variable power supply can be used to generate the pulse waveforms, Allegro highly recommends using the Allegro Sensor IC Evaluation Kit, available on the Allegro Web site On-line Store. The manual for that kit is available for download free of charge, and provides additional information on programming these devices. Bit Field. The internal fuses unique to each register, represented as a binary number. Incrementing the bit field of a particular register causes its programmable parameter to change, based on the internal programming logic. Key. A series of VPM voltage pulses used to select a register, with a value expressed as the decimal equivalent of the binary value. The LSB of a register is denoted as key 1, or bit 0. Code. The number used to identify the combination of fuses activated in a bit field, expressed as the decimal equivalent of the binary value. The LSB of a bit field is denoted as code 1, or bit 0. Addressing. Incrementing the bit field code of a selected register by serially applying a pulse train through the VOUT pin of the device. Each parameter can be measured during the addressing process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent. Fuse Blowing. Applying a VPH voltage pulse of sufficient duration at the VP(HIGH) level to permanently set an addressed bit by blowing a fuse internal to the device. Once a bit (fuse) has been blown, it cannot be reset. Blow Pulse. A VPH voltage pulse of sufficient duration at the VP(HIGH) level to blow the addressed fuse. Cycling the Supply. Powering-down, and then powering-up the supply voltage. Cycling the supply is used to clear the programming settings in Try mode. Programming Pulse Requirements, Protocol at TA = 25°C Characteristic Symbol Notes Min. Typ. Max. Units VP(LOW) Programming Voltage - - 5.5 V 14 15 16 V 26 27 28 V Minimum supply current required to ensure proper fuse blowing. In addition, a minimum capacitance, CBLOW = 0.1 μF, must be connected between the VOUT and GND pins during programming to provide the current necessary for fuse blowing. 300 - - mA tOFF(HIGH) Duration at VP(LOW) level following a VP(HIGH) level. 30 - - μs tOFF(MID) Duration at VP(LOW) level following a VP(MID) level. 5 - - μs VP(MID) Measured at the VOUT pin. VP(HIGH) Programming Current Pulse Width IP tACTIVE(HIGH) Duration of VP(HIGH) level for VPH pulses during key/code selection. 30 - - μs tACTIVE(MID) Duration of VP(MID) level for VPH pulses during key/code selection. 15 - - μs Duration at VP(HIGH) level for fuse blowing. 30 - - μs Pulse Rise Time tBLOW tPr Rise time required for transitions from VP(LOW) to either VP(MID) or VP(HIGH). 1 - 100 μs Pulse Fall Time tPf Fall time required for transitions from VP(HIGH) to either VP(MID) to VP(LOW). 1 - 100 μs 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Programming Procedures Parameter Selection Each programmable parameter can be accessed through a specific register. To select a register, a sequence of voltage pulses consisting of a VPH pulse, a series of VPM pulses, and a VPH pulse (with no VCC supply interruptions) must be applied serially to the VOUT pin. The number of VPM pulses is called the key, and uniquely identifies each register. The pulse train used for selection of the first register, key 1, is shown in figure 1. V+ The A138x has three registers that select among the five programmable parameters: • Register 1: Quiescent voltage output, VOUT(Q) • Register 2: Sensitivity, Sens • Register 3: Sensitivity temperature coefficient, TCSens Polarity, POL Overall device locking, LOCK VP(HIGH) Bit Field Addressing After a programmable parameter has been selected, a VPH pulse transitions the programming logic into the bit field addressing state. Applying a series of VPM pulses to the VOUT pin of the device, as shown in figure 2, increments the bit field of the selected parameter. VP(MID) VP(LOW) tLOW tACTIVE 0 Code 2n – 1 VP(MID) Code 2 VP(HIGH) Code 1 V+ Code 2n – 2 Figure 1. Parameter selection pulse train. This shows the sequence for selecting the register corresponding to key 1, indicated by a single VPM pulse. When addressing the bit field, the number of VPM pulses is represented by a decimal number called a code. Addressing activates the corresponding fuse locations in the given bit field by incrementing the binary value of an internal DAC. The value of the bit field (and code) increments by one with the falling edge of each VPM pulse, up to the maximum possible code (see the Programming Logic table). As the value of the bit field code increases, the value of the programmable parameter changes. Measurements can be taken after each pulse to determine if the desired result for the programmable parameter has been reached. Cycling the supply voltage resets all the locations in the bit field that have unblown fuses to their initial states. Fuse Blowing VP(LOW) 0 Figure 2. Bit field addressing pulse train. Addressing the bit field by incrementing the code causes the programmable parameter value to change. The number of bits available for a given programming code, n, varies among parameters; for example, the bit field for VOUT(Q) has 6 bits available, which allows 63 separate codes to be used. After the required code is found for a given parameter, its value can be set permanently by blowing individual fuses in the appropriate register bit field. Blowing is accomplished by applying a VPH pulse, called a blow pulse, of sufficient duration at the VP(HIGH) level to permanently set an addressed bit by blowing a fuse internal to the device. Due to power requirements, the fuse for each bit in the bit field must be blown individually. To accomplish this, the code representing the desired parameter value must be translated to a binary number. For example, as shown 12 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package in figure 3, decimal code 5 is equivalent to the binary number 101. Therefore bit 2 (code 4) must be addressed and blown, the device power supply cycled, and then bit 0 (code 1) addressed and blown. An appropriate sequence for blowing code 5 is shown in figure 4. The order of blowing bits, however, is not important. Blowing bit 0 first, and then bit 2 is acceptable. Locking the Device Note: After blowing, the programming is not reversible, even after cycling the supply power. Although a register bit field fuse cannot be reset after it is blown, additional bits within the same register can be blown at any time until the device is locked. For example, if bit 1 (binary 10) has been blown, it is still possible to blow bit 0. The end result would be binary 11 (decimal code 3). The additional guidelines in this section should be followed to ensure the proper behavior of these devices: After the desired code for each parameter is programmed, the device can be locked to prevent further programming of any parameters. Additional Guidelines • A 0.1 μF blowing capacitor, CBLOW, must be mounted between the VOUT pin and the GND pin during programming, to ensure enough current is available to blow fuses. • The CBLOW blowing capacitor must be replaced in the final application with a suitable CL. (The maximum load capacitance is 10 nF for proper operation.) Bit Field Selection Address Code Format (Decimal Equivalent) Code 5 Code in Binary (Binary) 1 0 1 Fuse Blowing Target Bits Bit 2 Fuse Blowing Address Code Format • The power supply used for programming must be capable of delivering at least 26 V and 300 mA. • Be careful to observe the tLOW delay time before powering down the device after blowing each bit. • The following programming order is recommended: Bit 0 1. POL 2. TCSENS 3. Sens 4. VOUT(Q) 5. LOCK (only after all other parameters have been programmed and validated, because this prevents any further programming of the device) Code 4 Code 1 (Decimal Equivalents) Figure 3. Example of code 5 broken into its binary components, which are code 4 and code 1. V+ VP(HIGH) VP(MID) VP(LOW) Register Selection (Key 1) 0 Addressing (Code 4) Register Selection (Key 1) Blow (Code 4 in Key 1) Blow (Code 1 in Key 1) tBLOW VCC = 0 V VCC = 0 V Addressing (Code 1) VCC = 0 V Programming of Code 5 in Key 1 Figure 4. Example of programming pulses applied to the VOUT pin that result in permanent parameter settings. In this example, the register corresponding to key 1 is selected and code 5 is addressed and blown. 13 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Programming Modes Try Mode Blow Mode Try mode allows a single programmable parameter to be tested without permanently setting its value. Multiple parameters cannot be tested simultaneously in this mode. After powering the VCC supply, select the desired parameter register and address its bit field. When addressing the bit field, each VPM pulse increments the value of the parameter register, up to the maximum possible code (see Programming Logic table). The addressed parameter value remains stored in the device even after the programming drive voltage is removed from the VOUT pin, allowing the value to be measured. Note that for accurate time measurements, the blow capacitor, CBLOW, should be removed during output voltage measurement. After the required value of the programmable parameter is found using Try mode, its corresponding code should be blown to make its value permanent. To do this, select the required parameter register, and address and blow each required bit separately (as described in the Fuse Blowing section). The supply must be cycled between blowing each bit of a given code. After a bit is It is not possible to decrement the value of the register without resetting the parameter bit field. To reset the bit field, and thus the value of the programmable parameter, cycle the supply (VCC) voltage. To lock the device, address the LOCK bit and apply a blow pulse with CBLOW in place. After locking the device, no future programming of any parameter is possible. blown, cycling the supply will not reset its value. Lock Mode 14 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Programming State Machine Power-Up VPM Initial VPH VPH Parameter Selection VPM SENS VPM VOUT(Q) VPM TCSENS, POL, LOCK VPM 2n – 1 n = total bits in register VPM VPH Bit Field Addressing VPM 1 VPM VPM 2 VPH VPM = VP(LOW) –VP(MID) –VP(LOW) VPH = VP(LOW) –VP(HIGH) –VP(LOW) Fuse Blowing User Power-Down Required Initial State After system power-up, the programming logic is Bit Field Addressing State This state allows the selection of the reset to a known state. This is referred to as the Initial state. All the bit field locations that have intact fuses are set to logic 0. While in the Initial state, any VPM pulses on the VOUT pin are ignored. To enter the Parameter Selection state, apply one VPH pulse on the VOUT pin. individual bit fields to be programmed in the selected parameter Parameter Selection State This state allows the selection of the the value of the selected programming parameter; fuses must be parameter register containing the bit fields to be programmed. To select a parameter register, increment through the keys by applying VPM pulses on the VOUT pin. Register keys select among the following programming parameters: • 1 pulse - Sens • 2 pulses - VOUT(Q) • 3 pulses - TCSENS, POL, and LOCK To enter the Bit Field Addressing state, apply one VPH pulse on the VOUT pin. register (see Programming Logic table). To leave this state, either cycle device power or blow the fuses for the selected code. Note that merely addressing the bit field does not permanently set blown to do so. Fuse Blowing State To blow an addressed bit field, apply a VPH pulse on the VOUT pin. Power to the device should then be cycled before additional programming is attempted. Note: Each bit representing a decimal code must be blown individually (see the Fuse Blowing section). 15 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Programming Logic Table Programmable Parameter (Register Key) Sens (1) VOUT(Q) (2) TCSENS , POL, LOCK (3) Bit Field Address Binary Format [MSB → LSB] Decimal Equivalent Code 000000 0 Description Initial value (Sensinit) 111111 63 Maximum value of sensitivity (Sens) in range 000000 0 Initial value (VOUT(Q)init) 111111 63 Maximum value of quiescent voltage output (VOUT(Q)) in range; B = 0 G 000000 0 Initial value of sensitivity temperature coefficient range (TCSensinit) 000111 7 Maximum value of sensitivity temperature coefficient (TCSens) in range 001000 8 POL bit, switches polarity (causes VOUT to increase with a negative [north polarity] field applied to the branded face of the device) 010000 16 LOCK bit, enables permanent locking of all programming bit fields in the device 16 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Package LH, 3 Pin; (SOT-23W) +0.12 2.98 –0.08 1.49 D 4°±4° 3 A +0.020 0.180–0.053 0.96 D +0.10 2.90 –0.20 +0.19 1.91 –0.06 2.40 0.70 D 0.25 MIN 1.00 2 1 0.55 REF 0.25 BSC 0.95 Seating Plane Gauge Plane 8X 10° REF B PCB Layout Reference View Branded Face 1.00 ±0.13 +0.10 0.05 –0.05 0.95 BSC 0.40 ±0.10 For Reference Only; not for tooling use (reference dwg. 802840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Active Area Depth, 0.28 mm REF B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion D Hall element, not to scale NNT 1 C Standard Branding Reference View N = Last two digits of device part number T = Temperature code 17 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Package UA, 3-Pin SIP +0.08 4.09 –0.05 45° B C E 2.04 1.52 ±0.05 1.44 E +0.08 3.02 –0.05 Mold Ejector Pin Indent 2X10° E Branded Face 45° 1 D Standard Branding Reference View A 1.02 MAX 0.51 REF = Supplier emblem N = Last two digits of device part number T = Temperature code 0.79 REF 1 2 3 +0.03 0.41 –0.06 14.99 ±0.25 +0.05 0.43 –0.07 NNT For Reference Only; not for tooling use (reference DWG-9013) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Dambar removal protrusion (6X) B Gate and tie bar burr area C Active Area Depth, 0.50 mm REF D Branding scale and appearance at supplier discretion E Hall element, not to scale 1.27 NOM Please note that there are changes to the existing UA package drawing pending. Please contact the Allegro Marketing department for additional information. 18 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A1381, A1382, A1383, and A1384 Programmable Linear Hall Effect Sensor ICs with Analog Output Available in a Miniature Thin Profile Surface Mount Package Revision History Revision Revision Date Rev. 9 December 10, 2012 Description of Revision Update product availability Copyright ©2009-2012, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 19 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com