STMicroelectronics M24512-W Random and sequential read mode Datasheet

M24512-x
M24256-Bx
512 Kbit and 256 Kbit serial I²C bus EEPROM
with three Chip Enable lines
Features
■
Supports the I2C bus 100 kHz Standard-mode,
400 kHz Fast-mode and 1 MHz Fast-mode
Plus
■
Supply voltage ranges:
– 1.7 V to 5.5 V (M24256-BF)
– 1.8 V to 5.5 V (M24xxx-R)
– 2.5 V to 5.5 V (M24xxx-W)
■
Write Control input
■
Byte and Page Write
■
Random and sequential read modes
■
Self-timed programming cycle
■
Automatic address incrementing
■
Enhanced ESD/latch-up protection
■
More than 1 000 000 write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
Table 1.
Reference
SO8 (MW)
208 mils width
SO8 (MN)
150 mils width
TSSOP8 (DW)
Device summary
Part numbers
M24512-x
M24512-R, M24512-HR, M24512-W
M24256-Bx
M24256-BF, M24256-BR,
M24256-BHR, M24256-BW
WLCSP (CS)
January 2009
Rev 13
1/37
www.st.com
1
Contents
M24512-x, M24256-Bx
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
3
4
2/37
2.6.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 16
3.10
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17
3.11
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.13
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.14
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.15
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M24512-x, M24256-Bx
Contents
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3/37
List of tables
M24512-x, M24256-Bx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
4/37
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating conditions (M24xxx-R and M24xxx-HR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating conditions (M24256-BF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (M24xxx-R and M24xxx-HR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC characteristics (M24256-BF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC characteristics (M24xxx-W, M24xxx-R, M24256-BF see Table 8, Table 9
Table 10 and Table 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1 MHz AC characteristics (M24xxx-HR, see Table 9 and Table 11). . . . . . . . . . . . . . . . . . 26
SO8W – 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 28
SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 29
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30
WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Available M24256-Bx products (package, voltage range, temperature grade). . . . . . . . . . 33
Available M24512-x products (package, voltage range, temperature grade) . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
M24512-x, M24256-Bx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M24256-BF, M24xxx-R/W – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . 10
M24xxx-HR – Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SO8W – 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 28
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 29
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30
WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5/37
Description
1
M24512-x, M24256-Bx
Description
The M24512-W, M24512-R, M24512-HR, M24256-BF, M24256-BW, M24256-BR and
M24256-BHR devices are I2C-compatible electrically erasable programmable memories
(EEPROM). They are organized as 64 Kb × 8 bits and 32 Kb × 8 bits, respectively.
I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C
bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Logic diagram
6##
% %
3#,
3$!
- X
- "X
7#
633
Table 2.
Signal names
Signal name
6/37
!)E
Function
Direction
E0, E1, E2
Chip Enable
Inputs
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
M24512-x, M24256-Bx
Figure 2.
Description
SO and TSSOP connections
E0
E1
E2
VSS
8
7
6
5
1
2
3
4
VCC
WC
SCL
SDA
AI04035e
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3.
WLCSP connections (top view, marking side, with balls on the underside)
VCC
E1
E0
WC
E2
SDA
SCL
VSS
ai14712
7/37
Signal description
M24512-x, M24256-Bx
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 6. indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 6. indicates how
the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code. When not connected (left floating), these inputs
are read as Low (0,0,0).
Figure 4.
Device select code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device Select and Address bytes are
acknowledged, Data bytes are not acknowledged.
8/37
M24512-x, M24256-Bx
2.5
Signal description
VSS ground
VSS is the reference for the VCC supply voltage.
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8 and Table 9).
In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line
with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC, the VCC rise time must not
vary faster than 1 V/µs.
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise in VCC), the device does not respond to any
instruction until VCC reaches the power on reset threshold voltage (this threshold is lower
than the minimum VCC operating voltage defined in Table 8 and Table 9). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode. However,
the device must not be accessed until VCC reaches a valid and stable VCC voltage within the
specified [VCC(min), VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power on reset threshold voltage, the device stops responding to any instruction
sent to it.
2.6.4
Power-down conditions
During power-down (where VCC decreases continuously), the device must be in the Standby
Power mode (mode reached after decoding a Stop condition, assuming that there is no
internal Write cycle in progress).
9/37
Signal description
M24512-x, M24256-Bx
Figure 5.
M24256-BF, M24xxx-R/W – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
Bus line pull-up resistor
(k )
100
fC = 400 kHz, tLOW = 1.3 µs
Rbus x Cbus time
constant must be less than
500 ns
VCC
10
Rbus
I²C bus
master
SCL
M24xxx
SDA
1
10
100
Cbus
1000
Bus line capacitor (pF)
ai14796
Bus line pull-up resistor (k )
Figure 6.
M24xxx-HR – Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1 MHz
100
VCC
fC = 1 MHz, tLOW = 500 ns,
time constant Rbus x Cbus
must be less than 150 ns
10
fC = 1 MHz, extended case
where tLOW = 700 ns,
time constant Rbus x Cbus
must be less than 270 ns
Rbus
I²C bus
master
SCL
M24xxx
SDA
Cbus
1
10
100
Bus line capacitor (pF)
ai14795b
10/37
M24512-x, M24256-Bx
Figure 7.
Signal description
I2C bus protocol
SCL
SDA
SDA
Input
Start
condition
SCL
1
2
SDA
MSB
SDA
Change
Stop
condition
3
7
8
9
ACK
Start
condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
Stop
condition
AI00792c
Table 3.
Device select code
Device type identifier(1)
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
Device select code
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 4.
b15
Table 5.
b7
Most significant address byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Least significant address byte
b6
b5
b4
11/37
Device operation
3
M24512-x, M24256-Bx
Device operation
The device supports the I2C protocol. This is summarized in Figure 7.. Any device that
sends data on to the bus is defined to be a transmitter, and any device that reads the data to
be a receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24256-Bx and M24512-x devices are
always slaves in all communications.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
12/37
M24512-x, M24256-Bx
3.5
Device operation
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 3. (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the Device Select code, it deselects itself from the bus, and goes into Standby mode.
Table 6.
Operating modes
Mode
Current Address
Read
RW bit
WC(1)
Bytes
1
X
1
0
X
Initial sequence
Start, Device Select, RW = 1
Start, Device Select, RW = 0, Address
Random Address
Read
1
X
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
1
re-Start, Device Select, RW = 1
Similar to Current or Random Address
Read
Start, Device Select, RW = 0
≤ 128 for 512
Kbit devices
Page Write
0
VIL
≤ 64 for 256
Kbit devices
Start, Device Select, RW = 0
1. X = VIH or VIL.
13/37
Device operation
Figure 8.
M24512-x, M24256-Bx
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
Data in N
Stop
Page Write
(cont'd)
NO ACK
AI01120d
14/37
M24512-x, M24256-Bx
3.6
Device operation
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9., and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write
instruction with Write Control (WC) driven High (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 8..
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte (Table 4.) is sent first, followed by the least significant byte (Table 5.). Bits b15 to b0
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
3.7
Byte Write
After the Device Select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
3.8
Page Write
The Page Write mode allows up to 64 bytes (for the M24256-Bx) or 128 bytes (for the
M24512-x) to be written in a single Write cycle, provided that they are all located in the same
‘row’ in the memory: that is, the most significant memory address bits (b15-b6 for the
M24256-Bx, and b15-b7 for the M24512-x) are the same. If more bytes are sent than will fit
up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as
data starts to become overwritten in an implementation dependent way.
The bus master sends from 1 to 64 bytes (for the M24256-Bx) or from 1 to 128 bytes (for the
M24512-x) of data, each of which is acknowledged by the device if Write Control (WC) is
Low. If Write Control (WC) is High, the contents of the addressed memory location are not
modified, and each data byte is followed by a NoAck. After each byte is transferred, the
internal byte address counter (the 7 least significant address bits only) is incremented. The
transfer is terminated by the bus master generating a Stop condition.
15/37
Device operation
3.9
M24512-x, M24256-Bx
ECC (error correction code) and write cycling
The M24256-Bx and M24512-x devices offer an ECC (error correction code) logic which
compares each 4-byte word with its six associated ECC EEPROM bits. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by word (4 bytes) in order to
benefit from the larger amount of Write cycles.
The M24256-Bx and M24512-x devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device by multiples of 4-bytes.
Figure 9.
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
Byte addr
Byte addr
ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
ACK
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
Data in N
Stop
Page Write
(cont'd)
ACK
AI01106d
16/37
M24512-x, M24256-Bx
Device operation
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
operation is
addressing the
memory
YES
Send Address
and Receive ACK
ReStart
NO
Stop
Start
condition
YES
Data for the
Write operation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847d
3.10
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 16., but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 10., is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
17/37
Device operation
3.11
M24512-x, M24256-Bx
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
3.12
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11.) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
3.13
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11., without acknowledging the byte.
3.14
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
18/37
M24512-x, M24256-Bx
Device operation
Figure 11. Read mode sequences
ACK
Data out
Stop
Start
Dev sel
NO ACK
R/W
ACK
Random
Address
Read
Byte addr
Dev sel *
ACK
ACK
Data out 1
ACK
NO ACK
Data out N
ACK
Byte addr
ACK
Byte addr
R/W
ACK
Dev sel *
Start
Dev sel *
Start
Data out
R/W
R/W
ACK
NO ACK
Stop
Start
Dev sel
Sequential
Random
Read
ACK
Byte addr
R/W
ACK
Sequential
Current
Read
ACK
Start
Start
Dev sel *
ACK
Stop
Current
Address
Read
ACK
Data out 1
R/W
NO ACK
Stop
Data out N
AI01105d
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
3.15
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Standby mode.
19/37
Initial delivery state
4
M24512-x, M24256-Bx
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Absolute maximum ratings
Symbol
TA
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
Lead temperature during soldering
See
note (1)
VIO
Input or output range
–0.50
VCC + 0.6
V
VCC
Supply voltage
–0.50
6.5
V
VESD
Electrostatic discharge voltage (human body model) (2)
–4000
4000
V
ECOPACK®
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST
7191395 specification, and the European directive on the restriction of the use of certain hazardous
substances in electrical and electronic equipment (RoHS) 2002/95/EC.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)
20/37
°C
M24512-x, M24256-Bx
6
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (M24xxx-W)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (M24xxx-R and M24xxx-HR)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
1.7
5.5
V
Ambient operating temperature
–40
85
°C
Operating conditions (M24256-BF)
Symbol
VCC
TA
Table 11.
Parameter
AC test measurement conditions
Symbol
CL
Parameter
Min.
Load capacitance
Max.
100
Input rise and fall times
Unit
pF
50
ns
Input levels
0.2VCC to 0.8VCC
V
Input and output timing reference levels
0.3VCC to 0.7VCC
V
Figure 12. AC test measurement I/O waveform
Input Levels
0.8VCC
0.2VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
AI00825B
21/37
DC and AC parameters
Table 12.
Symbol
M24512-x, M24256-Bx
Input parameters
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
8
pF
CIN
Input capacitance (other pins)
6
pF
ZL(2)
Input impedance
(E2, E1, E0, WC)
VIN < 0.3VCC
30
kΩ
ZH(2)
Input impedance
(E2, E1, E0, WC)
VIN > 0.7VCC
500
kΩ
1. Sampled only, not 100% tested.
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 13.
DC characteristics (M24xxx-W)
Symbol
Parameter
ILI
Input leakage current
(SCL, SDA, E0, E1,
E2)
ILO
Output leakage
current
ICC
ICC0
ICC1
Test conditions (see Table 8 and
Table 11)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
±2
µA
VCC = 2.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
2
mA
5(1)
mA
Supply current (Read)
Supply current (Write) During tW, 2.5 V < VCC < 5.5 V
Standby supply
current
Device not
Device grade 3
selected(2), VIN = VSS
Device grade 6
or VCC, VCC = 2.5 V
5
VIN = VSS or VCC, VCC = 5.5 V
5
µA
µA
2
VIL
Input low voltage
(SCL, SDA, WC)
–0.45
0.3VCC
V
VIH
Input high voltage
(SCL, SDA, WC)
0.7VCC
VCC+0.6
V
VOL
Output low voltage
0.4
V
IOL = 2.1 mA, VCC = 2.5 V
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a READ command (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a WRITE command).
22/37
M24512-x, M24256-Bx
Table 14.
Symbol
DC and AC parameters
DC characteristics (M24xxx-R and M24xxx-HR)
Parameter
ILI
Input leakage current
(E1, E2, SCL, SDA)
ILO
Output leakage current
ICC
ICC0
Test conditions (in addition to
those in Table 9)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.8 V, fc= 400 kHz
(rise/fall time < 50 ns)
0.8
mA
VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.0 V, fc= 400 kHz
(rise/fall time < 50 ns)
2
mA
1.8 V < VCC < 5.5 V, fc= 1 MHz(1)
(rise/fall time < 50 ns)
2.5
mA
During tW, 1.8 V < VCC < 5.5 V
5(2)
mA
Device not
VIN = VSS or VCC, VCC = 1.8 V
1
µA
Device not selected(3),
VIN = VSS or VCC, VCC = 2.5 V
2
µA
Device not selected(3),
VIN = VSS or VCC, VCC = 5.5 V
3
µA
V
Supply current (Read)
Supply current (Write)
selected(3),
ICC1
Standby supply current
VIL
Input low voltage
(SCL, SDA, WC)
VIH
Input high voltage
(SCL, SDA, WC)
VOL
Output low voltage
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
2.5 V ≤ VCC ≤5.5 V
–0.45
0.3 VCC
1.8 V ≤ VCC < 2.5 V
0.75VCC
VCC+1
2.5 V ≤ VCC ≤ 5.5 V
0.7VCC
VCC+1
V
IOL = 1 mA, VCC = 1.8 V
0.2
V
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
IOL = 3.0 mA, VCC = 5.5 V
0.4
V
1. Only for M24xxx-HR6.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a READ command (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a WRITE command).
23/37
DC and AC parameters
Table 15.
M24512-x, M24256-Bx
DC characteristics (M24256-BF)(1)
Symbol
Parameter
ILI
Input leakage current
(E1, E2, SCL, SDA)
ILO
Output leakage current
ICC
ICC0
Test condition (in addition to
those in Table 9)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.7 V, fc= 400 kHz
(rise/fall time < 50 ns)
0.8
mA
VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
1
mA
VCC = 5.0 V, fc= 400 kHz
(rise/fall time < 50 ns)
2
mA
1.7 V < VCC < 5.5 V, fc= 1 MHz(2)
(rise/fall time < 50 ns)
2.5
mA
During tW, 1.7 V < VCC < 5.5 V
5(3)
mA
Device not
VIN = VSS or VCC, VCC = 1.7 V
1
µA
Device not selected(4),
VIN = VSS or VCC, VCC = 2.5 V
2
µA
Device not selected(4),
VIN = VSS or VCC, VCC = 5.5 V
3
µA
V
Supply current (Read)
Supply current (Write)
selected(4),
ICC1
Standby supply current
VIL
Input low voltage
(SCL, SDA, WC)
VIH
Input high voltage
(SCL, SDA, WC)
VOL
Output low voltage
1.7 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
2.5 V ≤ VCC ≤ 5.5 V
–0.45
0.3 VCC
1.7 V ≤ VCC < 2.5 V
0.75VCC
VCC+1
2.5 V ≤ VCC ≤ 5.5 V
0.7VCC
VCC+1
IOL = 1 mA, VCC = 1.7 V
0.2
V
IOL = 2.1 mA, VCC = 2.5 V
0.4
V
IOL = 3.0 mA, VCC = 5.5 V
0.4
V
1. Preliminary data.
2. Only for M24xxx-HR6.
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a READ command (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a WRITE command).
24/37
V
M24512-x, M24256-Bx
Table 16.
DC and AC parameters
AC characteristics (M24xxx-W, M24xxx-R, M24256-BF see Table 8, Table 9
Table 10 and Table 11)
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
Clock pulse width high
600
ns
tCLCH
tLOW
Clock pulse width low
1300
ns
tDL1DL2(1)
tXH1XH2(2)
tXL1XL2(2)
tF
SDA (out) fall time
20
100
ns
tR
Input signal rise time
20
300
ns
tF
Input signal fall time
20
300
ns
tDXCX
tSU:DAT
Data in set up time
100
ns
tCLDX
tHD:DAT
Data in hold time
0
ns
tCLQX
tDH
Data out hold time
200
ns
tCLQV(3)
tCHDX(4)
tAA
Clock low to next data valid (access time)
200
tSU:STA
Start condition set up time
600
ns
tDLCL
tHD:STA
Start condition hold time
600
ns
tCHDH
tSU:STO
Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
tWR
Write time
tNS
Parameter
Pulse width ignored (input filter on SCL and
SDA) - single glitch
Min.
Max.
Unit
400
kHz
900
ns
5
ms
100
ns
1. Sampled only, not 100% tested.
2. Values recommended by I²C-bus/Fast-Mode specification.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. For a re-Start condition, or following a Write cycle.
25/37
DC and AC parameters
Table 17.
M24512-x, M24256-Bx
1 MHz AC characteristics (M24xxx-HR, see Table 9 and Table 11)
Test conditions specified in Table 9
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
MHz
tCHCL
tHIGH
Clock pulse width high
300
-
ns
tCLCH
tLOW
Clock pulse width low
400
-
ns
tXH1XH2(1)
tR
Input signal rise time
20
300
ns
tXL1XL2(1)
tF
Input signal fall time
20
300
ns
tDL1DL2(2)
tF
SDA (out) fall time
20
100
ns
tDXCX
tSU:DAT
Data in setup time
80
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
tCLQX
tDH
Data out hold time
50
-
ns
tCLQV(3)(4)
tAA
Clock low to next data valid (access time)
50
500
ns
tCHDX(5)
tSU:STA
Start condition setup time
250
-
ns
tDLCL
tHD:STA
Start condition hold time
250
-
ns
tCHDH
tSU:STO
Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next
Start condition
500
-
ns
tW
tWR
Write time
-
5
ms
50
ns
tNS(2)
Pulse width ignored (input filter on SCL and
SDA)
1. Values recommended by the I²C-bus Fast-Mode specification.
2. Characterized only, not tested in production.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC, assuming
that the Rbus × Cbus time constant is less than 150 ns (as specified in Figure 5).
5. For a reStart condition, or following a Write cycle.
26/37
M24512-x, M24256-Bx
DC and AC parameters
Figure 13. AC waveforms
tXL1XL2
tCHCL
tXH1XH2
tCLCH
SCL
tDLCL
tXL1XL2
SDA In
tCHDX
tCLDX
tXH1XH2
Start
condition
SDA
Input
SDA tDXCX
Change
tCHDH tDHDL
Start
Stop
condition condition
SCL
SDA In
tW
tCHDH
tCHDX
Stop
condition
Write cycle
Start
condition
tCHCL
SCL
tCLQV
SDA Out
tCLQX
Data valid
tDL1DL2
Data valid
AI00795e
27/37
Package mechanical data
7
M24512-x, M24256-Bx
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 14. SO8W – 8-lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 18.
SO8W – 8-lead plastic small outline, 208 mils body width, package data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
2.5
Max
0.0984
A1
0
0.25
0
0.0098
A2
1.51
2
0.0594
0.0787
b
0.4
0.35
0.51
0.0157
0.0138
0.0201
c
0.2
0.1
0.35
0.0079
0.0039
0.0138
CP
0.1
0.0039
D
6.05
0.2382
E
5.02
6.22
0.1976
0.2449
E1
7.62
8.89
0.3
0.35
-
-
-
-
k
0°
10°
0°
10°
L
0.5
0.8
0.0197
0.0315
N (number of pins)
8
e
1.27
0.05
1. Values in inches are converted from mm and rounded to 4 decimal digits.
28/37
Min
8
M24512-x, M24256-Bx
Package mechanical data
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 19.
SO8N – 8-lead plastic small outline, 150 mils body width, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.0689
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.1
0.0039
D
4.9
4.8
5
0.1929
0.189
0.1969
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
-
-
0.05
-
-
h
0.25
0.5
0.0098
0.0197
k
0°
8°
0°
8°
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
29/37
Package mechanical data
M24512-x, M24256-Bx
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 20.
TSSOP8 – 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
0.050
0.150
0.800
1.050
b
0.190
c
0.090
1.000
CP
Max
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394
α
0°
N
8
8°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
30/37
Min
1.200
A1
A2
Typ
8
M24512-x, M24256-Bx
Package mechanical data
Figure 17. WLCSP, 0.5 mm pitch, package outline
Orientation reference
D
2
3
1
A
e2
e
B
C
E
D
B
G
E
e3
F
e1
A2
A1
A
1. Drawing is not to scale.
Table 21.
WLCSP, 0.5 mm pitch, package mechanical data
Inches(1)
Millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.60
0.55
0.65
0.0236
0.0217
0.0256
A1
0.245
0.22
0.27
0.0096
0.0087
0.0106
A2
0.355
0.330
0.380
0.0140
0.0130
0.0150
B
Ø 0.311
Ø 0.0122
D
1.97
1.95
1.99
0.0776
0.0768
0.0783
E
1.785
1.765
1.805
0.0703
0.0695
0.0711
e
0.5
0.0197
e1
0.866
0.0341
e2
0.25
0.0098
e3
0.433
0.0170
F
0.552
0.502
0.602
0.0217
0.0198
0.0237
0.392
0.342
0.442
0.0154
0.0135
0.0174
G
N
(2)
8
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.
31/37
Part numbering
8
M24512-x, M24256-Bx
Part numbering
Table 22.
Ordering information scheme
Example:
M24512–
H W MW 6
T
P /AB
Device type
M24 = I2C serial access EEPROM
Device function
512– = 512 Kbit (64 Kb × 8)
256–B = 256 Kbit (32 Kb × 8)
Clock frequency
Blank: fC max = 400 kHz
H: fC max = 1 MHz
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package
MW = SO8 (208 mils width)
MN = SO8 (150 mils body width)
DW = TSSOP8
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C. Device tested with
standard test flow
3 = Automotive: device tested with high reliability certified flow(1)
over –40 to 125 °C
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(2)
/A = F8L in CSP package
/AB = F8L for device grade 3
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive
environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801.
Please ask your nearest ST sales office for a copy.
2. Used only for device grade 3 and WLCSP packages.
32/37
M24512-x, M24256-Bx
Part numbering
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 23.
Available M24256-Bx products (package, voltage range, temperature
grade)
M24256-BW
2.5 V to 5.5 V
Package
M24256-BR
1.8 V to 5.5 V
M24256-BHR
1.8 V to 5.5 V
M24256-BF
1.7 V to 5.5 V
SO8N (MN)
Range 6, Range 3
Range 6
Range 6
-
SO8W (MW)
Range 6
-
-
-
TSSOP (DW)
Range 6
Range 6
Range 6
Range 6
WLCSP
-
Range 6
-
-
Table 24.
Available M24512-x products (package, voltage range, temperature
grade)
Package
M24512-W
2.5 V to 5.5 V
M24512-R
1.8 V to 5.5 V
M24512-HR
1.8 V to 5.5 V
SO8N (MN)
Range 6, Range 3
Range 6
Range 6
SO8W (MW)
Range 6
-
-
TSSOP (DW)
Range 6
Range 6
-
33/37
Revision history
9
Revision history
Table 25.
Date
Document revision history
Revision
Changes
29-Jan-2001
1.1
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data
updated
10-Apr-2001
1.2
LGA8 Package Mechanical data and illustration updated
SO16 package removed
16-Jul-2001
1.3
LGA8 Package given the designator “LA”
02-Oct-2001
1.4
LGA8 Package mechanical data updated
13-Dec-2001
1.5
Document becomes Preliminary Data
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
12-Jun-2001
1.6
Document promoted to Full Datasheet
22-Oct-2003
2.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to –0.45V.
3.0
LGA8 package is Not for New Design. 5V and -S supply ranges, and
Device Grade 5 removed. Absolute Maximum Ratings for VIO(min) and
VCC(min) changed. Soldering temperature information clarified for RoHS
compliant devices. Device grade information clarified. AEC-Q100-002
compliance. VIL specification unified for SDA, SCL and WC
4.0
Initial delivery state is FFh (not necessarily the same as Erased).
LGA package removed, TSSOP8 and SO8N packages added (see
Package mechanical data section and <Blue>Table 22., Ordering
information scheme).
Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.
ZL Test Conditions modified in <Blue>Table 12., Input parameters and
Note 2. added.
ICC and ICC1 values for VCC = 5.5V added to <Blue>Table 13., DC
characteristics (M24xxx-W).
Note added to <Blue>Table 13., DC characteristics (M24xxx-W).
Power On Reset paragraph specified.
tW max value modified in <Blue>Table 16., AC characteristics (M24xxx-W,
M24xxx-R, M24256-BF see Table 8, Table 9 Table 10 and Table 11) and
note 4 added. Plating technology changed in <Blue>Table 22., Ordering
information scheme.
Resistance and capacitance renamed in <Blue>Figure 6., M24xxx-HR –
Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
bus at maximum frequency fC = 1 MHz.
02-Sep-2004
22-Feb-2005
34/37
M24512-x, M24256-Bx
M24512-x, M24256-Bx
Table 25.
Date
05-May-2006
16-Oct-2006
02-Jul-2007
16-Oct-2007
Revision history
Document revision history (continued)
Revision
Changes
5
Power On Reset paragraph replaced by Section 2.6: Supply voltage
(VCC). Figure 4: Device select code added.
ECC (error correction code) and write cycling added and specified at 1
Million cycles.
ICC0 added and ICC1 specified over the whole voltage range in Table 13
and Table 14.
PDIP8 package removed. Packages are ECOPACK® compliant. Small
text changes.
6
M24256-BW and M24256-BR part numbers added.
Section 3.9: ECC (error correction code) and write cycling updated.
ICC and ICC1 modified in Table 14: DC characteristics (M24xxx-R and
M24xxx-HR).
tW modified in Table 16: AC characteristics (M24xxx-W, M24xxx-R,
M24256-BF see Table 8, Table 9 Table 10 and Table 11).
SO8Narrow package specifications updated (see Table 19 and
Figure 15). Blank option removed from below Plating technology in
Table 22: Ordering information scheme.
7
Section 2.6: Supply voltage (VCC) modified.
Section 3.9: ECC (error correction code) and write cycling modified.
JEDEC standard and European directive references corrected below
Table 7: Absolute maximum ratings.
Rise/fall time conditions modified for ICC and VIH max modified in
Table 13: DC characteristics (M24xxx-W) and Table 14: DC
characteristics (M24xxx-R and M24xxx-HR)
Note 1 removed from Table 13: DC characteristics (M24xxx-W).
SO8W package specifications modified in Section 7: Package mechanical
data.
Table 23: Available M24256-Bx products (package, voltage range,
temperature grade) and Table 24: Available M24512-x products (package,
voltage range, temperature grade) added.
8
Section 2.5: VSS ground added. Small text changes.
VIO max changed and Note 1 updated to latest standard revision in
Table 7: Absolute maximum ratings.
Note removed from Table 12: Input parameters.
VIH min and VIL max modified in Table 14: DC characteristics (M24xxx-R
and M24xxx-HR).
Removed tCH1CH2, tCL1CL2 and tDH1DH2, and added tXL1XL2, tDL1DL2 and
Note 2 in Table 16: AC characteristics (M24xxx-W, M24xxx-R, M24256BF see Table 8, Table 9 Table 10 and Table 11).
tXH1XH2, tXL1XL2 and Note 2 added to Table 17: 1 MHz AC characteristics
(M24xxx-HR, see Table 9 and Table 11).
Figure 13: AC waveforms modified.
Package mechanical data inch values calculated from mm and rounded to
4 decimal digits (see Section 7: Package mechanical data).
35/37
Revision history
Table 25.
Date
Document revision history (continued)
Revision
Changes
9
1 MHz frequency introduced (M24512-HR root part number).
Section 2.6.3: Device reset modified.
Figure 5: M24256-BF, M24xxx-R/W – Maximum Rbus value versus bus
parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC =
400 kHz modified, Figure 6: M24xxx-HR – Maximum Rbus value versus
bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC
= 1 MHz added.
tNS moved from Table 12 to Table 16. ILO test conditions modified in
Table 13.
Table 14: DC characteristics (M24xxx-R and M24xxx-HR) and Table 17: 1
MHz AC characteristics (M24xxx-HR, see Table 9 and Table 11) modified.
Small text changes.
10
Small text changes. M24256-BHR root part number added.
Section 2.6.3: Device reset on page 9 updated.
Figure 6: M24xxx-HR – Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz on
page 10 updated.
Caution removed in Section 3.9: ECC (error correction code) and write
cycling.
22-Apr-2008
11
M24512-W and M24256-BW offered in the device grade 3 option
(automotive temperature range):
– Table 8: Operating conditions (M24xxx-W),
– Table 13: DC characteristics (M24xxx-W),
– /AB Process letters added to Table 22: Ordering information scheme,
– Table 23: Available M24256-Bx products (package, voltage range,
temperature grade) and
– Table 24: Available M24512-x products (package, voltage range,
temperature grade) updated accordingly).
Small text changes.
22-Dec-2008
12
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 7: Package
mechanical data).
13
M24256-BF part number added (VCC = 1.7 V to 5.5 V voltage range
added, see Table 10, Table 15, Table 16 and Table 23).
ICC1 test conditions modified in Table 13: DC characteristics (M24xxx-W),
Table 14: DC characteristics (M24xxx-R and M24xxx-HR) and Table 15:
DC characteristics (M24256-BF).
14-Dec-2007
27-Mar-2008
21-Jan-2009
36/37
M24512-x, M24256-Bx
M24512-x, M24256-Bx
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2009 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
37/37