INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4085B gates Dual 2-wide 2-input AND-OR-invert gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4085B gates Dual 2-wide 2-input AND-OR-invert gate DESCRIPTION The HEF4085B is a dual 2-wide 2-input AND-OR-invert gate, each with an additional input (A4 or B4) which can be used as either an expander input or an inhibit input. A HIGH on A4 or B4 forces the output (OA or OB) LOW independent of the other inputs (A0 to A3 or B0 to B3). The outputs OA and OB are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4085BP(N): 14-lead DIL; plastic (SOT27-1) HEF4085BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4085BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. LOGIC FUNCTION OA = A0 ⋅ A1 + A2 ⋅ A3 + A4 OB = B0 ⋅ B1 + B2 ⋅ B3 + B4 FAMILY DATA, IDD LIMITS category GATES See Family Specifications Fig.3 Logic diagram (one gate). January 1995 2 Philips Semiconductors Product specification HEF4085B gates Dual 2-wide 2-input AND-OR-invert gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays An, Bn → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 15 VDD V Dynamic power dissipation per package (P) 5 tTLH 75 155 ns 48 ns + (0,55 ns/pF) CL 30 60 ns 19 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 65 135 ns 38 ns + (0,55 ns/pF) CL 30 55 ns 19 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 60 120 ns 10 ns + (1,0 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL ns/pF) CL 60 120 ns 10 ns + (1,0 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL ns/pF) CL TYPICAL FORMULA FOR P (µW) 750 fi + ∑ (foCL) × VDD2 10 3200 fi + ∑ (foCL) × VDD 2 15 9200 fi + ∑ (foCL) × VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3