3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
128 x 128
per-channel variable or constant throughput delay modes and microprocessor
read and write access to individual channels. As an important function of a digital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT72V8988 is an ideal solution for most switching needs.
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
IDT72V8988
128 x 128 channel non-blocking switch
Automatic signal identification (ST-BUS®, GCI)
4 RX inputs—32 channels at 64 Kbit/s per serial line
4 TX outputs—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
Frame Integrity for data applications
3.3V Power Supply
Available in 44-pin Plastic Leaded Chip Carrier (PLCC), and
44-pin Plastic Quad Flatpack (PQFP)
Operating Temperature Range -40°°C to +85°°C
3.3V I/O with 5V Tolerant Inputs
FUNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum
delay are high priority requirements in today’s integrated data and multimedia
networks. The IDT72V8988 provides these functions on a per-channel basis
using a standard microprocessor control interface. Each of the four serial lines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
In Processor Mode, the microprocessor can access the input and output time
slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS® formats, IDT72V8988 has incorporated an
internal circuit to automatically identify the polarity and format of the frame
synchronization.
A functional block diagram of the IDT72V8988 device is shown on page 1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µs wide frames each containing 32, 8-bit channels. Four input (RX0-3) and
DESCRIPTION:
The IDT72V8988 is an ST-BUS®/GCI compatible digital switch controlled
by a microprocessor. The IDT72V8988 can handle as many as 128, 64 Kbit/s
input and output channels. Those 128 channels are divided into 4 serial inputs
and outputs, each of which consists of 32 channels. The IDT72V8988 provides
FUNCTIONAL BLOCK DIAGRAM
C4i
F0i
VCC
ODE
GND
Timing
Unit
Output MUX
RX0
RX1
RX2
RX3
TX0
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Control Register
Connection
Memory
TX1
TX2
TX3
Microprocessor Interface
5704 drw01
DS CS R/W A0/ DTA D0/
A5
D7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
AUGUST 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5704/5
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
ODE
TX0
TX1
TX2
DNC(1)
43
42
41
40
RX0
DTA
2
DNC(1)
RX1
3
44
RX2
4
1
DNC(1)
5
INDEX
6
PIN CONFIGURATION
15
31
D2
A1
16
30
D3
A2
17
29
D4
28
A0
DNC(1)
D1
27
32
D5
14
26
D0
C4i
D6
33
25
13
24
GND
F0i
D7
DNC(1)
34
CS
35
12
23
11
VCC
DS
VCC
R/W
DNC(1)
DNC(1)
22
36
21
37
10
20
9
VCC
A5
VCC
A4
DNC(1)
19
TX3
38
A3
39
8
18
7
VCC
DNC(1)
RX3
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TX1
DNC(1)
34
ODE
TX0
38
TX2
DTA
DNC(1)
40
35
RX0
41
36
RX1
42
37
RX2
39
DNC(1)
43
INDEX
44
PLCC: 0.05in. pitch, 0.65in. x 0.65in
(J44-1, order code: J)
TOP VIEW
RX3
1
33
TX3
VCC
2
32
DNC(1)
VCC
3
31
VCC
4
30
DNC(1)
DNC(1)
VCC
5
29
DNC(1)
VCC
6
28
GND
D0
D1
D4
22
23
21
11
20
A2
19
D2
D3
18
24
17
25
10
16
9
A1
15
26
14
27
8
13
7
12
F0i
C4i
A0
DNC(1)
D5
D6
CS
D7
DS
R/W
A5
A4
A3
DNC(1)
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PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
NOTES:
1. DNC - Do Not Connect.
2
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
PIN DESCRIPTIONS
SYMBOL
GND
VCC
DTA
RX0-3
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-3
ODE
NAME
Ground.
VCC
Data Acknowledgment
(Open Drain)
RX Input 0 to 3
Frame Pulse
I/O
O
I
I
Clock
Address 0 to 5
Data Strobe
I
I
I
Read/Write
Chip Select
Data Bus 0 to 7
I
I
I/O
TX Outputs 0 to 3
(Three-state Outputs)
Output Drive Enable
O
I
DESCRIPTION
Ground Rail.
+3.3 Volt Power Supply.
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS® and GCI.
4.096 MHz serial clock for shifting data in and out of the data streams.
These lines provide the address to IDT72V8988 internal registers.
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Active LOW input enabling a microprocessor read or write of control register or internal memories.
These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
3
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
FUNCTIONAL DESCRIPTION (Cont'd)
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT72V8988. Output channels are selected into
specific modes such as: Processor Mode or Connection mode, Variable or
Constant throughput delay modes, Output Drivers Enabled or in three-state
condition.
four output (TX0-3) serial streams are provided in the IDT72V8988 device
allowing a complete 128 x 128 channel non-blocking switch matrix to be
constructed. The serial interface clock for the device is 4.096 MHz.
The received serial data is internally converted to parallel by the on chip
serial-to-parallel converters and stored sequentially in a 128-position Data
Memory. By using an internal counter that is reset by the input 8 KHz frame pulse,
F0i, the incoming serial data streams can be framed and sequentially addressed.
Depending on the type of information to be switched, the IDT72V8988 device
can be programmed to perform time slot interchange functions with different
throughput delay capabilities on a per-channel basis. The Variable Delay
mode, most commonly used for voice applications, can be selected ensuring
minimum throughput delay between input and output data. In Constant Delay
mode, used in multiple or grouped channel data applications, the integrity of the
information through the switch is maintained.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master output three-state control pin. If the ODE input
is held LOW all TDM (Time Division Multiplexed) outputs will be placed in high
impedance regardless Connection Memory High programming. However, if
ODE is HIGH, the contents of Connection Memory High control the output state
on a per-channel basis.
SERIAL INTERFACE TIMING
The IDT72V8988 master clock (C4i) is 4.096 MHz signal allowing serial data
link configuration at 2.048 Mb/s to be implemented. The IDT72V8988 can
automatically detect the presence of an input frame pulse, identify the type of
backplane present on the serial interface, and format the synchronization pulse
according to ST-BUS® or GCI interface specifications (active HIGH in GCI or
active LOW in ST-BUS®). Upon determining the correct interface Connected
to the serial port, the internal timing unit establishes the appropriate serial data
bit transmit and sampling edges. In ST-BUS® mode, every second falling edge
of the 4.096 MHz clock marks a boundary and the input data is clocked in by
the rising edge, three quarters of the way into the bit cell. In GCI mode every
second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit
boundaries.
CONNECTION MEMORY
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is split into HIGH
and LOW parts and is associated with particular TX output streams. In Processor
Mode, data output on the TX streams is taken from the Connection Memory Low
and originates from the microprocessor (Figure 2). Where as in Connection
Mode (Figure 1), data is read from Data Memory and originated from the
incoming RX streams. Data destined for a particular channel on the serial output
stream is read internally during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locations are mapped to corresponding 8-bit x 32-channel output. The contents
of the Data Memory at the selected address are then transferred to the parallelto-serial converters before being output. By having the output channel to specify
the input channel through the Connection Memory, the same input channel can
be broadcast to several output channels.
DELAY THROUGH THE IDT72V8988
The transfer of information from the input serial streams to the output serial
streams results in a delay through the device. The delay through the
IDT72V8988 device varies according to the mode selected in the V/C bit of the
Connection Memory High.
VARIABLE DELAY MODE
The delay in Variable Delay Mode is dependent only on the combination
of source and destination on the input and output streams. The minimum delay
achievable in the IDT72V8988 device is three time slots. In the IDT72V8988
device, the information that is to be output in the same channel position as the
information is input (position n), relative to frame pulse, will be output in the
following frame (channel n, frame n+1). The same occurs if the input channels
succeeding (n+1, n+2) the channel position as the information is input.
PROCESSOR MODE
In Processor Mode the CPU writes data to the Connection Memory Low
locations which correspond to the output link and channel number. The contents
of the Connection Memory Low are transferred to the parallel-to-serial
converter one channel before it is to be output and are transmitted each frame
to the output until it is changed by the CPU.
RX
Receive
Serial Data
Streams
Data
Memory
Connection
Memory
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
TX
Data
Memory
Connection
Memory
Transmit
Serial Data
Streams
TX
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Microprocessor
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Figure 2. Processor Mode
Figure 1. Connection Mode
4
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
The information switched to the third time slot after the input has entered the
device (for instance, input channel 0 to output channel 3 or input channel 30 to
output channel 1), will always appear on the output three channels later in the
same incoming frame.
Any switching configuration that provides three or more time slots between
input and output channels, will have a throughput delay equal to the difference
between the output and input channels; i.e., the throughput delay will be less
than one frame. Table 1 shows the possible delays for the IDT72V8988 device
in Variable Delay Mode. An example is shown in Figure 3.
SOFTWARE CONTROL
If the A5, A1, A0 address line inputs are LOW then the IDT72V8988 Internal
Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8988 Data and
Connect memories. See Figure 6 for accessing internal memories.
The data in the control register consists of Memory Select and Stream
Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
Stream Address bits define internal memory subsections corresponding to input
or output streams.
The Processor Enable bit (bit 6) places every output channel on every
output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW (CML, Table 5) are output on the output streams once every frame unless
the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8988 behaves as
if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory
High (CMH, Table 4) locations were set to HIGH, regardless of the actual value.
If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
the CML define the source information (stream and channel) of the time slot that
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) for that particular channel.
CONSTANT DELAY MODE
In this mode frame integrity is maintained in all switching configurations by
making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
In the IDT72V8988, the minimum throughput delay achievable in Constant
Delay mode will be 32 time slots; for example, when input time slot 32 (channel
31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay
is achieved when the first time slot in a frame (channel 0) is switched to the last
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).
To summarize, any input time slot from input frame N will be always switched
to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:
DELAY=[32+(32-IN)+(OUT-1)]
IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).
MICROPROCESSOR PORT
The IDT72V8988 microprocessor port is a non-multiplexed bus architecture. The parallel port consists of an 8-bit parallel data bus (D0-D7), six address
input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel
microport allows the access to the Control Registers, Connection Memory Low,
Connection Memory High, and the Data Memory. All locations are read/write
access able except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
Memory are multiplexed with accesses from the input and output TDM ports.
This can cause variable Data Acknowledge delays (DTA). In the IDT72V8988
device, the DTA output provides a maximum acknowledgment delay of 800ns
for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
can be 1220ns.
INITIALIZATION
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two Connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
As the connection memory can be in any state after a power up, the ODE
pin should be used to hold the TX streams in high-impedance until the perchannel output enable control in the connection memory high is appropriately
programmed.
TABLE 1 VARIABLE DELAY MODE
TABLE 2 ADDRESS MAPPING
Input Channel
Output Channel
Throughput Delay
A5
A4
A3
A2
A1
A0
LOCATION
n
m=n, n+1 or n+2
m-n+32 time slot
n
m>n+2
m-n time slot
X
0
0
X
0
0
X
0
0
0
0
0
0
0
1
Control Register
Channel 0
Channel 1
n
m<n
32-(n-m) time slot
0
1
1
1
1
1
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
Channel 31
5
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
Incoming Now
Time Slot 32 31 30 29 28............ 3
A B C D E F
G H
Outgoing Next
2 1
I
J
32 Slots
E F G H
32 Slots
5
4
3 2
32 31.........7 6
J J J
G H I
4
3
2 1 Time Slot
J
32 Slots
Switching
2 1
I
5
Figure 3. Variable Delay Mode
Incoming
A B C D
6
32 Slots
For J: DELAY=3 Slots, 32 Slots, 33 Slots, and 34 Slots
For G, H, and I: DELAY= 3 slots
Time Slot 32 31 30 29 28............ 3
32 31........7
1
Outgoing Now
Outgoing
32 31 30 29 28............. 3 2 1 Time Slot
J
J
32 Slots
I
H
G F E
D C B A
32 Slots
5704 drw07
For Slot 1 ("A"): IN=32, OUT=1, DELAY=(32-32)+32+(1-1)=32 time slots minimum delay
For Slot 32 ("J"): IN=1, OUT=32, DELAY=(32-1)+32+(32-1)=94 time slots maximum delay
Figure 4. Constant Delay Mode
6
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Control Register
Commercial Temperature Range
CRb7
CRb6
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CRb5
CRb4
0
1
1
CRb4
CRb3
CRb2
CRb1
CRb0
CRb3
1
0
1
Connection Memory High
Connection Memory Low
Data Memory
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
100000
100001
100010
Channel 31
Channel 31
Channel 31
Channel 31
111111
CRb1
0
0
1
1
External Address Bits
CRb0 Stream
0
0
1
1
0
2
1
3
A5-A0
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Figure 5. Addressing Internal Memories
7
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
TABLE 3 CONTROL REGISTER
Bit
7
6
5
4
3
2
1
0
SM
PE
X
MS1
MS0
X
STA1
STA0
Name
Description
7
SM (Split Memory)
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory, except
when the Control Register is accessed again. The Memory Select bits need to specify the memory for the
operations.
6
PE (Processor Mode)
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when in highimpedance. When 0, the Connection Memory bits for each channel determine what is output.
5,2
unused
4-3
MS1-MS0
(Memory Select Bits)
0-0 - Not to be used.
0-1 - Data Memory (read only from the CPU)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
1-0
STA1-0
(Stream Address Bits)
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
subsection of memory made accessible for subsequent operations.
x = don't care
TABLE 4 CONNECTION MEMORY HIGH
Bit
7
6
5
4
3
2
1
0
X
V/C
X
X
X
CS
X
OE
Name
7,5,4,3,1
Description
unused
6
V/C (Variable/Constant
This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis.
Throughput Delay Mode)
2
CS
(Channel Source)
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
0
OE (Output Enable)
This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to
be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it.
x = don't care
TABLE 5 CONNECTION MEMORY LOW
Bit
6
5
4
3
2
1
0
X
SAB1
SAB0
CAB4
CAB3
CAB2
CAB1
CAB0
Name
7
6-5
7
Description
unused
SAB2-0(1)
(Source Stream Address Bits)
These three bits are used to select eight source streams for the Connection.
4-0(1) CAB2-0(1)
These five bits are used to select 32 different source channels for the Connection (the stream where the channel
(Source Channel Address Bits) is present is defined by bits SAB2-0). Bit 4 is the most significant bit.
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the Connection which is output on the channel and stream associated with this location.
8
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vcc
Vi
Parameter
Min.
Max.
Unit
Symbol Voltage
-0.3
5.0
V
GND - 0.3
VCC +0.5
V
Voltage on Digital Inputs
VO
Voltage on Digital Outputs
IO
Current at Digital Outputs
TS
Storage Temperature
PD
Package Power Dissapation
GND - 0.3
-55
VCC +0.3
V
20
mA
+125
°C
1
W
RECOMMENDED OPERATING
CONDITIONS
Symbol
Parameter
Min.
VCC
Positive Supply
VI
Input Voltage
TOP
Operating Temperature
Commercial
Typ.(1)
Max.
Unit
3.0
3.3
3.6
V
0
5.25
V
-40
25
+85
°C
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject
to production testing.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections
of this specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Min.
Typ.(1)
Max.
Units
Test Conditions
ICC
Supply Current
3
5
mA
Outputs Unloaded
VIH
Input High Voltage
2.0
V
VIL
Input Low Voltage
0.8
V
IIL
Input Leakage (Inputs)
15
µA
CI
Symbol
Parameter
VI between GND and VCC
Input Capacitance
10
pF
VOH
Output High Voltage
2.4
V
IOH = 10mA
IOH
Output High Current
10
mA
Sourcing. VOH = 0.8V
VOL
Output Low Voltage
0.4
V
IOL = 5mA
IOL
Output Low Current
5
mA
Sinking. VOL = 0.4V
I OZ
High Impedance Leakage
5
µA
VO between GND and VCC
CO
Output Pin Capacitance
10
pF
NOTE:
1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Test Point
VCC
S1 is open circuit except when testing
output levels or high impedance states.
RL
Output
Pin
S1
S2
S2 is switched to VCC or GND when
testing output levels or high impedance
states.
CL
GND
GND
5704 drw09
Figure 6. Output Load
9
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
ST-BUS® TIMING
(1)
Min.
Typ.(2)
Max.
Units
tF0iW
Frame Pulse Width
244
ns
tF0iS
Frame Pulse Setup Time
5
20
190
ns
tF0iH
Frame Pulse Hold Time
5
20
190
ns
tDAA
TX delay Active to Active
40
60
ns
tSTiS
RX Setup Time
10
ns
tSTiH
RX Hold Time
10
ns
tC4i
Clock Period
244
ns
tCL
CK Input Low
122
ns
tCH
CK Input High
122
ns
tr, tf
Clock Rise/Fall Time
10
ns
Test Conditions
CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
C4i
F0i
Bit Cells
Channel 31
Bit 0
Channel 0
Bit 7
5704 drw10
Figure 7. ST-BUS® Timing
10
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
(1)
GCI TIMING
Min.
Typ.(2)
Max.
Units
tC4i
Clock Period
244
ns
tCL, tCH
Pulse Width
122
ns
tWFH
Frame Width High
244
ns
tF0iS
Frame Setup
5
20
190
ns
tF0iH
Frame Hold
5
20
190
ns
tDAA
Data Delay/Clock Active to Active
40
60
ns
tSTiS
Serial Input Setup
10
ns
tSTiH
Serial Input Hold
10
ns
tr, tf
Clock Rise/Fall Time
10
ns
Test Conditions
CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
tWFH
F0i
tF0iS
tr
tF0iH
tCL
tf
tCH
tC4i
C4i
TX
Ch. 31
Bit 7
Ch. 0
Bit 0
Ch. 0
Bit 1
tDAA
tSTiS
RX
Ch. 31
Bit 7
Ch. 0
tSTiH
Bit 0
Ch. 0
Bit 1
5704 drw11
Figure 8. GCI Timing
11
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristics
(1)
SERIAL STREAM TIMING
Min.
Typ.(2)
Max.
Unit
Test Conditions
tTAZ
TX0-3 Delay - Active to High Z
30
45
ns
RL = 1KΩ(3), CL = 150pF
tTZA
TX0-3 Delay - High Z to Active
45
60
ns
CL = 150pF
tOED
Output Driver Enable Delay
45
60
ns
RL = 1KΩ(3), CL = 150pF
tZDO
High Z to Valid Data
32
cycles
C4i cycles
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Bit Cell Boundary
(GCI)
C4i
(ST-BUS)
tTAZ
ODE
tOED
TX0-3
tOED
TX0-3
tTZA
5704 drw13
TX0-3
5704 drw12
Figure 10. Output Driver Enable
Figure 9. Serial Outputs and External Control
12
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS
Symbol
Characteristics
(1)
MICROPROCESSOR TIMING
Min.
Typ.(2)
Max.
Unit
Test Conditions
tCSS
CS Setup from DS Rising
0
ns
tRWS
R/W Setup from DS Rising
5
ns
tADS
Add Setup from DS Rising
5
ns
tCSH
CS Hold after DS Falling
0
ns
tRWH
R/W Hold after DS Falling
5
ns
tADH
Add Hold after DS Falling
5
ns
tDDR
Data Setup from DTA Low on Read
10
ns
CL = 150pF
tDHR
Data Hold on Read
10
50
90
ns
RL = 1KΩ(3), CL = 150pF
tDSW
Data Setup on Write (Fast Write)
10
ns
tSWD
Valid Data Delay on Write (Slow Write)
122
ns
tDHW
Data Hold on Write
5
ns
tAKD
Acknowledgment Delay:
Reading Data Memory
Reading/Writing Connection Memory
Writing to Control Register
Reading to Control Register
560
300/370
45
45
1220
730/800
70
70
ns
ns
ns
ns
Acknowledgment Hold Time
10
20
40
ns
tAKH
CL = 150pF
RL = 1KΩ(3), CL = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
CS
tCSS
tCSH
tRWS
tRWH
tADS
tADH
R/W
A0-A5
D0-D7
READ
VALID DATA
tSWD
tDHR
tDSW
D0-D7
WRITE
VALID DATA
tDDR
tAKD
DTA
tDHW
tAKH
5704 drw15
Figure 11. Motorola Non-Multiplexed Bus Timing
13
ORDERING INFORMATION
IDT
XX
XXXXXX
Device Type
Package
X
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
J
DB
Plastic Leaded Chip Carrier (PLCC, J44-1)
Plastic Quad Flatpack (PQFP, DB44-1)
72V8988
128 x 128 3.3V Time Slot Interchange Digital Switch
5704 drw16
DATASHEET DOCUMENT HISTORY
05/24/2000
08/21/2000
01/24/2001
04/05/2001
03/10/2003
05/09/2003
08/20/2003
pgs.
pgs.
pgs.
pg.
pg.
pgs.
pg.
1, 2, 13 and 14.
1, 2 and 14.
1 and 9.
11.
1.
1-3, 5, 12 and 14.
9.
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800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
14
for Tech Support:
408-330-1753
email: [email protected]