FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12515-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89630 Series
MB89635/T635/636/637/T637/P637/W637/PV630
■ DESCRIPTION
The MB89630 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as
dual-clock control system, five operating speed control stages, a UART, timers, a PWM timer, a serial interface,
an A/D converter, an external interrupt, and a watch prescaler.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• High-speed operating capability at low voltage
• Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.
• Five types of timers
8-bit PWM timer: 2 channels (Also usable as a reload timer)
8-bit pulse-width count timer (Continuous measurement capable, applicable to remote control, etc.)
16-bit timer/counter
21-bit time-base timer
• UART
CLK-synchronous/CLK-asynchronous data transfer capable (6, 7, and 8 bits)
• Serial interface
Switchable transfer direction to allows communication with various equipment.
• 10-bit A/D converter
Activation by an external input capable
(Continued)
MB89630 Series
(Continued)
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
Subclock mode
Watch mode
• Bus interface function
With hold and ready function
■ PACKAGE
2
64-pin Plastic SH-DIP
64-pin Plastic QFP
64-pin Plastic QFP
(DIP-64P-M01)
(FPT-64P-M06)
(FPT-64P-M09)
64-pin Ceramic SH-DIP
64-pin Ceramic MDIP
64-pin Ceramic MQFP
(DIP-64C-A06)
(MDP-64C-P02)
(MQP-64C-P01)
MB89630 Series
■ PRODUCT LINEUP
Part number
Parameter
MB89635
MB89636
MB89637
MB89T635 MB89T637 MB89P637 MB89W637 MB89PV630
Classification
Mass production products
(mask ROM products)
ROM size
RAM size
CPU functions
Ports
16 K × 8
bits
24 K × 8
bits
32 K × 8
bits
(internal
mask ROM)
(internal
mask ROM)
(internal
mask ROM)
512 × 8 bits 768 × 8 bits
1024 × 8
bits
External ROM
products
Fixed to external
ROM
512 × 8
bits
One-time
PROM
product
EPROM
product
32 K × 8 bits
(Internal PROM,
programming with
general-purpose
EPROM programmer)
Piggyback/
evaluation
product (for
evaluation
and
development)
32 K × 8 bits
(external
ROM)
1024 × 8 bits
Number of instructionns:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 to 6.4 µs/10 MHz, 61 µs/32.768 kHz
3.6 to 57.6 µs/10 MHz, 562.5 µs/32.768 kHz
Input ports:
Output ports (N-ch open-drain):
I/O ports (N-ch open-drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
5 (All also serve as peripherals.)
8 (All also serve as peripherals.)
4 (All also serve as peripherals.)
8 (All also serve as bus control.)
28 (27 ports also serve as bus pins and peripherals.)
53
Clock timer
21 bits × 1 (in main clock)/15 bits × 1 (at 32.768 kHz)
8-bit PWM
timer
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) × 2
channels
7/8-bit resolution PWM operation (conversion cycle: 51.2 µs to 839 ms) × 2 channels
8-bit pulse
width count
timer
8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit pulse width measurement operation (continuous measurement capable,
measurement of “H” pulse width/ “L” pulse width/ from ↑ to ↑/from ↓ to ↓ capable)
16-bit timer/
counter
16-bit timer operation (operating clock cycle: 0.4 µs)
16-bit event counter operation (rising edge/falling edge/both edge selectability)
8-bit serial I/O
UART
10-bit A/D
converter
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
Switching two I/O systems by software capable
Transfer data length (6, 7, and 8 bits)
Transfer rate (300 to 62500 bps. at 10 MHz osciliation)
10-bit resolution × 8 channels
A/D conversion mode (conversion time: 13.2 µs)
Sense mode (conversion time: 7.2 µs)
Continuous activation by an external activation or an internal timer capable
(Continued)
3
MB89630 Series
(Continued)
Part number
MB89635
Parameter
MB89636
MB89637
MB89T635 MB89T637 MB89P637 MB89W637 MB89PV630
External
interrupt input
4 independent channels (edge selection, interrupt vector, source flag).
Rising edge/falling edge selectability
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby mode
Sleep mode, stop mode, watch mode, and subclock mode
Process
CMOS
Operating
voltage*1
2.2 V to 6.0 V
2.7 V to 6.0 V
EPROM for use
MBM27C256A-20
*1: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
In the case of the MB89PV630, the voltage varies with the restrictions of the EPROM for use.
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89635
MB89T635
Package
MB89636
MB89637
MB89T637
MB89P637
DIP-64P-M01
DIP-64C-A06
×
×
MB89PV630
×
×
×
×
×
×
×*
×*
×*
FPT-64P-M06
FPT-64P-M09
MB89W637
MDP-64C-P02
×
×
×
×
MQP-64C-P01
×
×
×
×
: Available
×: Not available
* : To convert pin pitches, an adapter socket (manufacturer: Sun Hayato Co., Ltd.) is available.
64SD-64QF2-8L: For conversion from (DIP-64P-M01, DIP-64C-A06, or MDP-64C-P02) to FPT-64P-M09
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89630 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
On the MB89P637/W637, the program area starts from address 8007H but on the MB89PV630 and MB89637
starts from 8000H.
(On the MB89P637/W637, addresses 8000H to 8006H comprise the option setting area, option settings can be
read by reading these addresses. On the MB89PV630/MB89637, addresses 8000H to 8006H could also be used
as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P637/
W637.)
• The stack area, etc., is set at the upper limit of the RAM.
• The external area is used.
2. Current Consumption
• In the case of the MB89PV630, add the current consumed by the EPROM which connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-up resistor cannot be set for P50 to P53 on the MB89P637 and MB89W637.
• Options are fixed on the MB89PV630, MB89T635, and MB89T637.
■ CORRESPONDENCE BETWEEN THE MB89630 AND MB89630R SERIES
• The MB89630R series is the reduction version of the MB89630 series. For their differences, refer to the
MB89630R series data sheet.
• The the MB89630 and MB89630R series consist of the following products:
MB89630 series
MB89635
MB89T635
MB89636
MB89637
MB89630R series
MB89635R
MB89T635R
MB89636R
MB89T637R
MB89P637
MB89W637
MB89PV630
5
MB89630 Series
■ PIN ASSIGNMENT
(Top view)
P31/UO1
P30/UCK1
P43/PTO1
P42/UI2
P41/UO2
P40/UCK2
P53/PTO2
P52
P51/BZ
P50/ADST
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVCC
AVR
AVSS
P74/EC
P73/INT3
P72/INT2
P71/INT1/X0A*
P70/INT0/X1A*
RST
MOD0
MOD1
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
64
63
62
92
61
91
60
90
59
89
58
88
57
87
56
86
55
85
54
84
53
83
52
82
51
81
50
80
49
79
48
47
46
45
44
Each pin inside
43
the dashed line is
42
for MB89PV630 only. 41
40
39
38
37
36
35
34
33
(DIP-64P-M01)
(DIP-64C-A06)
(MDP-64C-P02)
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
VCC
P32/UI1
P33/SCK1
P34/SO1
P35/SI1
P36/PWC
P37/WTO
VSS
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
P27/ALE
*: When the dual-clock system is selected.
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P52
P53/PTO2
P40/UCK2
P41/UO2
P42/UI2
P43/PTO1
P30/UCK1
P31/UO1
VCC
P32/UI1
P33/SCK1
P34/SO1
P35/SI1
P36/PWC
P37/WTO
VSS
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P71/INT1/X0A*
P70/INT0/X1A*
RST
MOD0
MOD1
X0
X1
VSS
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P51/BZ
P50/ADST
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVCC
AVR
AVSS
P74/EC
P73/INT3
P72/INT2
(FPT-64P-M09)
6
*: When the dual-clock system is selected.
MB89630 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
P53/PTO2
P40/UCK2
P41/UO2
P42/UI2
P43/PTO1
P30/UCK1
P31/UO1
VCC
P32/UI1
P33/SCK1
P34/SO1
P35/SI1
P36/PWC
(Top view)
1
2
3
4
5
6
85
77
7
86
76
8
87
75
9
88
74
10
89
73
11
90
72
12
91
71
13
92
70
14
93
69
15
16
17
18
19 Each pin inside the dashed line
is for MB89PV630 only.
94
95
96
65
66
67
68
84
83
82
81
80
79
78
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P37/WTO
VSS
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
RST
MOD0
MOD1
X0
X1
VSS
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
20
21
22
23
24
25
26
27
28
29
30
31
32
P52
P51/BZ
P50/ADST
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVCC
AVR
AVSS
P74/EC
P73/INT3
P72/INT2
P71/INT1/X0A*
P70/INT0/X1A*
(FPT-64P-M06)
(MQP-64C-P01)
*: When the dual-clock system is selected.
• Pin assignment on package top (MB89PV630 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
65
N.C.
73
A2
81
N.C.
89
OE
66
VPP
74
A1
82
O4
90
N.C.
67
A12
75
A0
83
O5
91
A11
68
A7
76
N.C.
84
O6
92
A9
69
A6
77
O1
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
71
A4
79
O3
87
CE
95
A14
72
A3
80
VSS
88
A10
96
VCC
N.C.: Internally connected. Do not use.
7
MB89630 Series
■ PIN DESCRIPTION
Pin no.
QFP2*3
QFP1*4
MQFP*5
30
22
23
X0
31
23
24
X1
28
20
21
MOD0
29
21
22
MOD1
27
19
20
RST
56 to 49
48 to 41
48 to 41
40 to 33
40
32
33
39
31
38
Circuit
type
Function
A
Main clock crystal oscillator pins
D
Operating mode selection pins
Connect directly to VCC or VSS
C
Reset I/O pin
This pin is an N-ch open-drain output type with a
pull-up resistor, and a hysteresis input type. “L” is
output from this pin by an internal reset source.
The internal circuit is initialized by the input of “L”.
49 to 42 P00/AD0 to
P07/AD7
F
General-purpose I/O ports
When an external bus is used, these ports
function as the multiplex pins of the lower address
output and the data I/O.
41 to 34 P10/A08 to
P17/A157
F
General-purpose I/O ports
When an external bus is used, these ports
function as an upper address output.
P20/BUFC
H
General-purpose output-only port
When an external bus is used, this port can also
be used as a buffer control output by setting the
BCTR.
32
P21/HAK
H
General-purpose output-only port
When an external bus is used, this port can also
be used as a hold acknowledge by setting the
BCTR.
30
31
P22/HRQ
F
General-purpose output-only port
When an external bus is used, this port can also
be used as a hold request input by setting the
BCTR.
37
29
30
P23/RDY
F
General-purpose output-only port
When an external bus is used, this port functions
as a ready input.
36
28
29
P24/CLK
H
General-purpose output-only port
When an external bus is used, this port functions
as a clock output.
35
27
28
P25/WR
H
General-purpose output-only port
When an external bus is used, this port functions
as a write signal output.
34
26
27
P26/RD
H
General-purpose output-only port
When an external bus is used, this port functions
as a read signal output.
*1: DIP-64P-M01, DIP-64C-A06
*2: MDP-64C-P02
*3: FPT-64P-M09
8
Pin name
SH-DIP*1
MDIP*2
*4: FPT-64P-M06
*5: MQP-M64C-P01
(Continued)
MB89630 Series
(Continued)
Pin no.
SH-DIP
MDIP*2
*1
QFP2*3
QFP1*4
MQFP*5
Pin name
Circuit
type
Function
33
25
26
P27/ALE
H
General-purpose output-only port
When an external bus is used, this port functions as
an address latch signal output.
2
58
59
P30/UCK1
G
General-purpose I/O port
Also serves as the clock I/O 1 for the UART. This
port is a hysteresis input type.
1
57
58
P31/UO1
F
General-purpose I/O port
Also serves as the data output 1 for the UART.
63
55
56
P32/UI1
G
General-purpose I/O port
Also serves as the data input 1 for the UART. This
port is a hysteresis input type.
62
54
55
P33/SCK1
G
General-purpose I/O port
Also serves as the data input for the 8-bit serial
I/O. This port is a hysteresis input type.
61
53
54
P34/SO1
F
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O.
60
52
53
P35/SI1
G
General-purpose I/O port
Also serves as the data input for the 8-bit serial
I/O. This port is a hysteresis input type.
59
51
52
P36/PWC
G
General-purpose I/O port
Also serves as the measured pulse input for the
8-bit pulse width counter. This port is a hysteresis
input type.
58
50
51
P37/WTO
F
General-purpose I/O port
Also serves as the toggle output for the 8-bit pulse
width counter.
6
62
63
P40/UCK2
G
General-purpose I/O port
Also serves as the clock I/O 2 for the UART. This
port is a hysteresis input type.
5
61
62
P41/UO2
F
General-purpose I/O port
Also serves as the data output 2 for the UART.
4
60
61
P42/UI2
G
General-purpose I/O port
Also serves as the data input 2 for the UART. This
port is a hysteresis input type.
3
59
60
P43/PTO1
F
General-purpose I/O port
Also serves as the toggle output for the 8-bit PWM
timer.
10
2
3
P50/ADST
K
General-purpose I/O port
Also serves as an A/D converter external activation.
This port is a hysteresis input type.
9
1
2
P51/BZ
J
General-purpose I/O port
Also serves as a buzzer output.
*1: DIP-64P-M01, DIP-64C-A06
*2: MDP-64C-P02
*3: FPT-64P-M09
*4: FPT-64P-M06
*5: MQP-M64C-P01
(Continued)
9
MB89630 Series
(Continued)
Pin no.
Function
8
64
1
P52
J
General-purpose I/O port
7
63
64
P53/PTO2
J
General-purpose I/O port
Also serves as the toggle output for the 8-bit PWM
timer.
11 to 18
3 to 10
4 to 11
P60/AN0 to
P67/AN7
I
N-ch open-drain output-only ports
Also serve as an A/D converter analog input.
26,
25
18,
17
19,
18
P70/INT0/X1A,
P71/INT1/X0A
24,
23
16,
15
17,
16
P72/INT2,
P73/INT3
E
Input-only ports
Also serve as an external interrupt input.
These ports are a hysteresis input type.
22
14
15
P74/EC
E
General-purpose input port
Also serves as the external clock input for the
16-bit timer/counter. This port is a hysteresis input
type.
64
56
57
VCC
—
Power supply pin
32, 57
24,49
25, 50
VSS
—
Power supply (GND) pin
19
11
12
AVCC
—
A/D converter power supply pin
20
12
13
AVR
—
A/D converter reference voltage input pin
21
13
14
AVSS
—
A/D converter power supply pin
Use this pin at the same voltage as VSS.
*1: DIP-64P-M01, DIP-64C-A06
*2: MDP-64C-P02
*3: FPT-64P-M09
10
Circuit
type
QFP2
*3
QFP1*4
MQFP*5
Pin name
SH-DIP*1
MDIP*2
B/E
*4: FPT-64P-M06
*5: MQP-M64C-P01
Input-only ports
These ports are a hysteresis input type.
Also serve as an external interrupt input (at singleclock operation).
Subclock crystal oscillator pins (at dual-clock
operation)
MB89630 Series
• External EPROM pins (MB89PV630 only)
Pin no.
Pin name
I/O
Function
MDIP
MQFP
65
66
VPP
O
“H” level output pin
66
67
68
69
70
71
72
73
74
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
75
76
77
77
78
79
O1
O2
O3
I
Data input pins
78
80
VSS
O
Power supply (GND) pin
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
I
Data input pins
84
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
88
A10
O
Address output pin
86
89
OE
O
ROM output enable pin
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
Address output pins
90
94
A13
O
91
95
A14
O
92
96
VCC
O
EPROM power supply pin
—
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
11
MB89630 Series
■ I/O CIRCUIT TYPE
Type
A
Circuit
Remarks
• Crystal or ceramic oscillation type (main clock)
External clock input selection versions of MB89PV630,
MB89P637, MB89W637, MB89635, MB89T635, MB89636,
MB89637, and MB89T637
At an oscillation feedback resistor of approximately
1 MΩ/5 V
X1
X0
Standby control signal
• Crystal or ceramic oscillation type (main clock)
Oscillation selection versions of MB89PV630, MB89P637,
MB89W637, MB89635, MB89T635, MB89636, MB89637,
and MB89T637
At an oscillation feedback resistor of approximately
1 MΩ/5 V
X1
X0
Standby control signal
B
• Crystal or ceramic oscillation type (subclock)
MB89PV630, MB89P637, MB89W637, MB89635,
MB89636, and MB89637 with dual-clock system
At an oscillation feedback resistor of approximately
4.5 MΩ/5 V
X1A
X0A
Standby control signal
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5 V
• Hysteresis input
R
P-ch
N-ch
D
E
• Hysteresis input
R
• Pull-up resistor optional (except P70 and P71)
F
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (except P22 and P23)
(Continued)
12
MB89630 Series
(Continued)
Type
Circuit
Remarks
G
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
H
• CMOS output
P-ch
N-ch
I
• Analog input
N-ch
Analog input
J
• CMOS input
R
P-ch
N-ch
• Pull-up resistor optional
K
• Hysteresis input
R
P-ch
N-ch
• Pull-up resistor optional
13
MB89630 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (option selection)
and wake-up from stop mode.
14
MB89630 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P637
The MB89P637 is an OTPROM version of the MB89630 series.
1. Features
• 32-Kbytes PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode is illustrated below.
EPROM mode
(Corresponding addresses
on the EPROM programmer)
Normal operating mode
0000H
I/O
0080H
0100H
Register
RAM
0200H
0480H
External area
0000H
8000H
Option setting area
Option setting area
0007H
8007H
Program area
(EPROM)
32 KB
PROM
32 KB
FFFFH
7FFFH
3. Programming to the EPPROM
In EPROM mode, the MB89P637 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer by using the dedicated socket adapter.
However, the electronic signature mode cannot be used.
When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the EPROM can be programmed
as follows:
15
MB89630 Series
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH.
(Note that addresses 8000H to FFFFH in the operating mode assign to 0000H to 7FFFH in EPROM mode).
(3) Load option data into addresses 0000H to 0006H of the EPROM programmer.
(For information about each corresponding option, see “8. OTPROM Option Bit Map.”).
(4) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This
dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity
of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all
filters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,
nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and
exposure to them should be prevented to realize maximum system reliability. If used in such an environment,
the package windows should be covered by an opaque label or substance.
16
MB89630 Series
7. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
DIP-64C-M01
ROM-64SD-28DP-8L
FPT-64P-M06
ROM-64QF-28DP-8L
FPT-64P-M09
ROM-64QF2-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
8. OTPROM Option Bit Map
Bit 7
0000H
0001H
0002H
0003H
0004H
0005H
0006H
Bit 6
Bit 5
Bit 4
Vacancy
Vacancy
Vacancy
Single/dualclock system
Readable
Readable
Readable
1: Dual clock
and writable and writable and writable 0: Single clock
Bit 3
Reset pin
output
1: Yes
0: No
P03
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P33
Pull-up
1: No
0: Yes
P43
Vacancy
Pull-up
Readable and 1: No
Readable
Readable
Readable
0: Yes
and writable and writable and writable writable
Bit 2
Power-on
reset
1: Yes
0: No
P02
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P32
Pull-up
1: No
0: Yes
P42
Pull-up
1: No
0: Yes
Bit 1
Oscillation stabilization (F/CH)
11:218
10:214
P01
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P31
Pull-up
1: No
0: Yes
P41
Pull-up
1: No
0: Yes
01:217
00:24
P00
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
P30
Pull-up
1: No
0: Yes
P40
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Readable
and writable
Reserved bit
Readable
and writable
P07
Pull-up
1: No
0: Yes
P17
Pull-up
1: No
0: Yes
P37
Pull-up
1: No
0: Yes
Vacancy
P06
Pull-up
1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P36
Pull-up
1: No
0: Yes
Vacancy
P05
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P35
Pull-up
1: No
0: Yes
Vacancy
P04
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P34
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Readable
and writable
Vacancy
Readable
and writable
Vacancy
Readable
and writable
Vacancy
P74
Pull-up
1: No
0: Yes
P73
Pull-up
1: No
0: Yes
P72
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Readable
and writable
Vacancy
Readable
and writable
Readable
and writable
Readable
and writable
Readable
and writable
Readable
and writable
Readable and Readable
and writable
writable
Bit 0
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the blank bit.
The read value of the vacant bit is 1, unless 0 is written to it.
• Always write 1 to the reserved bit.
17
MB89630 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
LCC-32(Square)
ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address
Single chip
Corresponding addresses on the EPROM programmer
0000H
I/O
0080H
RAM
0480H
Not available
8000H
0000H
Not available
Not available
8006H
0006H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0006H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
18
MB89630 Series
■ BLOCK DIAGRAM
X0A
X1A
Subclock oscillator
(32.768 kHz)
21-bit time-base timer
Clock controller
CMOS I/O port
Reset circuit
(Watchdog timer)
8-bit PWC timer
Watch prescaler
8-bit serial I/O
R ST
8
P32/UI1
P31/UO1
P30/UCK1
UART
P40/UCK2
P41/UO2
P42/UI2
MOD0
MOD1
External bus
interface
UART baud rate
generator
CMOS I/O port
Port 2
P27 /ALE
P26 /RD
P25 /W R
P24 /CLK
P23 /RDY
P22 /HRQ
P21 /HAK
P20 /BUFC
P 3 3 / S C K1
Port 4
P1 0/A0 8
to P17 /A15
CMOS I/O port
P35/SI1
P34/SO1
P43/PTO1
N-ch open-drain I/O port
CMOS output port
8-bit PWM timer
P53/PTO2
P52
Port 5
8
Port0 and port1
P0 0/AD0
to P0 7/AD 7
P 3 7 / WT O
P 3 6 / P WC
Port 3
Main clock oscillator
Internal bus
X0
X1
Buzzer output
P51/BZ
RAM
3
10-bit A/D converter
F 2 M C- 8L
CPU
N-ch open-drain output port
8
Port 6
8
P 5 0 / A D ST
A V CC, A V SS ,
AVR
P60/AN0
t o P 6 7 / A N7
RO M
External interrupt
Other pins
VCC × 2, VSS × 2
16-bit timer/counter
4
Port 7
Input port
P70/INT0
P71/INT1
P72/INT2
P73/INT3
P74/EC
19
MB89630 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89630 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89630 series is structured as illustrated below.
Memory Space
0000H
MB89PV630
0000H
0080H
0200H
0080H
RAM
1 KB
RAM
768 B
0100H
0100H
Register
0200H
0000H
I/O
0080H
0100H
Register
MB89636
I/O
RAM
512 B
RAM
1 KB
0100H
0000H
I/O
I/O
0080H
MB89635
MB89T635
MB89637
MB89T637
MB89P637
MB89W637
Register
Register
0200H
0200H
0280H
0380H
0480H
0480H
External area
External area
8000H
External area
*2
External area
8007H
8000H
8007H
*2
A000H
C000H
External ROM
32 KB
FFFFH
ROM*1
32 KB
1
ROM*
24 KB
ROM*1
16 KB
FFFFH
FFFFH
FFFFH
*1: The ROM area is an external area depending on the mode.
The internal ROM cannot be used on the MB89T635 and MB89T637.
*2: Addresses 8000H to 8006H for the MB89P637 and MB89W637 comprise an option area, do not use
this area for the MB89PV630 and MB89637.
20
MB89630 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A16-bit register for index modification
Extra pointer (EP):
A16-bit pointer for indicating a memory address
Stack pointer (SP):
A16-bit register for indicating a stack area
Program status (PS):
A16-bit register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
21
MB89630 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
22
MB89630 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89653A (RAM 512 × 8 bits). The bank
currently in use is indicated by the register bank pointer (RP).
Register Bank Configuraiton
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
23
MB89630 Series
■ I/O MAP
Address
Read/
write
Register
name
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register DD07 DD06 DD05 DD04 DD03 DD02 DD01 DD00
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register DD17 DD16 DD15 DD14 DD13 DD12 DD11 DD10
04H
(R/W)
PDR2
Port 2 data register
05H
(W)
BCTR
External bus pin control register
Register description
06H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00
PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10
PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20
—
—
—
—
—
—
HLD
BUF
Vacancy
07H
(R/W)
SYCC System clock control register
SMC
—
—
WT1
WT0
SCS
CS1
CS0
08H
(R/W)
STBC
STP
SLP
SPL
RST
TMD
—
—
—
09H
(R/W)
WDTE Watchdog timer control register CS
—
—
—
0AH
(R/W)
TBCR
—
—
—
TBC1 TBC0 TBR
0BH
(R/W)
WPCR Watch prescaler control register WIF
—
—
—
WS1
WS0
WCLR
0CH
(R/W)
CHG3 Port 3 switching register
—
—
—
0DH
(R/W)
PDR3
Port 3 data register
0EH
(W)
DDR3
Port 3 data direction register DD37 DD36 DD35 DD34 DD33 DD32 DD31 DD30
0FH
(R/W)
PDR4
Port 4 data register
—
—
—
—
PD43 PD42 PD41 PD40
10H
(W)
DDR4
Port 4 data direction register
—
—
—
—
DD43 DD42 DD41 DD40
11H
(R/W)
BUZR
Buzzer register
—
—
—
—
12H
(R/W)
PDR5
Port 5 data register
—
—
—
—
13H
(R/W)
PDR6
Port 6 data register
14H
(R)
PDR7
Port 7 data register
15H
(R/W)
PCR1
PWC pulse width control register 1
EN
TOE
IE
—
16H
(R/W)
PCR2
PWC pulse width control register 2
FC
RM
TO
—
17H
(R/W)
RLBR
PWC reload buffer register
RLB7 RLB6 RLB5 RLB4 RLB3 RLB2 RLB1 RLB0
18H
(R/W)
TMCR 16-bit timer control register
19H
(R/W)
TCHR 16-bit timer count register (H)
TC15 TC14 TC13 TC12 TC11 TC10 TC09 TC08
1AH
(R/W))
TCLR
TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00
System clock control register
Time-base timer control register
—
WIE
—
CG35 CG34 CG33
PD37 PD36 PD35 PD34 PD33 PD32 PD31 PD30
—
—
BUZ1 BUZ0
PD53 PD52 PD51 PD50
PD67 PD66 PD65 PD64 PD63 PD62 PD61 PD60
—
16-bit timer count register (L)
1BH
TBOF TBIE
WTE3 WTE2 WTE1 WTE0
—
—
—
—
TCR
PD74 PD73 PD72 PD71 PD70
—
C1
UF
IR
BF
C0
W1
W0
TCS1 TCS0 TCEF TCIE TCS
Vacancy
1CH
(R/W)
SMR1 Serial mode register
SIOF SIOE SCKE SOE
1DH
(R/W)
SDR1
SD07 SD06 SD05 SD04 SD03 SD02 SD01 SD00
Serial data register
1EH
Vacancy
1FH
Vacancy
CKS1 CKS0 BDS
SST
(Continued)
24
MB89630 Series
(Continued)
Address
Read/
write
Register
name
20H
(R/W)
ADC1
A/D converter control register 1 ANS3 ANS2 ANS1 ANS0 ADI
21H
(R/W)
ADC2
A/D converter control register 2
—
22H
(R/W)
ADDH
A/D converter data register (H)
—
23H
(R/W)
ADDL
A/D converter data register (L)
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
24H
(R/W)
EIC1
External interrupt control register 1
EIR1
25H
(R/W)
EIC2
External interrupt control register 2
EIR3
Register description
Bit 7
26H
Vacancy
27H
Vacancy
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ADMV SIFM AD
TIM1 TIM0 ADCK ADIE ADMD EXT
—
—
—
—
—
Bit 0
—
TEST
ADD9 ADD8
SEL1 EIE1
EIR0 INTE SEL0 EIE0
SEL3 EIE3
EIR2
—
SEL2 EIE2
28H
(R/W)
CNTR1 PWM timer control register 1
PTX1 PTX2 P7M1 P7M2 SC11 SC10 SC21 SC20
29H
(R/W)
CNTR2 PWM timer control register 2
TPE1 TPE2 CK12
2AH
(R/W)
CNTR3 PWM timer control register 3
2BH
(W)
COMR1 PWM timer compare register 1
CM17 CM16 CM15 CM14 CM13 CM12 CM11 CM10
2CH
(W)
COMR2 PWM timer compare register 2
CM27 CM26 CM25 CM24 CM23 CM22 CM21 CM20
2DH
(R/W)
SMC
UART serial mode control register
2EH
(R/W)
SRC
UART serial rate control register
2FH
(R/W)
SSD
UART serial status and data register RDRF ORFE TDRE TIE
30H
(R)
(W)
SIDR UART serial input data register
SODR UART serial output data register
31H
to
7BH
—
OE2
PEN
SBL
—
—
OE3
—
TIR1
TIR2
TIE1
TIE2
CH12
—
—
—
—
—
MC1
MC0
CR
SCS1 SCS0 RC2
SMDE
RIE
PSEL
UCKE UOE
RC1
RC0
TD8/
TP
RD8/
RP
SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0
SOD7 SOD6 SOD5 SOD4 SOD3 SOD2 SOD1 SOD0
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1 L31
L30
L21
L20
L11
L10
L01
L00
7DH
(W)
ILR2
Interrupt level settingregister 2
L71
L70
L61
L60
L51
L50
L41
L40
7EH
(W)
ILR3
Interrupt level setting register 3 LB1
LB0
LA1
LA0
L91
L90
L81
L80
7FH
Vacancy
Notes: • Do not use vacancies.
• — represents a vacant bit.
25
MB89630 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
*
AVCC
VSS – 0.3
VSS + 7.0
V
*
AVR
VSS – 0.3
VSS + 7.0
V
AVR must not exceed
AVCC + 0.3.
VI
VSS – 0.3
VCC + 0.3
V
Except P50 to P53
VI2
VSS – 0.3
VSS + 7.0
V
P50 to P53
VO
VSS – 0.3
VCC + 0.3
V
Except P50 to P53
VO2
VSS – 0.3
VSS + 7.0
V
P50 to P53
“L” level maximum output current
IOL
20
mA
“L” level average output current
IOLAV
4
mA
“L” level total maximum output current
∑IOL
100
mA
“L” level total average output current
∑IOLAV
40
mA
“H” level maximum output current
IOH
–20
mA
“H” level average output current
IOHAV
–4
mA
“H” level total maximum output current
∑IOH
–50
mA
“H” level total average output current
∑IOHAV
–20
mA
Power consumption
PD
500
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
Power supply voltage
A/D converter reference input voltage
Input voltage
Output voltage
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
Average value (operating
current × operating rate)
* : Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
Precautions:Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
26
MB89630 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Parameter
Min.
Max
2.2*
6.0*
Unit
Remarks
V
Normal operation
assurance range*
MB89635/637
VCC
2.7*
6.0*
V
Normal operation
assurance range*
MB89PV630/P637/
W637/T635/T637
AVCC
1.5
6.0
V
Retains the RAM state in
stop mode
A/D converter reference input voltage
AVR
3.0
AVCC
V
Operating temperature
TA
–40
+85
°C
Power supply voltage
* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics.”
6
Operating voltage (V)
5
Analog accuracy assured in the
AVCC = 3.5 V to 6.0 V range
Operation assurance range
4
3
2
1
1.0
2.0 3.0 4.0
5.0
6.0
7.0
8.0
9.0
10.0
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
4.0 2.0
0.8
Minimum execution time (instruction cycle) (µs)
0.4
Note: The shaded area is assured only for the MB89635/636/637.
Figure 1
Operating Voltage vs. Main Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
27
MB89630 Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Condition
Value
Unit
Remarks
Min.
Typ.
Max.
VIH1
P00 to P07, P10 to P17,
P22, P23, P31, P34,
P37, P41, P43,
P51 to P53
0.7 VCC
VCC + 0.3
V
P51 to P53
with pull-up
resistor
VIH2
P51 to P53
0.7 VCC
VSS + 6.0
V
Without pull-up
resistor
VIHS
RST, MOD0, MOD1,
P30, P32, P33, P35,
P36, P40, P42,P50,
P72 to P74
0.8 VCC
VCC + 0.3
V
P50 with
pull-up
resistor
VIHS2
P50, P70, P71
0.8 VCC
VSS + 6.0
V
Without pull-up
resistor
VIL
P00 to P07, P10 to P17,
P22, P23, P31, P34,
P37, P41, P43
VSS − 0.3
0.3 VCC
V
VILS
P30, P32, P33, P35,
P36, P40, P42,
P50 to P53,
P70 to P74,
RST,
MOD0, MOD1
VSS − 0.3
0.2 VCC
V
VD
P50 to P53
VSS − 0.3
VSS + 6.0
V
“H” level input
voltage
“L” level input
voltage
Open-drain
output pin
application
voltage
Pin
“H” level output
VOH
voltage
P00 to P07, P10 to P17,
P20 to P27, P30 to P37, IOH = –2.0 mA
P40 to P43
4.0
V
“L” level output
VOL
voltage
P00 to P07, P10 to P17,
P20 to P27 P30 to P37,
IOL = 4.0 mA
P40 to P43, P50 to P53,
P60 to P67, RST
0.4
V
Input leakage
current
(Hi-z output
leakage
current)
ILI
P00 to P07, P10 to P17,
P20 to P23, P30 to P37,
P40 to P43, P50 to P53, 0.0 V < VI < VCC
P70 to P74,
MOD0, MOD1
±5
µA
Without pull-up
resistor
Pull-up
resistance
RPULL
P00 to P07, P10 to P17,
P30 to P37, P40 to P43, VI = 0.0 V
P50 to P53, P72 to P74
25
50
100
kΩ
With pull-up
resistor
(Continued)
28
MB89630 Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Pin
Symbol
Condition
ICC1
FCH = 10 MHz
VCC = 5.0 V
tinst*2 = 0.4 µs
ICC2
FCH = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
Value
Unit
Remarks
Min.
Typ.
Max.
—
12
20
mA
—
1.0
2
mA 636/637/T637/
MB89635/T635/
ICCS2
MB89P637/
W637
—
1.5
2.5
mA
FCH = 10 MHz
VCC = 5.0 V
tinst*2 = 0.4 µs
—
3
7
mA
FCH = 10 MHz
VCC = 3.0 V
tinst*2 = 6.4 µs
—
0.5
1.5
mA
FCL = 32.768 kHz,
—
50
100
µA 636/637/T637/
Sleep mode
ICCS1
PV630
MB89635/T635/
Power supply
current*1
ICCL
VCC
VCC = 3.0 V
Subclock mode
PV630
—
500
700
µA
—
25
50
µA
—
3
15
µA
—
—
1
µA
MB89P637/
W637
FCL = 32.768 kHz,
ICCLS
VCC = 3.0 V
Subclock sleep
mode
FCL = 32.768 kHz,
ICCT
VCC = 3.0 V
• Watch mode
• Main clock stop
mode at dualclock system
TA = +25°C
ICCH
• Subclock stop
mode
• Main clock stop
mode at singleclock system
(Continued)
29
MB89630 Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Pin
Symbol
IA
Power supply
current*1
AVCC
IAH
Input capacitance CIN
Value
Condition
Other than AVCC,
AVSS, VCC, and VSS
Unit
Min.
Typ.
Max.
FCH = 10 MHz,
when A/D
conversion
is activated
—
6
—
mA
FCH = 10 MHz,
TA = +25°C,
when A/D
conversion
is stopped
—
—
1
µA
f = 1 MHz
—
10
pF
Remarks
*1: The power supply current is measured at the external clock.
In the case of the MB89PV630, the current consumed by the connected EPROM and ICE is not included.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
RST “L” pulse width
Symbol
Condition
tZLZH
—
Value
Min.
Max.
48 tHCYL
—
tZLZH
RST
0.2 VCC
30
0.2 VCC
Unit
ns
Remarks
MB89630 Series
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Remarks
Min.
Max.
—
50
ms
Power-on reset function only
1
—
ms
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
0.2 V
0.2 V
VCC
0.2 V
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling
time
Symbol
Pin
Condition
Value
Min.
Typ.
Max.
Unit
Remarks
FCH
X0, X1
1
—
10
MHz
FCL
X0A, X1A
—
32.768
—
kHz
tHCYL
X0, X1
100
—
1000
ns
tLCYL
X0A, X1A
—
30.5
—
µs
PWH
PWL
X0
20
—
—
ns
External clock
PWLH
PWLL
X0A
—
15.2
—
µs
External clock
tCR
tCF
X0
—
—
10
ns
External clock
—
31
MB89630 Series
X0 and X1 Timing and Conditions
tHCYL
PWH
PWL
tCR
tCF
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal
or
ceramic reasonator is used
X0
When an external clock is used
X1
X0
X1
Open
X0A and X1A Timing and Conditions
tLCYL
PWLH
PWLL
tCR
tCF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
Subclock Conditions
When a crystal
or
ceramic reasonator is used
X0A
X1A
When an external clock is used
X0A
X1A
Open
32
MB89630 Series
(4) Instruction Cycle
Symbol
Parameter
Instruction cycle
(minimum execution time)
Value (typical)
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH) tinst = 0.4 µs when operating at
FCH = 10 MHz
2/FCL
µs
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
tinst
Note: When operating at 10 MHz, the cycle varies with the set execution time.
(5) Clock Output Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Clock time
tCYC
CLK
CLK ↑ → CLK ↓
tCHCL
CLK
Condition
—
Value
Unit
Min.
Max.
1/2 tinst*
—
µs
1/4 tinst* – 70 ns
1/4 tinst*
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
33
MB89630 Series
(6) Bus Read Timing
(VCC = +5.0 V±10%, 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Valid address → RD ↓ time tAVRL
RD pulse width
tRLRH
Pin
Condition
Value
Unit
Max.
RD, A15 to 08,
AD7 to 0
1/4 tinst*– 64 ns
—
µs
RD
1/2 tinst*– 20 ns
—
µs
1/2 tinst*
200
µs
No wait
No wait
Valid address → data read
tAVDV
time
AD7 to 0,
A15 to 08
RD ↓ → data read time
tRLDV
RD, AD7 to 0
1/2 tinst*– 80 ns
120
µs
RD ↑ → data hold time
tRHDX
AD7 to 0, RD
0
—
µs
RD ↑ → ALE ↑ time
tRHLH
RD, ALE
1/4 tinst*– 40 ns
—
µs
RD ↑ → address loss time
tRHAX
RD, A15 to 08
1/4 tinst*– 40 ns
—
µs
RD ↓ → CLK ↑ time
tRLCH
1/4 tinst*– 40 ns
—
µs
CLK ↓ → RD ↑ time
tCLRH
0
—
ns
RD ↓ → BUFC ↓ time
tRLBL
RD, BUFC
–5
—
ns
BUFC ↑ → valid address
time
tBHAV
A15 to 08,
AD7 to 0,
BUFC
5
—
ns
—
RD, CLK
* : For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
0.8 V
tRHLH
ALE
0.8 V
2.4 V
0.7 VCC
0.7 VCC
2.4 V
0.8 V
0.3 VCC
0.3 VCC
0.8 V
AD
tRHDX
tAVDV
A
2.4 V
tRLCH
0.8 V
tAVRL
2.4V
tCLRH
2.4 V
0.8V
0.8 V
tRHAX
tRLDV
tRLRH
RD
2.4 V
0.8 V
tRLBL
tBHAV
2.4 V
BUFC
34
Remarks
Min.
0.8 V
MB89630 Series
(7) Bus Write Timing
(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Value
Min.
Max.
Unit Remarks
Valid address → ALE ↓ time tAVLL
AD7 to 0, ALE
A15 to 08
1/4 tinst*1 – 64 ns
—
µs
ALE ↓ time → address loss
time
AD7 to 0, ALE
A15 to 08
5
—
ns
tLLAX
Valid address → WR ↓ time tAVWL
WR, ALE
1/4 tinst*1 – 60 ns
—
µs
WR pulse width
tWLWH
WR
1/2 tinst*1 – 20 ns
—
µs
Write data → WR ↑ time
tDVWH
AD7 to 0, WR
1/2 tinst*1 – 60 ns
—
µs
WR ↑ → address loss time
tWHAX
WR, A15 to
08
1/4 tinst*1 – 40 ns
—
µs
WR ↑ → data hold time
tWHDX
AD7 to 0, WR
1/4 tinst*1 – 40 ns
—
µs
WR ↑ → ALE ↑ time
tWHLH
WR, ALE
1
1/4 tinst* – 40 ns
—
µs
WR ↓ → CLK ↑ time
tWLCH
1
1/4 tinst* – 40 ns
—
µs
CLK ↓ → WR ↑ time
tCLWH
0
—
ns
ALE pulse width
tLHLL
ALE
1/4 tinst*1 – 35 ns
—
µs
ALE ↓ → CLK ↑ time
tLLCH
ALE,CLK
1/4 tinst* – 30 ns
—
µs
—
WR, CLK
1
*1: For information on tinst, see “(4) Instruction Cycle.”
*2: This characteristics are also applicable to the bus read timing.
2.4 V
CLK
0.8 V
tLHLL
ALE
tWHLH
2.4 V
0.8 V
0.8 V
tAVLL
AD
tLLCH
tLLAX
2.4 V 2.4 V
2.4 V
0.8 V 0.8 V
0.8 V
2.4 V
0.8 V
tDVWH
A
2.4 V
tWHDX
2.4 V
tCLWH
tWLCH
0.8 V
0.8 V
tAVWL
tWHAX
tWLWH
WR
2.4 V
0.8V
35
MB89630 Series
(8) Ready Input Timing
(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
RDY valid → CLK ↑ time
tYVCH
CLK ↑ → RDY loss time
tCHYX
Pin
Condition
RDY, CLK
—
Value
60
—
ns
*
0
—
ns
*
2.4 V
2.4 V
ALE
AD
Address
Data
A
WR
tYVCH tCHYX
RDY
tYVCH
Note: The bus cycle is also extended in the read cycle in the same manner.
36
Remarks
Max.
* : This characteristics are also applicable to the read cycle.
CLK
Unit
Min.
tCHYX
MB89630 Series
(9) Serial I/O Timing
(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Value
Unit Remarks
Min.
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
Serial clock cycle time
tSCYC
SCK1, UCK1,
UCK2
SCK1 ↓ → SO1 time
UCK1 ↓ → UO1 time
UCK2 ↓ → UO2 time
tSLOV
SCK1, SO1
UCK1, UO1
UCK2, UO2
Valid SI1 → SCK1 ↑
Valid UI1 → UCK1 ↑
Valid UI2 → UCK2 ↑
tIVSH
SI1, SCK1
UI1, UCK1
UI2, UCK2
SCK1 ↑ → valid SI1 hold time
UCK1 ↑ → valid UI1 hold time tSHIX
UCK2 ↑ → valid UI2 hold time
SCK1, SI1
UCK1, UI1
UCK2, UI2
Serial clock “H” pulse width
tSHSL
SCK1, UCK1,
UCK2
1 tinst*
—
µs
Serial clock “L” pulse width
tSLSH
SCK1, UCK1,
UCK2
1 tinst*
—
µs
SCK1 ↓ → SO1 time
UCK1 ↓ → UO1 time
UCK2 ↓ → UO2 time
tSLOV
SCK1, SO1
UCK1, UO1
UCK2, UO2
0
200
ns
Valid SI1 → SCK1 ↑
Valid UI1 → UCK1 ↑
Valid UI2 → UCK2 ↑
tIVSH
SI1, SCK1
UI1, UCK1
UI2, UCK2
1/2 tinst*
—
µs
SCK1 ↓ → valid SI1 hold time
UCK1 ↓ → valid UI1 hold time tSHIX
UCK2 ↓ → valid UI2 hold time
SCK1, SI1
UCK1, UI1
UCK2, UI2
1/2 tinst*
—
µs
Internal
shift clock
mode
External
shift clock
mode
* : For information on tinst, see “(4) Instruction Cycle.”
37
MB89630 Series
Internal Shift Clock Mode
tSCYC
SCK1
UCK1
UCK2
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO1
UO1
UO2
0.8 V
tIVSH
SI1
UI1
UI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Shift Clock Mode
tSHSL
tSLSH
SCK1
UCK1
UCK2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
SO1
UO1
UO2
2.4 V
0.8 V
tIVSH
SI1
UI1
UI
38
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB89630 Series
(10) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
Peripheral input “H” pulse width 2
tILIH2
Peripheral input “L” pulse width 2
tIHIL2
Peripheral input “H” pulse width 3
tILIH3
Peripheral input “L” pulse width 3
tIHIL3
Value
Pin
PWC, INT0 to INT3,EC
ADST
ADST
Unit
Remarks
Min.
Max.
2 tinst*
—
µs
2 tinst*
—
µs
8 inst
2 t *
—
µs
A/D mode
28 tinst*
—
µs
A/D mode
28 tinst*
—
µs
Sense mode
8 inst
—
µs
Sense mode
2 t *
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
PWC,
EC,
INT0 to INT3
tILIH1
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tIHIL2
(tIHIL3)
tILIH2
(tILIH3)
ADST
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
39
MB89630 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 3.5 V to 6.0 V, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Value
Pin
Resolution
Linearity error
—
Differential linearity error
—
Total error
Zero transition voltage
VOT
Full-scale transition
voltage
VFST
AN0 to
AN7
A/D mode conversion time
Analog port input current
IAIN
Analog input voltage
Reference voltage
supply current
—
AN0 to
AN7
AVR
IR
Max.
—
—
10
bit
—
—
±2.0
LSB
—
—
±1.5
LSB
—
—
±3.0
LSB
Remarks
At AVCC = VCC
AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB mV
—
Reference voltage
Typ.
AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV
Interchannel disparity
—
Unit
Min.
—
—
4
LSB
—
13.2
—
µs
—
—
10
µA
0.0
—
AVR
V
0.0
—
AVCC
V
—
200
At 10 MHz
oscillation
µA AVR = 5.0 V
Precautions: • The smaller the | AVR–AVSS |, the greater the error would become relatively.
• The output impedance of the external circuit for the analog input must satisfy the following conditions:
Output impedance of the external circuit < Approx. 10 kΩ
If the output impedance of the external circuit is too high, an analog voltage sampling time might be
insufficient (sampling time = 6 µs at 10MHz oscillation.)
Analog Input Circuit Model
Analog input
C0
Converter
RON1
RON1:
RON2:
C0:
C1:
Approx.
Approx.
Approx.
Approx.
1.5 Ω
1.5 Ω
60 pF
4 pF
RON2
C1
Note: The values mentioned here should be used as a guideline.
40
MB89630 Series
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values caused by the zero transition error, full-scale
transition error, linearity error, quantization error, and noise
Total error
Theoretical I/O characteristics
3FF
3FF
VFST
3FE
3FE
3FD
1.5 LSB
Digital output
Digital output
3FD
004
003
Actual conversion
value
{1 LSB × N + 0.5 LSB}
004
VNT
003
VOT
002
Actual conversion
value
002
1 LSB
Theoretical value
001
001
0.5 LSB
AVR
AVSS
1 LSB =
VFST – VOT
1022
AVR
AVSS
Analog input
Analog input
(V)
Digital output N total error = VNT – {1 LSB × N + 0.5 LSB}
1 LSB
(Continued)
41
MB89630 Series
(Continued)
Zero transition error
Full-scale transition error
004
Theoretical value
Actual conversion
value
3FF
Actual conversion
value
Digital output
Digital output
003
002
3FE
VFST
(Actual
measurement)
3FD
Actual conversion
value
001
Actual conversion value
3FC
VOT (Actual measurement)
AVR
AVSS
Analog input
Analog input
Differential linearity error
Linearity error
3FF
Theoretical value
Actual conversion
value
3FE
N+1
{1 LSB × N + VOT}
Actual conversion
value
VNT
VFST
(Actual
measurement)
004
Digital output
Digital output
3FD
V(N + 1)T
N
N–1
003
VNT
Actual conversion value
Actual conversion value
002
Theoretical value
001
N–2
VOT (Actual measurement)
AVR
AVSS
Analog input
Digital output N linearity error =
42
VNT – {1 LSB × N + VOT}
1 LSB
AVR
AVSS
Analog input
Digital output N differential linearity error =
V(N + 1)T – VNT
1 LSB
–1
MB89630 Series
■ EXAMPLE CHARACTERISTICS
(2) “H” Level Output Voltage
(1) “L” Level Output Voltage
VOL vs. IOL
VOL (V)
VCC = 2.5 V
TA = +25°C
0.5
VCC = 3.0 V
0.4
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.3
0.2
0.1
0.0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
VIN vs. VCC
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
TA = +25°C
1
2
3
4
5
6
7
VCC (V)
VCC – VOH (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
–0.5
VCC – VOH vs. IOH
TA = +25°C
VCC = 2.5 V
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
–1.0
–1.5
–2.0
–2.5
–3.0
IOH (mA)
(4) “H” Level Input Voltage/“L” Level Input
Voltage (Hysteresis Input)
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
VIN vs. VCC
TA = +25°C
VIHS
VILS
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
43
MB89630 Series
(5) Power Supply Current (External Clock)
ICC1 vs. VCC, ICC2 vs. VCC
ICC (mA)
16
ICCS (mA)
5.0
Divide by 4 (ICC1)
FcH = 10 MHz
TA = +25°C
14
ICCS1 vs. VCC, I CCS2 vs. VCC
FCH = 10 MHz
TA = +25°C
4.5
4.0
12
Divide by 4 (ICCS2)
3.5
10
Divide by 8
8
3.0
2.5
Divide by 8
2.0
6
Divide by 16
4
Divide by 16
1.5
Divide by 64 (ICCS2)
1.0
Divide by 64 (ICC2)
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
2.0
6.5
VCC (V)
ICCL vs. VCC
ICCL (µA)
200
0.5
TA = +25°C
40
140
35
120
30
100
25
80
20
60
15
40
10
20
5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VCC (V)
3.5
4.0
4.5
5.0
0
2.0
5.5
6.0
6.5
VCC (V)
ICCLS vs. VCC
TA = +25°C
45
160
2.5
3.0
ICCLS (µA)
50
180
0
2.0
2.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VCC (V)
(Continued)
44
MB89630 Series
(Continued)
ICCT vs. VCC
ICCT (µA)
20
TA = +25°C
18
1.6
14
1.4
12
1.2
10
1.0
8
0.8
6
0.6
4
0.4
2
0.2
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
TA = +25°C
1.8
16
0
2.0
ICCH vs. VCC
ICCH (µA)
2.0
0
2.0
6.5
VCC (V)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VCC (V)
(6) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1000
TA = +25°C
100
10
1
2
3
4
5
6
VCC (V)
45
MB89630 Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1
Symbol
dir
off
ext
#vct
#d8
#d16
dir: b
rel
@
A
AH
AL
T
TH
TL
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
×
(×)
(( × ))
Instruction Symbols
Meaning
Direct address (8 bits)
Offset (8 bits)
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
The number of instructions
#:
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
46
MB89630 Series
Table 2
Mnemonic
Transfer Instructions (48 instructions)
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Note: During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
47
MB89630 Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
(Continued)
48
MB89630 Series
(Continued)
Mnemonic
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
~
#
Operation
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
49
L
50
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0
R0,#d8
R0,#d8
dir: 0 dir: 0,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1
R1,#d8
R1,#d8
dir: 1 dir: 1,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2
R2,#d8
R2,#d8
dir: 2 dir: 2,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3
R3,#d8
R3,#d8
dir: 3 dir: 3,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4
R4,#d8
R4,#d8
dir: 4 dir: 4,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5
R5,#d8
R5,#d8
dir: 5 dir: 5,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6
R6,#d8
R6,#d8
dir: 6 dir: 6,rel
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7
R7,#d8
R7,#d8
dir: 7 dir: 7,rel
9
A
B
C
D
E
F
A
SUBC
A
XCH
A, T
XOR
A
AND
A
OR
A
MOV
MOV
CLRB
BBC
INCW
DECW
MOVW
MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
DAS
R7
R6
R5
R4
R3
R2
R1
R0
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
R7
R6
R5
R4
R3
R2
R1
R0
rel
rel
rel
rel
CALLV
BLT
#7
rel
CALLV
BGE
#6
rel
CALLV
BZ
#5
CALLV
BNZ
#4
rel
CALLV
BN
#3
CALLV
BP
#2
CALLV
BC
#1
CALLV
BNC
#0
rel
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
dir: 4 dir: 4,rel
A,ext
ext,A
A,#d16
A,PC
ADDCW SUBCW XCHW
XORW
ANDW
ORW
MOVW
MOVW
CLRB
BBC
INCW
DECW
MOVW
MOVW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
ADDC
CLRB
BBC
INCW
DECW
MOVW
MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
8
A
A
SETC
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@EP
A,@EP
A,@EP
A,@EP
@EP,A
A,@EP
A,@EP
A,@EP @EP,#d8 @EP,#d8
dir: 7 dir: 7,rel
A,@EP
@EP,A EP,#d16
A,EP
CMPW
CMP
JMP
CALL
PUSHW POPW
MOV
MOVW
CLRC
addr16
addr16
IX
IX
ext,A
PS,A
7
F
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
dir: 6
dir: 6,rel A,@IX +d @IX +d,A
IX,#d16
A,IX
E
6
D
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW
MOVW
MOVW
XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir
dir,#d8
dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
C
5
B
CLRB
BBC
INCW
DECW
JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
MOV
CMP
ADDC
SUBC
A,#d8
A,#d8
A,#d8
A,#d8
A
A
DIVU
SETI
9
4
8
RORC
7
3
6
ROLC
A
5
PUSHW POPW
MOV
MOVW
CLRI
A
A
A,ext
A,PS
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
MB89630 Series
■ INSTRUCTION MAP
MB89630 Series
■ MASK OPTIONS
Part number
MB89635
MB89636
MB89637
MB89P637
MB89W637
MB89PV630
MB89T635
MB89T637
Specifying procedure
Specify when
ordering
masking
Set with EPROM
programmer
Setting not
possible
No.
1
Pull-up resistors
P00 to P07, P10 to P17,
P30 to P37, P40 to P43,
P50 to P53, P72 to P74
2
Power-on reset selection
With power-on reset
Without power-on reset
Selectable
Setting possible
Fixed to with power-on reset
3
Selection of the main clock
oscillation stabilization time
(at 10 MHz)
Approx. 218/FCH (Approx. 26.2 ms)
Approx. 217/FCH (Approx. 13.1 ms)
Approx. 214/FCH (Approx. 1.6 ms)
Approx. 24/FCH (Approx. 0 ms)
FCH : Main clock frequency
Selectable
Setting possible
Fixed to 218/FCH
(Approx. 26.2 ms)
4
Reset pin output
Reset output provided
No reset output
Selectable
Setting possible
Fixed to with reset output
Selectable by
Can be set per pin* Fixed to without pull-up resistor
pin
Single/dual-clock system
Single clock
Dual clock
5
Selectable
Setting possible
MB89PV630-101Single-clock
system
MB89T635-101 Single-clock
system
MB89T637-101 Single-clock
system
MB89PV630-102Dual-clock
systems
MB89T635-102 Dual-clock
systems
MB89T637-101 Dual-clock
systems
* : Pull-up resistors cannot be set for P50 to P53.
51
MB89630 Series
■ ORDERING INFORMATION
Part number
MB89635P-SH
MB89T635P-SH
MB89636P-SH
MB89637P-SH
MB89P637-SH
MB89T637P-SH
52
Package
64-pin Plastic SH-DIP
(DIP-64P-M01)
MB89635PF
MB89T635PF
MB89636PF
MB89637PF
MB89P637PF
MB89T637PF
64-pin Plastic QFP
(FPT-64P-M06)
MB89635PFM
MB89T635PFM
MB89636PFM
MB89637PFM
MB89T637PFM
64-pin Plastic QFP
(FPT-64P-M09)
MB89W637C-SH
64-pin Ceramic SH-DIP
(DIP-64C-A06)
MB89PV630C-SH
64-pin Ceramic MDIP
(MDP-64C-P02)
MB89PV630CF
64-pin Ceramic MQFP
(MQP-64C-P01)
Remarks
MB89630 Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
+0.22
58.00 –0.55
+.008
2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
5.65(.222)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.50
1.00 –0
+.020
.039 –0
0.51(.020)MIN
0.45±0.10
(.018±.004)
15°MAX
19.05(.750)
TYP
1.778±0.18
(.070±.007)
55.118(2.170)REF
1.778(.070)
MAX
C
1994 FUJITSU LIMITED D64001S-3C-4
64-pin Plastic QFP
(FPT-64P-M06)
Dimensions in mm (inches)
24.70±0.40(.972±.016)
3.35(.132)MAX
20.00±0.20(.787±.008)
51
0.05(.002)MIN
(STAND OFF)
33
52
32
14.00±0.20
(.551±.008)
18.70±0.40
(.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
64
20
"A"
LEAD No.
1
19
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
0.15±0.05(.006±.002)
0.20(.008)
M
Details of "A" part
0.25(.010)
Details of "B" part
"B"
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F64013S-3C-2
0.30(.012)
0.18(.007)MAX
0.63(.025)MAX
0 10°
1.20±0.20
(.047±.008)
Dimensions in mm (inches)
53
MB89630 Series
64-pin Plastic QFP
(FPT-64P-M09)
48
14.00±0.20(.551±.008)SQ
33
12.00±0.10(.472±.004)SQ
49
+0.20
1.50 –0.10
+.008
.059 –.004
32
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
LEAD No.
17
1
0.65(.0256)TYP
Details of "A" part
16
0.30±0.10
(.012±.004)
"A"
0.13(.005)
M
+0.05
0.127 –0.02
+.002
.005 –.001
0.10±0.10 (STAND OFF)
(.004±.004)
0.10(.004)
0
C
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
1994 FUJITSU LIMITED F64018S-1C-2
64-pin Ceramic SH-DIP
(DIP-64C-A06)
56.90±0.56
(2.240±.022)
8.89(.350) DIA
TYP
R1.27(.050)
REF
18.75±0.25
(.738±.010)
INDEX AREA
1.27±0.25
(.050±.010)
5.84(.230)MAX
0.25±0.05
(.010±.004)
3.40±0.36
(.134±.014)
1.45(.057)
MAX
C
54
1994 FUJITSU LIMITED D64006SC-1-2
1.778±0.180
(.070±.007)
0.90±0.10
(.0355±.0040)
+0.13
0.46 –0.08
+.005
.018 –.003
19.05±0.25
(.750±.010)
0°~9°
55.118(2.170)REF
Dimensions in mm (inches)
MB89630 Series
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
INDEX AREA
2.54±0.25
(.100±.010)
33.02(1.300)REF
0.25±0.05
(.010±.002)
1.27±0.25
(.050±.010)
10.16(.400)MAX
1.778±0.25
(.070±.010)
C
19.05±0.30
(.750±.012)
+0.13
0.46 –0.08
+.005
.018 –.003
55.12(2.170)REF
3.43±0.38
(.135±.015)
0.90±0.13
(.035±.005)
Dimensions in mm (inches)
1994 FUJITSU LIMITED M64002SC-1-4
64-pin Ceramic MQFP
(MQP-64C-P01)
INDEX AREA
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
+0.40
1.20 –0.20
+.016
.047 –.008
1.00±0.25
(.039±.010)
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.30(.012)TYP
7.62(.300)TYP
0.40±0.10
(.016±.004)
18.00(.709)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
1994 FUJITSU LIMITED M64004SC-1-3
10.82(.426)
0.15±0.05 MAX
(.006±.002)
Dimensions in mm (inches)
55
MB89630 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
F9602
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.