OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com 0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift OPERATIONAL AMPLIFIERS Check for Samples: OPA2180, OPA4180 FEATURES APPLICATIONS • • • • • • • • • • • • • • 1 2 • • • Bridge Amplifiers Strain Gauges Test Equipment Transducer Applications Temperature Measurement Electronic Scales Medical Instrumentation Resister Thermal Detectors Precision Active Filters DESCRIPTION The OPA2180 and OPA4180 operational amplifiers use zero-drift techniques to simultaneously provide low offset voltage (75 μV), and near zero-drift over time and temperature. These miniature, high-precision, low quiescent current amplifiers offer high input impedance and rail-to-rail output swing within 18 mV of the rails. The input common-mode range includes the negative rail. Either single or dual supplies can be used in the range of +4.0 V to +36 V (±2 V to ±18 V). 50 nV/div • • • Low Offset Voltage: 75 μV (max) Zero-Drift: 0.1 μV/°C Low Noise: 10 nV/√Hz Very Low 1/f Noise Excellent DC Precision: – PSRR: 126 dB – CMRR: 114 dB – Open-Loop Gain (AOL): 120 dB Quiescent Current: 525 μA (max) Wide Supply Range: ±2 V to ±18 V Rail-to-Rail Output: Input Includes Negative Rail Low Bias Current: 250 pA (typ) RFI Filtered Inputs MicroSIZE Packages The dual version is offered in MSOP-8 and SO-8 packages. The quad is offered in SO-14 and TSSOP-14 packages. All versions are specified for operation from –40°C to +105°C. Peak-to-Peak Noise = 250 nV Time (1 s/div) Zero-Drift Amplifier Portfolio VERSION PRODUCT OFFSET VOLTAGE (µV) OFFSET VOLTAGE DRIFT (µV/°C) Single (1) OPA188 (4 V to 36 V) 25 0.085 2 OPA333 (5 V) 10 0.05 0.35 Single Dual Quad (1) Quad (1) BANDWIDTH (MHz) OPA378 (5 V) 50 0.25 0.9 OPA735 (12 V) 5 0.05 1.6 OPA2188 (4 V to 36 V) 25 0.085 2 OPA2180 (4 V to 36 V) 75 0.35 2 OPA2333 (5 V) 10 0.05 0.35 OPA2378 (5 V) 50 0.25 0.9 OPA2735 (12 V) 5 0.05 1.6 OPA4188 (4 V to 36 V) 25 0.085 2 OPA4180 (4 V to 36 V) 75 0.35 2 OPA4330 (5 V) 50 0.25 0.35 Shaded rows denote future product releases. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE INFORMATION (1) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING OPA2180 SO-8 D –40°C to +105°C 2180 OPA2180 (2) MSOP-8 DGK –40°C to +105°C TBD SO-14 D –40°C to +105°C OPA4180 PRODUCT ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DUAL OPA2180ID Rails, 100 OPA2180IDR Tape and Reel, 2500 OPA2180IDGKT Tape and Reel, 250 OPA2180IDGKR Tape and Reel, 2500 OPA4180ID Rails, 90 OPA4180IDR Tape and Reel, 2000 QUAD OPA4180 (2) TSSOP-14 (1) (2) PW –40°C to +105°C OPA4180 OPA4180IPW Rails, 90 OPA4180IPWR Tape and Reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Shaded rows denote future product releases. ABSOLUTE MAXIMUM RATINGS (1) Supply voltage Signal input terminals OPA2180, OPA4180 UNIT ±20, 40 (single supply) V Voltage (V–) – 0.5 to (V+) + 0.5 V Current ±10 mA Output short-circuit (2) Continuous Operating temperature –55 to +125 °C Storage temperature –65 to +150 °C Junction temperature +150 °C 1.5 kV 1 kV ESD ratings (1) (2) 2 Human body model (HBM) Charged device model (CDM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied. Short-circuit to ground, one amplifier per package. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±2 V to ±18 V (VS = +4 V to +36 V) At TA = +25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted. OPA2180, OPA4180 PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage dVOS/dT Input offset voltage drift PSRR Power-supply rejection ratio μV 15 75 TA = –40°C to +105°C 0.1 0.35 μV/°C VS = 4 V to 36 V, VCM = VS/2 0.1 0.5 μV/V 0.5 μV/V TA = –40°C to +105°C, VS = 4 V to 36 V, VCM = VS/2 See note (1) Long-term stability Channel separation, dc μV μV/V 1 INPUT BIAS CURRENT IB IOS ±0.25 VCM = VS/2 Input bias current TA = –40°C to +105°C ±0.5 Input offset current TA = –40°C to +105°C ±1 nA ±5 nA ±2 nA ±2.5 nA NOISE Input voltage noise f = 0.1 Hz to 10 Hz 0.25 μVPP en Input voltage noise density f = 1 kHz 10 nV/Hz in Input current noise density f = 1 kHz 10 fA/Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio (V+) – 1.5 V– V (V–) < VCM < (V+) – 1.5 V 104 114 dB TA = –40°C to +105°C, (V–) + 0.5 V < VCM < (V+) – 1.5 V 100 104 dB INPUT IMPEDANCE Differential 100/6 MΩ/pF Common-mode 6/9.5 1012 Ω/pF OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ 110 120 dB TA = –40°C to +105°C, (V–) + 500 mV < VO < (V+) – 500 mV, RL = 10 kΩ 104 114 dB FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate Settling time THD+N (1) 2 MHz G = +1 0.8 V/μs 0.1% VS = ±18 V, G = 1, 10-V step 22 μs 0.01% VS = ±18 V, G = 1, 10-V step 30 μs 1 μs 0.0001 % Overload recovery time VIN × G = VS Total harmonic distortion + noise f = 1 kHz, G = 1, VOUT = 1 VRMS 1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits, or approximately 4 μV. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 3 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±2 V to ±18 V (VS = +4 V to +36 V) (continued) At TA = +25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted. OPA2180, OPA4180 PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT No load Voltage output swing from rail 8 18 mV RL = 10 kΩ 250 300 mV TA = –40°C to +105°C, RL = 10 kΩ 325 360 mV ±18 ISC Short-circuit current RO Open-loop output resistance CLOAD Capacitive load drive f = 2 MHz, IO = 0 mA mA 120 Ω 1 nF POWER SUPPLY ±2 (or 4) VS Operating voltage range IQ Quiescent current (per amplifier) ±18 (or 36) V 525 μA 600 μA 450 TA = –40°C to +105°C, IO = 0 mA TEMPERATURE Specified range –40 +105 °C Operating range –40 +125 °C Storage range –65 +150 °C THERMAL INFORMATION: OPA2180 OPA2180 THERMAL METRIC (1) D (SO) DGK (MSOP) 8 PINS 8 PINS θJA Junction-to-ambient thermal resistance 111.0 159.3 θJCtop Junction-to-case (top) thermal resistance 54.9 37.4 θJB Junction-to-board thermal resistance 51.7 48.5 ψJT Junction-to-top characterization parameter 9.3 1.2 ψJB Junction-to-board characterization parameter 51.1 77.1 θJCbot Junction-to-case (bottom) thermal resistance n/a n/a (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. THERMAL INFORMATION: OPA4180 OPA4180 THERMAL METRIC (1) D (SO) PW (TSSOP) 14 PINS 14 PINS θJA Junction-to-ambient thermal resistance TBD TBD θJCtop Junction-to-case (top) thermal resistance TBD TBD θJB Junction-to-board thermal resistance TBD TBD ψJT Junction-to-top characterization parameter TBD TBD ψJB Junction-to-board characterization parameter TBD TBD θJCbot Junction-to-case (bottom) thermal resistance TBD TBD (1) 4 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com PIN CONFIGURATIONS OPA2180 D, DGK PACKAGES (SO-8, MSOP-8) (TOP VIEW) OUT A 1 -IN A 2 +IN A 3 V- 4 A B 8 V+ 7 OUT B 6 -IN B 5 +IN B OPA4180 D, PW PACKAGES (SO-14, TSSOP-14) (TOP VIEW) 14 OUT D OUT A 1 -IN A 2 +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 -IN B 6 OUT B 7 A D 13 -IN D 10 +IN C B C 9 -IN C 8 OUT C Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 5 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Table 1. Characteristic Performance Measurements DESCRIPTION FIGURE IB and IOS vs Common-Mode Voltage Figure 1 Input Bias Current vs Temperature Figure 2 Output Voltage Swing vs Output Current (Maximum Supply) Figure 3 CMRR vs Temperature Figure 4 0.1-Hz to 10-Hz Noise Figure 5 Input Voltage Noise Spectral Density vs Frequency Figure 6 Open-Loop Gain and Phase vs Frequency Figure 7 Open-Loop Gain vs Temperature Figure 8 Open-Loop Output Impedance vs Frequency Figure 9 Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 10, Figure 11 No Phase Reversal Figure 12 Positive Overload Recovery Figure 13 Negative Overload Recovery Figure 14 Small-Signal Step Response (100 mV) Figure 15, Figure 16 Large-Signal Step Response Figure 17, Figure 18 Large-Signal Settling Time (10-V Positive Step) Figure 19 Large-Signal Settling Time (10-V Negative Step) Figure 20 Short-Circuit Current vs Temperature Figure 21 Maximum Output Voltage vs Frequency Figure 22 Channel Separation vs Frequency Figure 23 EMIRR IN+ vs Frequency Figure 24 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. IB AND IOS vs COMMON-MODE VOLTAGE INPUT BIAS CURRENT vs TEMPERATURE 4000 500 IB+ -IB 300 IOS IB- 3000 Input Bias Current (pA) IB and IOS (pA) +IB 400 200 100 0 -100 IOS 2000 1000 0 -1000 -200 -300 -2000 -20 -15 -10 0 -5 10 5 15 20 -55 -35 5 -15 VCM (V) Figure 1. 45 65 85 105 125 Figure 2. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (Maximum Supply) 20 19 18 17 16 15 14 -14 -15 -16 -17 -18 -19 -20 CMRR vs TEMPERATURE Common-Mode Rejection Ratio (mV/V) Output Voltage (V) 25 Temperature (°C) -40°C +85°C +125°C 40 (V-) < VCM < (V+) - 1.5 V 35 (V-) + 0.5 V < VCM < (V+) - 1.5 V 30 VSUPPLY = ±2 V 25 20 15 10 5 0 0 2 4 6 8 10 12 14 18 16 20 22 24 -55 -35 -15 Output Current (mA) 5 25 45 65 85 105 125 Temperature (°C) Figure 3. Figure 4. 0.1-Hz TO 10-Hz NOISE INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 50 nV/div Voltage Noise Density (nV/ÖHz) 100 10 Peak-to-Peak Noise = 250 nV Time (1 s/div) 1 0.1 1 10 100 1k 10k 100k Frequency (Hz) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 7 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. OPEN-LOOP GAIN AND PHASE vs FREQUENCY Gain Phase 120 VSUPPLY = 36 V, RL = 10 kW 2.5 Phase (°) 90 60 40 AOL (mV/V) 2 80 1.5 1 45 20 0 −20 VSUPPLY = 4 V, RL = 10 kW 135 100 Gain (dB) OPEN-LOOP GAIN vs TEMPERATURE 3 180 140 0.5 10 100 1k 10k 100k Frequency (Hz) 1M 10M 0 100M 0 -55 G007 -35 5 -15 25 45 65 85 105 125 Temperature (°C) Figure 7. Figure 8. OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) 10k 40 RL = 10 kW 35 ROUT = 0 W 30 Overshoot (%) ZO (W) 1k 100 10 ROUT = 25 W 25 ROUT = 50 W 20 15 G = +1 +18 V ROUT 10 Device 1 -18 V 5 RL CL 0 1m 1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 700 800 900 1000 Frequency (Hz) Capacitive Load (pF) Figure 9. Figure 10. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) NO PHASE REVERSAL 40 ROUT = 0 W 35 Device ROUT = 50 W 30 25 -18 V 37 VPP Sine Wave (±18.5 V) 5 V/div Overshoot (%) +18 V ROUT = 25 W 20 15 RI = 10 kW 10 RF = 10 kW G = -1 +18 V ROUT Device 5 CL RL = 10 kW VIN VOUT -18 V 0 0 100 200 300 400 500 600 700 800 900 1000 Time (100 ms/div) Capacitive Load (pF) Figure 11. 8 Figure 12. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. POSITIVE OVERLOAD RECOVERY NEGATIVE OVERLOAD RECOVERY VIN VOUT 20 kW 20 kW 5 V/div Device 5 V/div +18 V 2 kW VOUT VIN -18 V +18 V 2 kW VOUT Device VIN -18 V G = -10 G = -10 VOUT VIN Time (5 ms/div) Time (5 ms/div) Figure 13. Figure 14. SMALL-SIGNAL STEP RESPONSE (100 mV) SMALL-SIGNAL STEP RESPONSE (100 mV) +18 V RL = 10 kW CL = 10 pF 20 mV/div 20 mV/div RL = 10 kW CL = 10 pF G = +1 RI = 2 kW RF = 2 kW +18 V Device Device -18 V RL CL CL -18 V G = -1 Time (20 ms/div) Time (1 ms/div) Figure 15. Figure 16. LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE G = +1 RL = 10 kW CL = 10 pF 5 V/div 5 V/div G = -1 RL = 10 kW CL = 10 pF Time (50 ms/div) Time (50 ms/div) Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 9 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. LARGE-SIGNAL SETTLING TIME (10-V Positive Step) LARGE-SIGNAL SETTLING TIME (10-V Negative Step) 10 6 4 12-Bit Settling 2 0 -2 (±1/2 LSB = ±0.024%) -4 -6 -8 6 4 12-Bit Settling 2 0 -2 (±1/2 LSB = ±0.024%) -4 -6 -8 -10 -10 0 10 20 30 40 50 60 0 10 Figure 19. Figure 20. 40 50 60 MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 30 15 20 12.5 Output Voltage (VPP) VS = ±15 V ISC, Source 0 ISC, Sink -10 -20 10 Maximum output voltage without slew-rate induced distortion. 7.5 VS = ±5 V 5 2.5 -30 VS = ±2.25 V 0 -55 -35 -15 5 25 45 65 85 105 125 1k 10k 100k 1M 10M Frequency (Hz) Temperature (°C) Figure 21. Figure 22. CHANNEL SEPARATION vs FREQUENCY EMIRR IN+ vs FREQUENCY 160 -60 Channel A to B Channel B to A -70 140 -80 120 EMIRR IN+ (dB) Channel Separation (dB) 30 Time (ms) 10 -90 -100 -110 -120 100 80 60 40 -130 20 -140 -150 1 10 20 Time (ms) SHORT-CIRCUIT CURRENT vs TEMPERATURE ISC (mA) G = -1 8 D From Final Value (mV) D From Final Value (mV) 10 G = -1 8 10 100 1k 10k 100k 1M 10M 100M 0 10M 100M Frequency (Hz) Frequency (Hz) Figure 23. Figure 24. Submit Documentation Feedback 1G 10G Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com APPLICATION INFORMATION The OPAx180 family of operational amplifiers combine precision offset and drift with excellent overall performance, making them ideal for many precision applications. The precision offset drift of only 0.085 µV/°C provides stability over the entire temperature range. In addition, the device offers excellent overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. OPERATING CHARACTERISTICS The OPAx180 family of amplifiers is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the specifications apply from –40°C to +105°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. EMI REJECTION The OPAx180 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI interference from sources such as wireless communications and densely populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx180 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 25 shows the results of this testing on the OPAx180. Detailed information can also be found in the Application Report EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from the TI website. 160 140 EMIRR IN+ (dB) 120 100 80 60 40 20 0 10M 100M 1G 10G Frequency (Hz) Figure 25. OPAx180 EMIRR Testing Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 11 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com GENERAL LAYOUT GUIDELINES For best operational performance of the device, good printed circuit board (PCB) layout practices are recommended. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply applications. PHASE-REVERSAL PROTECTION The OPAx180 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPAx180 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 26. +18 V Device 5 V/div -18 V 37 VPP Sine Wave (±18.5 V) VIN VOUT Time (100 ms/div) Figure 26. No Phase Reversal CAPACITIVE LOAD AND STABILITY The dynamic characteristics of the OPAx180 have been optimized for a range of common operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 27 and Figure 28 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, refer to the Applications Report, Feedback Plots Define Op Amp AC Performance (SBOA015), available for download from the TI website, for details of analysis techniques and application circuits. 40 40 RL = 10 kW ROUT = 0 W 35 35 ROUT = 0 W ROUT = 25 W 25 ROUT = 50 W 20 15 G = +1 +18 V ROUT 10 ROUT = 50 W -18 V 25 20 15 RI = 10 kW 10 Device 5 ROUT = 25 W 30 Overshoot (%) Overshoot (%) 30 RL G = -1 +18 V ROUT CL Device 5 CL RL = 10 kW -18 V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 27. Small-Signal Overshoot versus Capacitive Load (100-mV Output Step) 12 RF = 10 kW Figure 28. Small-Signal Overshoot versus Capacitive Load (100-mV Output Step) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL OVERSTRESS Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Figure 29 shows how a series input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications. V+ IOVERLOAD 10 mA max Device VOUT VIN 5 kW Figure 29. Input Current Protection An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. When the operational amplifier connects into a circuit, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through ESD cells and rarely involves the absorption device. If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal operation. However, its zener voltage should be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 13 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com APPLICATION EXAMPLES The application examples of Figure 30 and Figure 31 highlight only a few of the circuits where the OPAx180 family of devices can be used. 15 V U2 ½ OPA2180 VOUTP 3.3 V VDIFF/2 -15 V R5 1 kW Ref 1 Ref 2 RG 500 W + VCM 10 R7 1 kW U1 INA159 VOUT Sense -15 V -VDIFF/2 U5 ½ OPA2180 VOUTN 15 V Figure 30. Discrete INA + Attenuation for ADC with 3.3-V Supply +15 V (5 V) Out In REF5050 1 mF 1 mF R2 49.1 kW R3 60.4 kW R1 4.99 kW OPA2180 VOUT 0°C = 0 V 200°C = 5 V R5 (1) 105.8 kW RTD Pt100 R4 1 kW (1) R5 provides positive-varying excitation to linearize output. Figure 31. RTD Amplifier with Linearization 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 OPA2180 OPA4180 SBOS584B – NOVEMBER 2011 – REVISED DECEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (November 2011) to Revision B Page • Changed footnote 1 of Electrical Characteristics table ......................................................................................................... 3 • Updated Figure 7 .................................................................................................................................................................. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): OPA2180 OPA4180 15 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty 75 Green (RoHS & no Sb/Br) OPA2180ID ACTIVE SOIC D 8 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR OPA2180IDGK PREVIEW VSSOP DGK 8 80 TBD Call TI Call TI OPA2180IDGKR PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI OPA2180IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4180ID PREVIEW SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4180IDR PREVIEW SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA4180IPW PREVIEW TSSOP PW 14 90 Green (RoHS & no Sb/Br) Call TI Level-2-260C-1 YEAR OPA4180IPWR PREVIEW TSSOP PW 14 2000 Green (RoHS & no Sb/Br) Call TI Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA2180IDR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2180IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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