DATASHEET HIP6006 FN4306 Rev.3.00 April 1, 2005 Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller The HIP6006 provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N Channel MOSFETs in a synchronous-rectified buck topology. The HIP6006 integrates all of the control, output adjustment, monitoring and protection functions into a single package. The output voltage of the converter can be precisely regulated to as low as 1.27V, with a maximum tolerance of 1% over temperature and line voltage variations. The HIP6006 provides simple, single feedback loop, voltagemode control with fast transient response. It includes a 200kHz free-running triangle-wave oscillator that is adjustable from below 50kHz to over 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The HIP6006 protects against over-current conditions by inhibiting PWM operation. The HIP6006 monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. Features • Drives Two N-Channel MOSFETs • Operates From +5V or +12V Input • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio • Excellent Output Voltage Regulation - 1.27V Internal Reference - 1% Over Line Voltage and Temperature • Over-Current Fault Monitor - Does Not Require Extra Current Sensing Element - Uses MOSFETs rDS(ON) • Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to Over 1MHz • 14 Pin, SOIC and TSSOP Package • Pb-Free Available (RoHS Compliant) Pinout Applications HIP6006 (SOIC, TSSOP) TOP VIEW • Power Supply for Pentium®, Pentium Pro, PowerPC™ and Alpha™ Microprocessors RT 1 14 VCC • High-Power 5V to 3.xV DC-DC Regulators OCSET 2 13 PVCC • Low-Voltage Distributed Power Supplies SS 3 12 LGATE COMP 4 11 PGND FB 5 10 BOOT EN 6 9 UGATE GND 7 8 PHASE Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # HIP6006CB 0 to 70 14 Ld SOIC M14.15 HIP6006CB-T 0 to 70 14 Ld SOIC) (T&R) M14.15 HIP6006CBZ (Note) 0 to 70 14 Ld SOIC (Pb-free) M14.15 HIP6006CBZ-T (Note) 0 to 70 14 Ld SOIC) (T&R) (Pb-free) M14.15 HIP6006CV 0 to 70 14 Ld TSSOP M14.173 HIP6006CV-T 0 to 70 14 Ld TSSOP (T&R) M14.173 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN4306 Rev.3.00 April 1, 2005 Page 1 of 12 HIP6006 Typical Application 12V +5V OR +12V VCC SS OCSET MONITOR AND PROTECTION EN BOOT RT OSC UGATE PHASE HIP6006 REF + FB - - +VO +12V PVCC LGATE + PGND GND COMP Block Diagram VCC POWER-ON RESET (POR) EN 10A + - OCSET OVERCURRENT SOFTSTART SS BOOT 4V 200A UGATE PHASE REFERENCE FB PWM COMPARATOR 1.27 VREF + - + - ERROR AMP INHIBIT PWM GATE CONTROL LOGIC PVCC LGATE PGND COMP GND RT FN4306 Rev.3.00 April 1, 2005 OSCILLATOR Page 2 of 12 HIP6006 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . +15.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead tips only) Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS EN = VCC; UGATE and LGATE Open - 5 - mA EN = 0V - 50 100 A Rising VCC Threshold VOCSET = 4.5VDC - - 10.4 V Falling VCC Threshold VOCSET = 4.5VDC 8.2 - - V Enable - Input threshold Voltage VOCSET = 4.5VDC 0.8 - 2.0 V - 1.27 - V VCC SUPPLY CURRENT Nominal Supply ICC Shutdown Supply POWER-ON RESET Rising VOCSET Threshold OSCILLATOR Free Running Frequency RT = OPEN, VCC = 12 185 200 215 kHz Total Variation 6k < RT to GND < 200k -15 - +15 % - 1.9 - VP-P 1.258 1.270 1.282 V - 88 - dB - 15 - MHz - 6 - V/s 350 500 - mA - 5.5 10 300 450 - mA - 3.5 6.5 170 200 230 A - 10 - A Ramp Amplitude VOSC RT = OPEN REFERENCE Reference Voltage ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate GBW SR COMP = 10pF GATE DRIVERS Upper Gate Source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V Upper Gate Sink RUGATE ILGATE = 0.3A Lower Gate Source ILGATE VCC = 12V, VLGATE = 6V Lower Gate Sink RLGATE ILGATE = 0.3A IOCSET VOCSET = 4.5VDC PROTECTION OCSET Current Source Soft Start Current FN4306 Rev.3.00 April 1, 2005 ISS Page 3 of 12 HIP6006 Typical Performance Curves 80 70 RT PULLUP TO +12V 60 IVCC (mA) RESISTANCE (k) 1000 100 RT PULLDOWN TO VSS CGATE = 3300pF 50 40 CGATE = 1000pF 30 20 10 CGATE = 10pF 10 10 100 SWITCHING FREQUENCY (kHz) 1000 FIGURE 1. RT RESISTANCE vs FREQUENCY Functional Pin Description 0 100 200 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz) 900 1000 FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY SS (Pin 3) RT 1 14 VCC OCSET 2 13 PVCC Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A current source, sets the soft-start interval of the converter. SS 3 12 LGATE COMP (Pin 4) and FB (Pin 5) COMP 4 11 PGND FB 5 10 BOOT EN 6 9 UGATE GND 7 8 PHASE COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. RT (Pin 1) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: (RT to GND) Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation.: 7 4 10 Fs 200kHz – --------------------R T k (RT to 12V) OCSET (Pin 2) Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200A current source (IOCS), and the upper MOSFET on-resistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation: I OCS R OCSET I PEAK = -------------------------------------------r DS ON An over-current trip cycles the soft-start function. FN4306 Rev.3.00 April 1, 2005 This pin is the open-collector enable pin. Pull this pin below 1V to disable the converter. In shutdown, the soft start pin is discharged and the UGATE and LGATE pins are held low. GND (Pin 7) 6 5 10 Fs 200kHz + --------------------R T k EN (Pin 6) Signal ground for the IC. All voltage levels are measured with respect to this pin. PHASE (Pin 8) Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. UGATE (Pin 9) Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. BOOT (Pin 10) This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. PGND (Pin 11) This is the power ground connection. Tie the lower MOSFET source to this pin. Page 4 of 12 HIP6006 LGATE (Pin 12) Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. PVCC (Pin 13) SOFT-START (1V/DIV) Provide a bias supply for the lower gate drive to this pin. VCC (Pin 14) Provide a 12V bias supply for the chip to this pin. The HIP6006 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages and the enable (EN) pin. The POR monitors the bias voltage at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN Less a fixed voltage drop (see over-current protection). With the EN pin held to VCC, the POR function initiates soft start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation. The Power-On Reset (POR) function inhibits operation with the chip disabled (EN pin low). With both input supplies above their POR thresholds, transitioning the EN pin high initiates a soft start interval. Soft Start The POR function initiates the soft start sequence. An internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 3 shows the soft start interval with CSS = 0.1F. Initially the clamp on the error amplifier (COMP pin) controls the converter’s output voltage. At t1 in Figure 3, the SS voltage reaches the valley of the oscillator’s triangle wave. The oscillator’s triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 3. At t3 the SS voltage exceeds the reference voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. FN4306 Rev.3.00 April 1, 2005 OUTPUT VOLTAGE (1V/DIV) 0V 0V t1 t2 t3 TIME (5ms/DIV) FIGURE 3. SOFT-START INTERVAL SOFT-START Initialization OUTPUT INDUCTOR Functional Description 4V 2V 0V 15A 10A 5A 0A TIME (20ms/DIV) FIGURE 4. OVER-CURRENT OPERATION Over-Current Protection The over-current function protects the converter from a shorted output by using the upper MOSFETs on-resistance, rDS(ON) to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200A (typical) current sink develops a voltage across ROCSET that is reference to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET, the over-current function initiates a soft-start sequence. The soft-start function discharges CSS with a 10A current sink and inhibits PWM operation. The soft-start function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 4 shows this Page 5 of 12 HIP6006 operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 4 is 2.5W. The over-current function will trip at a peak inductor current (IPEAK) determined by: I OCSET R OCSET I PEAK = --------------------------------------------------r DS ON where IOCSET is the internal OCSET current source (200A typical). The OC trip point varies mainly due to the MOSFETs rDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine I PEAK for I PEAK I OUT MAX + I 2 where I is the output inductor ripple current. Figure 5 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 6 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the HIP6006 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the HIP6006 must be sized to handle up to 1A peak current. Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, Css close to the SS pin because the internal current source is only 10A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. , +VIN BOOT CBOOT For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. Application Guidelines D1 HIP6006 Q1 LO VOUT PHASE SS +12V CO Q2 LOAD HIP6006 VCC CVCC CSS GND Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. VIN HIP6006 Q1 LO VOUT PHASE LGATE Q2 D2 CIN CO PGND Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (Vout) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of Vout/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peakto-peak oscillator voltage VOSC. Modulator Break Frequency Equations RETURN FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS FN4306 Rev.3.00 April 1, 2005 LOAD UGATE FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES 1 F LC = --------------------------------------2 L O C O 1 F ESR = --------------------------------------------2 ESR C O The compensation network consists of the error amplifier (internal to the HIP6006) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a Page 6 of 12 HIP6006 7. Estimate Phase Margin - Repeat if Necessary VIN OSC DRIVER PWM COMPARATOR LO - DRIVER + VOSC VOUT PHASE CO ESR (PARASITIC) ZFB VE/A - ZIN + REFERENCE ERROR AMP Figure 8 shows an asymptotic plot of the DC-DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak do to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. 100 FZ1 FZ2 DETAILED COMPENSATION COMPONENTS FP1 FP2 80 ZFB C1 VOUT ZIN C3 R2 R3 R1 COMP 40 20 20LOG (R2/R1) 20LOG (VIN/VOSC) 0 FB + HIP6006 OPEN LOOP ERROR AMP GAIN 60 GAIN (dB) C2 -40 REF -60 COMPENSATION GAIN MODULATOR GAIN -20 CLOSED LOOP GAIN FLC 10 100 1K FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 7. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180o The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use these guidelines for locating the poles and zeros of the compensation network: Compensation Break Frequency Equations 1 F Z1 = ---------------------------------2 R 2 C1 1 F P1 = ------------------------------------------------------C1 C2 2 R2 ---------------------- C1 + C2 1 F Z2 = -----------------------------------------------------2 R1 + R3 C3 1 F P2 = ---------------------------------2 R3 C3 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain FN4306 Rev.3.00 April 1, 2005 FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with 20dB/decade slope and a phase margin greater than 45o. Include worst case component variations when determining phase margin. Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be Page 7 of 12 HIP6006 careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0F ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT I = -------------------------------- ---------------Fs x L V IN VOUT= I x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6006 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O I TRAN t RISE = -------------------------------V IN – V OUT FN4306 Rev.3.00 April 1, 2005 L O I TRAN t FALL = ------------------------------V OUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. MOSFET Selection/Considerations The HIP6006 requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the lower MOSFETs body diode. The gate-charge losses are dissipated by the HIP6006 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, Page 8 of 12 HIP6006 PUPPER = IO2 x rDS(ON) x D + 1 Io x VIN x tSW x Fs 2 PLOWER = IO2 x rDS(ON) x (1 - D) Where: D is the duty cycle = VO / VIN, tSW is the switching interval, and Fs is the switching frequency. VCC less the input supply. For +5V main power and +12 VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logiclevel MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to PVCC. +12V +5V OR LESS tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. VCC HIP6006 BOOT UGATE Figure 9 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC . The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. A logic-level MOSFET can only be used for Q1 if the MOSFETs absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC . For Q2, a logic-level MOSFET can be used if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to PVCC. +12V DBOOT + VCC HIP6006 VD NOTE: VG-S VCC - 5V PHASE PVCC Standard-gate MOSFETs are normally recommended for use with the HIP6006. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFETs absolute gate-to-source voltage rating determine whether logic-level MOSFETs are appropriate. Q1 + +5V OR +12V LGATE PGND Q2 D2 NOTE: VG-S PVCC GND FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION Schottky Selection Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. +5V OR +12V - BOOT CBOOT UGATE Q1 PHASE NOTE: VG-S VCC - VD +5V PVCC OR +12V + LGATE PGND Q2 D2 NOTE: VG-S PVCC GND FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION Figure 10 shows the upper gate drive supplied by a direct connection to VCC . This option should only be used in converter systems where the main input voltage is +5 VDC or less. The peak upper gate-to-source voltage is approximately FN4306 Rev.3.00 April 1, 2005 Page 9 of 12 HIP6006 HIP6006 DC-DC Converter Application Circuit and circuit board description, can be found in application note AN9722. See Intersil’s home page on the web: www.intersil.com. The figure below shows an application circuit of a DC-DC Converter for a microprocessor application. Detailed information on the circuit, including a complete Bill-of-Materials 12VCC VIN C17-18 2x 1F 1206 C1-3 3x 680F RTN C12 1F 1206 R7 10k C19 VCC 6 ENABLE 2 OCSET MONITOR AND PROTECTION SS 3 3.01k PHASE TP2 Q1 U1 HIP6006 REF 5 C14 33pF C15 R5 0.01F 15k L1 8 PHASE VOUT 13 PVCC Q2 12 LGATE -+ + ++ -- CR2 MBR 340 11 PGND 4 R2 1k C20 0.1F 9 UGATE OSC R1 SPARE FB R6 10 BOOT RT 1 C13 0.1F CR1 4148 1000pF 14 7 COMP GND C6-9 4x 1000F RTN JP1 COMP TP1 C16 R3 1k SPARE R4 SPARE Component Selection Notes: C1-C3 - 3 each 680F 25W VDC, Sanyo MV-GX or equivalent C6-C9 - 4 each 1000F 6.3W VDC, Sanyo MV-GX or equivalent L1 - Core: Micrometals T50-52B; Winding: 10 Turns of 17AWG CR1 - 1N4148 or equivalent CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent Q1, Q2 - Intersil MOSFET; RFP25N05 FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT FN4306 Rev.3.00 April 1, 2005 Page 10 of 12 HIP6006 Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- e A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE A2 c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX 14 0o 14 7 8o Rev. 1 6/00 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) FN4306 Rev.3.00 April 1, 2005 Page 11 of 12 HIP6006 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N INDEX AREA 0.25(0.010) M H 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e A1 B 0.25(0.010) M µ B S 0.050 BSC 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS 14 0o 14 8o 0o 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2001-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4306 Rev.3.00 April 1, 2005 Page 12 of 12