NTHD4102P Power MOSFET −20 V, −4.1 A, Dual P−Channel ChipFETt Features • Offers an Ultra Low RDS(ON) Solution in the ChipFET Package • Miniature ChipFET Package 40% Smaller Footprint than TSOP−6 • Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin http://onsemi.com V(BR)DSS RDS(ON) TYP Environments such as Portable Electronics 64 mW @ −4.5 V • Simplifies Circuit Design since Additional Boost Circuits for Gate • • ID MAX −20 V Voltages are not Required Operated at Standard Logic Level Gate Drive, Facilitating Future Migration to Lower Levels using the same Basic Topology Pb−Free Package is Available 85 mW @ −2.5 V −4.1 A 120 mW @ −1.8 V S1 S2 Applications • Optimized for Battery and Load Management Applications in • • G1 G2 Portable Equipment such as MP3 Players, Cell Phones, and PDAs Charge Control in Battery Chargers Buck and Boost Converters D1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter P−Channel MOSFET Symbol Value Unit Drain−to−Source Voltage VDSS −20 V Gate−to−Source Voltage VGS "8.0 V ID −2.9 A Continuous Drain Current (Note 1) Steady State t ≤ 10 s Power Dissipation (Note 1) TA = 25°C TA = 85°C −2.1 TA = 25°C −4.1 Steady State t ≤ 10 s tp = 10 ms PD P−Channel MOSFET ChipFET CASE 1206A STYLE 2 PIN CONNECTIONS MARKING DIAGRAM W 1.1 2.1 D1 8 1 S1 1 8 D1 7 2 G1 2 7 D2 6 3 S2 3 D2 5 4 G2 4 C7 M G Pulsed Drain Current TA = 25°C D2 IDM −13.8 A TJ, TSTG −55 to 150 °C Source Current (Body Diode) IS −1.1 A Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C C7 = Specific Device Code M = Month Code G = Pb−Free Package Symbol Max Unit ORDERING INFORMATION 113 °C/W Operating Junction and Storage Temperature 6 5 THERMAL RESISTANCE RATINGS Parameter Junction−to−Ambient, Steady State (Note 1) Junction−to−Ambient, t ≤ 10s (Note 1) RqJA 60 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces) © Semiconductor Components Industries, LLC, 2005 November, 2005 − Rev. 5 1 Device Package Shipping † NTHD4102PT1 ChipFET 3000/Tape & Reel NTHD4102PT1G ChipFET (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTHD4102P/D NTHD4102P ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(Br)DSS VGS = 0 V, ID = −250 mA −20 Drain−to−Source Breakdown Voltage Temperature Coefficient V(Br)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V −15 VGS = 0 V VDS = −16 V mV/°C TJ = 25°C −1.0 TJ = 85°C −5.0 IGSS VDS = 0 V, VGS = "8.0 V VGS(TH) VGS = VDS, ID = −250 mA mA "100 nA −1.5 V ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Gate Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(ON) Forward Transconductance gFS −0.45 2.7 mV/°C VGS = −4.5 V, ID = −2.9 A 64 80 mW VGS = −2.5 V, ID = −2.2 A 85 110 VDS = −1.8 V, ID = −1.0 A 120 170 VDS = −10 V, ID = −2.9 A 7.0 S 750 pF CHARGES, CAPACITANCES, AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Total Gate Charge VGS = 0 V, f = 1.0 MHz, VDS = −16 V 100 45 QG(TOT) 7.6 VGS = −4.5 V, VDS = −16 V, ID = −2.6 A 8.6 nC ns Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 1.3 2.6 td(ON) 5.5 10 12 25 32 40 23 35 −0.8 −1.2 V 20 40 ns SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr VGS = −4.5 V, VDD = −16 V, ID = −2.6 A, RG = 2.0 W td(OFF) tf DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = −1.1 A VGS = 0 V, dIS/dt = 100 A/ms, IS = 1.0 A QRR 15 5 0.01 2. Pulse test: pulse width ≤ 300 ms, duty cycle ≤ 2% 3. Switching characteristics are independent of operating junction temperatures http://onsemi.com 2 mC NTHD4102P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 8 −2.4 V 7 6 5 4 3 2 −1.8 V 1 −1.6 V −1.4 V 0 0 1 2 3 4 5 7 6 8 7 6 5 4 3 125°C 2 25°C 1 TJ = −55°C 0 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.5 1 1.5 2 2.5 3 3.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0 4 1.5 0.2 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0.18 0.16 VGS = −2.5 V 0.14 0.12 0.1 VGS = −4.5 V 0.08 0.06 0.04 VGS = −4.5 V 1.3 1.1 0.9 0.7 0.02 0.5 −50 0 2 3 6 4 5 −ID, DRAIN CURRENT (AMPS) −25 0 25 VGS = 0 V 1000 TJ = 125°C TJ = 100°C 100 10 1 TJ = 25°C 0.1 3 75 100 125 Figure 4. On−Resistance Variation with Temperature 10000 2 50 TJ, JUNCTION TEMPERATURE (°C) Figure 3. On−Resistance vs. Drain Current and Gate Voltage −IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 9 TJ = 25°C VGS = −10 V to −2.8 V 9 −ID, DRAIN CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS) 10 4 5 6 7 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 8 150 NTHD4102P 1000 TJ = 25°C C, CAPACITANCE (pF) 900 800 700 Ciss 600 500 400 300 200 100 Coss Crss 0 0 2 4 6 8 10 12 14 16 18 20 −VGS −VDS 5 QT 4 3 Q2 Q1 2 1 ID = −2.7 A TJ = 25°C 0 1 0 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4 2 3 5 6 Qg, TOTAL GATE CHARGE (nC) 7 8 Figure 7. Gate−to−Source and Drain−to−Source Voltage vs. Total Gate Charge Figure 6. Capacitance Variation 1000 5 −IS, SOURCE CURRENT (AMPS) VDD = −10 V ID = −1.0 A VGS = −4.5 V 100 td(off) tf tr td(on) 10 1 1 10 VGS = 0 V TJ = 25°C 4 3 2 1 0 0.4 100 0.5 0.6 0.7 Figure 8. Resistive Switching Time Variation vs. Gate Resistance 10 10 ms 1 100 ms 1 ms 10 ms VGS = −8 V SINGLE PULSE TC = 25°C 0.01 0.1 0.9 1.0 1.1 1.2 Figure 9. Diode Forward Voltage vs. Current 100 0.1 0.8 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) RG, GATE RESISTANCE (OHMS) −I D, DRAIN CURRENT (AMPS) t, TIME (ns) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 10. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 NTHD4102P PACKAGE DIMENSIONS ChipFET] CASE 1206A−03 ISSUE G D 8 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. q 6 L 5 HE 5 6 7 8 4 3 2 1 E 1 2 3 e1 4 b c e STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. A SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 DIM A b c D E e e1 L HE q MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5° NOM MIN 1.00 0.25 0.10 2.95 1.55 MIN 0.039 0.010 0.004 0.116 0.061 MAX 0.043 0.014 0.008 0.122 0.067 0.017 0.079 0.05 (0.002) SOLDERING FOOTPRINT* 2.032 0.08 2.032 0.08 0.457 0.018 0.635 0.025 1.092 0.043 0.635 0.025 0.178 0.007 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 mm Ǔ ǒinches 0.66 0.026 Basic 0.254 0.010 SCALE 20:1 Style 2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 mm Ǔ ǒinches NTHD4102P ChipFET is a trademark of Vishay Siliconix. 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