TI LM4838MTX/NOPB Stereo 2w audio power amplifiers with dc volume control and selectable gain Datasheet

LM4838
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SNAS131F – JANUARY 2001 – REVISED MARCH 2013
LM4838
Stereo 2W Audio Power Amplifiers
with DC Volume Control and Selectable Gain
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FEATURES
DESCRIPTION
•
•
•
The LM4838 is a monolithic integrated circuit that
provides DC volume control, and stereo bridged
audio power amplifiers capable of producing 2W into
4Ω with less than 1.0% THD or 2.2W into 3Ω with
less than 1.0% THD (see Notes below).
1
23
•
•
•
DC Volume Control Interface
System Beep Detect
Stereo Switchable Bridged/Single-Ended
Power Amplifiers
Selectable Internal/External Gain and Bass
Boost
“Click and Pop” Suppression Circuitry
Thermal Shutdown Protection Circuitry
APPLICATIONS
•
•
•
Portable and Desktop Computers
Multimedia Monitors
Portable Radios, PDAs, and Portable TVs
Boomer™ audio integrated circuits were designed
specifically to provide high quality audio while
requiring a minimum amount of external components.
The LM4838 incorporates a DC volume control,
stereo bridged audio power amplifiers and a
selectable gain or bass boost, making it optimally
suited for multimedia monitors, portable radios,
desktop, and portable computer applications.
The LM4838 features an externally controlled, lowpower consumption shutdown mode, and both a
power amplifier and headphone mute for maximum
system flexibility and performance.
Note: When properly mounted to the circuit board,
the LM4838NJB, LM4838PWP, and LM4838NYC will
deliver 2W into 4Ω. The LM4838PW and LM4838YZR
will deliver 1.1W into 8Ω. See Application Information
section Exposed-DAP package PCB Mounting
Considerations for more information.
Note: An LM4838NJB and LM4838PWP that have
been properly mounted to the circuit board and
forced-air cooled will deliver 2.2W into 3Ω.
Table 1. Key Specifications
VALUE
UNIT
into 3Ω (NJB & PWP)
2.2
W (typ)
into 4Ω (NJB, PWP, NYC)
2.0
W (typ)
into 8Ω (PW, PWP, YZR, NJB, & NYC)
1.1
W (typ)
Single-ended mode - THD+N at 85mW into 32Ω
1.0
%(typ)
Shutdown current
0.7
µA (typ)
PO at 1% THD+N
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Boomer is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM4838
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Block Diagram
Figure 1. LM4838 Block Diagram
Connection Diagrams
Top View
Figure 2. WQFN Package
See Package Number NJB0028A for Exposed-DAP WQFN
2
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Top View
Figure 3. TSSOP Package
See Package Number PW0028A for TSSOP
See Package Number PWP0028A for Exposed-DAP TSSOP
Top View
Figure 4. 36 Bump DSBGA Package
See Package Number YZR0036AAA
Table 2. 36 Bump DSBGA Pinout Table
6
NC
Right Out -
VDD
Right Out +
GND
NC
5
GND
Right Gain 2
Right Gain 1
Gain Select
Shutdown
Mode
4
Bypass
NC
NC
DC Vol
Mute
VDD
3
HP Sense
NC
NC
Beep In
Right Dock
GND
2
GND
Left Gain 2
Left Gain 1
Left In
Left Dock
Right In
1
NC
Left Out -
VDD
Left Out +
GND
NC
Pin Designator
A
B
C
D
E
F
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Connection Diagram
Top View
7
6
5
4
3
2
1
A
B
C
D
E
F
G
Figure 5. 49 Bump CS-BGA Package
See Package Number NYC0049A
Table 3. 49 Bump CS-BGA Pinout Table
7
Right Out -
Right Gain 1
GND
Bypass
HP Sense
GND
Left Gain 1
6
Right Out -
Right Gain 2
GND
GND
GND
Left Gain 2
Left Out VDD
5
VDD
VDD
GND
GND
GND
Left Out -
4
Right Out +
Right Out +
GND
GND
GND
Left Out +
VDD
3
GND
GND
GND
GND
GND
GND
Left Out +
2
Shutdown
Gain Select
VDD
GND
Right In
Left In
GND
1
Mode
Mute
DC Vol
GND
Right Dock
Beep In
Left Dock
Pin
Designator
A
B
C
D
E
F
G
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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Absolute Maximum Ratings (1) (2)
Supply Voltage
6.0V
Storage Temperature
-65°C to +150°C
−0.3V to VDD +0.3V
Input Voltage
Power Dissipation (3)
Internally limited
(4)
2000V
ESD Susceptibility
ESD Susceptibility (5)
200V
Junction Temperature
150°C
Soldering Information
Small Outline Package
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
θJC (typ)—NJB0028A
3°C/W
θJA (typ)—NJB0028A
42°C/W
θJC (typ)—PW0028A
20°C/W
θJA (typ)—PW0028A
80°C/W
θJC (typ)—PWP0028A
2°C/W
(6)
41°C/W
θJA (typ)—PWP0028A (exposed DAP) (7)
54°C/W
θJA (typ)—PWP0028A (exposed DAP) (8)
59°C/W
θJA (typ)—PWP0028A (exposed DAP)
θJA (typ)—PWP0028A (exposed DAP)
(9)
93°C/W
θJA (typ)—IYZR0036AAA
100°C/W
θJC (typ)—IYZR0036AAA (10)
65°C/W
θJA (typ)—NYC0049A
100°C/W
θJC (typ)—NYC0049A (11)
54°C/W
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θ JA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX − TA )/θJA. For the LM4838, TJMAX = 150°C, and the typical junction-toambient thermal resistance for each package can be found in the Absolute Maximum Ratings section above.
(4) Human body model, 100pF discharged through a 1.5kΩ resistor.
(5) Machine Model, 220pF – 240pF discharged through all pins.
(6) The θJA given is for an PWP0028A package whose exposed-DAP is soldered to a 2in2 piece of 1 ounce printed circuit board copper on
a bottom side layer through 21 8mil vias.
(7) The θJA given is for an PWP0028A package whose exposed-DAP is soldered to an exposed 2in 2 piece of 1 ounce printed circuit board
copper.
(8) The θJA given is for an PWP0028A package whose exposed-DAP is soldered to an exposed 1in 2 piece of 1 ounce printed circuit board
copper.
(9) The θJA given is for an PWP0028A package whose exposed-DAP is not soldered to any copper.
(10) All bumps have the same thermal resistance and contribute equally when used to lower thermal resistance. The LM4838YZR demo
board (views featured in the Application Information section) is a four layer board with two inner layers. The second inner layer is a VDD
plane with the bottom outside layer a GND plane. The planes measure 1,900mils x 1,750mils (48.26mm x 44.45mm) and aid in
spreading heat due to power dissipation within the IC.
(11) All bumps have the same thermal resistance and contribute equally when used to lower thermal resistance. The LM4838NYC Demo
Board is a four layer PC Board with 2 inner layers. The second inner layer and bottom outside layers are both grounded. The planes
measure 3200 x 3700 mills and aid in spreading heat due to power dissipation within the IC.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤TMAX
−40°C ≤TA ≤ 85°C
2.7V≤ VDD ≤ 5.5V
Supply Voltage
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Electrical Characteristics for Entire IC (1) (2)
The following specifications apply for VDD = 5V unless otherwise noted. Limits apply for TA = 25°C.
Parameter
VDD
LM4838
Test Conditions
Typical
(3)
Limit (4)
Supply Voltage
Units
(Limits)
2.7
V (min)
5.5
V (max)
30
mA (max)
IDD
Quiescent Power Supply Current
VIN = 0V, IO = 0A
15
ISD
Shutdown Current
Vshutdown = VDD
0.7
VIH
Headphone Sense High Input Voltage
4
V (min)
VIL
Headphone Sense Low Input Voltage
0.8
V (max)
(1)
(2)
(3)
(4)
2.0
μA (max)
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 1.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to TI's AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test,
or statistical analysis.
Electrical Characteristics for Volume Attenuators (1) (2)
The following specifications apply for VDD = 5V. Limits apply for TA = 25°C.
Parameter
CRANGE
AM
(1)
(2)
(3)
(4)
Attenuator Range
Mute Attenuation
LM4838
Test Conditions
Typical
(3)
Gain with VDCVol = 5V, No Load
Limit (4)
Units
(Limits)
±0.75
dB (max)
Attenuation with VDCVol = 0V (BM & SE)
-75
dB (min)
Vmute = 5V, Bridged Mode (BM)
-78
dB (min)
Vmute = 5V, Single-Ended Mode (SE)
-78
dB (min)
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 1.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to TI's AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test,
or statistical analysis.
Electrical Characteristics for Single-Ended Mode Operation (1) (2)
The following specifications apply for VDD = 5V. Limits apply for TA = 25°C.
Parameter
PO
(1)
(2)
(3)
(4)
6
Output Power
Test Conditions
LM4838
Typical (3)
Limit (4)
Units
(Limits)
THD = 1.0%; f = 1kHz; RL = 32Ω
85
mW
THD = 10%; f = 1 kHz; RL = 32Ω
95
mW
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 1.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to TI's AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test,
or statistical analysis.
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Electrical Characteristics for Single-Ended Mode Operation(1)(2) (continued)
The following specifications apply for VDD = 5V. Limits apply for TA = 25°C.
Parameter
LM4838
Test Conditions
Typical
THD+N
Total Harmonic Distortion+Noise
VOUT = 1VRMS, f=1kHz, RL = 10kΩ, AVD
=1
PSRR
Power Supply Rejection Ratio
SNR
Xtalk
(3)
Limit (4)
Units
(Limits)
0.065
%
CB = 1.0 μF, f =120 Hz, VRIPPLE = 200
mVrms
58
dB
Signal to Noise Ratio
POUT =75 mW, R L = 32Ω, A-Wtd Filter
102
dB
Channel Separation
f=1kHz, CB = 1.0 μF
65
dB
Electrical Characteristics for Bridged Mode Operation (1) (2)
The following specifications apply for VDD = 5V, unless otherwise noted. Limits apply for TA = 25°C.
Parameter
VOS
Output Offset Voltage
PO
Output Power
LM4838
Test Conditions
VIN = 0V, No Load
THD + N = 1.0%; f=1kHz; RL = 3Ω
(5)
THD + N = 1.0%; f=1kHz; RL = 4Ω (6)
Typical (3)
Limit (4)
Units
(Limits)
5
±50
mV (max)
2.2
W
2
W
THD = 1% (max);f = 1 kHz;
RL = 8Ω
1.1
1.0
W (min)
THD+N = 10%;f = 1 kHz; RL = 8Ω
1.5
W
PO = 1W, 20 Hz< f < 20 kHz,
RL = 8Ω, AVD = 2
0.3
%
THD+N
Total Harmonic Distortion+Noise
PO = 340 mW, RL = 32Ω
1.0
%
PSRR
Power Supply Rejection Ratio
CB = 1.0 µF, f = 120 Hz,
VRIPPLE = 200 mVrms; RL = 8Ω
74
dB
SNR
Signal to Noise Ratio
VDD = 5V, POUT = 1.1W, RL = 8Ω, AWtd Filter
93
dB
Xtalk
Channel Separation
f=1kHz, CB = 1.0 μF
70
dB
(1)
(2)
(3)
(4)
(5)
(6)
All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical
application as shown in Figure 1.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at 25°C and represent the parametric norm.
Limits are specified to TI's AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test,
or statistical analysis.
When driving 3Ω loads from a 5V supply the LM4838NJB and LM4838PWP must be mounted to the circuit board and forced-air cooled.
When driving 4Ω loads from a 5V supply the LM4838NJB, LM4838PWP, and LM4838NYC must be mounted to the circuit board.
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TYPICAL APPLICATION
Figure 6. Typical Application Circuit (NJB0028A Package Pinout )
Truth Table for Logic Inputs (7)
Gain Sel
Mode
Headphone
Sense
Mute
Shutdown
Output Stage Set To
DC Volume
Output Stage
Configuration
0
0
0
0
0
Internal Gain
Fixed
BTL
0
0
1
0
0
Internal Gain
Fixed
SE
0
1
0
0
0
Internal Gain
Adjustable
BTL
0
1
1
0
0
Internal Gain
Adjustable
SE
1
0
0
0
0
External Gain
Fixed
BTL
1
0
1
0
0
External Gain
Fixed
SE
1
1
0
0
0
External Gain
Adjustable
BTL
1
1
1
0
0
External Gain
Adjustable
SE
X
X
X
1
0
Muted
X
Muted
X
X
X
X
1
Shutdown
X
X
(7)
8
If system beep is detected on the Beep In pin, the system beep will be passed through the bridged amplifier regardless of the logic of
the Mute and HP sense pins.
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Typical Performance Characteristics
PWP Specific Characteristics
LM4838PWP
THD+N vs Output Power
LM4838PWP
THD+N vs Frequency
Figure 7.
Figure 8.
LM4838PWP
THD+N vs Output Power
LM4838PWP
THD+N vs Frequency
Figure 9.
Figure 10.
LM4838PWP
Power Dissipation vs Output Power
LM4838PWP
Power Derating Curve
Figure 11.
These curves show the thermal dissipation ability of the LM4838PWP
at different ambient temperatures given these conditions:
500LFPM + 2in2: The part is soldered to a 2in2, 1 oz. copper plane
with 500 linear feet per minute of forced-air flow across it.
2in2on bottom: The part is soldered to a 2in2, 1oz. copper plane that
is on the bottom side of the PC board through 21 8 mil vias.
2in2: The part is soldered to a 2in2, 1oz. copper plane.1in2: The part
is soldered to a 1in2, 1oz. copper plane.
Not Attached: The part is not soldered down and is not forced-air
cooled.
Figure 12.
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Typical Performance Characteristics
Non-PWP Specific Characteristics
10
THD+N vs Frequency
THD+N vs Frequency
Figure 13.
Figure 14.
THD+N vs Frequency
THD+N vs Frequency
Figure 15.
Figure 16.
THD+N vs Frequency
THD+N vs Frequency
Figure 17.
Figure 18.
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Typical Performance Characteristics
Non-PWP Specific Characteristics (continued)
THD+N vs Frequency
THD+N vs Frequency
Figure 19.
Figure 20.
THD+N vs Frequency
THD+N vs Frequency
Figure 21.
Figure 22.
THD+N vs Frequency
THD+N vs Output Power
Figure 23.
Figure 24.
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Typical Performance Characteristics
Non-PWP Specific Characteristics (continued)
12
THD+N vs Output Power
THD+N vs Output Power
Figure 25.
Figure 26.
THD+N vs Output Power
THD+N vs Output Power
Figure 27.
Figure 28.
THD+N vs Output Power
THD+N vs Output Power
Figure 29.
Figure 30.
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Typical Performance Characteristics
Non-PWP Specific Characteristics (continued)
THD+N vs Output Power
THD+N vs Output Power
Figure 31.
Figure 32.
THD+N vs Output Power
THD+N vs Output Power
Figure 33.
Figure 34.
THD+N vs Output Voltage
Docking Station Pins
THD+N vs Output Voltage
Docking Station Pins
Figure 35.
Figure 36.
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Typical Performance Characteristics
14
Output Power vs
Load Resistance
Dropout Voltage
Figure 37.
Figure 38.
Output Power vs
Load Resistance
Output Power vs
Load Resistance
Figure 39.
Figure 40.
Power Supply
Rejection Ratio
Output Power vs
Load Resistance
Figure 41.
Figure 42.
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Typical Performance Characteristics (continued)
Noise Floor
Noise Floor
Figure 43.
Figure 44.
Volume Control
Characteristics
External Gain/
Bass Boost Characteristics
Figure 45.
Figure 46.
Power Dissipation vs
Output Power
Power Dissipation vs
Output Power
Figure 47.
Figure 48.
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Typical Performance Characteristics (continued)
Power Derating Curve
Crosstalk
Figure 49.
Figure 50.
Output Power
vs Supply voltage
Output Power
vs Supply Voltage
Figure 51.
Figure 52.
Supply Current
vs Supply Voltage
LM4838YZR
Power Derating Curve
Figure 53.
16
These curves show the thermal dissipation of the LM4838YZR at
different ambient temperatures with a thermal plane of size shown on
an outside PCB layer using 1oz. copper.
Figure 54.
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APPLICATION INFORMATION
EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATIONS
The LM4838's exposed-DAP (die attach paddle) packages (PWP, NJB) provide a low thermal resistance
between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the
die to the surrounding PCB copper traces, ground plane and, finally, surrounding air. The result is a low voltage
audio power amplifier that produces 2.1W at ≤ 1% THD with a 4Ω load. This high power is achieved through
careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the
LM4838's high power performance and activate unwanted, though necessary, thermal shutdown protection.
The PWP and NJB packages must have their exposed DAPs soldered to a grounded copper pad on the PCB.
The DAP's PCB copper pad is connected to a large grounded plane of continuous unbroken copper. This plane
forms a thermal mass heat sink and radiation area. Place the heat sink area on either outside plane in the case
of a two-sided PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to
the inner layer or backside copper heat sink area with 32(4x8) (PWP) or 6(3x2) (NJB) vias. The via diameter
should be 0.012in–0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plating-through and
solder-filling the vias.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2.5in2 (min) area is necessary for 5V operation with a 4Ω load.
Heatsink areas not placed on the same PCB layer as the LM4838 PWP and NJB packages should be 5in2 (min)
for the same supply voltage and load resistance. The last two area recommendations apply for 25°C ambient
temperature. Increase the area to compensate for ambient temperatures above 25°C. In systems using cooling
fans, the LM4838PWP can take advantage of forced air cooling. With an air flow rate of 450 linear-feet per
minute and a 2.5in2 exposed copper or 5.0in2 inner layer copper plane heatsink, the LM4838PWP can
continuously drive a 3Ω load to full power. The LM4838NJB achieves the same output power level without forced
air cooling. In all circumstances and conditions, the junction temperature must be held below 150°C to prevent
activating the LM4838's thermal shutdown protection. The LM4838's power de-rating curve in the Typical
Performance Characteristics shows the maximum power dissipation versus temperature. Example PCB layouts
for the exposed-DAP TSSOP and NJB packages are shown in the Demonstration Board Layout section. Further
detailed and specific information concerning PCB layout, fabrication, and mounting an NJB (WQFN) package is
available in TI's AN1187.
The YZR and NYC packages (LM4838YZR and LM4838NYC) thermals work in a similar way to the NJB and
PWP packages in that a thermal plane increases the heat transfer from the die. The thermal plane can be any
electrical potential but needs to be below the package to aid in the spreading the heat from the die out to
surrounding PCB areas to reduce the thermal resistance of the DSBGA package. The thermal plane is most
effective when placed on the top or first internal PCB layers. The traces connecting the bumps also contribute to
spreading heat away from the die. The same recommendations for the size of the thermal plane as given above
apply for the YZR and NYC packages, namely 2.5in2 minimum for top layer thermal plane and 5in2 minimum for
internal or bottom layers.
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω
LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ω load from 2.1W to 2.0W. This problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
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BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 6, the LM4838 output stage consists of two pairs of operational amplifiers, forming a twochannel (channel A and channel B) stereo amplifier. (Though the following discusses channel A, it applies
equally to channel B.)
Figure 6 shows that the first amplifier's negative (-) output serves as the second amplifier's input. This results in
both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase
difference, a load is placed between −OUTA and +OUTA and driven differentially (commonly referred to as
“bridge mode”). This results in a differential gain of
AVD = 2 * (Rf/R i)
(1)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. This produces four
times the output power when compared to a single-ended amplifier under the same conditions. This increase in
attainable output power assumes that the amplifier is not current limited or that the output signal is not clipped.
To ensure minimum output signal clipping when choosing an amplifier's closed-loop gain, refer to the Audio
Power Amplifier Design section.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing channel A's and channel B's outputs at half-supply. This eliminates the coupling capacitor that single
supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. Equation 2
states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and
driving a specified output load.
PDMAX = (VDD)2/(2π2RL)
Single-Ended
(2)
However, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher
internal power dissipation for the same conditions.
The LM4838 has two operational amplifiers per channel. The maximum internal power dissipation per channel
operating in the bridge mode is four times that of a single-ended amplifier. From Equation 3, assuming a 5V
power supply and a 4Ω load, the maximum single channel power dissipation is 1.27W or 2.54W for stereo
operation.
PDMAX = 4 * (VDD)2/(2π2RL)
Bridge Mode
(3)
The LM4838's power dissipation is twice that given by Equation 2 or Equation 3 when operating in the singleended mode or bridge mode, respectively. Twice the maximum power dissipation point given by Equation 3 must
not exceed the power dissipation given by Equation 4:
PDMAX′ = (TJMAX − TA)/θJA
(4)
The LM4838's TJMAX = 150°C. In the NJB package soldered to a DAP pad that expands to a copper area of 5in2
on a PCB, the LM4838's θJA is 20°C/W. In the PWP package soldered to a DAP pad that expands to a copper
area of 2in2 on a PCB, the LM4838PWP's θJA is 41°C/W. For the LM4838PW package, θJA = 80°C/W. At any
given ambient temperature TA, use Equation 4 to find the maximum internal power dissipation supported by the
IC packaging. Rearranging Equation 4 and substituting PDMAX for PDMAX′ results in Equation 5. This equation
gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the
LM4838's maximum junction temperature.
TA = TJMAX – 2*PDMAX θJA
(5)
For a typical application with a 5V power supply and an 4Ω load, the maximum ambient temperature that allows
maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 99°C
for the NJB package and 45°C for the PWP package.
TJMAX = PDMAX θJA + TA
18
(6)
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Equation 6 gives the maximum junction temperature TJMAX. If the result violates the LM4838's 150°C TJMAX,
reduce the maximum junction temperature by reducing the power supply voltage or increasing the load
resistance. Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases.
If the result of Equation 2 is greater than that of Equation 3, then decrease the supply voltage, increase the load
impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to
reduce θJA. The heat sink can be created using additional copper area around the package, with connections to
the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the
Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the θJA is the sum of θJC, θCS,
and θSA. (θJC is the junction-to-case thermal impedance, θCS is the case-to-sink thermal impedance, and θSA is
the sink-to-ambient thermal impedance.) Refer to the Typical Performance Characteristics curves for power
dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10 µF in parallel with a 0.1 µF filter capacitor to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4838's supply pins and ground. Do not substitute a ceramic capacitor for the tantalum. Doing so
may cause oscillation. Keep the length of leads and traces that connect capacitors between the LM4838's power
supply pin and ground as short as possible. Connecting a 1µF capacitor, CB, between the BYPASS pin and
ground improves the internal bias voltage's stability and the amplifier's PSRR. The PSRR improvements increase
as the BYPASS pin capacitor value increases. Too large a capacitor, however, increases turn-on time and can
compromise the amplifier's click and pop performance. The selection of bypass capacitor values, especially CB,
depends on desired PSRR requirements, click and pop performance (as explained in the following section,
Selecting Proper External Components), system cost, and size constraints.
SELECTING PROPER EXTERNAL COMPONENTS
Optimizing the LM4838's performance requires properly selecting external components. Though the LM4838
operates well when using external components with wide tolerances, best performance is achieved by optimizing
component values.
The LM4838 is unity-gain stable, giving a designer maximum design flexibility. The gain should be set to no more
than a given application requires. This allows the amplifier to achieve minimum THD+N and maximum signal-tonoise ratio. These parameters are compromised as the closed-loop gain increases. However, low gain circuits
demand input signals with greater voltage swings to achieve maximum output power. Fortunately, many signal
sources such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the Audio Power Amplifier
Design section for more information on selecting the proper gain.
INPUT CAPACITOR VALUE SELECTION
Amplifying the lowest audio frequencies requires a high value input coupling capacitor (0.33µF in Figure 6), but
high value capacitors can be expensive and may compromise space efficiency in portable designs. In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150 Hz. Applications using speakers with this limited frequency response reap little
improvement by using a large input capacitor.
Besides effecting system cost and size, the input coupling capacitor has an affect on the LM4838's click and pop
performance. When the supply voltage is first applied, a transient (pop) is created as the charge on the input
capacitor changes from zero to a quiescent state. The magnitude of the pop is directly proportional to the input
capacitor's size. Higher value capacitors need more time to reach a quiescent DC voltage (usually VDD/2) when
charged with a fixed current. The amplifier's output charges the input capacitor through the feedback resistor, Rf.
Thus, pops can be minimized by selecting an input capacitor value that is no higher than necessary to meet the
desired −6dB frequency.
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As shown in Figure 6, the input resistor (RIR, RIL = 20k) ( and the input capacitor (CIR, CIL = 0.33µF) produce a
−6dB high pass filter cutoff frequency that is found using Equation 7.
(7)
As an example when using a speaker with a low frequency limit of 150Hz, the input coupling capacitor, using
Equation 7, is 0.053µF. The 0.33µF input coupling capacitor shown in Figure 6 allows the LM4838 to drive a high
efficiency, full range speaker whose response extends below 30Hz.
OPTIMIZING CLICK AND POP REDUCTION PERFORMANCE
The LM4838 contains circuitry that minimizes turn-on and shutdown transients or “clicks and pops”. For this
discussion, turn-on refers to either applying the power supply voltage or when the shutdown mode is deactivated.
While the power supply is ramping to its final value, the LM4838's internal amplifiers are configured as unity gain
buffers. An internal current source changes the voltage of the BYPASS pin in a controlled, linear manner. Ideally,
the input and outputs track the voltage applied to the BYPASS pin. The gain of the internal amplifiers remains
unity until the voltage on the BYPASS pin reaches 1/2 VDD . As soon as the voltage on the BYPASS pin is
stable, the device becomes fully operational. Although the BYPASS pin current cannot be modified, changing the
size of CB alters the device's turn-on time and the magnitude of “clicks and pops”. Increasing the value of CB
reduces the magnitude of turn-on pops. However, this presents a tradeoff: as the size of CB increases, the turnon time increases. There is a linear relationship between the size of CB and the turn-on time. Here are some
typical turn-on times for various values of CB:
CB
TON
0.01µF
2ms
0.1µF
20ms
0.22µF
44ms
0.47µF
94ms
1.0µF
200ms
DOCKING STATION INTERFACE
Applications such as notebook computers can take advantage of a docking station to connect to external devices
such as monitors or audio/visual equipment that sends or receives line level signals. The LM4838 has two
outputs, Right Dock and Left Dock, which connect to outputs of the internal input amplifiers that drive the volume
control inputs. These input amplifiers can drive loads of >1kΩ (such as powered speakers) with a rail-to-rail
signal. Since the output signal present on the RIGHT DOCK and LEFT DOCK pins is biased to VDD/2, coupling
capacitors should be connected in series with the load when using these outputs. Typical values for the output
coupling capacitors are 0.33µF to 1.0µF. If polarized coupling capacitors are used, connect their "+" terminals to
the respective output pin, see Figure 6.
Since the DOCK outputs precede the internal volume control, the signal amplitude will be equal to the input
signal's magnitude and cannot be adjusted. However, the input amplifier's closed-loop gain can be adjusted
using external resistors. These 20k resistors (RFR, RFL) are shown in Figure 6 and they set each input amplifier's
gain to -1. Use Equation 7 to determine the input and feedback resistor values for a desired gain.
- AVR = RFR/RIR and - AVL = RFL/RIL
(8)
Adjusting the input amplifier's gain sets the minimum gain for that channel. Although the single ended output of
the Bridge Output Amplifiers can be used to drive line level outputs, it is recommended that the R & L Dock
Outputs simpler signal path be used for better performance.
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BEEP DETECT FUNCTION
Computers and notebooks produce a system “beep“ signal that drives a small speaker. The speaker's auditory
output signifies that the system requires user attention or input. To accommodate this system alert signal, the
LM4838's beep input pin is a mono input that accepts the beep signal. Internal level detection circuitry at this
input monitors the beep signal's magnitude. When a signal level greater than VDD/2 is detected on the BEEP IN
pin, the bridge output amplifiers are enabled. The beep signal is amplified and applied to the load connected to
the output amplifiers. A valid beep signal will be applied to the load even when MUTE is active. Use the input
resistors connected between the BEEP IN pin and the stereo input pins to accommodate different beep signal
amplitudes. These resistors (RBEEP) are shown as 200kΩ devices in Figure 6. Use higher value resistors to
reduce the gain applied to the beep signal. The resistors must be used to pass the beep signal to the stereo
inputs. The BEEP IN pin is used only to detect the beep signal's magnitude: it does not pass the signal to the
output amplifiers. The LM4838's shutdown mode must be deactivated before a system alert signal is applied to
BEEP IN pin.
MICRO-POWER SHUTDOWN
The voltage applied to the SHUTDOWN pin controls the LM4838's shutdown function. Activate micro-power
shutdown by applying VDD to the SHUTDOWN pin. When active, the LM4838's micro-power shutdown feature
turns off the amplifier's bias circuitry, reducing the supply current. The logic threshold is typically VDD/2. The low
0.7 µA typical shutdown current is achieved by applying a voltage that is as near as VDD as possible to the
SHUTDOWN pin. A voltage that is less than VDD may increase the shutdown current.
There are a few ways to control the micro-power shutdown. These include using a single-pole, single-throw
switch, a microprocessor, or a microcontroller. When using a switch, connect an external 10kΩ pull-up resistor
between the SHUTDOWN pin and VDD. Connect the switch between the SHUTDOWN pin and ground. Select
normal amplifier operation by closing the switch. Opening the switch connects the SHUTDOWN pin to VDD
through the pull-up resistor, activating micro-power shutdown. The switch and resistor ensure that the
SHUTDOWN pin will not float. This prevents unwanted state changes. In a system with a microprocessor or a
microcontroller, use a digital output to apply the control voltage to the SHUTDOWN pin. Driving the SHUTDOWN
pin with active circuitry eliminates the need for a pull up resistor.
MODE FUNCTION
The LM4838's MODE function has 2 states controlled by the voltage applied to the MODE pin. Mode 0, selected
by applying 0V to the MODE pin, forces the LM4838 to effectively function as a "line-out," unity-gain amplifier.
Mode 1, which uses the internal DC controlled volume control is selected by applying VDD to the MODE pin. This
mode sets the amplifier's gain according to the DC voltage applied to the DC VOL CONTROL pin. Unanticipated
gain behavior can be prevented by connecting the MODE pin to VDD or ground. Note: Do not let the mode pin
float.
MUTE FUNCTION
The LM4838 mutes the amplifier and DOCK outputs when VDD is applied to the MUTE pin. Even while muted,
the LM4838 will amplify a system alert (beep) signal whose magnitude satisfies the BEEP DETECT circuitry.
Applying 0V to the MUTE pin returns the LM4838 to normal, unmuted operation. Prevent unanticipated mute
behavior by connecting the MUTE pin to VDD or ground. Do not let the mute pain float.
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Figure 55. Headphone Sensing Circuit
HP SENSE FUNCTION ( Head Phone In )
Applying a voltage between 4V and VDD to the LM4838's HP-IN headphone control pin turns off the amps that
drive the Left out "+" and Right out "+" pins. This action mutes a bridged-connected load. Quiescent current
consumption is reduced when the IC is in this single-ended mode.
Figure 55 shows the implementation of the LM4838's headphone control function. With no headphones
connected to the headphone jack, the R1-R2 voltage divider sets the voltage applied to the HP SENSE pin at
approximately 50mV. This 50mV puts the LM4838 into bridged mode operation. The output coupling capacitor
blocks the amplifier's half supply DC voltage, protecting the headphones.
The HP-IN threshold is set at 4V. While the LM4838 operates in bridged mode, the DC potential across the load
is essentially 0V. Therefore, even in an ideal situation, the output swing cannot cause a false single-ended
trigger. Connecting headphones to the headphone jack disconnects the headphone jack contact pin from R2 and
allows R1 to pull the HP Sense pin up to VDD through R4. This enables the headphone function, turns off both of
the "+" output amplifiers, and mutes the bridged speaker. The remaining single-ended amplifiers then drive the
headphones, whose impedance is in parallel with resistors R2 and R3. These resistors have negligible effect on
the LM4838's output drive capability since the typical impedance of headphones is 32Ω.
Figure 55 also shows the suggested headphone jack electrical connections. The jack is designed to mate with a
three-wire plug. The plug's tip and ring should each carry one of the two stereo output signals, whereas the
sleeve should carry the ground return. A headphone jack with one control pin contact is sufficient to drive the HPIN pin when connecting headphones.
A microprocessor or a switch can replace the headphone jack contact pin. When a microprocessor or switch
applies a voltage greater than 4V to the HP-IN pin, a bridge-connected speaker is muted and the single ended
output amplifiers 1A and 2A will drive a pair of headphones.
GAIN SELECT FUNCTION (Bass Boost)
The LM4838 features selectable gain, using either internal or external feedback resistors. Either set of feedback
resistors set the gain of the output amplifiers. The voltage applied to the GAIN SELECT pin controls which gain is
selected. Applying VDD to the GAIN SELECT pin selects the external gain mode. Applying 0V to the GAIN
SELECT pin selects the internally set unity gain.
In some cases a designer may want to improve the low frequency response of the bridged amplifier or
incorporate a bass boost feature. This bass boost can be useful in systems where speakers are housed in small
enclosures. A resistor, RLFE, and a capacitor, CLFE, in parallel, can be placed in series with the feedback resistor
of the bridged amplifier as seen in Figure 56.
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Figure 56. Low Frequency Enhancement
At low, frequencies CLFE is a virtual open circuit and at high frequencies, its nearly zero ohm impedance shorts
RLFE. The result is increased bridge-amplifier gain at low frequencies. The combination of RLFE and CLFE form a 6dB corner frequency at
fC = 1/(2πRLFEC LFE)
(9)
The bridged-amplifier low frequency differential gain is:
AVD = 2(RF + RLFE) / R i
(10)
Using the component values shown in Figure 1 (RF = 20kΩ, RLFE = 20kΩ, and CLFE = 0.068µF), a first-order, 6dB pole is created at 120Hz. Assuming R i = 20kΩ, the low frequency differential gain is 4. The input (Ci) and
output (CO) capacitor values must be selected for a low frequency response that covers the range of frequencies
affected by the desired bass-boost operation.
DC VOLUME CONTROL
The LM4838 has an internal stereo volume control whose setting is a function of the DC voltage applied to the
DC VOL CONTROL pin.
The LM4838 volume control consists of 31 steps that are individually selected by a variable DC voltage level on
the volume control pin. The range of the steps, controlled by the DC voltage, are from 0dB - 78dB. Each gain
step corresponds to a specific input voltage range, as shown in table 2.
To minimize the effect of noise on the volume control pin, which can affect the selected gain level, hysteresis has
been implemented. The amount of hysteresis corresponds to half of the step width, as shown in Volume Control
Characterization Graph (DS200133-40).
For highest accuracy, the voltage shown in the 'recommended voltage' column of the table is used to select a
desired gain. This recommended voltage is exactly halfway between the two nearest transitions to the next
highest or next lowest gain levels.
The gain levels are 1dB/step from 0dB to -6dB, 2dB/step from -6dB to -36dB, 3dB/step from -36dB to -47dB,
4dB/step from -47db to -51dB, 5dB/step from -51dB to -66dB, and 12dB to the last step at -78dB.
VOLUME CONTROL TABLE ( Table 2 )
Gain (dB)
Voltage Range (% of Vdd)
Low
High
Recommended
Voltage Range (Vdd = 5)
Low
High
Recommended
Voltage Range (Vdd = 3)
Low
High
Recommended
0
77.5%
100.00%
100.000%
3.875
5.000
5.000
2.325
3.000
3.000
-1
75.0%
78.5%
76.875%
3.750
3.938
3.844
2.250
2.363
2.306
-2
72.5%
76.25%
74.375%
3.625
3.813
3.719
2.175
2.288
2.231
-3
70.0%
73.75%
71.875%
3.500
3.688
3.594
2.100
2.213
2.156
-4
67.5%
71.25%
69.375%
3.375
3.563
3.469
2.025
2.138
2.081
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Voltage Range (% of Vdd)
Recommended
Voltage Range (Vdd = 5)
Low
High
Voltage Range (Vdd = 3)
Low
High
Recommended
Low
High
Recommended
-5
65.0%
68.75%
66.875%
3.250
3.438
3.344
1.950
2.063
2.006
-6
62.5%
66.25%
64.375%
3.125
3.313
3.219
1.875
1.988
1.931
-8
60.0%
63.75%
61.875%
3.000
3.188
3.094
1.800
1.913
1.856
-10
57.5%
61.25%
59.375%
2.875
3.063
2.969
1.725
1.838
1.781
-12
55.0%
58.75%
56.875%
2.750
2.938
2.844
1.650
1.763
1.706
-14
52.5%
56.25%
54.375%
2.625
2.813
2.719
1.575
1.688
1.631
-16
50.0%
53.75%
51.875%
2.500
2.688
2.594
1.500
1.613
1.556
-18
47.5%
51.25%
49.375%
2.375
2.563
2.469
1.425
1.538
1.481
-20
45.0%
48.75%
46.875%
2.250
2.438
2.344
1.350
1.463
1.406
-22
42.5%
46.25%
44.375%
2.125
2.313
2.219
1.275
1.388
1.331
-24
40.0%
43.75%
41.875%
2.000
2.188
2.094
1.200
1.313
1.256
-26
37.5%
41.25%
39.375%
1.875
2.063
1.969
1.125
1.238
1.181
-28
35.0%
38.75%
36.875%
1.750
1.938
1.844
1.050
1.163
1.106
-30
32.5%
36.25%
34.375%
1.625
1.813
1.719
0.975
1.088
1.031
-32
30.0%
33.75%
31.875%
1.500
1.688
1.594
0.900
1.013
0.956
-34
27.5%
31.25%
29.375%
1.375
1.563
1.469
0.825
0.937
0.881
-36
25.0%
28.75%
26.875%
1.250
1.438
1.344
0.750
0.862
0.806
-39
22.5%
26.25%
24.375%
1.125
1.313
1.219
0.675
0.787
0.731
-42
20.0%
23.75%
21.875%
1.000
1.188
1.094
0.600
0.712
0.656
-45
17.5%
21.25%
19.375%
0.875
1.063
0.969
0.525
0.637
0.581
-47
15.0%
18.75%
16.875%
0.750
0.937
0.844
0.450
0.562
0.506
-51
12.5%
16.25%
14.375%
0.625
0.812
0.719
0.375
0.487
0.431
-56
10.0%
13.75%
11.875%
0.500
0.687
0.594
0.300
0.412
0.356
-61
7.5%
11.25%
9.375%
0.375
0.562
0.469
0.225
0.337
0.281
-66
5.0%
8.75%
6.875%
0.250
0.437
0.344
0.150
0.262
0.206
-78
0.0%
6.25%
0.000%
0.000
0.312
0.000
0.000
0.187
0.000
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8Ω Load
The following are the desired operational parameters:
Power Output:
1 WRMS
Load Impedance:
8Ω
Input Level:
1 VRMS
Input Impedance:
20 kΩ
Bandwidth:
100 Hz−20 kHz ± 0.25 dB
The design begins by specifying the minimum supply voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the Typical
Performance Characteristics section. Another way, using Equation 10, is to calculate the peak output voltage
necessary to achieve the desired output power for a given load impedance. To account for the amplifier's dropout
voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the Typical Performance
Characteristics curves, must be added to the result obtained by Equation 10. The result is Equation 11.
(11)
(12)
VDD ≥ (VOUTPEAK+ (VODTOP + VODBOT))
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The Output Power vs Supply Voltage graph for an 8Ω load indicates a minimum supply voltage of 4.6V. This is
easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom,
allowing the LM4838 to produce peak output power in excess of 1W without clipping or other audible distortion.
The choice of supply voltage must also not create a situation that violates of maximum power dissipation as
explained above in the Power Dissipation section.
After satisfying the LM4838's power dissipation requirements, the minimum differential gain needed to achieve
1W dissipation in an 8Ω load is found using Equation 12.
(13)
Thus, a minimum overall gain of 2.83 allows the LM4838's to reach full output swing and maintain low noise and
THD+N performance.
The last step in this design example is setting the amplifier's −6dB frequency bandwidth. To achieve the desired
±0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the
lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth
limit. The gain variation for both response limits is 0.17dB, well within the ±0.25dB desired limit. The results are
an
fL = 100Hz/5 = 20Hz
(14)
and an
fH = 20kHz x 5 = 100kHz
(15)
As mentioned in the Selecting Proper External Components section, Ri (Right & Left) and Ci (Right & Left) create
a highpass filter that sets the amplifier's lower bandpass frequency limit. Find the input coupling capacitor's value
using Equation 14.
Ci≥ 1/(2πRifL)
(16)
The result is
1/(2π*20kΩ*20Hz) = 0.397μF
(17)
Use a 0.39μF capacitor, the closest standard value.
The product of the desired high frequency cutoff (100kHz in this example) and the differential gain AVD,
determines the upper passband response limit. With AVD = 3 and fH = 100kHz, the closed-loop gain bandwidth
product (GBWP) is 300kHz. This is less than the LM4838's 3.5MHz GBWP. With this margin, the amplifier can
be used in designs that require more differential gain while avoiding performance,restricting bandwidth
limitations.
Recommended Printed Circuit Board Layout
The following figures show the recommended PC board layouts that are optimized for the different package
options of the LM4838 and associated external components. This circuit is designed for use with an external 5V
supply and 4Ω speakers.
This circuit board is easy to use. Apply 5V and ground to the board's VDD and GND pads, respectively. Connect
4Ω speakers between the board's −OUTA and +OUTA and OUTB and +OUTB pads.
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LM4838
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Figure 57. Recommended NJB PC Board Layout:
Component-Side Silkscreen
Figure 58. Recommended NJB PC Board Layout:
Component-Side Layout
26
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Figure 59. Recommended NJB PC Board Layout:
Upper Inner-Layer Layout
Figure 60. Recommended NJB PC Board Layout:
Lower Inner-Layer Layout
Figure 61. Recommended NJB PC Board Layout:
Bottom-Side Layout
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Table 4. Analog Audio LM4838 NJB28 Eval Board
Assembly Part Number: 980011368-100
Revision: A1
Bill of Material
Item
Part Number
Part Description
Qty
Ref Designator
1
551011368-001
LM4838 Eval Board PCB
etch 001
1
10
482911368-001
LM4838 28L LLP
1
U4
20
151911368-001
Cer Cap 0.068µF 50V
10% 1206
2
CBS1, CBS2
25
152911368-001
Tant Cap 0.1µF 10V 10%
Size = A 3216
3
CS1, CS2, CV
26
152911368-002
Tant Cap 0.33µF 10V
10% Size = A 3216
3
Cin1, Cin2, Cin3
27
152911368-003
Tant Cap 1µF 16V 10%
Size = A 3216
3
CB, C01, C02
28
152911368-004
Tant Cap 10µF 10V 10%
Size = C 6032
1
CS3
29
152911368-005
Tant Cap 220µF 16V 10%
Size = D 7343
2
Cout1, Cout2
30
472911368-001
Res 1.5K Ohm 1/8W 1%
1206
2
RL1, RL2
31
472911368-002
Res 20k Ohm 1/8W 1%
1206
10
Rin1, Rin2, RF1, RF2
Remark
Rl1, Rl2, RBS1, RBS2
Rdock1, Rdock2
28
32
472911368-003
Res 100k Ohm 1/8W 1%
1206
2
RS, RPU
33
472911368-004
Res 200k Ohm 1/16W 1%
0603
2
Rbeep1, Rbeep2
40
131911368-001
Stereo Headphone Jack
W/ Switch
1
U2
Mouser # 161-3500
41
131911368-002
Slide Switch
4
Mode, Mute, Gain, SD
Mouser # 10SP003
42
131911368-003
Potentiometer
1
U1
Mouser # 317-290-100K
43
131911368-004
RCA Jack
3
RightIn, BeepIn, LeftIn
Mouser # 16PJ097
44
131911368-005
Banana Jack, Black
3
GND, Right Out-, Left Out-
Mouser # ME164-6219
45
131911368-006
Banana Jack, Red
3
Vdd, Right Out+, Left Out+
Mouser # ME164-6218
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LM4838 PW & PWP Demo Board Artwork
Figure 62. Top Layer SilkScreen
Figure 63. Top Layer TSSOP
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Figure 64. Inner Layer (2) LM4838 PW / PWP
Figure 65. Inner Layer (3) LM4838 PW / PWP
30
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Figure 66. Bottom Layer TSSOP
Table 5. Analog Audio LM4838 TSSOP Eval Board
Assembly Part Number: 980011373-100
Revision: A
Bill of Material
Item
Part Number
Part Description
Qty
Ref Designator
1
551011373-001
LM4838 Eval Board PCB
etch 001
1
10
482911373-001
LM4838 TSSOP
1
20
151911368-001
Cer Cap 0.068µF 50V 10%
1206
2
CBS
25
152911368-001
Tant Cap 0.1µF 10V 10%
Size = A 3216
3
CS, CS, CV
26
152911368-002
Tant Cap 0.33µF 10V 10%
Size = A 3216
3
CIN
27
152911368-003
Tant Cap 1µF 16V 10%
Size = A 3216
3
CB, CO1, CO2
28
152911368-004
Tant Cap 10µF 10V 10%
Size = C 6032
1
CS1
29
152911368-005
Tant Cap 220µF 16V 10%
Size = D 7343
2
CoutL, R
30
472911368-001
Res 1.5K Ohm 1/8W 1%
1206
2
RL
31
472911368-002
Res 20K Ohm 1/8W 1%
1206
10
RIN(4), RF(2),
RDOCK(2), RBS(2)
32
472911368-003
Res 100K Ohm 1/8W 1%
1206
2
RPU, RS
33
472911368-004
Res 200K Ohm 1/16W 1%
0603
2
RBEEP
40
131911368-001
Stereo Headphone Jack W/
Switch
1
41
131911368-002
Slide Switch
4
Remark
Mouser # 1613500
mute, mode, Gain,
SD
Mouser #
10SP003
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LM4838
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Table 5. Analog Audio LM4838 TSSOP Eval Board
Assembly Part Number: 980011373-100
Revision: A
Bill of Material (continued)
Item
Part Number
Part Description
Qty
Ref Designator
Remark
42
131911368-003
Potentiometer
1
Volume Control
Mouser # 3172090-100K
43
131911368-004
RCA Jack
3
Right-In, Beep-In,
Left-In
Mouser #
16PJ097
44
131911368-005
Banana Jack, Black
3
Mouser # ME1646219
45
131911368-006
Banana Jack, Red
3
Mouser # ME1646218
LM4838 YZR Demo Board Artwork
Figure 67. LM4838 DSBGA Silk Screen
32
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Figure 68. LM4838 DSBGA Top Layer
Figure 69. LM4838 DSBGA Upper Inner Layer
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LM4838
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Figure 70. LM4838 DSBGA Lower Inner Layer
Figure 71. LM4838 DSBGA Bottom Layer
34
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SNAS131F – JANUARY 2001 – REVISED MARCH 2013
Table 6. Analog Audio LM4838 YZR36 Board
Bill of Material
Part Description µΩ
Qty
Reference Designator
LM4838 YZR36 Evaluation Board PCB
1
P/N: 551011755 - 002 rev A
LM4838YZR
1
U1
Ceramic Capacitor 0.068µF 50V 10%
Size = 1206
2
CBS1, CBS2
Tantalum Capacitor 0.1µF 10V 10%
Size = 1206
3
CS1, CS2, CV
Tantalum Capacitor 0.33µF 10V 10%
Size = 1206
3
CIN1, CIN2, CIN3
Tantalum Capacitor 1.0µF 16V 10%
Size = 1210
4
CS3, CB, CO1, CO2
Tantalum Capacitor 220µF 16V 10%
Size = 7343
2
COUT1, COUT2
Resistor 1.5kΩ 1/10W 1%
Size = 0805
2
RL1, RL2
Resistor 20kΩ 1/10W 1%
Size = 0805
10
RIN1, RIN2, RF1, RF2, Rl1, Rl2, RBS1, RBS2,
RDOCK1, RDOCK2
Resistor 100kΩ 1/10W 1%
Size = 0805
2
RS, RPU
Resistor 120kΩ 1/10W 1%
Size = 0805
2
RBEEP1, RBEEP2
Resistor 1MΩ 1/10W 1%
Size = 0805
1
RV
Jumper Header Vertical Mount
0.100” spacing
1
J1 (Docking RT LF)
RCA Jack PCB mount
3
J2 (LeftIn), J3 (Beep In), J4 (Right In)
Banana Jack, Black
3
J5B (GND), J6A (Right Out -), J7A (Left Out -)
Banana Jack, Red
3
J5A (VDD), J6B (Right Out +), J7B (Left Out +)
Stereo Headphone Jack W/Switch
1
J8
Single Turn Potentiometer 100kΩ 20%
1
J9
Jumper Header Vertical Mount
0.100” spacing 3x4
1
Mute, SD, Gain, Mode
Jumper Header Vertical Mount
0.100” spacing 1x3
1
DC IN
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LM4838
SNAS131F – JANUARY 2001 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F
•
36
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 35
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM4838MTEX/NOPB
ACTIVE
HTSSOP
PWP
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM4838MTE
LM4838MTX/NOPB
ACTIVE
TSSOP
PW
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LM4838MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM4838MTEX/NOPB
HTSSOP
PWP
28
2500
330.0
16.4
LM4838MTX/NOPB
TSSOP
PW
28
2500
330.0
16.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.8
10.2
1.6
8.0
16.0
Q1
6.8
10.2
1.6
8.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM4838MTEX/NOPB
HTSSOP
PWP
28
2500
367.0
367.0
35.0
LM4838MTX/NOPB
TSSOP
PW
28
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0028A
PowerPAD TM - 1.1 mm max height
SCALE 1.800
PLASTIC SMALL OUTLINE
C
6.6
TYP
6.2
A
SEATING PLANE
PIN 1 ID
AREA
28
1
9.8
9.6
NOTE 3
0.1 C
26X 0.65
2X
8.45
14
B
15
4.5
4.3
NOTE 4
0.30
0.19
0.1
C A
28X
1.1 MAX
B
0.20
TYP
0.09
SEE DETAIL A
3.15
2.75
0.25
GAGE PLANE
5.65
5.25
THERMAL
PAD
0 -8
0.10
0.02
0.7
0.5
(1)
DETAIL A
TYPICAL
4214870/A 10/2014
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-153, variation AET.
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EXAMPLE BOARD LAYOUT
PWP0028A
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
(3)
SOLDER
MASK
OPENING
28X (1.5)
28X (0.45)
SOLDER MASK
DEFINED PAD
1
28X (0.45)
28X (1.3)
28
26X
(0.65)
SYMM
(5.5)
(9.7)
SOLDER
MASK
OPENING
(1.3) TYP
14
15
( 0.2) TYP
VIA
(1.3)
SEE DETAILS
SYMM
(0.9) TYP
METAL COVERED
BY SOLDER MASK
(0.65) TYP
(5.8)
(6.1)
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214870/A 10/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
PWP0028A
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.127 THICK
STENCIL
28X (1.5)
28X (0.45)
METAL COVERED
BY SOLDER MASK
1
28X (1.3)
28
26X (0.65)
28X (0.45)
(5.5)
BASED ON
0.127 THICK
STENCIL
SYMM
14
15
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SYMM
(5.8)
(6.1)
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.127
0.152
0.178
3.55 X 6.37
3.0 X 5.5 (SHOWN)
2.88 X 5.16
2.66 X 4.77
4214870/A 10/2014
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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