TI1 TLC27M4CPWLE Lincmos precision quad operational amplifier Datasheet

TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
LinCMOS™ PRECISION QUAD OPERATIONAL AMPLIFIERS
Check for Samples: TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
FEATURES
1
•
•
•
•
•
•
•
•
•
•
1OUT
1IN–
1IN +
VDD
2IN +
2IN–
2OUT
13
3
12
4
11
5
10
6
9
7
8
3 2
1IN +
NC
VDD
NC
2IN +
4OUT
4IN –
4IN +
GND
3IN +
3IN –
3OUT
4
1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4IN +
NC
GND
NC
3IN +
NC – No internal connection
DISTRIBUTION OF TLC27M9
INPUT OFFSET VOLTAGE
40
35
Percentage of Units – %
The extremely high input impedance, low bias
currents, make these cost-effective devices ideal for
applications that have previously been reserved for
general-purpose bipolar products, but with only a
fraction of the power consumption.
14
2
FK PACKAGE
(TOP VIEW)
DESCRIPTION
The TLC27M4 and TLC27M9 quad operational
amplifiers combine a wide range of input offset
voltage grades with low offset voltage drift, high input
impedance, low noise, and speeds comparable to
that of general-purpose bipolar devices. These
devices use Texas Instruments silicon-gate
LinCMOS™ technology, which provides offset voltage
stability far exceeding the stability available with
conventional metal-gate processes.
1
1IN –
1OUT
NC
4OUT
4IN –
•
D, J, N, OR PW PACKAGE
(TOP VIEW)
Trimmed Offset Voltage
– TLC27M9 . . . 900 µV Max at TA = 25°C,
VDD = 5 V
Input Offset Voltage Drift . . . Typically
0.1 µV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over Specified
Temperature Range:
– 0°C to 70°C . . . 3 V to 16 V
– –40°C to 85°C . . . 4 V to 16 V
– –55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix Types)
Low Noise . . . Typically 32 nV/√Hz
at f = 1 kHz
Low Power . . . Typically 2.1 mW at
TA = 25°C, VDD = 5 V
Output Voltage Range Includes Negative Rail
High Input Impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also Available
in Tape and Reel
Designed-In Latch-Up Immunity
2IN –
2OUT
NC
3OUT
3IN –
•
2
30
301 Units Tested From 2 Wafer Lots
VDD = 5 V
TA = 25°C
N Package
25
20
15
10
5
0
– 1200
– 600
0
600
1200
VIO – Input Offset Voltage – μV
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1987–2012, Texas Instruments Incorporated
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
Four offset voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC27M4 (10 mV)
to the high-precision TLC27M9 (900 μV). These advantages, in combination with good common-mode rejection
and supply voltage rejection, make these devices a good choice for new state-of-the-art designs as well as for
upgrading existing designs.
In general, many features associated with bipolar technology are available on LinCMOS™ operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27M4 and
TLC27M9. The devices also exhibit low voltage single-supply operation, and low power consumption, making
them ideally suited for remote and inaccessible battery-powered applications. The common-mode input voltage
range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC27M4 and TLC27M9 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015; however, care should be exercised in
handling these devices, as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for
operation from –40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TA
VIOmax
AT 25°C
900 µV
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
(1)
2
SMALL
OUTLINE
(D) (1)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW) (1)
CHIP
FORM
(Y)
TLC27M9CD
—
—
TLC27M9CN
—
—
2 mV
TLC27M4BCD
—
—
TLC27M4BCN
—
—
5 mV
TLC27M4ACD
—
—
TLC27M4ACN
10 mV
TLC27M4CD
—
—
TLC27M4CN
TLC27M4CPW
—
—
900 µV
TLC27M9ID
—
—
TLC27M9IN
—
—
2 mV
TLC27M4BID
—
—
TLC27M4BIN
—
—
5 mV
TLC27M4AID
—
—
TLC27M4AIN
—
—
10 mV
TLC27M4ID
—
—
TLC27M4IN
TLC27M41PW
—
900 µV
TLC27M9MD
TLC27M9MFK
TLC27M9MJ
TLC27M9MN
—
—
10 mV
TLC27M4MD
TLC27M4MFK
TLC27M4MJ
TLC27M4MN
—
—
TLC27M4Y
The D and PW package is available taped and reeled. Add R suffix to the device type (e.g., TLC279CDR).
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
EQUIVALENT SCHEMATIC (EACH AMPLIFIER)
VDD
P3
P4
R6
R1
R2
N5
IN –
P5
P1
P6
P2
IN +
R5
C1
OUT
N3
N1
R3
N2
D1
N4
R4
D2
N6
N7
R7
GND
Copyright © 1987–2012, Texas Instruments Incorporated
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Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
3
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
TLC27M4Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC27M4C. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
VDD
(14)
(13)
(12) (11)
(10)
(9)
(8)
(4)
(3)
+
1IN +
1IN–
(1)
1OUT
(2)
–
+
(7)
2OUT
–
(10)
68
+
3IN +
(6)
2IN +
2IN–
(8)
3OUT
(9)
–
3IN–
4OUT
(5)
+
(14)
–
(12)
(13)
4IN +
4IN–
(11)
(1)
(2)
(3)
(4)
108
(5)
(6)
(7)
GND
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 ´ 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
4
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VDD
VALUE
UNIT
18
V
(2)
Differential input voltage, VID (3)
±VDD
Input voltage range, VI (any input)
–0.3 V to VDD
Input current, II
±5
mA
Output current, lO (each output)
±30
mA
Total current into VDD
45
mA
Total current out of GND
45
mA
Duration of short-circuit current at (or below) 25°C
(4)
unlimited
Continuous total dissipation
See Dissipation Rating Table
C suffix
0 to 70
°C
I suffix
–40 to 85
°C
M suffix
–55 to 125
°C
–65 to 150
°C
Case temperature for 60 seconds: FK package
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
300
°C
Operating free-air temperature, TA
Storage temperature range
(1)
(2)
(3)
(4)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground.
Differential voltages are at IN+ with respect to IN –.
The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded (see application section).
DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
950 mW
7.6 mW/°C
608 mW
494 mW
—
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
J
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
N
1575 mW
12.6 mW/°C
1008 mW
819 mW
—
PW
700 mW
5.6 mW/°C
448 mW
—
—
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
3
16
4
16
4
16
VDD = 5 V
–0.2
3.5
–0.2
3.5
0
3.5
VDD = 10 V
–0.2
8.5
–0.2
8.5
0
8.5
0
70
–40
85
–55
125
Supply voltage, VDD
Common mode input voltage, VIC
Operating free-air temperature, TA
Copyright © 1987–2012, Texas Instruments Incorporated
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UNIT
V
V
°C
5
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC27M4C
TLC27M4AC
TLC27M4BC
TLC27M9C
TA (1)
MIN
VO = 1.4 V,
RS = 50 Ω,
TLC27M4C
VIO
VIC = 0,
RL = 100 kΩ
VIC = 0,
RL = 100 kΩ
Full range
TLC274BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (2)
VO = 2.5 V,
VIC = 2.5 V
IIB
Input bias current (2)
VO = 2.5 V,
VIC = 2.5 V
VOH
High-level output voltage
VOL
Low-level output voltage
Large-signal differential voltage
amplification
AVD
CMRR
kSVR
IDD
(1)
(2)
(3)
6
Common-mode input voltage range
Common-mode rejection ratio
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
Supply current (four amplifiers)
VID = –100 mV,
VO = 0.25 V to 2 V,
RL = 100 kΩ
IOL = 0
RL = 100 kΩ
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
10
12
0.9
5
mV
6.5
25°C
250 2000
3000
25°C
210
Full range
900
µV
1500
25°C to 70°C
1.7
25°C
0.1
70°C
7
25°C
0.6
70°C
40
25°C
–0.2
to
4
Full range
–0.2
to
3.5
25°C
3.2
3.9
0°C
3
3.9
70°C
3
4
(3)
VID = 100 mV,
1.1
25°C
VO = 1.4 V,
RS = 50 Ω,
TLC279C
TYP MAX
Full range
TLC27M4AC
Input offset voltage
VICR
25°C
UNIT
µV/°C
300
600
–0.3
to
4.2
pA
pA
V
V
V
25°C
0
50
0°C
0
50
70°C
0
50
25°C
25
170
0°C
15
200
70°C
15
140
25°C
65
91
0°C
60
91
70°C
60
92
25°C
70
93
0°C
60
92
70°C
60
mV
V/mV
dB
dB
94
25°C
420 1120
0°C
500 1280
70°C
340
µA
880
Full range is 0°C to 70°C.
The typical values of input bias current and input offset current below 5 pA were determined mathematically.
This range also applies to each input individually.
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC27M4C
TLC27M4AC
TLC27M4BC
TLC27M9C
TA (1)
MIN
VO = 1.4 V,
RS = 50 Ω,
TLC27M4C
VIO
VIC = 0,
RL = 100 kΩ
VIC = 0,
RL = 100 kΩ
Full range
TLC274BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (2)
VO = 5 V,
VIC = 5 V
IIB
Input bias current (2)
VO = 5 V,
VIC = 5 V
VOH
Low-level output voltage
Large-signal differential voltage
amplification
AVD
CMRR
kSVR
(1)
(2)
(3)
Common-mode rejection ratio
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
Supply current (four amplifiers)
VID = 100 mV,
VID = –100 mV,
VO = 1 V to 6 V,
RL = 100 kΩ
IOL = 0
RL = 100 kΩ
VIC = VICRmin
VDD = 5 V to 10 V, VO = 1.4 V
VO = 5 V,
No load
VIC = 5 V,
10
12
0.9
5
mV
6.5
25°C
260 2000
3000
25°C
220 1200
Full range
µV
1900
25°C to 70°C
2.1
25°C
0.1
70°C
7
25°C
0.7
70°C
50
25°C
–0.2
to
9
Full range
–0.2
to
8.5
(3)
High-level output voltage
VOL
IDD
Common-mode input voltage range
1.1
25°C
VO = 1.4 V,
RS = 50 Ω,
TLC279C
TYP MAX
Full range
TLC27M4AC
Input offset voltage
VICR
25°C
UNIT
µV/°C
300
600
–0.3
to
9.2
pA
pA
V
V
25°C
8
8.7
0°C
7.8
8.7
70°C
7.8
8.7
V
25°C
0
50
0°C
0
50
70°C
0
50
25°C
25
275
0°C
15
320
70°C
15
230
25°C
65
94
0°C
60
94
70°C
60
94
25°C
70
93
0°C
60
92
70°C
60
mV
V/mV
dB
dB
94
25°C
570 1200
0°C
690 1600
70°C
440 1120
µA
Full range is 0°C to 70°C.
The typical values of input bias current and input offset current below 5 pA were determined mathematically.
This range also applies to each input individually.
Copyright © 1987–2012, Texas Instruments Incorporated
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7
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC27M4I
TLC27M4AI
TLC27M4BI
TLC27M9I
TA (1)
MIN
VO = 1.4 V,
RS = 50 Ω,
TLC27M4I
VIO
VIC = 0,
RL = 100 kΩ
VIC = 0,
RL = 100 kΩ
Full range
TLC27M4BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (2)
VO = 2.5 V,
VIC = 2.5 V
IIB
Input bias current (2)
VO = 2.5 V,
VIC = 2.5 V
VOH
High-level output voltage
VOL
Low-level output voltage
Large-signal differential voltage
amplification
AVD
CMRR
kSVR
IDD
(1)
(2)
(3)
8
Common-mode input voltage range
Common-mode rejection ratio
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
Supply current (four amplifiers)
VID = –100 mV,
VO = 0.25 V to 2 V,
RL = 100 kΩ
IOL = 0
RL = 100 kΩ
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
10
13
0.9
5
mV
6.5
25°C
250 2000
3000
25°C
210
Full range
900
µV
2000
25°C to 85°C
1.7
25°C
0.1
85°C
24 1000
µV/°C
25°C
0.6
85°C
200 2000
25°C
–0.2
to
4
Full range
–0.2
to
3.5
25°C
3.2
3.9
–40°C
3
3.9
85°C
3
4
(3)
VID = 100 mV,
1.1
25°C
VO = 1.4 V,
RS = 50 Ω,
TLC27M9I
TYP MAX
Full range
TLC27M4AI
Input offset voltage
VICR
25°C
UNIT
–0.3
to
4.2
pA
pA
V
V
V
25°C
0
50
–40°C
0
50
85°C
0
50
25°C
25
170
–40°C
15
270
85°C
15
130
25°C
65
91
–40°C
60
90
85°C
60
90
25°C
70
93
–40°C
60
91
85°C
60
mV
V/mV
dB
dB
94
25°C
420 1120
–40°C
630 1600
85°C
320
µA
800
Full range is –40°C to 85°C.
The typical values of input bias current and input offset current below 5 pA were determined mathematically.
This range also applies to each input individually.
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC27M4I
TLC27M4AI
TLC27M4BI
TLC27M9I
TA (1)
MIN
VO = 1.4 V,
RS = 50 Ω,
TLC27M4I
VIO
VIC = 0,
RL = 100 kΩ
VIC = 0,
RL = 100 kΩ
Full range
TLC27M4BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (2)
VO = 5 V,
VIC = 5 V
IIB
Input bias current (2)
VO = 5 V,
VIC = 5 V
VOH
Low-level output voltage
Large-signal differential voltage
amplification
AVD
CMRR
kSVR
(1)
(2)
(3)
Common-mode rejection ratio
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
Supply current (four amplifiers)
VID = 100 mV,
VID = –100 mV,
VO = 1 V to 6 V,
RL = 100 kΩ
IOL = 0
RL = 100 kΩ
VIC = VICRmin
VDD = 5 V to 10 V, VO = 1.4 V
VO = 5 V,
No load
VIC = 5 V,
10
13
0.9
5
mV
7
25°C
260 2000
3500
25°C
220 1200
Full range
µV
2900
25°C to 85°C
2.1
25°C
0.1
85°C
26 1000
µV/°C
25°C
0.7
85°C
220 2000
25°C
–0.2
to
9
Full range
–0.2
to
8.5
(3)
High-level output voltage
VOL
IDD
Common-mode input voltage range
1.1
25°C
VO = 1.4 V,
RS = 50 Ω,
TLC27M9I
TYP MAX
Full range
TLC27M4AI
Input offset voltage
VICR
25°C
UNIT
–0.3
to
9.2
pA
pA
V
V
25°C
8
8.7
–40°C
7.8
8.7
85°C
7.8
8.7
V
25°C
0
50
–40°C
0
50
85°C
0
50
25°C
25
275
–40°C
15
390
85°C
15
220
25°C
65
94
–40°C
60
93
85°C
60
94
25°C
70
93
–40°C
60
91
85°C
60
mV
V/mV
dB
dB
94
25°C
570 1200
–40°C
900 1800
85°C
410 1040
µA
Full range is –40°C to 85°C.
The typical values of input bias current and input offset current below 5 pA were determined mathematically.
This range also applies to each input individually.
Copyright © 1987–2012, Texas Instruments Incorporated
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9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC27M4M
TLC27M9M
TA (1)
MIN
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
TLC27M9M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
Input offset voltage
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (2)
VICR
VOH
Low-level output voltage
Large-signal differential voltage
amplification
AVD
CMRR
kSVR
(1)
(2)
(3)
10
Common-mode input voltage range
High-level output voltage
VOL
IDD
VO = 2.5 V,
Input bias current (2)
IIB
25°C
TLC27M4M
Common-mode rejection ratio
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
Supply current (four amplifiers)
VO = 2.5 V,
VIC = 2.5 V
VIC = 2.5 V
1.1
VID = –100 mV,
VO = 0.25 V to 2 V,
RL = 100 kΩ
IOL = 0
RL = 100 kΩ
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
10
12
25°C
210
900
3750
25°C to 125°C
1.7
25°C
0.1
125°C
1.4
25°C
0.6
85°C
9
25°C
0
to
4
Full range
0
to
3.5
(3)
VID = 100 mV,
UNIT
TYP MAX
mV
µV
µV/°C
pA
15
nA
pA
35
–0.3
to
4.2
nA
V
V
25°C
3.2
3.9
–55°C
3
3.9
125°C
3
4
V
25°C
0
50
–55°C
0
50
125°C
0
50
25°C
25
170
–55°C
15
270
125°C
15
120
25°C
65
91
–55°C
60
89
125°C
60
91
25°C
70
93
–55°C
60
91
125°C
60
94
mV
V/mV
dB
dB
25°C
420 1120
–55°C
680 1760
125°C
280
µA
720
Full range is –55°C to 125°C.
The typical values of input bias current and input offset current below 5 pA were determined mathematically.
This range also applies to each input individually.
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Copyright © 1987–2012, Texas Instruments Incorporated
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TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC27M4M
TLC27M9M
TA (1)
MIN
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
TLC27M9M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 100 kΩ
Full range
Input offset voltage
αVIO
Average temperature coefficient of input
offset voltage
IIO
Input offset current (2)
VO = 5 V,
Input bias current (2)
IIB
25°C
TLC27M4M
VO = 5 V,
VIC = 5 V
VIC = 5 V
1.1
Common-mode input voltage range
25°C
220 1200
4300
25°C to 125°C
2.1
25°C
0.1
125°C
1.8
25°C
0.7
125°C
10
0
to
9
(3)
Full range
VOH
High-level output voltage
VOL
Low-level output voltage
Large-signal differential voltage
amplification
AVD
CMRR
kSVR
IDD
(1)
(2)
(3)
Common-mode rejection ratio
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
Supply current (four amplifiers)
VID = 100 mV,
VID = –100 mV,
VO = 1 V to 6 V,
RL = 100 kΩ
IOL = 0
RL = 100 kΩ
VIC = VICRmin
VDD = 5 V to 10 V, VO = 1.4 V
VO = 5 V,
No load
VIC = 5 V,
10
12
25°C
VICR
UNIT
TYP MAX
mV
µV
µV/°C
pA
15
nA
pA
35
–0.3
to
9.2
nA
V
–0.2
to
8.5
V
25°C
8
8.7
–55°C
7.8
8.6
125°C
7.8
8.8
V
25°C
0
50
–55°C
0
50
125°C
0
50
25°C
25
275
–55°C
15
420
125°C
15
190
25°C
65
94
–55°C
60
93
125°C
60
93
25°C
70
93
–55°C
60
91
125°C
60
94
mV
V/mV
dB
dB
25°C
570 1200
–55°C
980 2000
125°C
360
µA
960
Full range is –55°C to 70°C.
The typical values of input bias current and input offset current below 5 pA were determined mathematically.
This range also applies to each input individually.
Copyright © 1987–2012, Texas Instruments Incorporated
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11
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC27M4Y
MIN
MAX
1.1
10
UNIT
VIO
Input offset voltage
VO = 1.4 V,
RS = 50 Ω,
αVIO
Temperature coefficient of input offset
voltage
TA = 25°C to 70°C
IIO
Input offset current (1)
VO = 2.5 V,
IIB
Input bias current (1)
VO = 2.5 V,
VICR
Common-mode input voltage range (2)
VOH
High-level output voltage
VID = 100 mV,
RL = 100 kΩ
VOL
Low-level output voltage
VID = –100 mV,
IOL = 0
AVD
Large-signal differential voltage
amplification
VO = 0.25 V to 2 V, RL= 100 kΩ
25
170
V/mV
CMRR
Common-mode rejection ratio
VIC = VICRmin
65
91
dB
kSVR
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
VDD = 5 V to 10 V,
VO = 1.4 V
70
93
dB
IDD
Supply current (four amplifiers)
VO = 2.5 V,
No load
VIC = 2.5 V,
(1)
(2)
VIC = 0,
RL = 100 kΩ
TYP
mV
1.7
µV/°C
VIC = 2.5 V
0.1
pA
VIC = 2.5 V
0.6
pA
–0.2
to
4
–0.3
to
4.2
V
3.2
3.9
V
0
420
50
1120
mV
µA
The typical values of input bias current and input offset current below 5 pA were determined mathematically
This range also applies to each input individually.
ELECTRICAL CHARACTERISTICS
VDD = 10 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VO = 1.4 V,
RS = 50 Ω,
αVIO
Temperature coefficient of input offset
voltage
TA = 25°C to 70°C
IIO
Input offset current (1)
VO = 5 V,
VIC = 5 V
VO = 5 V,
VIC = 5 V
IIB
Input bias current
(1)
VIC = 0,
RL = 100 kΩ
VICR
Common-mode input voltage range (2)
VOH
High-level output voltage
VID = 100 mV,
RL = 100 kΩ
VOL
Low-level output voltage
VID = –100 mV,
IOL = 0
AVD
Large-signal differential voltage
amplification
VO = 1 V to 6 V,
RL= 100 kΩ
CMRR
Common-mode rejection ratio
VIC = VICRmin
kSVR
Supply-voltage rejection ratio
(ΔVDD/ΔVIO)
VDD = 5 V to 10 V,
VO = 1.4 V
IDD
Supply current (four amplifiers)
VO = 5 V,
No load
VIC = 5 V,
(1)
(2)
12
TLC27M4Y
MIN
TYP
MAX
1.1
10
UNIT
mV
1.7
µV/°C
0.1
pA
0.6
pA
–0.2
to
9
–0.3
to
9.2
V
8
8.7
0
V
50
mV
25
275
V/mV
65
94
dB
70
93
dB
570
1200
µA
The typical values of input bias current and input offset current below 5 pA were determined mathematically.
This range also applies to each input individually.
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27M4C
TLC27M4AC
TLC27M4BC
TLC27M9C
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
BOM
Maximum output-swing
bandwidth
VO = VOH,
RL = 100 kΩ,
B1
φm
Unity-gain bandwidth
VI = 10 mV,
See Figure 3
VI = 10 mV,
CL = 20 pF,
Phase margin
RS = 20 Ω
CL = 20 pF,
See Figure 1
CL = 20 pF
f = B1,
See Figure 3
TYP
25°C
0.43
0°C
0.46
70°C
0.36
25°C
0.40
0°C
0.43
70°C
0.34
25°C
32
25°C
55
0°C
60
70°C
50
25°C
525
0°C
610
70°C
400
25°C
40°
0°C
41°
70°C
39°
UNIT
MAX
V/µs
nV/√Hz
kHz
kHz
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27M4C
TLC27M4AC
TLC27M4BC
TLC27M9C
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
BOM
Maximum output-swing
bandwidth
VO = VOH,
RL = 100 kΩ,
B1
φm
Unity-gain bandwidth
Phase margin
VI = 10 mV,
See Figure 3
VI = 10 mV,
CL = 20 pF,
Copyright © 1987–2012, Texas Instruments Incorporated
RS = 20 Ω
CL = 20 pF,
See Figure 1
CL = 20 pF
f = B1,
See Figure 3
TYP
25°C
0.62
0°C
0.67
70°C
0.51
25°C
0.56
0°C
0.61
70°C
0.46
25°C
32
25°C
35
0°C
40
70°C
30
25°C
635
0°C
710
70°C
510
25°C
43°
0°C
44°
70°C
42°
UNIT
MAX
V/µs
nV/√Hz
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kHz
kHz
13
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27M4I
TLC27M4AI
TLC27M4BI
TLC27M9I
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
BOM
Maximum output-swing
bandwidth
VO = VOH,
RL = 100 kΩ,
B1
φm
Unity-gain bandwidth
VI = 10 mV,
See Figure 3
VI = 10 mV,
CL = 20 pF,
Phase margin
TYP
25°C
0.43
–40°C
0.51
85°C
0.35
25°C
0.40
–40°C
0.48
85°C
0.32
RS = 20 Ω
25°C
32
25°C
55
CL = 20 pF,
See Figure 1
–40°C
75
CL = 20 pF
f = B1,
See Figure 3
85°C
45
25°C
525
–40°C
770
85°C
370
25°C
40°
–40°C
43°
85°C
38°
UNIT
MAX
V/µs
nV/√Hz
kHz
kHz
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27M4I
TLC27M4AI
TLC27M4BI
TLC27M9I
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
BOM
Maximum output-swing
bandwidth
VO = VOH,
RL = 100 kΩ,
B1
φm
14
Unity-gain bandwidth
VI = 10 mV,
See Figure 3
VI = 10 mV,
CL = 20 pF,
Phase margin
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TYP
25°C
0.62
–40°C
0.77
85°C
0.47
25°C
0.56
–40°C
0.70
85°C
0.44
RS = 20 Ω
25°C
32
25°C
35
CL = 20 pF,
See Figure 1
–40°C
45
85°C
25
CL = 20 pF
f = B1,
See Figure 3
25°C
635
–40°C
880
85°C
480
25°C
43°
–40°C
46°
85°C
41°
UNIT
MAX
V/µs
nV/√Hz
kHz
kHz
Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27M4M
TLC27M9M
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
BOM
Maximum output-swing
bandwidth
VO = VOH,
RL = 100 kΩ,
B1
φm
Unity-gain bandwidth
VI = 10 mV,
See Figure 3
VI = 10 mV,
CL = 20 pF,
Phase margin
RS = 20 Ω
CL = 20 pF,
See Figure 1
CL = 20 pF
f = B1,
See Figure 3
TYP
25°C
0.43
–55°C
0.54
125°C
0.29
25°C
0.40
–55°C
0.50
125°C
0.28
25°C
32
25°C
56
–55°C
80
125°C
40
25°C
525
–55°C
850
125°C
330
25°C
40°
–55°C
44°
125°C
36°
UNIT
MAX
V/µs
nV/√Hz
kHz
kHz
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27M4M
TLC27M9M
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
BOM
Maximum output-swing
bandwidth
VO = VOH,
RL = 100 kΩ,
φm
Unity-gain bandwidth
Phase margin
Copyright © 1987–2012, Texas Instruments Incorporated
0.62
–55°C
0.81
125°C
0.38
25°C
0.56
–55°C
0.73
125°C
0.35
25°C
32
25°C
35
CL = 20 pF,
See Figure 1
–55°C
50
125°C
20
VI = 10 mV,
See Figure 3
VI = 10 mV,
CL = 20 pF,
25°C
RS = 20 Ω
CL = 20 pF
B1
TYP
f = B1,
See Figure 3
25°C
635
–55°C
960
125°C
440
25°C
43°
–55°C
47°
125°C
39°
UNIT
MAX
V/µs
nV/√Hz
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kHz
kHz
15
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC27M4Y
MIN
TYP
MAX
UNIT
0.43
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 1 V
SR
VIPP = 2.5 V
0.40
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω
32
nV/√Hz
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
55
kHz
B1
Unity-gain bandwidth
VI = 10 mV,
See Figure 3
CL = 20 pF
525
kHz
φm
Phase margin
VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
40°
V/µs
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 10 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC27M4Y
MIN
TYP
MAX
UNIT
0.62
Slew rate at unity gain
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
VIPP = 1 V
SR
VIPP = 5.5 V
0.56
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω
32
nV/√Hz
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 100 kΩ,
CL = 20 pF,
See Figure 1
35
kHz
B1
Unity-gain bandwidth
VI = 10 mV,
See Figure 3
CL = 20 pF
635
kHz
φm
Phase margin
VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 3
43°
16
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V/µs
Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
PARAMETER MEASUREMENT INFORMATION
Single-Supply versus Split-Supply Test Circuits
Because the TLC27M4 and TLC27M9 are optimized for single-supply operation, circuit configurations used for
the various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either
circuit gives the same result.
VDD
VDD+
–
–
VO
VO
+
CL
+
VI
VI
RL
CL
RL
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
2 kΩ
2 kΩ
V DD+
VDD
20 Ω
–
–
VO
1/2 VDD
VO
+
+
20 Ω
20 Ω
20 Ω
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 2. Noise-Test Circuit
10 kΩ
10 kΩ
VDD+
VO
–
+
VI
VI
VO
+
1/2 VDD
–
VDD
100 Ω
100 Ω
CL
CL
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
Copyright © 1987–2012, Texas Instruments Incorporated
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17
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Input Bias Current
Because of the high input impedance of the TLC27M4 and TLC27M9 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature is
typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are
offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test socket.
One word of caution—many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current; the voltage
drop across the series resistor is measured and the bias current is calculated. This method requires that a device
be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not feasible
using this method.
7
1
V = VIC
8
14
Figure 4. Isolation Metal Around Device Inputs
(J and N packages)
Low-Level Output Voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well as
the differential input voltage level. When attempting to correlate low-level output readings with those quoted in
the electrical specifications, these two conditions should be observed. If conditions other than these are to be
used, please refer to Figure 14 through Figure 19 in the Typical Characteristics of this data sheet.
Input Offset Voltage Temperature Coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
18
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SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
PARAMETER MEASUREMENT INFORMATION (continued)
Full-Power Response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output, while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The fullpeak response is defined as the maximum output frequency, without regard to distortion, above which full peakto-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in
this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude.
The frequency is then increased until the maximum peak-to-peak output can no longer be maintained (Figure 5).
A square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak
output is reached.
(a) f = 1 kHz
(b) 1 kHz < f < BOM
(c) f = BOM
(d) f > BOM
Figure 5. Full-Power-Response Output Signal
Test Time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-testtime environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices and
require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with
reduced supply levels and lower temperatures.
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
αVIO
Temperature coefficient of input offset voltage
Distribution
High-level output voltage
vs High-level output current
vs Supply voltage
vs Free-air temperature
10, 11
12
13
VOL
Low-level output voltage
vs
vs
vs
vs
14, 15
16
17
18, 19
AVD
Differential voltage amplification
vs Supply voltage
vs Free-air temperature Free
vs Frequency
IIB
Input bias current
vs Free-air temperature
22
IIO
Input offset current
vs Free-air temperature
22
VIC
Common-mode input voltage
vs Supply voltage
23
IDD
Supply current
vs Supply voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Supply voltage
vs Free-air temperature
26
27
VOH
6, 7
8, 9
Common-mode input voltage
Differential input voltage
Free-air temperature
Low-level output current
20
21
32, 33
Normalized slew rate
vs Free-air temperature
28
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
29
B1
Unity gain bandwidth
vs Free-air temperature Free
vs Supply voltage
30
31
Phase shift
vs Frequency
φm
Phase margin
vs Supply voltage
vs Free-air temperature Free
vs Load capacitance
34
35
36
Vn
Equivalent input noise voltage
vs Frequency
37
20
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SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC27M4
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC27M4
INPUT OFFSET VOLTAGE
60
60
612 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
TA = 25°C
N Package
50
Percentage of Units – %
Percentage of Units – %
50
40
30
20
–5
–4
–3 –2 –1
0
1
2
3
VIO – Input Offset Voltage – mV
4
20
5
–5
–4
–3 –2 –1
0
1
2
3
VIO – Input Offset Voltage – mV
4
Figure 6.
Figure 7.
DISTRIBUTION OF TLC27M4 AND TLC27M9
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC27M4 AND TLC27M9
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
5
60
60
224 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
N Package
Outliers:
(1) 33.0 μV/C
50
Percentage of Units – %
Percentage of Units – %
30
0
0
40
40
10
10
50
612 Amplifiers Tested From 4 Wafer Lots
VDD = 10 V
TA = 25°C
N Package
30
20
40
224 Amplifiers Tested From 6 Wafer Lots
VDD = 10 V
TA = 25°C to 125°C
N Package
Outliers:
(1) 34.6 μV/°C
30
20
10
10
0
– 10 – 8 –6 –4 –2
0
2
4
6
8
α VIO – Temperature Coefficient – μV/°C
Figure 8.
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10
0
– 10 –8 –6 –4 – 2 0
2
4
6
8
α VIO – Temperature Coefficient – μV/°C
10
Figure 9.
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TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
16
VID = 100 mV
TA = 25°C
VID = 100 mV
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
5
4
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
2
1
0
0
–2
–4
–6
–8
IOH – High-Level Output Current – mA
12
10
8
VDD = 10 V
6
4
2
0
–5
– 10 – 15 – 20 – 25 – 30 – 35
IOH – High-Level Output Current – mA
Figure 11.
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
– 40
VDD –1.6
IOH = – 5 mA
VID = 100 mV
RL = 100 kΩ
14
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
TA = 25°C
VDD = 16 V
Figure 10.
TA = 25°C
12
10
8
6
4
2
0
0
2
4
6
8
10
12
VDD – Supply Voltage – V
Figure 12.
22
14
0
– 10
16
(1)
(1)
14
16
VDD –1.7
VID = 100 mA
VDD = 5 V
VDD –1.8
VDD –1.9
VDD –2
VDD = 10 V
VDD –2.1
VDD –2.2
VDD –2.3
VDD –2.4
– 75
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 13.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
500
VDD = 5 V
IOL = 5 mA
TA = 25°C
650
VOL – Low-Level Output Voltage – mV
VOL – Low-Level Output Voltage – mV
700
600
550
VID = – 100 mV
500
450
400
VID = – 1 V
350
0
0.5
1
1.5
2
2.5
3
3.5
VIC – Common-Mode Input Voltage – V
VDD = 10 V
IOL = 5 mA
TA = 25°C
450
400
VID = – 100 mV
VID = – 1 V
350
VID = – 2.5 V
300
250
300
4
0
Figure 15.
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
10
900
VIC = |VID/2|
700
TA = 25°C
600
500
VDD = 5 V
400
300
VDD = 10 V
200
100
0
0
–1
–2 –3 –4 –5 –6 –7 –8
VID – Differential Input Voltage – V
Figure 16.
–9 – 10
VOL – Low-Level Output Voltage – mV
IOL = 5 mA
VOL – Low-Level Output Voltage – mV
1
2
4
6
8
3
5
7
9
VIC – Common-Mode Input Voltage – V
Figure 14.
800
(1)
(1)
800
IOL = 5 mA
VID = – 1 V
VIC = 0.5 V
700
VDD = 5 V
600
500
400
VDD = 10 V
300
200
100
0
– 75
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 17.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1
3
VOL – Low-Level Output Voltage – V
0.8
VOL – Low-Level Output Voltage – V
VID = – 1 V
VIC = 0.5 V
TA = 25°C
0.9
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
0.3
0.2
0.1
0
1
2
3
4
5
6
7
IOL – Low-Level Output Current – mA
VDD = 16 V
2
VDD = 10 V
1.5
1
0.5
0
Figure 19.
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
RL = 100 kΩ
0°C
350
25°C
300
70°C
250
85°C
200
TA = 125°C
150
100
50
RL = 100 kΩ
450
– 40°C
400
30
500
AVD
AVD – Large-Signal Differential
Voltage Amplification – V/mV
450
5
10
15
20
25
IOL – Low-Level Output Current – mA
Figure 18.
TA = – 55°C
AVD
AVD – Large-Signal Differential
Voltage Amplification – V/mV
2.5
8
500
400
350
VDD = 10 V
300
250
200
150
VDD = 5 V
100
50
0
0
2
4
6
8
10
12
VDD – Supply Voltage – V
Figure 20.
24
VID = – 1 V
VIC = 0.5 V
TA = 25°C
0
0
(1)
(1)
14
16
0
– 75
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 21.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
10000
VDD = 10 V
VIC = 5 V
See Note A
1000
IIB
100
IIO
10
1
0.1
(1)
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
16
TA = 25°C
VIC – Common-Mode Input Voltage – V
I IB and I IO – Input Bias and Offset Currents – pA
TYPICAL CHARACTERISTICS
14
12
10
8
6
4
2
0
25
45
65
85
105
TA – Free-Air Temperature – °C
0
125
2
4
6
8
10
12
VDD – Supply Voltage – V
14
16
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 22.
Figure 23.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1600
1000
VO = VDD/2
No Load
1400
VO = VDD /2
No Load
900
TA = – 55°C
– 40°C
1000
0°C
800
25°C
600
70°C
400
TA = 125°C
200
700
600
VDD = 10 V
500
400
VDD = 5 V
300
200
100
0
0
2
4
6
8
10
12
VDD – Supply Voltage – V
Figure 24.
(1)
I DD – Supply Current – μA
I DD – Supply Current – μA
800
1200
14
16
0
– 75
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 25.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS
(1)
SLEW RATE
vs
SUPPLY VOLTAGE
0.9
0.9
AV = 1
VIPP = 1 V
RL = 100 kΩ
CL = 20 pF
TA = 25°C
See Figure 1
0.8
SR – Slew Rate – V/ μs
0.8
SR – Slew Rate – V/ μs
SLEW RATE
vs
FREE-AIR TEMPERATURE
0.7
0.6
0.5
0.4
2
4
6
8
10
12
VDD – Supply Voltage – V
14
0.5
0.4
VDD = 5 V
VIPP = 1 V
125
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
1.2
AV = 1
VIPP = 1 V
RL = 100 kΩ
CL = 20 pF
VDD = 5 V
1
0.9
0.8
0.7
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
VDD = 10 V
0.6
– 75
– 50
VDD = 5 V
VIPP = 2.5 V
Figure 27.
1.3
Normalized Slew Rate
VDD = 10 V
VIPP = 1 V
Figure 26.
1.4
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
Figure 28.
26
0.6
0.2
– 75
16
VO(PP) – Maximum Peak-to-Peak Output Voltage – V
0
(1)
0.7
0.3
0.3
1.1
VDD = 10 V
VIPP = 5.5 V
AV = 1
RL = 100 kΩ
CL = 20 pF
See Figure 1
125
10
9
VDD = 10 V
8
7
TA = 125°C
TA = 25°C
6
TA = – 55°C
5
VDD = 5 V
4
3
RL = 100 kΩ
See Figure 1
2
1
0
1
10
100
f – Frequency – kHz
1000
Figure 29.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS
(1)
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
800
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
800
700
600
500
400
300
– 75
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
750
B1 – Unity-Gain Bandwidth – kHz
B1 – Unity-Gain Bandwidth – kHz
900
700
650
600
550
500
450
400
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
0
125
2
4
6
8
10
12
VDD – Supply Voltage – V
Figure 30.
14
16
Figure 31.
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
VDD = 5 V
RL = 100 kΩ
TA = 25°C
105
0°
AVD
104
30°
103
60°
102
90°
Phase Shift
AVD
AVD – Large-Signal Differential
Voltage Amplification
106
Phase Shift
101
120°
1
150°
0.1
1
10
100
1k
10 k
f – Frequency – Hz
100 k
180°
1M
Figure 32.
(1)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS
(1)
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
VDD = 10 V
RL = 100 kΩ
TA = 25°C
105
0°
AVD
10 4
30°
103
60°
102
Phase Shift
AVD
AVD – Large-Signal Differential
Voltage Amplification
106
90°
Phase Shift
101
120°
1
150°
0.1
1
10
100
1k
10 k
f – Frequency – Hz
100 k
180°
1M
Figure 33.
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
45°
50°
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
43°
46°
φm – Phase Margin
φm – Phase Margin
48°
44°
42°
39°
35°
38°
0
2
4
6
8
10
12
VDD – Supply Voltage – V
Figure 34.
28
41°
37°
40°
(1)
VDD = 5 V
VI = 10 mV
TA = 25°C
See Figure 3
14
16
– 75
– 50
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 35.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
CAPACITIVE LOAD
44°
VDD = 5 V
VI = 10 mV
TA = 25°C
See Figure 3
42°
φm – Phase Margin
40°
38°
36°
34°
32°
30°
28°
0
10
20
30 40 50 60 70 80
CL – Capacitive Load – pF
90 100
Figure 36.
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
Vn – Equivalent Input Noise Voltage – nV/ Hz
300
VDD = 5 V
RS = 20 Ω
TA = 25°C
See Figure 2
250
200
150
100
50
0
1
10
100
f – Frequency – Hz
1000
Figure 37.
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APPLICATION INFORMATION
Single-Supply Operation
While the TLC27M4 and TLC27M9 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27M4 and TLC27M9 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27M4 and TLC27M9 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device
supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive decoupling
is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
R1
VREF = VDD
R2
VI
–
+
VREF
R3
VO
R3
R1 + R3
VO = (VREF – VI)
R4 + V
REF
R2
C
0.01 μF
Figure 38. Inverting Amplifier With Voltage Reference
–
Output
Logic
Logic
Logic
Power
Supply
+
(a) COMMON SUPPLY RAILS
–
Logic
+
Output
Logic
Logic
Power
Supply
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 39. Common Versus Separate Supply Rails
30
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
Input Characteristics
The TLC27M4 and TLC27M9 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at VDD – 1 V at TA = 25°C and at VDD – 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M4 and TLC27M9
very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M4 and
TLC27M9 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good
practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level as
the common-mode input (see Figure 40).
Unused amplifiers should be connected as unity-gain followers to avoid possible oscillation.
Noise Performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27M4 and TLC27M9 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.
–
–
VO
+
+
(a) NONINVERTING AMPLIFIER
(b) INVERTING AMPLIFIER
+
–
VI
VI
VO
VI
VO
(c) UNITY-GAIN AMPLIFIER
Figure 40. Guard-Ring Schemes
Copyright © 1987–2012, Texas Instruments Incorporated
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Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
31
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
Output Characteristics
The output stage of the TLC27M4 and TLC27M9 is designed to sink and source relatively high amounts of
current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current
capability can cause device damage under certain conditions. Output current capability increases with supply
voltage.
All operating characteristics of the TLC27M4 and TLC27M9 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs
at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases,
adding a small amount of resistance in series with the load capacitance alleviates the problem.
(a) CL = 20 pF, RL = NO LOAD
(b) CL = 170 pF, RL = NO LOAD
2.5 V
–
VO
+
VI
CL
TA = 25°C
f = 1 kHz
VIPP = 1 V
– 2.5 V
(d) TEST CIRCUIT
(c) CL = 190 pF, RL = NO LOAD
Figure 41. Effect of Capacitive Loads and Test Circuit
Although the TLC27M4 and TLC27M9 possess excellent high-level output voltage and current capability,
methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup
resistor (RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages
to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a
comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance
between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With
very low values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a drain
load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying
the output current.
32
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Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
C
+
IP
RP
Rp =
VO
–
IF
R2
R1
IL
VDD – VO
IF + IL + IP
IP = Pullup current required
by the operational amplifier
(typically 500 μA)
VO
+
VI
–
VDD
RL
Figure 42. Resistive Pullup to Increase VOH
Figure 43. Compensation for Input Capacitance
Feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads (discussed
previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with the feedback
resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
Electrostatic Discharge Protection
The TLC27M4 and TLC27M9 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents
functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be
exercised, however, when handling these devices, as exposure to ESD may result in the degradation of the
device parametric performance. The protection circuit also causes the input bias currents to be temperaturedependent and have the characteristics of a reverse-biased diode.
Latch-Up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27M4 and
TLC27M9 inputs and outputs were designed to withstand —100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground; it can be
triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
Copyright © 1987–2012, Texas Instruments Incorporated
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Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
33
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
1N4148
470 kΩ
100 kΩ
5V
1/4
TLC27M4
–
47 kΩ
100 kΩ
VO
+
R2
68 kΩ
100 kΩ
1 μF
R1
68 kΩ
C1
2.2 nF
C2
2.2 nF
NOTE: VOPP ≈ 2 V
fO =
1
2π √ R1R2C1C2
Figure 44. Wien Oscillator
34
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
www.ti.com
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
IS
5V
VI
1/4
TLC27M9
+
2N3821
–
R
NOTE: VI = 0 V to 3 V
V
IS = I
R
Figure 45. Precision Low-Current Sink
5V
Gain Control
1 MΩ
(see Note A)
100 kΩ
1 μF
+
ï
+
10 kΩ
0.1 μF
+
+
1 kΩ
1/4
TLC27M4
1 μF
100 kΩ
100 kΩ
NOTE A: Low to medium impedance dynamic mike
Figure 46. Microphone Preamplifier
10 MΩ
VDD
–
1 kΩ
–
1/4
TLC27M4
+
15 nF
1/4
TLC27M4
VO
VREF
+
100 kΩ
150 pF
NOTE: VDD = 4 V to 15 V
VREF = 0 V to VDD – 2 V
Figure 47. Photo-Diode Amplifier With Ambient Light Rejection
Copyright © 1987–2012, Texas Instruments Incorporated
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35
TLC27M4, TLC27M4A, TLC27M4B, TLC27M4Y, TLC27M9
SLOS093D – OCTOBER 1987 – REVISED OCTOBER 2012
www.ti.com
1 MΩ
VDD
33 pF
–
VO
+
1/4
TLC27M4
1N4148
100 kΩ
100 kΩ
NOTE: VDD = 8 V to 16 V
VO = 5 V, 10 mA
Figure 48. Low-Power Voltage Regulator
5V
1 MΩ
0.01 μF
VI
0.22 μF
+
VO
1/4
TLC27M4
–
1 MΩ
100 kΩ
100 kΩ
10 kΩ
0.1 μF
Figure 49. Single-Rail AC Amplifier
36
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Copyright © 1987–2012, Texas Instruments Incorporated
Product Folder Links: TLC27M4 TLC27M4A TLC27M4B TLC27M4Y TLC27M9
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
5962-90604042A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC27M4ACD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4AC
TLC27M4ACDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4AC
TLC27M4ACDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4AC
TLC27M4ACDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4AC
TLC27M4ACN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M4ACN
TLC27M4ACNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M4ACN
TLC27M4AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4AI
TLC27M4AIDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4AI
TLC27M4AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4AI
TLC27M4AIDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4AI
TLC27M4AIN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M4AIN
TLC27M4AINE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M4AIN
TLC27M4BCD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4BC
TLC27M4BCDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4BC
TLC27M4BCDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4BC
TLC27M4BCDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27M4BC
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC27M4BCN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M4BCN
TLC27M4BCNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M4BCN
TLC27M4BID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4BI
TLC27M4BIDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4BI
TLC27M4BIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4BI
TLC27M4BIDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27M4BI
TLC27M4BIN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M4BIN
TLC27M4BINE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M4BIN
TLC27M4CD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M4C
TLC27M4CDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M4C
TLC27M4CDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M4C
TLC27M4CDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M4C
TLC27M4CN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M4CN
TLC27M4CNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M4CN
TLC27M4CNSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M4
TLC27M4CNSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M4
TLC27M4CPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27M4
TLC27M4CPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27M4
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC27M4CPWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
0 to 70
TLC27M4CPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27M4
TLC27M4CPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27M4
TLC27M4ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M4I
TLC27M4IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M4I
TLC27M4IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M4I
TLC27M4IDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M4I
TLC27M4IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M4IN
TLC27M4INE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M4IN
TLC27M4IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
P27M4I
TLC27M4IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
P27M4I
TLC27M4IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
P27M4I
TLC27M4IPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
P27M4I
TLC27M4MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC27M4MJ
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
-55 to 125
TLC27M4MJB
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
-55 to 125
TLC27M9CD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M9C
TLC27M9CDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M9C
TLC27M9CDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M9C
TLC27M9CDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC27M9C
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC27M9CN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M9CN
TLC27M9CNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27M9CN
TLC27M9CNSLE
OBSOLETE
SO
NS
14
TBD
Call TI
Call TI
0 to 70
TLC27M9ID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M9I
TLC27M9IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M9I
TLC27M9IDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M9I
TLC27M9IDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC27M9I
TLC27M9IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M9IN
TLC27M9INE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27M9IN
TLC27M9MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC27M9MJ
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
-55 to 125
TLC27M9MJB
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
-55 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
11-Apr-2013
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC27M4ACDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC27M4AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC27M4BCDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC27M4BIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC27M4CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC27M4CNSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
TLC27M4CPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC27M4IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC27M4IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC27M9CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TLC27M9IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC27M4ACDR
SOIC
D
14
2500
367.0
367.0
38.0
TLC27M4AIDR
SOIC
D
14
2500
367.0
367.0
38.0
TLC27M4BCDR
SOIC
D
14
2500
367.0
367.0
38.0
TLC27M4BIDR
SOIC
D
14
2500
367.0
367.0
38.0
TLC27M4CDR
SOIC
D
14
2500
367.0
367.0
38.0
TLC27M4CNSR
SO
NS
14
2000
367.0
367.0
38.0
TLC27M4CPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC27M4IDR
SOIC
D
14
2500
367.0
367.0
38.0
TLC27M4IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC27M9CDR
SOIC
D
14
2500
367.0
367.0
38.0
TLC27M9IDR
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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