K4S641632F CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM Revision History Revision 0.0 (June, 2001) Revision 0.1 (Sep., 2001) • Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The K4S641632F is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) ORDERING INFORMATION FUNCTIONAL BLOCK DIAGRAM Part No. Max Freq. K4S641632F-TC50/TL50 200MHz(CL=3) Interface Package K4S641632F-TC55/TL55 183MHz(CL=3) K4S641632F-TC60/TL60 166MHz(CL=3) K4S641632F-TC70/TL70 143MHz(CL=3) K4S641632F-TC75/TL75 133MHz(CL=3) K4S641632F-TC1H/TL1H 100MHz(CL=2) K4S641632F-TC1L/TL1L 100MHz(CL=3) I/O Control Data Input Register LVTTL 54 TSOP(II) LWE LDQM Bank Select 1M x 16 1M x 16 Output Buffer 1M x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 1M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM PIN CONFIGURATION (Top view) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA7 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. L(U)DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S641632F-55/60 is 3.135V~3.6V. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol Min Max Unit Note CCLK 2.5 4.0 pF 1 CIN 2.5 5.0 pF 2 Address CADD 2.5 5.0 pF 2 DQ0 ~ DQ15 COUT 4.0 6.5 pF 3 Clock RAS, CAS, WE, CS, CKE, DQM Notes : 1. -75 only specify a maximum value of 3.5pF 2. -75 only specify a maximum value of 3.8pF 3. -75 only specify a maximum value of 6.0pF Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Version Test Condition Unit Note - 50 - 55 -60 - 70 - 75 -1H -1L Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P Active standby current in power-down mode Active standby current in non power-down mode (One bank active) 160 150 140 115 110 100 100 mA CKE ≤ VIL(max), tCC = 10ns 1 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N Precharge standby current in non power-down mode Burst length = 1 tRC ≥ tRC(min) IO = 0 mA CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 15 mA 6 CKE ≤ VIL(max), tCC = 10ns 3 ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N mA 1 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ ICC2NS Input signals are stable ICC3P 1 mA 3 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ ICC3NS Input signals are stable 25 ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 180 170 160 140 135 110 110 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 180 170 160 140 135 125 125 mA 2 Self refresh current ICC6 CKE ≤ 0.2V Operating current (Burst mode) C 1 mA 3 L 400 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S641632F-TC** 4. K4S641632F-TL** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH/VIL=VDDQ/VSSQ) Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA Output Output VOL (DC) = 0.4V, IOL = 2mA Z0 = 50Ω 50pF 870Ω 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit Notes : 1. The DC/AC Test Output Load of K4S641632F-50/55/60 is 30pF. 2. The VDD condition of K4S641632F-50/55/60 is 3.135V~3.6V. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -50 -55 -60 -70 -75 -1H -1L Unit Note Row active to row active delay tRRD(min) 10 11 12 14 15 20 20 ns 1 RAS to CAS delay tRCD(min) 15 16.5 18 20 20 20 20 ns 1 Row precharge time tRP(min) 15 16.5 18 20 20 20 20 ns 1 tRAS(min) 40 38.5 42 49 45 50 50 ns 1 Row active time tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to active delay tDAL(min) Last data in to new col. address Delay tCDL(min) Last data in to burst stop Col. address to col. address delay Number of valid output data 100 55 55 60 ns 1 CLK 2,5 - 5 1 CLK 2 tBDL(min) 1 CLK 2 tCCD(min) 1 CLK 3 65 70 70 ea 4 2 2CLK +15ns 2CLK +16.5ns CAS latency=3 CAS latency=2 68 us 2CLK +18ns 2CLK +20ns 2CLK +20ns 2CLK +20ns 2CLK +20ns 2 - 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter - 50 Symbol - 55 - 60 - 70 - 75 - 1H - 1L Unit Note Min Max Min Max Min Max Min Max Min Max Min Max Min Max CLK cycle time CAS latency=3 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 tCC CAS latency=2 5 1000 tSAC CAS latency=2 tOH CAS latency=2 5.5 1000 - 6 1000 - 7 1000 - 7.5 1000 10 10 1000 10 10 1000 ns 1 ns 1,2 ns 2 12 4.5 5 5 6 5.4 6 6 - - - - 6 6 7 2 2 2.5 3 3 3 3 - - - - 3 3 3 CLK high pulse width tCH 2 2 2.5 3 2.5 3 3 ns 3 CLK low pulse width tCL 2 2 2.5 3 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 1.5 2 1.5 2 2 ns 3 Input hold time tSH 1 1 1 1 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 1 1 1 ns 2 CLK to output CAS latency=3 in Hi-Z CAS latency=2 tSHZ 4.5 5 5 6 5.4 6 6 - - - - 6 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Output rise time trh Measure in linear region : 1.2V ~ 1.8V Output fall time tfh Output rise time Output fall time Typ Max Unit Notes 1.37 4.37 Volts/ns 3 Measure in linear region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3 trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6 Volts/ns 1,2 tfh Measure in linear region : 1.2V ~ 1.8V 2.0 2.9 5.0 Volts/ns 1,2 Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS. Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM IBIS SPECIFICATION 66MHz and 100MHz/133MHz Pull-up 0 IOH Characteristics (Pull-up) (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 100MHz 133MHz Min I (mA) 0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0 100MHz 133MHz Max I (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 66MHz Min 1 1.5 2 2.5 3 3.5 -100 I (mA) -200 -0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93.0 mA Voltage 0.5 0 -300 -400 -500 -600 Voltage IOH Min (100MHz/133MHz) IOH Min (66MHz) IOH Max (66 and 100MHz/133MHz) 66MHz and 100MHz/133MHz Pull-down IOL Characteristics (Pull-down) (V) 0.0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 100MHz 133MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 250 66MHz Min I (mA) 0.0 17.7 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9 200 150 mA Voltage 100MHz 133MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Voltage IOL Min (100MHz/133MHz) IOL Min (66MHz) IOL Max (100MHz/133MHz) Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM Minimum VDD clamp current (Referenced to VDD) VDD Clamp @ CLK, CKE, CS, DQM & DQ I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 20 15 mA VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 10 5 0 0 1 2 3 Voltage I (mA) Minimum VSS clamp current VSS Clamp @ CLK, CKE, CS, DQM & DQ I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 -3 -2 -1 0 0 -10 -20 mA VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 -30 -40 -50 -60 Voltage I (mA) Rev.0.1 Sept. 2001 K4S641632F CMOS SDRAM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address Auto precharge disable H X L H L H X V Write & column address Auto precharge disable Auto precharge enable X L H L L X H X L H H L X H X L L H L X H L Exit L H Entry H L Precharge power down mode Exit L Column address (A0 ~ A7) V L Column address (A0 ~ A7) H All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Clock suspend or active power down 3 3 L Bank selection 1,2 X X H Note 3 H Precharge A11, A9 ~ A0 L Bank active & row addr. Burst stop A10/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev.0.1 Sept. 2001