K4S643232E-TE/N CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V) Extended Temperature 86-TSOP Revision 1.4 December 2001 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM Revision History Revision 1.4 (December 4, 2001) • Not supported 90-Ball FBGA Revision 1.3 (October 24, 2001) • Removed CAS Latency 1 from the spec. Revision 1.2 (August 7, 2001) - Target • Added CAS Latency 1 Revision 1.1 (July 6, 2001) • Added K4S643232E-T/S(E/N)50 Revision 1.0 (April 6, 2001) Revision 0.0 (March 21, 2001) • Initial draft • Extended temperature (-25°c ~ 85°c ) • 3.3V Power supply (VDD &VDDQ) • Supported 90-ball FBGA as well as 86 - TSOP -2- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM 512K x 32Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The K4S643232E is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • • • • • 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle(4K/64ms) ORDERING INFORMATION Part NO. K4S643232E-TE/N50 K4S643232E-TE/N60 K4S643232E-TE/N70 • Extended Temperature range : -25oC to +85oC Max Freq. 200MHz 166MHz 143MHz Interface Package LVTTL 86 TSOP(II) • - E/N : Extended temperature (-25oC - 85oC) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 512K x 32 512K x 32 512K x 32 Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 32 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. -3- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM PIN CONFIGURATION (Top view) 86 - TSOP VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C VDD DQM0 WE CAS RAS CS N.C BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD N.C DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 -4- VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C VSS DQM1 N.C N.C CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS 86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch) Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. A0 ~ A10 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 BA0,1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. NC No Connection This pin is recommended to be left No connection on the device. 31 -5- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS •Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25oC to +85oC) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S643232E-60 is 3.135V ~ 3.6V CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Pin Symbol Min Max Unit CCLK - 4 pF CIN - 4.5 pF Address CADD - 4.5 pF DQ0 ~ DQ31 COUT - 6.5 pF Clock RAS, CAS, WE, CS, CKE, DQM -6- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = -25oC to +85oC, VIH(min)/VIL(max)=2.0V/0.8V) Parameter Operating Current (One Bank Active) Symbol ICC1 CAS Latency Test Condition Burst Length =1 tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0mA Speed -60 -70 3 175 170 155 2 150 150 150 mA ICC2P CKE ≤ VIL(max), tCC = 15ns 3 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2 ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 20 ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 ICC3P CKE ≤ VIL(max), tCC = 15ns 7 ICC3PS CKE ≤ VIL(max), tCC = ∞ 5 ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 55 ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 40 Operating Current (Burst Mode) ICC4 Io = 0 mA, Page Burst All bank Activated, tCCD = tCCD(min) Refresh Current ICC5 Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Self Refresh Current ICC6 Unit Note -50 2 mA mA mA tRC ≥ tRC(min) mA 3 190 180 170 2 150 150 150 3 190 185 165 2 160 160 160 CKE ≤ 0.2V mA 2 mA 3 3 mA 4 450 uA 5 Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232E-E** 5. K4S643232E-N** -7- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = -25oC to +85oC) Parameter Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Output Z0 = 50Ω 30pF 30pF 870Ω (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit Notes : 1. The VDD condition of K4S643232E-60 is 3.135V ~ 3.6V OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -50 -60 Unit -70 CAS Latency CL 3 2 3 2 3 2 CLK CLK cycle time tCC(min) 5 10 6 10 7 10 ns Row active to row active delay tRRD(min) CLK 1 RAS to CAS delay tRCD(min) 3 2 3 2 3 2 CLK 1 tRP(min) 3 2 3 2 3 2 CLK 1 tRAS(min) 8 5 7 5 7 5 CLK 1 Row precharge time Row active time 2 Note tRAS(max) 100 us Row cycle time tRC(min) CLK 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to new col.address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 Mode Register Set cycle time tMRS(min) 2 CLK Number of valid output data 11 7 10 7 CAS Latency=3 2 CAS Latency=2 1 10 7 ea 4 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following ns-unit based AC table. -8- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N Parameter CMOS SDRAM Symbol Version -50 -60 -70 Unit Row active to row active delay tRRD(min) 10 12 14 ns RAS to CAS delay tRCD(min) 15 18 20 ns Row precharge time tRP(min) 15 18 20 ns tRAS(min) 40 42 49 ns Row active time Row cycle time tRAS(max) 100 tRC(min) 55 us 60 70 ns 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter -50 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 CLK to valid output delay CAS Latency=3 CLK high pulse width tSAC tOH CAS Latency=3 tCH CAS Latency=2 CLK low pulse width Input setup time CAS Latency=3 tCL CAS Latency=2 CAS Latency=3 Max 1000 10 CAS Latency=2 Output data hold time 5 -60 tSS CAS Latency=2 Min 6 -70 Max 1000 10 Min 7 Unit Note ns 1 ns 1, 2 ns 2 ns 3 ns 3 ns 3 Max 1000 10 - 4.5 - 5.5 - 5.5 - 6 - 6 - 6 2 - 2 - 2 - 2 - 2.5 - 3 - 3 - 3 - 3 - 2 - 2.5 - 3 - 3 - 3 - 3 - 1.5 - 1.5 - 1.75 - 2.5 - 2.5 - 2.5 - Input hold time tSH 1 - 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - 1 - ns 2 - 4.5 - 5.5 - 5.5 ns - - 6 - 6 - 6 CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 tSHZ Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. -9- Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address H X L H L H X V Precharge Auto precharge enable H X L H L L X Entry H X L H H L X H X L L H L X H L Exit L H Entry H L Precharge power down mode Exit L Column address (A0 ~ A7) V L Column address (A0 ~ A7) H All banks Clock suspend or active power down L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Bank selection 3 3 L Burst Stop 1,2 X X Auto precharge disable Note 3 H Write & column address , A 9 ~ A0 L Bank active & row addr. Auto precharge disable A10/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes :1. OP Code : Operand code A0 ~ A10 & BA 0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) - 10 Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA0 ~ BA1 RFU Function A10/AP RFU A9 W.B.L Test Mode A8 A7 A6 TM A5 A4 CAS Latency CAS Latency A3 BT A2 A1 Burst Length A0 Burst Length Burst Type A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 Write Burst Length A9 0 Length 1 0 1 Reserved 1 0 1 Reserved Reserved Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length : x32 (256) POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle. - 11 Rev. 1.4 (Dec. 2001) K4S643232E-TE/N CMOS SDRAM BURST SEQUENCE (BURST LENGTH = 4) Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) Initial Address A2 A1 A0 Sequential Interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 12 Rev. 1.4 (Dec. 2001)