for AT&T CMOS SRAM K6R3024V1D Document Title 128Kx24 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Rev. 0.1 Design-In Specification Pin Configurations Modified ( page 2 ) Add Timing Diagram page 6 ~ 8 ) Modified Read Cycle Timing(2) 1) Version change from M to D 2) Cin from 20 to 15 pF 3) Icc from 300 to 170mA for 9ns products from 270 to 150mA for 10ns products from 240 to 130mA for 12ns products 4) Isb ( TTL ) from 120 to 40 mA for all products ( CMOS ) from 30 to 15 mA for all products 5) Part number change from -9 to -09 for 9ns products Change write parameter( tDW) from 6ns to 5ns at -10 Final Specification Release Dec. 05. 2000 Mar. 07. 2001 Design-In Preliminary April. 04.2001 June. 23.2001 Preliminary Preliminary Oct. 31. 2001 Dec. 19. 2001 Preliminary Final Rev. 0.2 Rev. 0.3 Rev. 0.4 Rev. 1.0 The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D 128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES GENERAL DESCRIPTION • Fast Access Time 9,10,12ns • Power Dissipation Standby (TTL) : 40mA(Max.) (CMOS) : 15mA(Max.) Operating K6R3024V1D-09 : 170mA(Max.) K6R3024V1D-10 : 150mA(Max.) K6R3024V1D-12 : 130mA(Max.) Single 3.3V Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • 119(7x17)Pin Ball Grid Array Package(14mmx22mm) • Operating in Commercial and Industrial Temperature range. The K6R3024V1D is a 3,145,728-bit high-speed Static Random Access Memory organized as 131,072 words by 24 bits. The K6R3024V1D uses 24 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG’s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R3024V1D is a three megabit static RAM constructed on an multilayer laminate substrate using three 3.3V, 128K x 8 static RAMS encapsulated in a Ball Grid Array(BGA). PIN FUNCTION Pin Name FUNCTIONAL BLOCK DIAGRAM A0-16 CS1 CS2 CS3 A0 - A16 17 WE 128K x 8 128K x 8 128K x 8 SRAM SRAM SRAM CS1,CS2,CS3 WE OE OE I/O 0 ~ I/O23 8 I/O0-7 8 8 I/O8-15 I/O16-23 ORDERING INFORMATION K6R3024V1D-HC09/HC10/HC12 Commercial Temp. K6R3024V1D-HI09/HI10/HI12 Industrial Temp. Pin Function Addresses Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs VCC Power(+3.3v) Vss Ground NC No Connection PIN CONFIGURATIONS (TOP VIEW) K6R3024V1D 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CS1 A A NC C I/O NC CS2 NC CS3 NC I/O D I/O VCC Vss Vss Vss VCC I/O E I/O Vss VCC Vss VCC Vss I/O F I/O VCC Vss Vss Vss VCC I/O G I/O Vss VCC Vss VCC Vss I/O H I/O VCC Vss Vss Vss VCC I/O J VCC Vss VCC Vss VCC Vss VCC K I/O VCC Vss Vss Vss VCC I/O L I/O Vss VCC Vss VCC Vss I/O M I/O VCC Vss Vss Vss VCC I/O N I/O Vss VCC Vss VCC Vss I/O P I/O VCC Vss Vss Vss VCC I/O R I/O NC NC NC NC NC I/O T NC A A WE A A NC U NC A A OE A A NC -2- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Symbol Rating Unit VIN, VOUT -0.5 to 4.6 V VCC -0.5 to 4.6 V Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Pd 2 W TSTG -65 to 150 °C Commercial TA 0 to 70 °C Industrial TA -40 to 85 °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE CS1 CS2 CS 3 OE WE I/O Power H X X X X Standby Mode High-Z Standby X L X X X Standby High-Z Standby X X H X X Standby High-Z Standby L H L L H Read DATAOUT Active L H L X L Write DATAIN Active L H L H H Outputs Disabled High-Z Active RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C) Parameter Min Typ Max Unit VCC 3.0 3.3 3.6 V Input High Voltage VIH 2.0 - Input Low Voltage VIL -0.3** - Supply Voltage Symbol VCC+0.3*** 0.8 V V * The above parameters are also guaranteed at industrial temperature range. ** V IL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA. *** VIH (Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. -3- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit ILI VIN=Vss to V CC - 6 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC - 2 µA Operating Current ICC -09 - 170 mA -10 - 150 mA -12 - 130 mA -09 - 40 mA -10 - 40 mA Input Leakage Current Standby Current Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA ISB Min. Cycle, CS=VIH f=0MHz, CS ≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V ISB1 -12 - 40 mA -09 - 15 mA -10 - 15 mA -12 - 15 mA Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V * The above parameters are also guaranteed at industrial temperature range. * CS represents CS1 , CS 2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3. CAPACITANCE*(TA=25°C, f=1.0MHz) Symbol Test Conditions MIN Max Unit Input/Output Capacitance Item CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 15 pF * Capacitance is sampled and not 100% tested AC TEST CONDITIONS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified) Parameter Value Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 3ns Input and output Timing Reference Levels 1.5V Output Load See Below * The above parameters are also guaranteed at industrial temperature range. Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V RL = 50Ω DOUT 319Ω VL = 1.5V ZO = 50Ω DOUT 30pF* 216Ω 5pF* * Including Scope and Jig Capacitance * Capacitive Load consists of all components of the test environment. -4- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D READ CYCLE* Parameter Symbol K6R3024V1D-09 K6R3024V1D-10 K6R3024V1D-12 Unit Min Max Min Max Min Max tRC 9 - 10 - 12 - ns Address Access Time tAA - 9 - 10 - 12 ns Chip Select to Output tCO - 9 - 10 - 12 ns Output Enable to Valid Output tOE - 4 - 5 - 6 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 4 0 5 0 6 ns Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns Chip Select to Power-Up Time tPU 0 - 0 - 0 - ns Chip Deselect to Power DownTime tPD - 9 - 10 - 12 ns Read Cycle Time WRITE CYCLE* Parameter Symbol K6R3024V1D-09 K6R3024V1D-10 Min Max Min K6R3024V1D-12 Max Min Max Unit Write Cycle Time tWC 9 - 10 - 12 - ns Chip Select to End of Write tCW 7 - 7 - 8 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 7 - 7 - 8 - ns Write Pulse Width(OE High) tWP 7 - 7 - 8 - ns Write Pulse Width(OE Low) tWP1 9 - 9 - 10 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 5 0 5 ns Data to Write Time Overlap tDW 5 - 5 - 7 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - ns * This parameter is guaranteed by design but not tested. These specifications are for the individual K6R3024V1D Static RAMs. -5- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Valid Data Previous Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOE tOHZ OE tOLZ tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than t LZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. CS represents CS1 , CS 2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3. -6- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW (10) (9) High-Z(8) Data out -7- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP(2) WE tDW Data in High-Z Data Valid tLZ Data out tDH High-Z tWHZ(6) High-Z(8) High-Z NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11. CS represents CS1 , CS2 and CS3 in this data sheet. CS2 as of opposite polarity to CS1 and CS3. -8- Revision 1.0 December 2001 for AT&T CMOS SRAM K6R3024V1D 119 BGA PACKAGE DIMENSIONS 14.00±0.10 1.27 1.27 22.00±0.10 Indicator of Ball(1A) Location 20.50±0.10 C0.70 C1.00 0.750±0.15 1.50REF 0.60±0.10 NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX. 0.60±0.10 12.50±0.10 -9- Revision 1.0 December 2001