SAMSUNG K7B403625M

K7B403625M
128Kx36 Synchronous SRAM
Document Title
128Kx36-Bit Synchronous Burst SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
Initial draft
May. 15. 1997
Preliminary
0.1
Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change ISB1 value from 10mA to 30mA.
Change ISB2 value from 10mA to 20mA.
Feb. 11. 1998
Preliminary
0.2
Change Undershoot spec
from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2)
Add Overshoot spec 4.6V((pulse width≤tCYC/2)
Change VIH max from 5.5V to VDD+0.5V
April. 14. 1998
Preliminary
0.3
Change ISB2 value from 20mA to 30mA.
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
May. 13. 1998
Preliminary
1.0
Final spec Release
May. 15. 1998
Final
2.0
Add VDDQ Supply voltage( 2.5V )
Dec. 02. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
128Kx36-Bit Synchronous Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
The K7B403625M is 4,718,592 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And
with CS1 high, ADSP is blocked to control signals.
It can be organized as 128K words of 36 bits. And it integrates
address and control registers, a 2-bit burst address counter and
high output drive circuitry onto a single integrated circuit for
reduced components counts implementation of high performance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK.
The K7B403625M is implemented with SAMSUNG′s high performance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to minimize ground bounce.
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
FAST ACCESS TIMES
PARAMETER
Symbol -75
-80
-90
Unit
Cycle Time
tCYC
8.5
10
12
ns
Clock Access Time
tCD
7.5
8
9
ns
Output Enable Access Time
tOE
3.5
3.5
3.5
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
BURST CONTROL
LOGIC
CONTROL
REGISTER
ADV
ADSC
A0~A16
A′0~A′1
ADDRESS
REGISTER
A2~A16
DATA-IN
REGISTER
CONTROL
REGISTER
GW
BW
WEa
WEb
WEc
WEd
128Kx36
MEMORY
ARRAY
A0 ~A1
ADSP
CS1
CS2
CS2
BURST
ADDRESS
COUNTER
OUTPUT
BUFFER
CONTROL
LOGIC
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
-2-
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
A6
A7
CS1
CS2
WEd
WEc
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
A9
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100 Pin TQFP
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A4
A3
A2
A1
A0
N.C.
N.C.
VSS
VDD
N.C.
N.C.
A10
A11
A12
A13
A14
A15
A16
(20mm x 14mm)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
100
PIN CONFIGURATION (TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
N.C.
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
PIN NAME
SYMBOL
PIN NAME
A0 - A16
Address Inputs
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,
50,81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
SYMBOL
PIN NAME
TQFP PIN NO.
VDD
VSS
N.C.
Power Supply(+3.3V)
Ground
No Connect
15,41,65,91
17,40,67,90
14,16,38,39,42,43,66
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
VDDQ
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
VSSQ
-3-
5,10,21,26,55,60,71,76
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
FUNCTION DESCRIPTION
The K7B403625M is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC
based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration
of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In K7B403625M, a 128Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and
DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN
(Interleaved Burst)
Case 1
HIGH
A1
0
0
1
1
First Address
Fourth Address
Case 2
A0
0
1
0
1
A1
0
0
1
1
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
1
0
0
BURST SEQUENCE TABLE
LBO PIN
A0
1
0
1
0
(Linear Burst)
Case 1
LOW
A1
0
0
1
1
First Address
Fourth Address
Case 2
A0
0
1
0
1
A1
0
1
1
0
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
0
0
1
A0
1
0
1
0
Note : 1. LBO pin must be tied to high or low, and floating state must not be allowed.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Read
Notes
1. X means "Don't Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffersmust
be disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
-4-
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
SYNCHRONOUS TRUTH TABLE
CS1
CS2
CS2
ADSP ADSC
ADV
WRITE
CLK
ADDRESS ACCESSED
OPERATION
H
X
X
X
L
X
X
↑
N/A
Not Selected
L
L
X
L
X
X
X
↑
N/A
Not Selected
L
X
H
L
X
X
X
↑
N/A
Not Selected
L
L
X
X
L
X
X
↑
N/A
Not Selected
L
X
H
X
L
X
X
↑
N/A
Not Selected
L
H
L
L
X
X
X
↑
External Address
Begin Burst Read Cycle
L
H
L
H
L
X
L
↑
External Address
Begin Burst Write Cycle
L
H
L
H
L
X
H
↑
External Address
Begin Burst Read Cycle
X
X
X
H
H
L
H
↑
Next Address
Continue Burst Read Cycle
H
X
X
X
H
L
H
↑
Next Address
Continue Burst Read Cycle
X
X
X
H
H
L
L
↑
Next Address
Continue Burst Write Cycle
H
X
X
X
H
L
L
↑
Next Address
Continue Burst Write Cycle
X
X
X
H
H
H
H
↑
Current Address
Suspend Burst Read Cycle
H
X
X
X
H
H
H
↑
Current Address
Suspend Burst Read Cycle
X
X
X
H
H
H
L
↑
Current Address
Suspend Burst Write Cycle
H
X
X
X
H
H
L
↑
Current Address
Suspend Burst Write Cycle
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
BW
WEa
WEb
WEc
WEd
Operation
H
H
X
X
X
X
READ
H
L
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
H
L
H
L
H
H
WRITE BYTE b
H
L
H
H
L
L
WRITE BYTE c and d
H
L
L
L
L
L
WRITE ALL BYTEs
L
X
X
X
X
X
WRITE ALL BYTEs
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
-5-
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
Voltage on V DD Supply Relative to VSS
VDD
-0.3 to 4.6
V
Voltage on V DDQ Supply Relative to VSS
VDDQ
VDD
V
V
Voltage on Input Pin Relative to VSS
VIN
-0.3 to 6.0
Voltage on I/O Pin Relative to VSS
VIO
-0.3 to VDDQ + 0.5
V
Power Dissipation
PD
1.2
W
Storage Temperature
TSTG
-65 to 150
°C
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature Range Under Bias
TBIAS
-10 to 85
°C
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C≤ T A≤70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.6
V
VDDQ
3.135
3.3
3.6
V
VSS
0
0
0
V
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.6
V
VDDQ
2.375
2.5
2.9
V
VSS
0
0
0
V
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
TEST CONDITION
MIN
MAX
UNIT
CIN
VIN=0V
-
5
pF
COUT
VOUT=0V
-
8
pF
*Note : Sampled not 100% tested.
-6-
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
Input Leakage Current(except ZZ)
IIL
VDD=Max , VIN=VSS to VDD
-2
+2
µA
Output Leakage Current
IOL
Output Disabled, VOUT=VSS to V DDQ
-2
+2
µA
-
350
ICC
Device Selected, IOUT=0mA,
ZZ≤VIL, All Inputs=VIL or VIH
Cycle Time ≥ tCYC min
-75
Operating Current
-80
-
325
-90
-
300
-75
-
100
-80
-
90
-90
-
80
ISB
Standby Current
Device deselected, IOUT=0mA,
ZZ≤VIL, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
mA
mA
mA
ISB1
Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V)
-
30
ISB2
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH
-
30
Output Low Voltage(3.3V I/O)
VOL
IOL = 8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
VOH
IOH = -4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
VOL
IOL = 1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
VOH
IOH = -1.0mA
2.0
-
V
mA
Input Low Voltage(3.3V I/O)
VIL
-0.5*
0.8
V
Input High Voltage(3.3V I/O)
VIH
2.0
VDD+0.5**
V
Input Low Voltage(2.5V I/O)
VIL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
VIH
1.7
VDD+0.5**
V
* V IL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH (Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ +0.5V
TEST CONDITIONS
(V DD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
2ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
2ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
-7-
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
Output Load(A)
Dout
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50Ω
Z0=50Ω
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319Ω / 1667Ω
Dout
353Ω / 1538Ω
* Capacitive Load consists of all components of
the test environment.
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
Cycle Time
SYMBOL
tCYC
-75
-80
-90
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
8.5
-
10
-
12
-
ns
Clock Access Time
tCD
-
7.5
-
8
-
9
ns
Output Enable to Data Valid
tOE
-
3.5
-
3.5
-
3.5
ns
Clock High to Output Low-Z
tLZC
0
-
0
-
0
-
ns
Output Hold from Clock High
tOH
2
-
2
-
2
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
3.5
-
3.5
-
3.5
ns
Clock High to Output High-Z
tHZC
2
3.5
2
3.5
2
3.5
ns
Clock High Pulse Width
tCH
3
-
4
-
4.5
-
ns
Clock Low Pulse Width
tCL
3
-
4
-
4.5
-
ns
Address Setup to Clock High
tAS
2.0
-
2.0
-
2.0
-
ns
Address Status Setup to Clock High
tSS
2.0
-
2.0
-
2.0
-
ns
Data Setup to Clock High
tDS
2.0
-
2.0
-
2.0
-
ns
Write Setup to Clock High(GW, BW, WEx)
tWS
2.0
-
2.0
-
2.0
-
ns
Address Advance Setup to Clock High
tADVS
2.0
-
2.0
-
2.0
-
ns
Chip Select Setup to Clock High
tCSS
2.0
-
2.0
-
2.0
-
ns
Address Hold from Clock High
tAH
0.5
-
0.5
-
0.5
-
ns
Address Status Hold from Clock High
tSH
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
0.5
-
0.5
-
ns
Write Hold from Clock High(GW, BW, WEx)
tWH
0.5
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
2
-
cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
4. At any given voltage and temperature, t HZC is less than tLZC.
-8-
December 1998
Rev 2.0
-9-
Data Out
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCSS
tAS
tSS
tOE
Q1-1
tHZOE
tADVH
tWH
tSS
A2
tSH
Q2-1
tCD
tOH
Q2-2
Q2-3
A3
Q2-4
(ADV INSERTS WAIT STATE)
BURST CONTINUED WITH
NEW BASE ADDRESS
tCYC
tCL
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tADVS
tCSH
tWS
tLZOE
A1
tAH
tSH
tCH
TIMING WAVEFORM OF READ CYCLE
Q3-1
Q3-2
Q3-3
Undefined
Don′t Care
Q3-4
tHZC
K7B403625M
128Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 10 -
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
Q0-3
tCSS
tAS
tSS
Q0-4
A1
tLZOE
tCSH
tAH
tSH
D1-1
tCL
tCYC
tCH
A2
D2-1
D2-2
(ADV SUSPENDS BURST)
D2-2
D2-3
(ADSC EXTENDED BURST)
TIMING WAVEFORM OF WRTE CYCLE
D2-4
D3-1
A3
tDS
tADVS
tWS
tSS
D3-2
tDH
tADVH
tWH
tSH
D3-3
Undefined
Don′t Care
D3-4
K7B403625M
128Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 11 -
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSP
CLOCK
tHZC
tSS
A1
tLZC
tCD
tSH
Q1-1
tHZOE
tAS
A2
tCL
tCYC
tDS
tADVS
tWS
tAH
tCH
D2-1
tDH
tADVH
tWH
A3
tLZOE
tOE
Q3-1
Q3-2
Q3-3
tOH
Q3-4
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
Undefined
Don′t Care
K7B403625M
128Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 12 -
Data In
Data Out
OE
ADV
CS
WRITE
ADDRESS
ADSC
CLOCK
tCSS
tSS
A1
tLZOE
tOE
tCSH
tSH
Q1-1
A2
Q2-1
A3
Q3-1
A4
Q4-1
tHZOE
D5-1
A5
tDS
tWS
D6-1
A6
tDH
tWH
D7-1
A7
tWS
tCD
A8
A9
Q8-1
tCL
tCYC
tWH
tCH
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH)
December 1998
Rev 2.0
Undefined
Don′t Care
Q9-1
tOH
K7B403625M
128Kx36 Synchronous SRAM
- 13 -
Data In
Data Out
OE
ADV
CS
WRITE
ADDRESS
ADSP
CLOCK
tCSS
tSS
tOE
tCSH
tLZOE
A1
tSH
Q1-1
A2
Q2-1
A3
tAS
Q3-1
A4
tAH
tCYC
tCH
A5
Q4-1
tCL
tHZOE
D5-1
A6
tDS
D6-1
tDH
A7
D7-1
tCD
A8
Q8-1
A9
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
Q9-1
tOH
Undefined
Don′t Care
K7B403625M
128Kx36 Synchronous SRAM
December 1998
Rev 2.0
- 14 -
ZZ
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCSS
tAS
tSS
A1
tLZOE
tOE
tCSH
tAH
tSH
Q1-1
ZZ Setup Cycle
tPDS
tHZC
Sleep State
tPUS
tCL
ZZ Recovery Cycle
tCYC
tCH
TIMING WAVEFORM OF POWER DOWN CYCLE
tWS
Normal Operation Mode
tHZOE
A2
D2-1
tWH
Undefined
Don′t Care
D2-2
K7B403625M
128Kx36 Synchronous SRAM
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
I/O[0:71]
Data
Address
A[0:17]
A[17]
A[0:16]
A[17]
Address
CLK
64-bits
Microprocessor
Address
CS2
CS2
CS2
ADSC
CLK
Data
CS2
CLK
Address
128Kx36
SB
SRAM
CLK
ADSC
128Kx36
SB
SRAM
(Bank 1)
(Bank 0)
OE
CS1
CS1
ADV
Data
WEx
WEx
OE
Cache
Controller
A[0:16]
ADV
ADSP
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HiGH)
CLOCK
tSS
tSH
ADSP
tAS
ADDRESS
[0:n]
A1
tAH
A2
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS
Bank 0 is deselected by CS2 , and Bank 1 selected by CS2
tADVH
ADV
OE
tOE
Data Out
(Bank 0)
Data Out
(Bank 1)
tLZOE
tHZC
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Q2-1
Q2-2
*Notes : n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
- 15 -
Q2-3
Q2-4
Don′t Care
Undefined
December 1998
Rev 2.0
K7B403625M
128Kx36 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units:millimeters/inches
0~8°
22.00 ±0.30
0.10
0.127 +- 0.05
20.00 ±0.20
16.00 ±0.30
14.00
±0.20
0.10 MAX
(0.83)
0.50
#1
0.65
±0.10
(0.58)
0.30 ±0.10
0.10 MAX
1.40
0.50 ±0.10
- 16 -
±0.10
1.60 MAX
0.05 MIN
December 1998
Rev 2.0