Preliminary CMOS SDRAM KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • SSTL_3 (Class II) compatible with multiplexed address • Dual banks operation • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) The KM416S1021C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part No. Max Freq. KM416S1021CT-G7 143MHz Interface Package KM416S1021CT-GS 100MHz(CL=2) SSTL_3 (Class II) 54 TSOP(II) KM416S1021CT-G8 125MHz * KM416S1021CT-GS : CL=2 only FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 512K x 16 Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. REV. 1. May '98 Preliminary CMOS SDRAM KM416S1021C PIN CONFIGURATION (Top view) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50Pin TSOP (II) (400mil x 825mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A10/AP Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 BA Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. L(U)DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Reference voltage Reference voltage for inputs. REV. 1. May '98 Preliminary CMOS SDRAM KM416S1021C ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Symbol Min Typ Max Unit Note Device supply voltage Parameter VDD VDDQ - 3.6 V 1 Output supply voltage VDDQ 3.0 3.3 3.6 V 1 3.26 3.43 3.6 V 8 2, 3 Input reference voltage VREF 1.3 1.5 1.7 V Termination voltage Vtt VREF-0.05 VREF VREF+0.05 V Input logic high voltage VIH VREF+0.2 - VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 VREF-0.2 V 2 Output logic high voltage VOH Vtt+0.8 - - V 5 Output logic low voltage VOL - - Vtt-0.8 V 5 Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 7 Notes : 1.Under all conditions, VDDQ must be less than or equal to VDD. 2. Typically, the value of VREF is expected to be about 0.45 * VDDQ of the transmitting device. VREF is expected to track variations in VDDQ. 3. Peak to peak AC noise on VREF may not exceed 2% VREF (DC) 4. Vtt of transmitting device must track VREF of receiving device. 5. Voltage level measured at device pin with IOH/IOL = -16mA/16mA. 6. Any input 0V ≤ VIN ≤ VDD+0.3V, all other pins are not under test = 0V. 7. Dout buffer is disabled, 0V ≤ VOUT ≤ VDD. 8. Apply to only the KM416S1021CT-GS. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Symbol Min Max Unit CLK, CKE, CS, RAS, CAS, WE & L(U)DQM CIN 2 4 pF Address CADD 2 4 pF DQ0 ~ DQ15 COUT 2 5 pF REV. 1. May '98 Preliminary CMOS SDRAM KM416S1021C DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol ICC1 ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode Active Standby current in non power-down mode (One bank active) ICC3P ICC3PS ICC3N ICC3NS Test Condition CAS Latency Burst length = 1 tRC ≥ tRC(min) IOL = 0 mA Version -7 -S -8 95 90 95 CKE ≤ VIL(max), tCC = 15ns 2 CKE & CLK ≤ VIL(max), tCC = ∞ 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 20 Unit Note mA 1 mA mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 6 CKE ≤ VIL(max), tCC = 15ns 3 CKE & CLK ≤ VIL(max), tCC = ∞ 2 mA CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 30 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 20 mA IOL = 0 mA Page burst tCCD = 2CLKs Operating current (Burst mode) ICC4 Refresh current ICC5 tRC ≥ tRC(min) Self refresh current ICC6 CKE ≤ VIL(max) 3 150 140 130 2 105 100 100 90 85 80 2 mA 1 mA 2 mA 3 Notes :1. Measured with outputs open. 2. Refresh period is 64ms. REV. 1. May '98 Preliminary CMOS SDRAM KM416S1021C AC OPERATING TEST CONDITIONS(VDD = 3.3V ± 0.3V, 3.43V ± 0.5%, TA = 0 to 70°C) Parameter Value Input reference voltage V 2.0 V Input signal maximum peak swing Inout signal minimum slew rate AC input levels (Vih/Vil) Unit 0.45 * VDDQ 1.0 V/ns VREF+0.4/VREF-0.4 V VREF V Vtt V Input timing measurement reference level Output timing measurement reference level Output load condition See Fig. 1 Vtt = 0.45 * V DDQ 50Ω Output Z0 = 50Ω VREF = 0.45 * V DDQ CLOAD=30pF (Fig. 1) Output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -7 -S -8 Unit Note Row active to row active delay tRRD(min) 14 20 16 ns 1 RAS to CAS delay tRCD(min) 21 20 24 ns 1 tRP(min) 21 20 24 ns 1 tRAS(min) 49 50 56 ns 1 Row precharge time Row active time tRAS(max) Row cycle time tRC(min) Last data in to new col. address delay tCDL(min) Last data in to row precharge tRDL(min) Last data in to burst stop Col. address to col. address delay Number of valid output data 100 70 70 us 80 ns 1 1 CLK 2 1 CLK 2 tBDL(min) 1 CLK 2 tCCD(min) 1 CLK 3 ea 4 CAS latency=3 2 - 2 CAS latency=2 1 1 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. REV. 1. May '98 Preliminary CMOS SDRAM KM416S1021C AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter -7 Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to Valid Output Delay CAS latency=3 7 -S Max 1000 12 Min - CAS latency=2 1000 10 5.5 tSAC tOH CLK high pulse width CLK low pulse width Min 8 Unit Note ns 1 ns 1,2 Max 1000 13 - 7 Output data hold time -8 Max 6 6 8 2.5 2 2.5 ns 2 tCH 3 3.5 3 ns 3 tCL 3 3.5 3 ns 3 Input setup time tSS 2 2 2.5 ns 3 Input hold time tSH 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 5.5 7 - 6 8 ns 8 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. REV. 1. May '98 Preliminary CMOS SDRAM KM416S1021C FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE KM416S1021BT-G7 (Unit : Number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 49ns 21ns 14ns 21ns 7ns 7ns 7ns 143MHz (7.0ns) 3 10 7 3 2 3 1 1 1 125MHz (8.0ns) 3 9 7 3 2 3 1 1 1 100MHz (10.0ns) 3 7 5 3 2 3 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 5 4 2 1 2 1 1 1 Frequency KM416S1021BT-GS (Unit : Number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (10.0ns) 2 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 5 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 3 2 2 2 1 1 1 Frequency KM416S1021BT-G8 (Unit : Number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 80ns 56ns 24ns 16ns 24ns 8ns 8ns 8ns 125MHz (8.0ns) 3 10 7 3 2 3 1 1 1 100MHz (10.0ns) 3 8 6 3 2 3 1 1 1 83MHz (12.0ns) 3 7 5 2 2 2 1 1 1 75MHz (13.0ns) 2 7 5 2 2 2 1 1 1 66MHz (15.0ns) 2 6 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 4 2 1 2 1 1 1 Frequency REV. 1. May '98 Preliminary CMOS SDRAM KM416S1021C SIMPLIFIED TRUTH TABLE Command Register CKEn-1 Mode register set Auto refresh Refresh H H Entry Self refresh CS RAS CAS WE DQM X L L L L X OP code L L L H X X L H H H H BA H X X X Bank active & row addr. H X L L H H X V Read & column address H X L H L H X V Bank selection X L H L L Entry Exit Entry X H X L H H L X H X L L H L X L H L H L Precharge power down mode Exit DQM No operation command L V L H H L H H X X X L V V V X X X X H X X X L H H H H X X X L V V V H X X X L H H H X H H X 3 3 Both banks Clock suspend or active power down 3 Row address H H Note 1,2 X Auto precharge enable Burst stop Precharge X Auto precharge enable Auto precharge disable A9 ~ A0 3 H Auto precharge disable A10/AP L L Write & column address Exit CKEn 4,5 Column address (A0 ~ A7 ) 4,5 X V L X H 4 Column address (A0 ~ A7 ) 4 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A10/AP, BA : Program keys. (@ MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA : bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) REV. 1. May '98