K4S643232C CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 November 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Revision History Revision 1.1 (November 17th, 1999) • Corrected typo in ordering information on page 3 Revision 1.0 (October, 1999) • Changed part number from KM432S2030CT-G/F to K4S643232C-TC/TL according to re-organized code system -2- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM 512K x 32Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The K4S643232C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • • • • • 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle ORDERING INFORMATION Part NO. K4S643232C-TC/L55 K4S643232C-TC/L60 K4S643232C-TC/L70 K4S643232C-TC/L80 K4S643232C-TC/L10 Max Freq. 183MHz 166MHz 143MHz 125MHz 100MHz Interface Package LVTTL 86 TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 512K x 32 512K x 32 512K x 32 Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 32 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. -3- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM PIN CONFIGURATION (Top view) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C VDD DQM0 WE CAS RAS CS N.C BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD N.C DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 -4- VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C VSS DQM1 N.C N.C CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS 86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch) REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disables input buffers for power down mode. A0 ~ A10 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 BA0,1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. NC No Connection This pin is recommended to be left No connection on the device. 31 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Pin Symbol Min Max Unit CCLK 2.5 4 pF CIN 2.5 4.5 pF Address CADD 2.5 4.5 pF DQ 0 ~ DQ31 COUT 4.0 6.5 pF Clock RAS, CAS, WE, CS, CKE, DQM -5- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Note VDD, VDDQ 3.0 3.3 3.6 V 4 Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V. DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol ICC1 ICC2P Precharge standby current in non power-down mode ICC2NS Active standby current in non power-down mode (One bank active) ICC3P -55 -60 -70 -80 -10 3 140 140 130 130 115 2 - - - 130 115 Burst length = 1 tRC ≥ tRC(min) Io = 0 mA Unit Note mA CKE ≤ VIL(max), t CC = 15ns ICC3N ICC3NS ICC4 mA 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 20 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 mA CKE ≤ VIL(max), t CC = 15ns 3 mA Refresh current ICC5 ICC6 3 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 30 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 20 mA Io = 0 mA Page burst 2 Banks activated tRC ≥ tRC(min) 2 2 ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ Operating current (Burst mode) Self refresh current Version CAS Latency ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N Active standby current in power-down mode Test Condition 3 220 200 180 150 130 2 - - - 130 110 3 200 200 180 160 150 2 - - - 160 150 CKE ≤ 0.2V mA 2 mA 3 2 mA 4 450 uA 5 Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. 3. Refresh period is 64ms. 4. K4S643232C-TC** 5. K4S643232C-TL** -6- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Output Z0 = 50Ω 50pF*1 50pF*1 870Ω (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit Note : 1. The DC/AC Test Output Load of K4S643232C-55/60/70 is 30pF. 2. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -55 -60 -70 -80 Unit -10 CAS Latency CL 3 2 3 2 3 2 3 2 3 2 CLK cycle time tCC(min) 5.5 - 6 - 7 - 8 10 10 12 Row active to row active delay tRRD(min) RAS to CAS delay tRCD(min) 3 - 3 - 3 - 3 2 2 tRP(min) 3 - 3 - 3 - 3 2 tRAS(min) 7 - 7 - 7 - 6 5 Row precharge time Row active time 2 tRAS(max) tRC(min) 10 - 10 - 10 Row cycle time in Auto refresh tRFC(min) 12 - 12 - 10 Last data in to row precharge tRDL(min) 2 Last data in to new col.address delay tCDL(min) Last data in to burst stop Col. address to col. address delay Mode Register Set cycle time tMRS(min) Number of valid output data CLK ns CLK 1 2 CLK 1 2 2 CLK 1 5 4 CLK 1 100 Row cycle time Note us - 9 7 7 6 CLK - 9 7 7 6 CLK 1,6 CLK 2, 5 1 CLK 2 tBDL(min) 1 CLK 2 tCCD(min) 1 CLK 2 CLK CAS Latency=3 2 CAS Latency=2 1 ea 1 4 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following ns-unit based AC table. -7- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Parameter CLK cycle time Version Symbol tCC(min) -55 -60 -70 -80 -10 5.5 6 7 8 10 Unit ns Row active to row active delay tRRD(min) 11 12 14 16 20 ns RAS to CAS delay tRCD(min) 16.5 18 21 20 20 ns Row precharge time tRP(min) 16.5 18 21 20 20 ns tRAS(min) 38.5 42 49 48 48 ns Row active time tRAS(max) 100 us Row cycle time tRC(min) 55 60 70 70 70 ns Row cycle time in Auto refresh tRFC(min) 66 72 70 70 70 ns 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency. 6. A new command should be issued after self refersh exit followed by tRFC. AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter -55 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 CLK to valid output delay CAS Latency=3 CLK high pulse width tSAC tOH CAS Latency=3 tCH CAS Latency=2 CLK low pulse width CAS Latency=3 tCL CAS Latency=2 Input setup time CAS Latency=3 Max 1000 - CAS Latency=2 Output data 5.5 -60 tSS CAS Latency=2 Min 6 -70 Max 1000 - Min 7 -80 Max 1000 - Min 8 -10 Max 1000 10 Min 10 Unit Note Max 1000 ns 1 ns 1, 2 12 - 5 - 5.5 - 5.5 - 6 - 6 - - - - - - - 6 - 8 2 - 2.5 - 2.5 - 2.5 - 2.5 - ns 2 2 - 2.5 - 3 - 3 - 3.5 - ns 3 - - - 2 - 2.5 - 3 - 3 - 3.5 - ns 3 - - - 1.5 - 1.5 - 2 - 2.5 - ns 3 - - - - 1.75 - Input hold time tSH 1 - 1 - 1 - 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - 1 - ns 2 - 5 - 5.5 - 5.5 - 6 - 6 - - - - - - - 6 - 8 CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 tSHZ ns Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. -8- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address H X L H L H X V Precharge Auto precharge enable H X L H L L X Entry H X L H H L X H X L L H L X H L Exit L H Entry H L Precharge power down mode Exit L Column address (A0 ~ A7) V L Column address (A0 ~ A7) H All banks Clock suspend or active power down L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Bank selection 3 3 L Burst Stop 1,2 X X Auto precharge disable Note 3 H Write & column address , A 9 ~ A0 L Bank active & row addr. Auto precharge disable A10/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes :1. OP Code : Operand code A0 ~ A10 & BA 0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) -9- REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA0 ~ BA1 RFU Function A10/AP RFU A9 W.B.L Test Mode A8 A7 A6 TM A5 A4 CAS Latency CAS Latency A3 BT A2 A1 Burst Length A0 Burst Length Burst Type A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 Write Burst Length A9 0 Length 1 0 1 Reserved 1 0 1 Reserved Reserved Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length : x32 (256) POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle. - 10 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM BURST SEQUENCE (BURST LENGTH = 4) Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) Initial Address A2 A1 A0 Sequential Interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 11 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM DEVICE OPERATIONS CLOCK (CLK) NOP and DEVICE DESELECT The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications. When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored. CLOCK ENABLE (CKE) POWER-UP The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are thesame as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for both banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. BANK ADDRESSES (BA0 ~ BA1) This SDRAM is organized as four independent banks of 524,288 words x 32 bits memory arrays. The BA0 ~ BA1 inputs are latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank addresses BA0 ~ BA1 are latched at bank active, read, write, mode register set and precharge operations. ADDRESS INPUTS (A0 ~ A10) The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0 ~ A10). The 11 bit row addresses are latched along with RAS and BA0 ~ BA1 during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA0 ~ BA1 during read or write command. - 12 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM DEVICE OPERATIONS (Continued) MODE REGISTER SET (MRS) active to initiate sensing and restoring the complete row of The mode register stores the data for controlling the various dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a operating modes of SDRAM. It programs the CAS latency, burst precharge command to that active bank can be asserted. The type, burst length, test mode and various vendor specific options maximum time any bank can be in the active state is determined to make SDRAM useful for variety of different applications. The by tRAS(max). The number of cycles for both tRAS (min) and default value of the mode register is not defined, therefore the tRAS(max) can be calculated similar to tRCD specification. mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, BURST READ RAS, CAS and WE (The SDRAM should be in active mode with The burst read command is used to access burst of data on con- CKE already high prior to writing the mode register). The state of secutive clock cycles from an active row in an active bank. The address pins A0 ~ A10 and BA0 ~ BA1 in the same cycle as CS, burst read command is issued by asserting low on CS and CAS RAS, CAS and WE going low is the data written in the mode with WE being high on the positive edge of the clock. The bank register. Two clock cycles is required to complete the write in the must be active for at least tRCD(min) before the burst read com- mode register. The mode register contents can be changed mand is issued. The first output appears in CAS latency number using the same command and clock cycle requirements during of clock cycles after the issue of burst read command. The burst operation as long as all banks are in the idle state. The mode length, burst sequence and latency from the burst read com- register is divided into various fields depending on the fields of mand is determined by the mode register which is already pro- functions. The burst length field uses A0 ~ A2, burst type uses grammed. The burst read can be initiated on any column A3, CAS latency (read latency from column address) use A4 ~ address of the active row. The address wraps around if the initial A6, vendor specific options or test mode use A7 ~ A8, A10/AP address does not start from a boundary such that number of out- and BA0 ~ BA1. The write burst length is programmed using A9. puts from each I/O are equal to the burst length programmed in A7 ~ A8, A10/AP and BA0 ~ BA1 must be set to low for normal the mode register. The output goes into high-impedance at the SDRAM operation. Refer to the table for specific codes for vari- end of the burst, unless a new burst read was initiated to keep ous burst length, burst type and CAS latencies. the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the BANK ACTIVATE other active bank or a precharge command to the same bank. The bank activate command is used to select a random row in The burst stop command is valid at every page burst length. an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write BURST WRITE operation can occur after a time delay of tRCD(min) from the time The burst write command is similar to burst read command and of bank activation. t RCD is an internal timing parameter of is used to write data into the SDRAM on consecutive clock SDRAM, therefore it is dependent on operating clock frequency. cycles in adjacent addresses depending on burst length and The minimum number of clock cycles required between bank burst sequence. By asserting low on CS, CAS and WE with valid activate and read or write command should be calculated by column address, a write burst is initiated. The data inputs are dividing tRCD(min) with cycle time of the clock and then rounding provided for the initial address in the same clock cycle as the off the result to the next higher integer. The SDRAM has four burst write command. The input buffer is deselected at the end internal banks in the same chip and shares part of the internal of the burst length, even though the internal writing can be com- circuitry to reduce chip area, therefore it restricts the activation pleted yet. The writing can be completed by issuing a burst read of four banks simultaneously. Also the noise generated during and DQM for blocking data inputs or burst write in the same or sensing of each bank of SDRAM is high, requiring some time for another active bank. The burst stop command is valid at every power supplies to recover before another bank can be sensed burst length. The write burst can also be terminated by using reliably. tRRD(min) specifies the minimum time required between DQM for blocking data and procreating the bank tRDL after the activating different bank. The number of clock cycles required last data input to be written into the active row. between different bank activation must be calculated similar to See DQM OPERATION also. tRCD specification. The minimum time required for the bank to be - 13 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM DEVICE OPERATIONS (Continued) DQM OPERATION AUTO REFRESH The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also. The storage cells of SDRAM need to be refreshed every 64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by driving tRFC with PRECHARGE clock cycle time and them rounding up to the next higher integer. The precharge operation is performed on an active bank by The auto refresh command must be followed by NOP's until the asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1 auto refresh operation is completed. All banks will be in the idle of the bank to be precharged. The precharge command can be state at the end of auto refresh operation. The auto refresh is the asserted anytime after tRAS(min) is satisfied from the bank active preferred refresh mode when the SDRAM is being used for nor- command in the desired bank. tRP is defined as the minimum mal data transactions. The auto refresh cycle can be performed number of clock cycles required to complete row precharge is once in 15.6us or a burst of 4096 auto refresh cycles once in calculated by dividing tRP with clock cycle time and rounding up 64ms. to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing SELF REFRESH before precharge command is asserted. The maximum time any The self refresh is another refresh mode available in the bank can be active is specified by tRAS(max). Therefore, each SDRAM. The self refresh is the preferred refresh mode for data bank activate command. At the end of precharge, the bank retention and low power operation of SDRAM. In self refresh enters the idle state and is ready to be activated again. Entry to mode, the SDRAM disables the internal clock and all the input Power down, Auto refresh, Self refresh and Mode register set buffers except CKE. The refresh addressing and timing are etc. is possible only when all banks are in idle state. internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by AUTO PRECHARGE asserting low on CS, RAS, CAS and CKE with high on WE. The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "t RP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write by asserting high on A10/AP, the bank is left active until a new command is asserted. Once auto precahrge command is given, no new commands are possible to that particular bank until the bank achieves idle state. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 4096 auto refresh cycles immediately after exiting in self refresh BOTH BANKS PRECHARGE mode. Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after performing precharge to all the banks, both banks are in idle state. - 14 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4 2) Clock Suspended During Read (BL=4) CLK CMD WR RD CKE Masked by CKE Masked by CKE Internal CKE DQ(CL2) D0 D1 D2 D3 DQ(CL3) D0 D1 D2 D3 Q0 D Q01 Q2 Q3 Q0 Q1 Q2 Q3 Suspended Dout Not Written 2. DQM Operation 2) Read Mask (BL=4) 1) Write Mask (BL=4) CLK CMD WR RD DQM Masked byDQM DQ(CL2) D0 DQ(CL3) D0 D1 D3 D1 Q0 Masked by DQM Hi-Z Hi-Z D3 DQM to Data-in Mask = 0 Q2 Q3 Q1 Q2 Q3 DQM to Data-out Mask = 2 3) DQM with Clock Suspended (Full Page Read) Note 2 CLK CMD RD CKE DQM DQ(CL2) DQ(CL3) Q0 Hi-Z Hi-Z Q2 Q1 Hi-Z Hi-Z Q4 Q3 Hi-Z Hi-Z Q6 Q7 Q8 Q5 Q6 Q7 *Note : 1. CKE to CLK disable/enable = 1CLK. 2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out. - 15 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD RD RD ADD A B DQ(CL2) QA0 DQ(CL3) QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 tCCD Note 2 2) Write interrupted by Write (BL=2) 3) Write interrupted by Read (BL=2) CLK CMD WR WR tCCD ADD A B DQ DA0 DB0 tCDL Note 3 WR Note 2 RD tCCD A DB1 Note 2 B DQ(CL2) DA0 DQ(CL3) DA0 QB0 QB1 QB0 QB 1 tCDL Note 3 *Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) - 16 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 CLK i) CMD RD WR DQM DQ ii) CMD D0 RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM Hi-Z DQ iii) CMD D0 RD WR DQM Hi-Z DQ iv) CMD D0 RD WR DQM Q0 DQ Hi-Z Note 1 D0 D3 (b) CL=3, BL=4 CLK RD i) CMD WR DQM D0 DQ ii) CMD RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM D0 DQ iii) CMD RD WR DQM D0 DQ iii) CMD RD WR DQM Hi-Z DQ iv) CMD D0 RD WR DQM DQ Q0 Hi-Z Note 1 D0 D3 *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. - 17 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM 5. Write Interrupted by Precharge & DQM CLK WR CMD PRE Note 3,4 Note 2 DQM DQ D0 D1 D2 D3 Masked by DQM *Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out. 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency. 6. Precharge 2) Normal Read (BL=4) 1) Normal Write (BL=4) CLK CLK CMD WR DQ D0 Note 2 PRE D1 D2 CMD D3 RD DQ(CL2) tRDL Note 1,4 PRE Q0 DQ(CL3) Q1 Q2 Q3 Q0 Q1 Q2 D1 D2 D3 D0 D1 D2 1 Q3 2 7. Auto Precharge 1) Normal Write (BL=4) 2) Normal Read (BL=4) CLK CLK CMD WR DQ D0 CMD D1 D2 D3 DQ(CL2) Note 3,4 Auto Precharge Starts DQ(CL3) RD D0 D3 Note 3 Auto Precharge Starts *Note : 1. tRDL : Last data in to row precharge delay 2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. 4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency - 18 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM 8. Burst Stop & Interrupted by Precharge 2) Write Burst Stop (BL=8) 1) Normal Write (BL=4) CLK CLK CMD WR CMD PRE DQM WR STOP DQM DQ D0 D1 D2 DQ D3 tRDL D0 D1 D2 Note 1,5 D3 D4 tBDL 3) Read Interrupted by Precharge (BL=4) D5 Note 2 4) Read Burst Stop (BL=4) CLK CLK CMD RD PRE DQ(CL2) Q0 DQ(CL3) CMD Note 3 Q1 Q0 1 DQ(CL2) Q1 2 DQ(CL3) RD STOP Q0 Q1 Q0 1 Q1 2 9. MRS 1) Mode Register Set CLK Note 4 CMD MRS PRE tRP ACT 2CLK *Note : 1. tRDL : 1 CLK 2. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely. 4. PRE : All banks precharge if necessary. MRS can be issued only at all banks precharge state. 5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency - 19 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit 2) Power Down (=Precharge Power Down) Exit CLK CLK CKE CKE tSS Internal CLK tSS Internal CLK Note 1 CMD Note 2 CMD RD NOP ACT 11. Auto Refresh & Self Refresh 1) Auto Refresh & Self Refresh Note 3 CLK ¡ó Note 4 CMD Note 5 PRE CMD AR ¡ó CKE ¡ó tRP 2) Self Refresh tRFC ¡ó Note 6 ¡ó CLK ¡ó Note 4 CMD PRE SR CMD CKE ¡ó tRP tRFC *Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, all banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are perfomed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of t RFC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended. - 20 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM 12. About Burst Type Control Basic MODE Random MODE Sequential Counting At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=1, 2, 4, 8 and full page. Interleave Counting At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting Random column Access tCCD = 1 CLK Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. 13. About Burst Length Control Basic MODE 1 At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. 2 At MRS A2,1,0 = "001". At auto precharge, tRAS should not be violated. 4 At MRS A2,1,0 = "010". 8 At MRS A2,1,0 = "011". Full Page Special MODE BRSW Random MODE Burst Stop Interrupt MODE RAS Interrupt (Interrupted by Precharge) CAS Interrupt At MRS A2,1,0 = "111". Wrap around mode(Infinite burst length) should be stopped by burst stop Ras interrupt or CAS interrupt At MRS A9 = "1". Read burst =1, 2, 4, 8, full page write Burst =1 At auto precharge of write, tRAS should not be violated. tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively Using burst stop command, any burst length control is possible. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. - 21 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 1) Current State IDLE Row Active Read Write Read with Auto Precharge Write with Auto Precharge Precharging CS RAS CAS WE BA ADDR ACTION Note H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL 2 L H L X BA CA, A10/AP ILLEGAL 2 L L H H BA RA L L H L BA A10/AP L L L H X X L L L L OP code OP code H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP L H L L BA CA, A10/AP Begin Write ; latch CA ; determine AP L L H H BA RA ILLEGAL L L H L BA A10/AP Precharge Row (& Bank) Active ; Latch RA NOP 4 Auto Refresh or Self Refresh 5 Mode Register Access 5 2 2 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New Read, Determine AP L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP Term burst, Precharge timing for Reads L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New read, Determine AP 3 L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP Term burst, precharge timing for Writes 3 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA CA, A10/AP ILLEGAL L L H X BA RA, RA10 ILLEGAL L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA CA, A10/AP ILLEGAL L L H X BA RA, RA10 ILLEGAL L L L X X X ILLEGAL 2 2 H X X X X X NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP NOP --> Idle after tRPL 4 - 22 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 1) Current State Row Activating Refreshing Mode Register Accessing CS RAS CAS WE BA ADDR ACTION Note L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRFC L H H X X X NOP --> Idle after tRFC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL H X X X X X NOP --> Idle after 2 clocks L H H H X X NOP --> Idle after 2 clocks L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL Abbreviations : RA = Row Address NOP = No Operation Command BA = Bank Address CA = Column Address AP = Auto Precharge *Note : 1. All entries assume the CKE was active (High) during the precharge clcok and the current clock cycle. 2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle. - 23 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 2) Current State Self Refresh All Banks Precharge Power Down All Banks Idle Any State other than Listed above CKE (n-1) CKE n CS RAS CAS WE ADDR ACTION Note H X X X X X X INVALID L H H X X X X Exit Self Refresh --> Idle after tRFC (ABI) 6 L H L H H H X Exit Self Refresh --> Idle after tRFC (ABI) 6 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI 7 L H L H H L X ILLEGAL 7 L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Low Power Mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down 8 H L L H H L X ILLEGAL 8 H L L H L X X ILLEGAL H L L L H H RA H L L L L H X H L L L L L OP Code Row (& Bank) Active Enter Self Refresh 8 Mode Register Access L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend next cycle 9 L H X X X X X Exit Clock Suspend next cycle 9 L L X X X X X Maintain Clcok Suspend Abbreviations : ABI = All Banks Idle, RA = Row Address *Note : 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restarts internal clock. A minimum setup time 1CLK + tSS must be satisfied before any command other than exit. 8. Power down and self refresh can be entered only from the both banks idle state. 9. Must be a legal command. - 24 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK tCL tCC HIGH CKE tRAS tRC *Note 1 tSH CS tRCD tRP tSS tSH RAS tSS tCCD tSH CAS tSH ADDR Ra tSS Ca Cb Cc Rb tSS *Note 2 *Note 2,3 *Note 2,3 BA0 ~ BA1 BS BS BS A10/AP Ra *Note 3 *Note 2,3 *Note 4 BS *Note 3 BS *Note 3 *Note 4 tRAC Rb tSH tSAC Qa DQ *Note 2 BS Db tSLZ Qc tSS tOH tSH WE tSS tSS tSH DQM Row Active Read Write Read Row Active Precharge : Don't care - 25 REV. 1.1 Nov. '99 K4S643232C 0 1 CMOS SDRAM *Note : 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1. 2 3 4 5 6 7 8 BA0 BA1 Active & Read/Write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 9 10 11 12 13 14 15 16 17 18 19 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command A10/AP BA0 BA1 0 1 Operation 0 0 Disable auto precharge, leave bank A active at end of burst. 0 1 Disable auto precharge, leave bank B active at end of burst. 1 0 Disable auto precharge, leave bank C active at end of burst. 1 1 Disable auto precharge, leave bank D active at end of burst. 0 0 Enable auto precharge, precharge bank A at end of burst. 0 1 Enable auto precharge, precharge bank B at end of burst. 1 0 Enable auto precharge, precharge bank C at end of burst. 1 1 Enable auto precharge, precharge bank D at end of burst. 4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted. A10/AP BA0 BA1 Precharge 0 0 0 Bank A 0 0 0 Bank B 0 1 1 Bank C 0 1 1 Bank D 1 x x All Banks - 26 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Power Up Sequence 0 1 2 3 4 6 7 8 9 10 11 12 13 ∼ ∼ ∼ ∼ ∼ CKE 5 ∼ CLOCK 14 15 16 17 18 19 High level is necessary CS tRP tRC RAS ∼ ∼ ∼ ∼ CAS ∼ ∼ ∼ ∼ ADDR ∼ ∼ ∼ ∼ BA0 ∼ ∼ ∼ ∼ BA1 ∼ ∼ ∼ ∼ A10/AP ∼ ∼ ∼ ∼ Key RAa RAa High-Z ∼ ∼ WE High level is necessary Precharge (All Banks) Auto Refresh ∼ DQM ∼ ∼ DQ Auto Refresh Mode Register Set Row Active (A-Bank) : Don't care - 27 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Read & Write Cycle at Same Bank @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Db1 Db2 Db3 18 19 CLOCK HIGH CKE *Note 1 tRC CS tRCD RAS *Note 2 CAS ADDR Ra Ca Rb Cb BA0 BA1 A10/AP Ra Rb tOH CL=2 Qa0 Qa1 Qa2 Qa3 Db0 tRAC *Note 3 tSAC tSHZ tRDL *Note 4 *Note 5 DQ tOH CL=3 Qa0 Qa1 Qa2 Qa3 Db0 tRAC *Note 3 tSAC tSHZ Db1 Db2 Db3 tRDL *Note 4 *Note 5 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) 5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency - 28 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Page Read & Write Cycle at Same Bank @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS tRCD RAS *Note 2 CAS ADDR Ra Ca Cb Cc Cd BA0 BA1 A10/AP Ra tRDL CL=2 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1 *Note 4 DQ CL=3 tCDL WE *Note 1 *Note 3 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency - 29 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Page Read Cycle at Different Bank @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE *Note 1 CS RAS *Note 2 CAS ADDR RAa RBb RAa RBb CAa RCc CBb RDd CCc CDd BA0 BA1 A10/AP RCc RDd QAa0 QAa1 QAa2 QBb0 CL=2 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 DQ CL=3 QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Bank) Read (B-Bank) Row Acive (C-Bank) Read (C-Bank) Row Active (D-Bank) Precharge (A-Bank) Read (D-Bank) Precharge (D-Bank) Precharge (C-Bank) Precharge (B-Bank) : Don't care *Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. - 30 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Page Write Cycle at Different Bank @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS *Note 2 CAS ADDR RAa RBb RAa RBb CAa CBb RCc RDd RCc RDd DBb0 DBb1 DBb2 DBb3 CCc CDd BA0 BA1 A10/AP DAa0 DAa1 DAa2 DQ DAa3 DCc0 DCc1 DDd0 DDd1 DDd2 tCDL tRDL *Note 3 WE *Note 1 DQM Row Active (A-Bank) Write (A-Bank) Row Active (B-Bank) Write (B-Bank) Row Active (D-Bank) Row Active (C-Bank) Write (D-Bank) Precharge (All Banks) Write (C-Bank) : Don't care *Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. 3.For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency - 31 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Read & Write Cycle at Different Bank @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CDb RBc 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa RDb CBc BA0 BA1 A10/AP RAa RBb RAc tCDL QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3 QAa0 QAa1 CL=2 *Note 1 QBc0 QBc1 QBc2 DQ CL=3 QBc0 QBc1 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Write (D-Bank) Row Active (D-Bank) Read (B-Bank) Precharge (B-Bank) : Don't care *Note : 1. tCDL should be met to complete write. - 32 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Read & Write Cycle with Auto Precharge I @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa RBb RAa RBb CAa CBb BA0 BA1 A10/AP DQ (CL=2) QAa0 QAa1 QAa2 QAa3 DQ (CL=3) QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 WE DQM Row Active (A-Bank) Read with Auto Precharge (A-Bank) Auto Precharge Start Point (A-Bank) Write with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) Row Active (B-Bank) : Don′t care *Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2, BRSW mode and Block write) - 33 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Read & Write Cycle with Auto Precharge II @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS Ra Rb Ra Rb ADDR Ca Cb Ra Ca BA0 BA1 A10/AP DQ Ra CL=2 Qa0 CL=3 Qa1 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da0 Da1 WE DQM Row Active (A-Bank) Read with Auto Pre charge (A-Bank) Row Active (B-Bank) Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank)* Precharge (B-Bank) Row Active (A-Bank) Write with Auto Precharge (A-Bank) : Don't care *Note: * When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at B Bank read command input point . - any command can not be issued at A Bank during tRP after A Bank auto precharge starts. - 34 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Read & Write Cycle with Auto Precharge III @Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Qb1 Qb2 Qb3 Qb0 Qb1 Qb2 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR Ra Ca Rb Cb BA0 BA1 A10/AP DQ Ra Rb CL=2 Qa0 CL=3 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qb0 Qa3 Qb3 WE DQM * Row Active (A-Bank) Read with Auto Precharge (A-Bank) Auto Precharge Start Point (A-Bank) Row Active (B-Bank) Read with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) : Don't care *Note : * Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point - 35 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR Ra Ca Cb Cc BA0 BA1 A10/AP Ra Qa0 DQ Qa1 Qa2 Qa3 Qb0 tSHZ Qb1 Dc0 Dc2 tSHZ WE *Note 1 DQM Row Active Read Clock Suspension Read Write DQM Read DQM Write DQM Write Clock Suspension : Don't care *Note : 1. DQM is needed to prevent bus contention. - 36 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA0 BA1 A10/AP RAa CL=2 1 1 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 DQ CL=3 2 2 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 WE DQM Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length. - 37 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA0 BA1 A10/AP RAa tBDL tRDL *Note 2,4 DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) *Note : Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) : Don't care 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. 4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency. - 38 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Burst Read Single bit Write Cycle @Burst Length=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK *Note 1 HIGH CKE CS RAS *Note 2 CAS ADDR RAa CAa RBb CAb RCc CBc CCd BA0 BA1 A10/AP RAa RBb CL=2 DAa0 CL=3 DAa0 RAc QAb0 QAb1 DBc0 QCd0 QCd1 DQ QAb0 QAb1 DBc0 QCd0 QCd1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Row Active (C-Bank) Read (C-Bank) Precharge (C-Bank) Write with Auto Precharge (B-Bank) Read with Auto Precharge (A-Bank) : Don't care *Note : 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. - 39 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 tSS 12 13 14 15 16 17 18 19 tSS *Note 1 tSS *Note 2 *Note 2 ∼ ∼ CKE 11 ∼ ∼ ∼ CLOCK 10 *Note 3 ∼ ∼ Ca ∼ ∼ ∼ ∼ A10/AP Ra ∼ ∼ ∼ ∼ BA ∼ ∼ ∼ ∼ ADDR ∼ ∼ ∼ ∼ CAS ∼ ∼ ∼ ∼ RAS ∼ ∼ CS Ra tSHZ ∼ ∼ DQ Precharge Power-down Entry Qa2 ∼ ∼ ∼ ∼ DQM Qa1 ∼ ∼ ∼ ∼ WE Qa0 Row Active Precharge Power-down Exit Read Active Power-down Entry Precharge Active Power-down Exit : Don ¡Ç t Care *Note : 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. 3. Can not violate minimum refresh specification. (64ms) - 40 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Self Refresh Entry & Exit Cycle 1 2 3 5 6 7 8 9 10 11 12 *Note 4 *Note 2 13 14 15 16 17 18 19 ∼ CLOCK 4 ∼ ∼ 0 tRFCmin ∼ *Note 1 *Note 6 *Note 3 ∼ CKE tSS ∼ ∼ ∼ ∼ ∼ ∼ RAS *Note 5 ∼ ∼ ∼ ∼ ADDR ∼ ∼ ∼ ∼ BA0~BA1 Hi-Z ∼ ∼ ∼ ∼ WE ∼ ∼ ∼ ∼ DQM ∼ ∼ Hi-Z DQ ∼ ∼ ∼ ∼ A10/AP *Note 7 ∼ ∼ ∼ ∼ CAS ∼ CS Self Refresh Entry Self Refresh Exit Auto Refresh : Don't care *Note : TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System colck restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. - 41 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM Mode Register Set Cycle 0 1 2 3 4 5 Auto Refresh Cycle 6 7 8 90 1 10 2 11 3 12 4 13 5 14 HIGH HIGH CKE 7 16 8 17 9 18 10 19 ∼ ∼ CLOCK 6 15 ∼ CS *Note 2 tRFC ∼ ∼ RAS *Note 1 ∼ ∼ CAS Key Ra Hi-Z Hi-Z ∼ DQ ∼ ∼ *Note 3 ADDR WE ∼ ∼ DQM ∼ ∼ ¡ó ¡ó MRS New Command Auto Refresh New Command : Don't care * All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. - 42 REV. 1.1 Nov. '99 K4S643232C CMOS SDRAM PACKAGE DIMENSIONS 86-TSOP2-400F Unit : Millimeters 0~8°C 0.25 TYP 0.010 #86 #43 #1 0.005+0.003 -0.001 22.62 MAX 0.891 22.22 0.875 ± 0.10 0.21 0.008 ± 0.004 0.10 MAX 0.004 ( 0.61 ) 0.024 0.20 +0.10 -0.03 0.45~0.75 0.018~0.030 0.125+0.075 -0.035 ± 0.05 ± 0.002 1.00 0.039 ± 0.10 ± 0.004 ( 0.50 ) 0.020 10.16 0.400 11.76±0.20 0.463±0.008 #44 1.20 MAX 0.047 0.05 MIN 0.010 0.50 0.0197 - 43 REV. 1.1 Nov. '99