FM25C041U
4K-Bit SPI™ Interface
Serial CMOS EEPROM
General Description
Functions
The FM25C041U is a 4K (4,096) bit serial interface CMOS
EEPROM (Electrically Erasable Programmable Read-Only
Memory). This device fully conforms to the SPI 4-wire protocol
which uses Chip Select (/CS), Clock (SCK), Data-in (SI) and Dataout (SO) pins to synchronously control data transfer between the
SPI microcontroller and the EEPROM. In addition, the serial
interface allows a minimal pin count, packaging designed to
simplify PC board layout requirements and offers the designer a
variety of low voltage and low power options.
■ SPI MODE 1 interface
■ 4,096 bits organized as 512 x 8
■ Extended 2.7V to 5.5V operating voltage
■ 2.1 MHz operation @ 4.5V - 5.5V
■ Self-timed programming cycle
■ "Programming complete" indicated by STATUS REGISTER
polling
■ /WP pin and BLOCK WRITE protection
This SPI EEPROM family is designed to work with the 68HC11 or
any other SPI-compatible, high-speed microcontroller and offers
both hardware (/WP pin) and software ("block write") data protection. For example, entering a 2-bit code into the STATUS REGISTER prevents programming in a selected block of memory and all
programming can be inhibited by connecting the /WP pin to VSS;
allowing the user to protect the entire array or a selected section.
In addition, SPI devices feature a /HOLD pin, which allows a
temporary interruption of the datastream into the EEPROM.
Features
■ Sequential read of entire array
■ 4 byte "Page write" mode to minimize total write time per
byte
■ /WP pin and BLOCK WRITE protection to prevent inadvertent programming as well as programming ENABLE and
DISABLE opcodes.
■ /HOLD pin to suspend data transfer
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power consumption for a continuously reliable non-volatile solution for all
markets.
■ Typical 1µA standby current (ISB) for "L" devices and 0.1µA
standby current for "LZ" devices.
■ Endurance: Up to 1,000,000 data changes
■ Data retention greater than 40 years
Block Diagram
/CS
/HOLD
SCK
SI
Instruction
Register
Program
Enable
Address
Counter/
Register
VPP
Decoder
VCC
VSS
Instruction
Decoder
Control Logic
and Clock
Generators
/WP
High Voltage
Generator
and
Program
Timer
EEPROM Array
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
SPI™ is a trademark of Motorola Corporation
© 2002 Fairchild Semiconductor Corporation
FM25C041U Rev. B
1
www.fairchildsemi.com
FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
February 2002
FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Connection Diagram
Dual-In-Line Package (N), SO Package (M8),
and TSSOP Package (MT8)
/CS
1
8
VCC
SO
2
7
/HOLD
/WP
3
6
SCK
VSS
4
5
SI
FM25C041U
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
/CS
Chip Select Input
SO
Serial Data Output
/WP
Write Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
/HOLD
Suspends Serial Data
Power Supply
VCC
Ordering Information
FM
25
C
XX
U
LZ
E
XX
Letter Description
Package
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
Temp. Range
None
V
E
0 to 70°C
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Ultralite
CS100UL Process
041
4K, mode 1
Density/Mode
Interface
2
FM25C041U Rev. B
C
CMOS technology
25
SPI
FM
Fairchild Nonvolatile
Memory Prefix
www.fairchildsemi.com
Ambient Storage Temperature
Ambient Operating Temperature
FM25C041U
FM25C041UE
FM25C041UV
-65°C to +150°C
All Input or Output Voltage with
Respect to Ground
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V (unless otherwise specified)
Symbol
ICC
ICCSB
Parameter
Conditions
Operating Current
/CS = VIL
Standby Current
/CS = VCC
IIL
Input Leakage
VIN = 0 to VCC
VOUT = GND to VCC
Min
-1
Max
Units
3
mA
50
µA
+1
µA
µA
IOL
Output Leakage
-1
+1
VIL
CMOS Input Low Voltage
-0.3
VCC * 0.3
V
VIH
CMOS Input High Voltage
0.7 * VCC
VCC + 0.3
V
0.4
V
VOL
Output Low Voltage
IOL = 1.6 mA
VOH
Output High Voltage
IOH = -0.8 mA
fOP
SCK Frequency
2.1
MHz
tRI
Input Rise Time
2.0
µs
tFI
Input Fall Time
2.0
µs
VCC - 0.8
V
tCLH
Clock High Time
(Note 2)
190
ns
ns
tCLL
Clock Low Time
(Note 2)
190
tCSH
Min /CS High Time
(Note 3)
240
ns
tCSS
/CS Setup Time
240
ns
ns
tDIS
Data Setup Time
100
tHDS
/HOLD Setup Time
90
ns
tCSN
/CS Hold Time
240
ns
ns
tDIN
Data Hold Time
100
tHDN
/HOLD Hold Time
90
tPD
Output Delay
tDH
Output Hold Time
tLZ
/HOLD to Output Low Z
tDF
Output Disable Time
tHZ
/HOLD to Output High Z
tWP
Write Cycle Time
CL = 200 pF
ns
100
ns
240
ns
0
CL = 200 pF
1–16 Bytes
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4)
Symbol
Test
COUT
Output Capacitance
3
8
pF
Input Capacitance
2
6
pF
CIN
ns
240
ns
100
ns
10
ms
AC Test Conditions
Output Load
Typ Max Units
CL = 200 pF
Input Pulse Levels
0.1 * VCC – 0.9 * VCC
Timing Measurement Reference Level
0.3 * VCC - 0.7 * VCC
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, for a fOP of 2.1MHz, the period equals 476ns. In this case if t CLH = is set to 190ns, then tCLL must be set to a minimum of 286ns.
Note 3: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
3
FM25C041U Rev. B
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FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature
-65°C to +150°C
All Input or Output Voltage with
Respect to Ground
Ambient Operating Temperature
FM25C041UL/LZ
FM25C041ULE/LZE
FM25C041ULV
+6.5V to -0.3V
Lead Temp. (Soldering, 10 sec.)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Power Supply (VCC)
2000V
2.7V–4.5V
DC and AC Electrical Characteristics 2.7V ≤ VCC ≤ 4.5V (unless otherwise specified)
25C041UL/LE
25C041ULZ/ZE
Symbol
Parameter
Part
Conditions
Min.
25C041ULV
Max.
Max
Units
3
10
N/A
mA
µA
µA
-1
1
µA
-1
1
µA
VCC * 0.3
-0.3
VCC * 0.3
V
VCC + 0.3
VCC * 0.7
VCC + 0.3
V
0.4
V
/CS = VIL
/CS = VCC
Min
ICC
ICCSB
Operating Current
Standby Current
IIL
Input Leakage
VIN = 0 to VCC
-1
1
IOL
Output Leakage
VOUT = GND to VCC
-1
1
VIL
Input Low Voltage
-0.3
VIH
Input High Voltage
VCC * 0.7
VOL
Output Low Voltage
IOL = 0.8 mA
VOH
Output High Voltage
IOH = –0.8 mA
fOP
SCK Frequency
1.0
1.0
MHz
tRI
Input Rise Time
2.0
2.0
µs
tFI
Input Fall Time
2.0
µs
tCLH
Clock High Time
(Note 6)
410
410
ns
tCLL
Clock Low Time
(Note 6)
410
410
ns
tCSH
Min. /CS High Time
(Note 7)
500
500
ns
tCSS
/CS Setup Time
500
500
ns
tDIS
Data Setup Time
100
100
ns
tHDS
/HOLD Setup Time
240
240
ns
tCSN
/CS Hold Time
500
500
ns
tDIN
Data Hold Time
100
100
ns
tHDN
/HOLD Hold Time
240
240
tPD
Output Delay
tDH
Output Hold Time
tLZ
/HOLD Output Low Z
tDF
Output Disable Time
tHZ
/HOLD to Output Hi Z
tWP
Write Cycle Time
L
LZ
3
10
1
0.4
VCC - 0.8
2.0
CL = 200 pF
500
CL = 200 pF
1-16 Bytes
Symbol
Test
COUT
Output Capacitance
3
8
pF
Input Capacitance
2
6
pF
V
ns
500
ns
240
240
ns
500
500
ns
240
240
ns
15
15
ms
0
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 8)
CIN
VCC - 0.8
0
ns
AC Test Conditions
Output Load
Typ Max Units
CL = 200pF
Input Pulse Levels
0.1 * VCC - 0.9 * VCC
Timing Measurement Reference Level
0.3 * VCC - 0.7 * VCC
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, for a fOP of 1MHz, the period equals 1000ns. In this case if tCLH = is set to 410ns, then tCLL must be set to a minimum of 590ns.
Note 7: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
4
FM25C041U Rev. B
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FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 5)
tCSI
CS
tCSS
Mode 2
SCK
tCLH
tCLL
tCSH
Mode 2
Mode 1
Mode 1
tDIS
SI
tDIH
Valid Input
tPD
tDH
SO
tDF
High Z
Valid Output
FIGURE 2. SPI Protocol
CS
Mode 2
Mode 1
SCK
SI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
High Z
SO
Don't Care
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIGURE 3. HOLD Timing
CS
Low state ( /CS = 0)
tHDS tHDH
tHDS tHDH
Don't Care
SCK
HOLD
tLZ
tHZ
SO
Output (n+2)
Output (n+1)
Output (n)
High Z
Output (n)
tDIS
SI
Input (n+2)
Input (n+1)
Input (n)
Don't Care
5
FM25C041U Rev. B
Input (n)
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FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
FIGURE 1. Synchronous Data Timing Diagram
Functional Description
Chip Select (/CS)
The Serial Peripheral Interface (SPI) of FM25C041U consists of
an 8-bit Instruction register to decode a specific instruction to be
executed. Six different instructions (Opcodes) are incorporated
on FM25C041U for various operations. Table2 lists the instructions set and the format for proper operation. All Opcodes, Array
addresses and Data are transferred in “MSB first-LSB last”
fashion. Detailed information is provided under individual instruction descriptions.
This is an active low input pin to the EEPROM and is generated by
a master that is controlling the EEPROM. A low level on this pin
selects the EEPROM and a high level deselects the EEPROM. All
serial communications with the EEPROM is enabled only when
this pin is held low.
Serial Clock (SCK)
TABLE 2. Instruction Set
This is an input pin to the EEPROM and is generated by the master
that is controlling the EEPROM. This is a clock signal that
synchronizes the communication between a master and the
EEPROM. All input information (SI) to the EEPROM is latched on
the falling edge of this clock input, while output data (SO) from the
EEPROM is driven after the rising edge of this clock input.
Instruction Instruction
Name
Opcode
Serial Input (SI)
This is an input pin to the EEPROM and is generated by the master
that is controlling the EEPROM. The master transfers Input
information (Instruction Opcodes, Array addresses and Data)
serially via this pin into the EEPROM. This Input information is
latched on the falling edge of the SCK.
Serial Output (SO)
Operation
WREN
00000110
Write Enabled
WRDI
00000100
Write Disabled
RDSR
00000101
Read Status Register
WRSR
00000001
Write Status Register
READ
0000A011
Read Data from Memory
Array
WRITE
0000A010
Write Data to Memory Array
Note:
As the FM25C041U requires 9 address bits (4,096 ÷ 8 = 512 bytes = 29),
the 9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I3. This
convention only applies to 4K SPI protocol.
This is an output pin from the EEPROM and is used to transfer
Output data via this pin to the controlling master. Output data is
serially shifted out on this pin after the rising edge of the SCK.
In addition to the Instruction register, FM25C041U also contains
an 8-bit Status register that can be accessed by RDSR and WRSR
instructions. Only the least significant (LSB) 4 bits are defined at
present and the most significant (MSB) 4 bits are undefined (don’t
care). The LSB 4 bits define Block Write Protection levels (BP1and
BP0), Write-enable status (WEN) and Busy/Rdy status (/RDY) of
the EEPROM. Table 3 illustrates the format:
Hold (/HOLD)
This is an active low input pin to the EEPROM and is generated by
the master that is controlling the EEPROM. When driven low, this
pin suspends any current communication with the EEPROM. The
suspended communication can be resumed by driving this pin
high. This feature eliminates the need to re-transmit the entire
sequence by allowing the master to resume the communication
from where it was left off. This pin should be tied high if this feature
is not used. Refer Hold Function description for additional
details.
TABLE 3. Status Register Format
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
X
X
X
X
BP1
BP0
WEN
RDY
Write Protect (/WP)
Refer RDSR and WRSR instruction descriptions for additional
information on Status register operations.
This is an active low input pin to the EEPROM. This pin allows
enabling and disabling of writes to memory array and status
register of the EEPROM. When this pin is held low, writes to the
memory array and status register are disabled. When this pin is
held high, writes to the memory array and status register are
enabled. Status of this pin does not affect operations other than
array write and status register write. /WP signal going low at any
time will inhibit programming, except when an internal write has
already begun. If an internal write cycle has already begun, /WP
signal going low will have no effect on the write. Refer Table1 for
Write Protection matrix.
Table1. Write Protection Matrix
/WP Pin
WEN Bit
Status Register
Protected Blocks
(by BP1-BP0)
Unprotected Blocks
Low
X
Write Protected
Write Protected
Write Protected
High
0
Write Protected
Write Protected
Write Protected
High
1
Write Allowed
Write Protected
Write Allowed
6
FM25C041U Rev. B
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FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Pin Description
SPI Modes 1 and 2
SPI communication
FM25C041U supports both MODE 1 and MODE 2 of operations.
The difference between MODE 1 and MODE 2 is determined by
the state of the SCK clock signal when a SPI cycle starts (when /
CS is driven low) as well as when the SPI cycle ends (when /CS
is driven high). Under MODE 2 of operation, the SCK signal is held
low both at the start and at the end of a SPI cycle. Under Mode 1
of operation, the SCK signal is held high both at the start and at the
end of a SPI cycle. However in both of these two modes, the input
data (SI) is sampled (latched in) at the falling edge of the SCK
clock signal and the output data (SO) is driven after the rising edge
of the SCK clock signal. See Figure 1 and Figure 2.
As mentioned before, serial communication with the EEPROM is
enabled when the /CS pin is held low and the /HOLD pin is held
high. Input data (Instruction Opcodes, Array addresses and Data)
on the SI pin is latched in on the falling edges of SCK clock signal,
starting from the first falling edge after the /CS pin goes low. During
the time the SI data is input into the EEPROM, the SO pin remains
in high impedance state. If the intended instruction is of read
nature (Array read and Status register read), then data from the
EEPROM is driven out actively on the SO pin from every rising
edge of the SCK after the last input data (SI) is latched in. During
the time the SO data is output from the EEPROM, the data on the
SI pin is ignored. Figure 2 illustrates the above. Refer Figure 1 for
timing information.
READ SEQUENCE (READ)
Reading the memory via the serial SPI link requires the following
sequence. The /CS pin is pulled low to select the EEPROM. The
READ opcode is transmitted on the SI pin followed by the byte
address (A7–A0) to be read. After this is done, data on the SI pin
becomes don’t care. The data (D7–D0) at the address specified is
then shifted out on the SO pin. If only one byte is to be read, the
/CS pin can be pulled back to the high level. It is possible to
continue the READ sequence as the byte address is automatically
incremented and data will continue to be shifted out as clock
pulses are continuously applied. When the end of memory array
is reached (last byte location), the address counter rolls over to the
start of memory array (first byte location) allowing the entire
memory to be read in one continuous READ cycle. See Figure 5.
HOLD function
An active communication with the EEPROM can be temporarily
suspended by bringing the /HOLD pin low when a EEPROM is
selected (/CS pin should be low) and a serial sequence with the
EEPROM is currently underway. To suspend the communication,
/HOLD pin must be driven low while SCK is high, otherwise the
Hold function will not be invoked until the next SCK low to high
transition. The EEPROM must remain selected during this sequence. Transitions on the SCK and SI pins are ignored during the
time the part is suspended and the SO pin will be in high
impedance state. Releasing the /HOLD pin back to high state will
allow the operation to resume from the point it was suspended.
/HOLD pin must be driven high while the SCK pin is high,
otherwise serial communication will not resume until the next SCK
low to high transition. Asserting a low on the /HOLD pin at any time
will tri-state the SO pin. Figure 3 illustrates Hold timing.
FIGURE 5. Read Sequence
/CS
System Configuration
SERIAL CLOCK (SPICK)
SS0
SPI
SS1
CHIP
SELECTION
SS2
SS3
SI
SO
SCK
/CS
Data
(n)
TABLE 3. Status Register Format
SI
SO
SCK
/CS
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
X
X
X
X
BP1
BP0
WEN
RDY
Bit3 (BP1) and Bit2 (BP0) together indicate Block write protection
previously set on the EEPROM. Refer Table 2.
Bit1 (WEN) indicates the Write enable status of the EEPROM.
This bit is a read-only bit and is read by executing RDSR
instruction. If this bit is “1” then the EEPROM is write enabled. If
this bit is “0” then the EEPROM is write disabled.
SI
SO
SCK
/CS
Bit0 (/RDY) indicates the Busy/Ready status of the EEPROM.
This bit is a read-only bit and is read by executing RDSR
instruction. If this bit is “1” then the EEPROM is busy doing a
program cycle. If this bit is “0” then the EEPROM is ready.
SI
SO
SCK
/CS
Note that if a RDSR instruction is executed when an internal
programming cycle is in progress, only the /RDY bit is valid.
All other bits are don’t cares.
7
FM25C041U Rev. B
Data
(2)
The Read Status Register (RDSR) instruction provides read
access to the status register. As mentioned before, of the 8bits of
data, only the LSB 4bits are valid and they indicate Block Protection information (BP1 and BP0), Write Enable status (WEN) and
Busy/Ready status (/RDY) of the EEPROM. MSB 4bits of are
invalid (Don’t cares) Following is the format of RDSR data:
FM25Cxxx
DATA IN (MISO)
Data
(1)
READ STATUS REGISTER (RDSR):
FIGURE 4. System Configuration
DATA OUT (MOSI)
Byte
Addr
SO
When multiple SPI peripherals (for e.g. EEPROMs) are present on
the bus, the SI, SO and the SCK signals can be tied together.
Figure 4 illustrates a typical system configuration with respect to
/CS, SCK, SI and SO pins.
MASTER MCU
Read
Opcode
SI
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FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Functional Description (Continued)
TABLE 4. Block Write Protection Levels
Level
Status Register Bits
BP1
FIGURE 6. Read Status Register
Array
Address
Protected
BP0
0
0
0
None
1
0
1
180-1FF
2
1
0
100-1FF
3
1
1
000-1FF
/CS
RDSR
OP-CODE
SI
SO
A WRITE command requires the following sequence. The /CS pin
is pulled low to select the EEPROM, then the WRITE opcode is
transmitted on the SI pin followed by the byte address (A7-A0) and
followed by the data (D7-D0) to be written. See Figure 9.
RDSR DATA
WRITE ENABLE (WREN):
FIGURE 9. Byte Write
When VCC is applied to the EEPROM, it “powers up” in a writedisabled state. Therefore, all programming modes (Write to memory
array and Status register), must be preceded by a WRITE ENABLE (WREN) instruction. See Figure 7.
/CS
FIGURE 7. Write Enable
SI
Write
Op-Code
Byte
Addr
Data
/CS
High Z
SO
SI
Internally, the programming will start after the /CS pin is brought
back to a high level. Note that the LOW to HIGH transition of the
/CS pin must occur during the SCK low time immediately after
clocking in the D0 data bit. See Figure 10.
WREN Op-Code
SO
FIGURE 10. Start of Programming
WRITE DISABLE (WRDI):
Executing this instruction disables all programming modes (Write
to memory array and Status register), preventing the EEPROM
from accidental writes. Once WRDI instruction is executed,
WREN instruction should be executed to re-enable all programming modes. See Figure 8.
/CS
Start of internal
programming
SCK
FIGURE 8. Write Disable
SI
D2
D1
D0
/CS
SO
SI
Programming status (Busy/Ready) of the EEPROM can be determined by executing a READ STATUS REGISTER (RDSR) instruction after a write command. Upon executing the RDSR
instruction, if Bit 0 of the RDSR data is “1”, it indicates the WRITE
cycle is still in progress. If it is “0” then the WRITE cycle has ended.
Note that while the internal programming is still in progress (Bit 0
= 1), only the RDSR instruction is enabled. It is recommended that
no other instruction be issued till the internal programming is
complete.
WRDI Op-Code
SO
WRITE SEQUENCE (WRITE):
Write to the array is enabled only when /WP pin is held high and
the EEPROM is write enabled previously (via WREN instruction).
Also, the address of the memory location(s) to be programmed
must be outside the protected address field selected by the Block
Write Protection Level. See Table 4.
8
FM25C041U Rev. B
High Z
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FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
The RDSR command requires the following sequence. The /CS
pin is pulled low to select the EEPROM and then the RDSR
opcode is transmitted on the SI pin. After this is done, data on the
SI pin becomes don’t care. The data from the Status Register is
then shifted out on the SO pin starting with D7 bit first and D0 last.
See Figure 6.
/CS
Programming will start after the /CS pin is forced back to a high
level. As in the WRITE instruction the LOW to HIGH transition of
the /CS pin must occur during the SCK low time immediately after
clocking in the last don’t care bit. See Figure 13.
/CS
Write
Op-Code
Byte
Addr
SR Data
xxxxBP1BP0xx
SO
FIGURE 11. Page Write
SI
WRSR
Op-Code
SI
Data
(1)
Data
(2)
Data
(3)
FIGURE 13. Start WRSR Condition
Data
(4)
/CS
SO
At the completion of a write cycle the EEPROM is automatically
returned to the write disabled state. Note that if the EEPROM is not
write enabled (WEN=0) before issuing the WRITE instruction, the
EEPROM will ignore the WRITE instruction and return to the
standby state when /CS is brought high.
SCK
SI
BP0
WRITE STATUS REGISTER (WRSR):
SO
The Write Status Register (WRSR) instruction provides write
access to the status register. This instruction is used to set Block
Write protection to a portion of the array as defined under Table
4. During a WRSR instruction only Bit3 (BP1) and Bit2 (BP0) can
be written with valid information while other bits are ignored.
Following is the format of WRSR data:
At the completion of this instruction the EEPROM is automatically
returned to write disabled state.
INVALID OPCODE
If an invalid code is received, then no data is shifted into the
EEPROM, and the SO data output pin remains high impedance
state until a new /CS falling edge reinitializes the serial communication. See Figure 14.
Status Register Write Data
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
X
X
X
X
BP1
BP0
X
X
FIGURE 14. Invalid Op-Code
X = Don’t Care
/CS
Note that the first four bits are don’t care bits followed by BP1 and
BP0 and two more don’t care bits.
SI
WRSR instruction is enabled only when /WP pin is held high and
the EEPROM is write enabled previously (via WREN instruction).
WRSR command requires the following sequence. The /CS pin is
pulled low to select the EEPROM and then the WRSR opcode is
transmitted on the SI pin followed by the data to be programmed.
See Figure 12.
SO
9
FM25C041U Rev. B
INVALID CODE
www.fairchildsemi.com
FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
FIGURE 12. Write Status Register
The FM25C041U is also capable of a 4 byte PAGE WRITE
operation. Page write is performed similar to byte write operation
described above. During a Page write operation, after the first byte
of data, additional bytes (up to 3 bytes) can be input, before
bringing the /CS pin high to start the programming. After receipt of
each byte of data, the EEPROM internally increments the two low
order address bits (A1-A0) by one. The high order address bits
(A8-A2) will remain constant. If the master should transmit more
than 4 bytes of data, the address counter (A1-A0) will “roll over”
and the previously loaded data will be reloaded. See Figure 11.
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.004
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Package Number M08A
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
2
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
3
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
10
FM25C041U Rev. B
www.fairchildsemi.com
FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0118
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Note: Metal mask option for 16-byte page size.
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
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11
FM25C041U Rev. B
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Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
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FM25C041U 4K-Bit SPI Interface Serial CMOS EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted