SEMTECH SC1165

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
October 25, 1999
DESCRIPTION
The SC1164/5 combines a synchronous voltage mode
controller with two low-dropout linear regulators
providing most of the circuitry necessary to implement
three DC/DC converters for powering advanced
®
microprocessors such as Pentium II.
The SC1164/5 switching section features an integrated
5 bit D/A converter, pulse by pulse current limiting,
integrated power good signaling, and logic compatible
shutdown. The SC1164/5 switching section operates at
a fixed frequency of 200kHz, providing an optimum
compromise between size, efficiency and cost in the
intended application areas. The integrated D/A converter provides programmability of output voltage from
2.0V to 3.5V in 100mV increments and 1.30V to 2.05V
in 50mV increments with no external components.
The SC1164/5 linear sections are low dropout regulators. The SC1164 supplies 1.5V for GTL bus and 2.5V
for non-GTL I/O.
For the SC1165 both LDO’s are adjustable.
FEATURES
• Synchronous design, enables no heatsink solution
• 95% efficiency (switching section)
• 5 bit DAC for output programmability
• On chip power good function
• Designed for Intel Pentium® ll requirements
• 1.5V, 2.5V or Adj. @ 1% for linear section
APPLICATIONS
• Pentium® ll or Deschutes microprocessor supplies
• Flexible motherboards
• 1.3V to 3.5V microprocessor supplies
• Programmable triple power supplies
ORDERING INFORMATION
(1)
Part Number
Package
SC1164CSW
SO-24
SC1165CSW
SO-24
Linear
Voltage
Temp.
Range (TJ)
1.5V/2.5V 0° to 125°C
Adj.
0° to 125°C
Note:
(1) Add suffix ‘TR’ for tape and reel.
PIN CONFIGURATION
BLOCK DIAGRAM
REF.
Top View
AGND
GATE1
LDOS1
LDOS2
VCC
OVP
PWRGOOD
CSCS+
PGNDH
DH
PGNDL
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GATE2
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
FET
CONTROLLER
2.5V/ADJ.
1.265V
REF.
FET
CONTROLLER
1.5V/ADJ.
(24 Pin SOIC)
LDOV
Pentium is a registered trademark of Intel Corporation
© 1999 SEMTECH CORP.
1
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
ABSOLUTE MAXIMUM RATINGS
Parameter
VCC to GND
PGND to GND
BST to GND
Operating Temperature Range
Symbol
VCC
Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering) 10 seconds
Thermal Impedance Junction to Ambient
Thermal Impedance Junction to Case
TA
Maximum
-0.3 to +7
±1
-0.3 to +15
0 to +70
Units
V
V
V
°C
TJ
TSTG
0 to +125
-65 to +150
°C
°C
TL
300
80
25
°C
°C/W
°C/W
θJA
θJC
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 25°C
PARAMETER
Switching Section
Output Voltage
Supply Voltage
Supply Current
Load Regulation
Line Regulation
Current Limit Voltage
Oscillator Frequency
Oscillator Max Duty Cycle
Peak DH Sink/Source Current
Peak DL Sink/Source Current
Output Voltage Tempco
Gain (AOL)
OVP threshold voltage
OVP source current
Power good threshold voltage
Dead time
Linear Sections
Quiescent current
Output Voltage (LDO1 SC1164)
Output Voltage (LDO2 SC1164)
Reference Voltage (SC1165)
Feedback Pin Bias Current (SC1165)
Gain (AOL)
Load Regulation
Line Regulation
Output Impedance
Notes: (1) See Output Voltage table.
(2) In application circuit.
© 1999 SEMTECH CORP.
CONDITIONS
MIN
IO = 2A
VCC
VCC = 5.0V
IO = 0.8A to 15A
BSTH-DH = 4.5V, DH-PGNDH = 3V
BSTL-DL = 4.5V, DL-PGNDL = 3V
55
175
90
1
1
LDOS (1,2) to GATE (1,2)
(2)
IO = 0 to 8A
8
1
0.5
70
200
95
7
15
85
225
65
35
120
10
85
50
LDOV = 12V
MAX
UNITS
See Note 1.
4.5
VOSENSE to VO
VOVP = 3.0V
TYP
115
100
5
2.475 2.500 2.525
1.485 1.500 1.515
1.252 1.265 1.278
10
90
0.3
0.3
1
V
mA
%
%
mV
kHz
%
A
A
o
ppm/ C
dB
%
mA
%
ns
mA
V
V
V
uA
dB
%
%
KΩ
2
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
PIN DESCRIPTION
Pin
1
2
3
4
5
6
Pin Name
AGND
GATE1
LDOS1
LDOS2
VCC
OVP
7
8
9
10
11
12
13
14
15
16
PWRGOOD
CSCS+
PGNDH
DH
PGNDL
DL
BSTL
BSTH
(1)
EN
17
18
19
20
21
22
23
24
VOSENSE
(1)
VID4
(1)
VID3
(1)
VID2
(1)
VID1
(1)
VID0
LDOV
GATE2
(1)
Pin Function
Small Signal Analog and Digital Ground
Gate Drive Output LDO1
Sense Input for LDO1
Sense Input for LDO2
Input Voltage
High Signal out if VO>setpoint +20%
Open collector logic output, high if VO
within 10% of setpoint
Current Sense Input (negative)
Current Sense Input (positive)
Power Ground for High Side Switch
High Side Driver Output
Power Ground for Low Side Switch
Low Side Driver Output
Supply for Low Side Driver
Supply for High Side Driver
Logic low shuts down the converter;
High or open for normal operation.
Top end of internal feedback chain
Programming Input (MSB)
Programming Input
Programming Input
Programming Input
Programming Input (LSB)
+12V for LDO section
Gate Drive Output LDO2
Top View
AGND
GATE1
LDOS1
LDOS2
VCC
OVP
PWRGOOD
CSCS+
PGNDH
DH
PGNDL
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GATE2
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
(24 Pin SOIC)
Note:
(1) All logic level inputs and outputs are open
collector TTL compatible.
3
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
OUTPUT VOLTAGE
Unless specified: VCC = 5.00V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; TA = 25oC
PARAMETER
Output Voltage
CONDITIONS
IO = 2A in Application Circuit
VID
MIN
43210
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
1.274
1.323
1.372
1.421
1.470
1.527
1.576
1.625
1.675
1.724
1.773
1.822
1.871
1.921
1.970
2.019
1.940
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
TYP
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
MAX
UNITS
1.326
1.377
1.428
1.479
1.530
1.573
1.624
1.675
1.726
1.776
1.827
1.878
1.929
1.979
2.030
2.081
2.060
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
4
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
© 1999 SEMTECH CORP.
2
4
VID2
VID3
+
+
C22
330uF
(NORMALLY 3.3V)
PWRGD
VID4
24
12
VID1
VID0
VINLIN
330uF
C21
19
20
21
22
6
1
C5
0.1uF
U1
R14 *
R18 **
100k
SC1164/5CSW
LDOS2
GATE1
GATE2
PGNDL
AGND
EN
VID3
VID2
VID1
VID0
OVP
VCC
CS+
9
Q4
BUK556
R15 *
LDOS1
VDD
BSTL
DL
PGNDH
DH
BSTH
VID4
PWRGOOD
VO SENSE
CS-
C9
330uF
3
23
14
13
10
11
15
18
7
17
8
+
+
0.1uF
C13
R17 **
100k
BUK556
Q3
R13 *
R4
5mOhm
1.00k
R6
C14
1500uF
+
+
+
C12
330uF
+
+
C17
1500uF
C16
1500uF
C11
330uF
+
C15
1500uF
2.32k
R5
C18
0.1uF
VLIN2
VLIN1
VCC_CORE
** R17, R18 REQUIRED IF VINLIN CAN BE PRESENT WITHOUT 12V BEING
PRESENT.
* SEE "SETTING LDO OUTPUT VOLTAGE" TABLE
NOTE: FOR SC1164, R12, R13, R14 AND R14 ARE NOT REQUIRED,
CONNECT LDOS1 (PIN3) DIRECTLY TO VLIN1 TO GENERATE 2.5V OUTPUT.
CONNECT LDOS2 (PIN4) DIRECTLY TO VLIN2 TO GENERATE 1.5V OUTPUT.
4uH
L1
Q1
BUK556
R12 *
C10
330uF
Q2
BUK556
TBD
10
5
R16
R1
OVP
C3
1500uF
+
16
C2
1500uF
+
EN
C1
0.1uF
5V
12V
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
APPLICATION CIRCUIT
5
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
MATERIALS LIST
Qty. Reference
Part/Description
Vendor
Notes
4
C1,C5,C13,C 0.1µF Ceramic
18
Various
6
C2,C3,C14C17
1500µF/6.3V
SANYO
6
C9-C12,
C21, C22
330µF/6.3V
Various
1
L1
4µH
4
Q1,Q2,Q3,
Q4
See notes
See notes
FET selection requires trade-off between efficiency and
cost. Absolute maximum RDS(ON) = 22 mΩ for Q1,Q2
1
R4
5mΩ
IRC
OAR-1 Series
1
R5
2.32kΩ, 1%, 1/8W
Various
1
R6
1kΩ, 1%, 1/8W
Various
1
R1
10Ω, 5%, 1/8W
Various
1
R12
1%, 1/8W
Various
See Table Below (Not required for SC1164)
1
R13
1%, 1/8W
Various
See Table Below (Not required for SC1164)
1
R14
1%, 1/8W
Various
See Table Below (Not required for SC1164)
1
R15
1%, 1/8W
Various
See Table Below (Not required for SC1164)
2
R17,R18
100kΩ, 5%,1/8W
Various
Required if Voltage is applied to the linear FET(s) without
12V applied to SC1164/5
1
U1
SC1164/5CSW
SEMTECH
MV-GX or equiv. Low ESR
8 Turns 16AWG on MICROMETALS T50-52D core
SETTING LDO OUTPUT VOLTAGE
1.265 ⋅ (R A + R B )
+ (IFB ⋅ R A )
RB
RB
RA
VOUT LDO1 (LDO2)
R12 (R14)
R13 (R15)
3.45V
105Ω
182Ω
3.30V
105Ω
169Ω
3.10V
102Ω
147Ω
2.90V
100Ω
130Ω
See layout diagram for clarification
2.80V
100Ω
121Ω
R A and R B must be low enough so
2.50V
100Ω
97.6Ω
that the (IFB ⋅ R A ) term does not cause
1.50V
100Ω
18.7Ω
significant error
VOUT =
Where :
IFB = Feedback pin bias current
R A = Top feedback resistor
R B = Bottom feedback resistor
6
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
95%
95%
90%
90%
85%
85%
Efficiency
Efficiency
October 25, 1999
80%
3.5V Std
3.5V Sync
3.5V Sync Lo Rds
75%
80%
2.8V Std
2.8V Sync
2.8V Sync Lo Rds
75%
70%
70%
0
2
4
6
8
10
12
14
0
16
2
4
6
10
12
14
16
10
12
14
16
Typical Efficiency at Vo=2.8V
95%
95%
90%
90%
85%
85%
Efficiency
Efficiency
Typical Efficiency at Vo=3.5V
80%
2.5V Std
2.5V Sync
2.5V Sync Lo Rds
75%
8
Io (Amps)
Io (Amps)
80%
2.0V Std
2.0V Sync
2.0V Sync Lo Rds
75%
70%
70%
0
2
4
6
8
Io (Amps)
10
12
14
16
0
2
4
6
8
Io (Amps)
Typical Efficiency at Vo=2.5V
Typical Efficiency at Vo=2.0V
Typical Ripple, Vo=2.8V, Io=10A
Transient Response Vo=2.8V, Io=300mA to 10A
7
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
as small as possible. This loop contains all the high current, fast transition switching. Connections should be as
wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b)
lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate
switching signals.
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1164/5 PWM
controller. High currents switching at 200kHz are present in the application and their effect on ground plane
voltage differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such
as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the input capacitor and bottom FET ground.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection between the output inductor and the sense resistor should
be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length
is not so important, however adding unnecessary
impedance will reduce efficiency.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
12V IN
5V
10
1
2
3
4
0.1uF
5
6
0.1uF
7
8
9
10
11
12
AGND
GATE2
GATE1
LDVO
LDOS1
VID0
LDOS2
VID1
VCC
VID2
OVP
VID3
PWRGOOD
VID4
CS-
VOSENSE
CS+
EN
PGNDH
BSTH
DH
BSTL
PGNDL
DL
24
23
2.32k
22
Cin
21
Q1
+
1.00k
20
5mOhm
Vout
19
4uH
18
+
Q2
Cout
17
16
15
14
13
SC1164/5
RA1
5V
Vo Lin1
Q3
+
Heavy lines indicate
high current paths.
+
RB1
Cout Lin1
Cin Lin
For SC1164, RA1, RA2, RB1 and RB2
are not required. LDOS1 connects to
Vo Lin1, LDOS2 connects to Vo Lin2
RA2
Vo Lin2
Q4
+
RB2
Cout Lin2
Layout diagram for the SC1164/5
8
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
4) The Output Capacitor(s) (Cout) should be located
as close to the load as possible, fast transient load
currents are supplied by Cout only, and connections
between Cout and the load must be short, wide copper areas to minimize inductance and resistance.
5) The SC1164/5 is best placed over a quiet ground
plane area, avoid pulse currents in the Cin, Q1, Q2
loop flowing in this area. PGNDH and PGNDL should
be returned to the ground plane close to the package.
The AGND pin should be connected to the ground
side of (one of) the output capacitor(s). If this is not
possible, the AGND pin may be connected to the
ground path between the Output Capacitor(s) and the
Cin, Q1, Q2 loop. Under no circumstances should
AGND be returned to a ground inside the Cin, Q1, Q2
loop.
5V supply through a 10Ω resistor, the Vcc pin should
be decoupled directly to AGND by a 0.1µF ceramic
capacitor, trace lengths should be as short as possible.
7) The Current Sense resistor and the divider across
it should form as small a loop as possible, the traces
running back to CS+ and CS- on the SC1164/5 should
run parallel and close to each other. The 0.1µF capacitor should be mounted as close to the CS+ and
CS- pins as possible.
8) Ideally, the grounds for the two LDO sections
should be returned to the ground side of (one of) the
output capacitor(s).
6) Vcc for the SC1164/5 should be supplied from the
5V
+
Vout
+
Currents in various parts of the power section
9
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the
most critical component. Because of fast transient load
current requirements in modern microprocessor core
supplies, the output capacitors must supply all transient
load current requirements until the current in the output
inductor ramps up to the new level. Output capacitor
ESR is therefore one of the most important criteria. The
maximum ESR can be simply calculated from:
R ESR
ILRIPPLE=
V
≤ t
It
Vt = Maximum transient voltage excursion
It = Transient current step
For example, to meet a 100mV transient limit with a
10A load step, the output capacitor ESR must be less
than 10mΩ. To meet this kind of ESR level, there are
three available capacitor technologies.
Each Capacitor
C
(µF)
ESR
(mΩ)
C
(µF)
ESR
(mΩ)
Low ESR Tantalum
330
60
6
2000
10
OS-CON
330
25
3
990
8.3
1500
44
5
7500
8.8
Low ESR Aluminum
The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the
cheapest, but taking up the most space.
INDUCTOR - Having decided on a suitable type and
value of output capacitor, the maximum allowable
value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will
cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above.
The maximum inductor value may be calculated from:
L≤
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a
combination of conduction losses, switching losses and
bottom FET body diode recovery losses.
a) Conduction losses are simply calculated as:
PCOND = IO2 ⋅ RDS( on ) ⋅ δ
Total
Qty.
Rqd.
VIN
4⋅L⋅ fOSC
Ripple current allowance will define the minimum permitted inductor value.
Where
Technology
fast enough to reduce the voltage dropped across the
ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional
excursions.
We must also be concerned with ripple current in the
output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced
by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
R ESR C
(VIN − VO )
It
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp
where
δ = duty cycle ≈
VO
VIN
b) Switching losses can be estimated by assuming a
switching time, if we assume 100ns then:
PSW = I O ⋅ V IN ⋅ 10 − 2
or more generally,
PSW =
IO ⋅ VIN ⋅ ( t r + t f ) ⋅ fOSC
4
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The resulting power dissipation in the top FET
will be:
PRR = Q RR ⋅ VIN ⋅ f OSC
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
10
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
FET type
RDS(on) (mΩ) PD (W)
Package
BUK556H 22
2.48
TO220
IRL2203
7.0
0.79
D PAK
Si4410
13.5
1.53
SO-8
2
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined by:
INPUT CAPACITORS - since the RMS ripple current in
the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may
be restrictions on input di/dt. These restrictions require
useable energy storage within the converter circuitry,
either as extra output capacitance or, more usually,
additional input capacitors. Choosing low ESR input
capacitors will help maximize ripple rating for a given
size.
PCOND = I O2 ⋅ R DS ( on ) ⋅ (1 − δ )
For the example above:
FET type
RDS(on) (mΩ) PD (W)
Package
BUK556H 22
1.95
TO220
IRL2203
7.0
0.62
D PAK
Si4410
13.5
1.20
SO-8
2
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed
o
circuit board material, thermal impedances of 40 C/W
2
o
for the D PAK and 80 C/W for the SO-8 are readily
achievable. The corresponding temperature rise is detailed below:
o
Temperature rise ( C)
FET type
Top FET
(1)
Bottom FET
(1)
BUK556H 49.6
39.0
IRL2203
31.6
24.8
122.4
96
Si4410
o
(1) With 20 C/W Heatsink
It is apparent that single SO-8 Si4410 are not adequate for
this application, but by using parallel pairs in each position, power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
11
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1164/5
October 25, 1999
OUTLINE DRAWING - SO-24
JEDEC MS-013AD
B17104B
ECN 99-667
12
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320