SK10/100EL15W 1:4 Clock Distribution HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100EL15W is a low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. This device is fully compatible with MC10EL15 & MC100EL15. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used, the VBB output should be connected to the CLK* input and bypassed to VCC via a 0.01 µF capacitor. The EL15W provides a VBB output for either single-ended use or as a DC bias for AC coupling to the device. The VBB pin should be used only as a bias for EL15W as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to VCC via a 0.01 µF capacitor. • • • • • • • • • The EL15W features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. Extended Supply Voltage Range: (VEE = –5.5V to –3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V, VEE=0V) 50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input 75KΩ Internal Input Pull-Down Resistors Fully Compatible with MC10EL15 and MC100EL15 Specified Over Industrial Temperature Range: –40oC to +85oC ESD Protection of >4000V Available in 16-Pin SOIC Package PIN Description Pin Name The common enable (EN*) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Functional Block Diagram Q0 1 Q0* 2 Q1 3 Q1* 4 Q D Function CLK Differential Clock Inputs SCLK Synchronous Clock Input EN* Synchronous Enable SEL Clock Select Input VBB Reference Output Voltage Q0Q3, Q0*-Q3* Differential Clock Outputs CLK SCLK SEL EN* Q EN* L X L L L 14 SCLK H X L L H 13 CLK X L H L L 16 VCC 15 1 0 Q2 5 12 CLK* X H H L H Q2* 6 11 VBB X X X H L* Q3 7 10 SEL Q3* 8 9 VEE Revision 1/February 12, 2001 *On next negative transition of CLK or SCLK. Truth Table 1 www.semtech.com SK10/100EL15W HIGH-PERFORMANCE PRODUCTS Package Information 16 Pin SOIC Package –A– 0.25 (0.010) M B S 9 –B 8 M 1 P 8 PL R x 45 ˚ 16 G C SEATING PLANE F –T– 0.25 (0.010) M T B S J D 168 PL A S K MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9/80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0o 7o 0o 7o P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 Revision 1/February 12, 2001 NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 2. Controlling dimension: millimeter. 3. Dimensions A and B do not include mold protrusion. 4. Maximum mold protrusion 0.150 (0.006) per side. 5. Dimension D does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. 2 www.semtech.com SK10/100EL15W HIGH-PERFORMANCE PRODUCTS DC Characteristics SK10/100EL15W DC Electrical Characteristics (Notes 1, 2) (VCC – VEE = +3.0V to +5.5V ; VOUT loaded 50Ω to VCC – 2.0V) TA = –40oC S y mb o l Ch a r a c t e r i s t i c IIN I nput Cur r ent ( Di f f ) ( SE) I EE Power Supply Cur rent 10EL 100EL VBB Output Reference Voltage5 10EL 100EL VCC VEE Power Supply Voltage Mi n TA = 0oC Typ Ma x Mi n - 150 150 150 20 21 35 35 1. 43 1. 38 Typ Ma x Mi n - 150 150 150 21 21 36 36 1. 30 1. 38 1. 26 1. 38 3. 0 5. 5 TA = +25oC Ma x Mi n - 150 150 150 21 22 36 38 1. 27 1. 35 1. 26 1. 38 3. 0 5. 5 3. 0 Typ TA = +85oC Typ Ma x Un i t - 150 150 150 µA µA 22 24 38 41 mA mA 1. 19 1. 26 mV mV 5. 5 V 1. 25 1. 31 1. 26 1. 38 5. 5 3. 0 AC Characteristics SK10/100EL15W AC Electrical Characteristics (VCC – VEE = +3.0V to +5.5V ; VOUT loaded 50Ω to VCC – 2.0V) TA = –40oC Symbol Characteristic t PLH t P HL Propagation Delay CL K t o Q ( Di f f ) CLK t o Q ( SE) SCLK t o Q TA = 0oC TA = +25oC TA = +85oC Min Max Min Max Min Max Min Max Un i t 560 470 465 650 710 685 580 500 495 675 695 700 591 510 510 695 680 705 620 545 566 740 725 745 ps ps ps 200 50 ps ps tskew Par t-to-Par t Skew Within-Device SkeW tS S e t u p T i me E N * 150 150 150 150 ps tH H o l d T i me E N * 400 400 400 400 ps VPP Mi n i mu m I n p u t S w i n g C L K 3 250 V C MR tr , tf C o mmo n Mo d e R a n g e C L K 4 V P P < 5 0 0 mV V P P > 5 0 0 mV Output Rise/Fall Times Qn , Qn * ( 2 0 % t o 8 0 %) Revision 1/February 12, 2001 200 50 1000 VEE + 1. 3 VCC 0. 4 VEE + 1. 5 VCC 0. 4 195 340 200 50 250 1000 VEE + 1. 3 VEE + 1. 5 VCC 0. 4 VCC 0. 4 205 350 3 200 50 250 1000 250 VEE + 1. 3 VCC 0. 4 VEE + 1. 3 VEE + 1. 5 VCC 0. 4 VEE + 1. 5 210 360 225 1000 mV VCC 0. 4 VCC 0. 4 V V 380 ps www.semtech.com SK10/100EL15W HIGH-PERFORMANCE PRODUCTS AC Characteristics (continued) Notes: 1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω resistor to VCC –2.0V. 2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow greater than 500 lfpm is maintained. 3. Minimum input swing for which AC parameters guaranteed. 4. CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.3V for VPP < 500 mV and VEE + 1.5V for VPP > 500 mV. 5. Voltages referenced to VCC = 0V (ECL mode). 6. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data Sheet. 7. For part ordering descriptions, see HPP Part Ordering Information Data Sheet. Ordering Information Ordering Code Package ID Temperature Range SK10EL15WD 16-SOIC Industrial SK10EL15WDT 16-SOIC Industrial SK100EL15WD 16-SOIC Industrial SK100EL15WDT 16-SOIC Industrial SK10EL15WU Die SK100EL15WU Die Contact Information Division Headquarters 10021 Willow Creek Road San Diego, CA 92131 Phone: (858) 695-1808 FAX: (858) 695-2633 Revision 1/February 12, 2001 Semtech Corporation High-Performance Products Division 4 Marketing Group 1111 Comstock Street Santa Clara, CA 95054 Phone: (408) 566-8776 FAX: (408) 727-8994 www.semtech.com