SPANSION S29GL-A

S29GL-A MirrorBit™ Flash Family
S29GL064A, S29GL032A, and S29GL016A
64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 200 nm MirrorBit Process Technology
Data Sheet
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S29GL-A_00
Revision A
Amendment 3
Issue Date April 22, 2005
A d v a n c e
I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
S29GL-A MirrorBit™ Flash Family
S29GL064A, S29GL032A, and S29GL016A
64 Megabit, 32 Megabit, and 16 Megabit
3.0-Volt only Page Mode Flash Memory
Featuring 200 nm MirrorBit Process Technology
ADVANCE
INFORMATION
Data Sheet
Distinctive Characteristics
Architectural Advantages
„
Single power supply operation
— 3 volt read, erase, and program operations
„
Manufactured on 200 nm MirrorBit process
technology
„
Secured Silicon Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
„
Flexible sector architecture
— 64Mb (uniform sector models): 128 32 Kword (64 KB)
sectors
„
Low power consumption (typical values at 3.0 V, 5
MHz)
— 18 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
„
Package options
— 48-pin TSOP
— 56-pin TSOP
— 64-ball Fortified BGA
— 48-ball fine-pitch BGA
Software & Hardware Features
„
— 64Mb (boot sector models): 127 32 Kword (64 KB)
sectors + 8 4Kword (8KB) boot sectors
— 32Mb (uniform sector models): 64 32Kword (64KB)
sectors
— 32Mb (boot sector models): 63 32Kword (64KB)
sectors + 8 4Kword (8KB) boot sectors
— 16MB (boot sector models): 31 31Kword (64KB)
sectors + 8 4Kword (8KB) boot sectors
„
Compatibility with JEDEC standards
— Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write
protection
„
100,000 erase cycles typical per sector
„
20-year data retention typical
Performance Characteristics
„
High performance
— 90 ns access time
— 4-word/8-byte page read buffer
— 25 ns page read times
— 16-word/32-byte write buffer which reduces overall
programming time for multiple-word updates
Publication Number S29GL-A_00
Revision A
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
— Unlock Bypass Program command reduces overall
multiple-word programming time
„
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
charging code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings on uniform
sector models
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
Amendment 3
Issue Date April 22, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
General Description
The S29GL-A family of devices are 3.0 V single power Flash memory manufactured using 200 nm MirrorBit technology. The S29GL064A is a 64-Mb device
organized as 4,194,304 words or 8,388,608 bytes. The S29GL032A is a 32-Mb
device organized as 2,097,152 words or 4,194,304 bytes. The S29Gl016A is a
16 Mb device organized as 1,048,576 words or 2,097,152 bytes. Depending on
the model number, the devices have an 8-bit wide data bus only, 16-bit wide
data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide
data bus by using the BYTE# input. The devices can be programmed either in
the host system or in standard EPROM programmers.
Access times as fast as 90 ns are available. Note that each access time has a
specific operating voltage range (VCC) as specified in the Product Selector Guide
and the Ordering Information–S29GL016A, Ordering Information–S29GL032A,
and Ordering Information–S29GL064A. Package offerings include 48-pin TSOP,
56-pin TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA, depending on
model number. Each device has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a VCC input, a high-voltage accelerated program
(ACC) feature provides shorter programming times through increased current
on the WP#/ACC input. This feature is intended to facilitate factory throughput
during system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-powersupply Flash standard. Commands are written to the device using standard
microprocessor write timing. Write cycles also internally latch addresses and
data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation begins, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause
an erase operation in a given sector to read or program any other sector and
then complete the erase operation. The Program Suspend/Program Resume
feature enables the host system to pause a program operation in a given sector
to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would thus also reset the de-
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S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
vice, enabling the host system to read boot-up firmware from the Flash memory
device.
The device reduces power consumption in the standby mode when it detects
specific voltage levels on CE# and RESET#, or when addresses are stable for a
specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting
a logic low on the WP#/ACC pin or WP# pin, depending on model number. The
protected sector is still protected even during accelerated programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or
data that can be permanently protected. Once this sector is protected, no further
changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron
injection.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
3
A d v a n c e
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Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
S29GL064A, S29GL032A, S29GL016A .............................................................6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic Symbol–S29GL064A (Models R1, R2, R8, R9) ................................... 11
Logic Symbol–S29GL064A (Model R5) .......................................................... 12
Logic Symbol–S29GL064A (Model R6, R7) .................................................. 12
Logic Symbol–S29GL032A (Models R1, R2) ..................................................13
Logic Symbol–S29GL032A (Models R3, R4) ..................................................13
Logic Symbol–S29GL016A (Models R1, R2) ...................................................13
Ordering Information–S29GL016A . . . . . . . . . . . 14
S29GL016A Standard Products ........................................................................ 14
Table 1. S29GL016A Ordering Options .................................... 14
Ordering Information–S29GL032A . . . . . . . . . . . 15
S29GL032A Standard Products .........................................................................15
Table 2. S29GL032A Ordering Options .................................... 15
Ordering Information–S29GL064A . . . . . . . . . . . 16
S29GL064A Standard Products ....................................................................... 16
Unprotection Addresses ........................................................ 34
Table 25. S29GL064A (Models R6, R7) Sector Group Protection/
Unprotection Addresses ........................................................ 34
Temporary Sector Group Unprotect ............................................................35
Figure 1. Temporary Sector Group Unprotect Operation ............ 35
Figure 2. In-System Sector Group Protect/Unprotect Algorithms 36
Secured Silicon Sector Flash Memory Region ............................................ 37
Write Protect (WP#) ........................................................................................ 38
Hardware Data Protection ............................................................................... 38
Common Flash Memory Interface (CFI) . . . . . . 40
Table 26. CFI Query Identification String ................................ 40
Command Definitions . . . . . . . . . . . . . . . . . . . . . 44
Reading Array Data ............................................................................................44
Reset Command ..................................................................................................44
Autoselect Command Sequence ..................................................................... 45
Enter/Exit Secured Silicon Sector Command Sequence .......................... 45
Figure 3. Write Buffer Programming Operation......................... 49
Figure 4. Program Operation ................................................. 50
Program Suspend/Program Resume Command Sequence .....................50
Figure 5. Program Suspend/Program Resume.......................... 51
Table 3. S29GL064A Valid Combinations ................................. 17
Chip Erase Command Sequence ..................................................................... 51
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 18
Sector Erase Command Sequence . . . . . . . . . . . 53
Table 4. Device Bus Operations ............................................. 18
Figure 6. Erase Operation ..................................................... 54
Word/Byte Configuration ..................................................................................19
Requirements for Reading Array Data .......................................................... 19
Writing Commands/Command Sequences .................................................. 19
Standby Mode ....................................................................................................... 20
Automatic Sleep Mode ....................................................................................... 21
RESET#: Hardware Reset Pin .......................................................................... 21
Output Disable Mode ......................................................................................... 21
Erase Suspend/Erase Resume Commands ................................................... 54
Command Definitions .........................................................................................56
Table 5. S29GL016A (Model R1) Top Boot Sector Addresses ...... 22
Table 6. S29GL016A (Model R2) Bottom Boot Sector
Addresses ........................................................................... 22
Table 7. S29GL032A (Models R1, R2) Sector Addresses ............ 23
Table 8. S29GL032A (Model R3) Top Boot Sector Addresses ...... 24
Table 9. S29GL032A (Model R4) Bottom Boot Sector Addresses . 24
Table 10. S29GL064A (Models R1, R2, R8, R9) Sector Addresses 25
Table 11. S29GL064A (Model R3) Top Boot Sector
Addresses ........................................................................... 26
Table 12. S29GL064A (Model R4) Bottom Boot Sector Addresses 27
Table 13. S29GL064A (Model R5) Sector Addresses ................. 28
Table 14. S29GL064A (Models R6, R7) Sector Addresses .......... 29
Autoselect Mode ................................................................................................. 30
Table 15. Autoselect Codes, (High Voltage Method) ................. 31
Sector Group Protection and Unprotection ................................................31
Table 16. S29GL016A (Model R1) Sector Group Protection/
Unprotection Addresses ........................................................ 32
Table 17. S29GL016A (Model R2) Sector Group Protection/
Unprotection Addresses ........................................................ 32
Table 18. S29GL032A (Models R1, R2) Sector Group Protection/
Unprotection Addresses ........................................................ 32
Table 19. S29GL032A (Models R3) Sector Group Protection/
Unprotection Address Table .................................................. 32
Table 20. S29GL032A (Models R4) Sector Group Protection/
Unprotection Address Table .................................................. 33
Table 21. S29GL064A (Models R1, R2, R8, R9) Sector Group
Protection/Unprotection Addresses ......................................... 33
Table 22. S29GL064A (Model R3) Top Boot Sector Protection/
Unprotection Addresses ........................................................ 33
Table 23. S29GL064A (Model R4) Bottom Boot Sector Protection/
Unprotection Addresses ........................................................ 34
Table 24. S29GL064A (Model R5) Sector Group Protection/
4
Table 30. Command Definitions (x16 Mode, BYTE# = VIH) ........ 56
Table 31. Command Definitions (x8 Mode, BYTE# = VIL) .......... 57
Write Operation Status .................................................................................... 58
DQ7: Data# Polling .............................................................................................58
Figure 7. Data# Polling Algorithm .......................................... 59
RY/BY#: Ready/Busy# ........................................................................................ 59
DQ6: Toggle Bit I ................................................................................................ 60
Figure 8. Toggle Bit Algorithm ............................................... 61
DQ2: Toggle Bit II ............................................................................................... 62
Reading Toggle Bits DQ6/DQ2 .......................................................................62
DQ5: Exceeded Timing Limits .........................................................................62
DQ3: Sector Erase Timer ................................................................................. 63
DQ1: Write-to-Buffer Abort ............................................................................ 63
Table 32. Write Operation Status ........................................... 63
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 64
Figure 9. Maximum Negative Overshoot Waveform .................. 64
Figure 10. Maximum Positive Overshoot Waveform .................. 64
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 65
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66
CMOS Compatible .............................................................................................. 66
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 11. Test Setup........................................................... 67
Table 33. Test Specifications ................................................. 67
Figure 12. Input Waveforms and Measurement Levels .............. 67
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 34. Read-Only Operations-S29GL064A Only .................... 68
Table 35. Read-Only Operations-S29GL032A Only .................... 68
Table 36. Read-Only Operation-S29GL016A Only ..................... 69
Figure 13. Read Operation Timings ........................................ 69
Figure 14. Page Read Timings ............................................... 70
Table 37. Hardware Reset (RESET#) ...................................... 70
Figure 15. Reset Timings ...................................................... 71
Table 38. Erase and Program Operations-S29GL064A ............... 72
Table 39. Erase and Program Operations-S29GL032A Only ........ 73
Table 40. Erase and Program Operations-S29GL016A Only ........ 74
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Figure 16. Program Operation Timings .................................... 75
Figure 17. Accelerated Program Timing Diagram....................... 75
Figure 18. Chip/Sector Erase Operation Timings ....................... 76
Figure 19. Data# Polling Timings
(During Embedded Algorithms) .............................................. 76
Figure 20. Toggle Bit Timings (During Embedded Algorithms)..... 77
Figure 21. DQ2 vs. DQ6 ........................................................ 77
Table 41. Temporary Sector Unprotect ................................... 77
Figure 22. Temporary Sector Group Unprotect Timing Diagram .. 78
Figure 23. Sector Group Protect and Unprotect Timing Diagram.. 78
Table 42. Alternate CE# Controlled Erase and Program
Operations-S29GL064A ........................................................ 79
Table 43. Alternate CE# Controlled Erase and Program
Operations-S29GL032A ........................................................ 80
Table 44. Alternate CE# Controlled Erase and Program
Operations-S29GL016A ........................................................ 81
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................ 82
April 22, 2005 S29GL-A_00_A3
Erase And Programming Performance . . . . . . . 83
Table 45. TSOP Pin and BGA Package Capacitance ................... 83
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 84
TS048—48-Pin Standard Thin Small Outline Package (TSOP) .............84
TS056—56-Pin Standard Thin Small Outline Package (TSOP) .............. 85
LAA064—64-Ball Fortified Ball Grid Array (BGA) ...................................86
VBN048—48-Ball Fine-pitch Ball Grid Array (BGA)
10x 6 mm Package ............................................................................................... 87
VBK048—Ball Fine-pitch Ball Grid Array (BGA)
8.15x 6.15 mm Package ........................................................................................88
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 89
Revision A (October 13, 2004) ........................................................................89
Revision A1 (December 17, 2004)s .................................................................89
Revision A2 (January 28, 2005) .......................................................................89
Revision A3 (April 20, 2005) ............................................................................89
S29GL-A MirrorBit™ Flash Family
5
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
S29GL064A, S29GL032A, S29GL016A
Part Number
S29GL064A
S29GL032A
S29GL016A
Speed Option
90
10
11
90
10
11
90
10
Max. Access Time (ns)
90
100
110
90
100
110
90
100
Max. CE# Access Time (ns)
90
100
110
90
100
110
90
100
Max. Page Access Time (ns)
25
30
30
25
30
30
25
30
Max. OE# Access Time (ns)
25
30
30
25
30
30
25
30
6
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
WP#/ACC
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
AMax**–A0
Timer
Address Latch
STB
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Note:
**AMAX GL064A = A21.
**AMAX GL032A = A20.
**AMAX GL016A = A19.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
7
A d v a n c e
I n f o r m a t i o n
Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
A191
3
A20
WE#
RESET#
1,2
A21
1
WP#/ACC
RY/BY#1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-Pin Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#1
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Notes:
1. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is VIO on S29GL064A (models R6, R7).
2. Pin 13 is NC on S29GL032A, and S29GL016A.
3. Pin 10 is NC on S29GL016A.
NC
NC
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A211
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin Standard TSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
NC
VIO
Notes:
1. Pin 15 is NC on S29GL032A.
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S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
64-ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
H8
NC
NC
NC
VIO1
VSS
NC
NC
NC
A7
B7
C7
D7
E7
F7
G7
H7
BYTE#2 DQ15/A-1
VSS
A13
A12
A14
A15
A16
A6
B6
C6
D6
E6
F6
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE#
RESET#
A213
A19
DQ5
DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
A18
A204
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
NC
NC
NC
NC
NC
NC
NC
1
VIO
Notes:
1. Ball D8 and Ball F1 are NC on S29GL064A (models R3, R4).
2. Ball F7 is NC on S29GL064A (model R5).
3. Ball C5 is NC on S29GL032A and S29GL016A.
4. Ball D4 is NC on S29GL016A.
Special Package Handling Instructions
Special handling is required for Flash Memory products in moulded packages
(TSOP and BGA). The package and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C for prolonged periods of
time.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
9
A d v a n c e
I n f o r m a t i o n
48-ball Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
1
G6
H6
DQ15/A-1
VSS
A13
A12
A14
A15
A16
BYTE#
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
A212
DQ12
VCC
DQ4
A3
B3
RY/BY# WP#/ACC
C3
A18
A19
D3
3
A20
DQ5
E3
F3
G3
H3
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
OE#
VSS
A3
A4
A2
A1
A0
CE#
Notes:
1. Ball F6 is VIO on S29GL064A (model R5).
2. Ball C4 is NC on S29GL032A and S29GL016A.
3. Ball D3 is NC on S29GL016A.
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(TSOP and BGA). The package and/or data integrity may be compromised if the
package body is exposed to temperatures above 150°C for prolonged periods of
time.
10
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Pin Descriptions
A21–A0
A20–A0
A19–A0
DQ7–DQ0
DQ14–DQ0
DQ15/A-1
=
=
=
=
=
=
CE#
OE#
WE#
WP#/ACC
=
=
=
=
ACC
WP#
RESET#
RY/BY#
BYTE#
VCC
=
=
=
=
=
=
VSS
NC
VIO
=
=
=
22 Address inputs
21 Address inputs
20 Address inputs
8 Data inputs/outputs
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
Chip Enable input
Output Enable input
Write Enable input
Hardware Write Protect input/Programming
Acceleration input
Acceleration input
Hardware Write Protect input
Hardware Reset Pin input
Ready/Busy output
Selects 8-bit or 16-bit mode
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
Device Ground
Pin Not Connected Internally
Output Buffer Power
Logic Symbols
Logic Symbol–S29GL064A (Models R1, R2, R8, R9)
22
A21–A0
CE#
16 or 8
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
VIO
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
11
A d v a n c e
I n f o r m a t i o n
Logic Symbol–S29GL064A (Models R3, R4)
22
A21–A0
CE#
16 or 8
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
Logic Symbol–S29GL064A (Model R5)
22
A21–A0
CE#
16
DQ15–DQ0
OE#
WE#
ACC
RESET#
VIO
RY/BY#
Logic Symbol–S29GL064A (Models R6, R7)
22
A21–A0
CE#
16
DQ15–DQ0
OE#
WE#
WP#
ACC
RESET#
VIO
12
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Logic Symbol–S29GL032A (Models R1, R2)
21
A20–A0
CE#
16 or 8
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
VIO
Logic Symbol–S29GL032A (Models R3, R4)
21
A20–A0
CE#
16 or 8
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
RY/BY#
BYTE#
Logic Symbol–S29GL016A (Models R1, R2)
20
A19–A0
CE#
16 or 8
DQ15–DQ0
(A-1)
OE#
WE#
WP#/ACC
RESET#
BYTE#
April 22, 2005 S29GL-A_00_A3
RY/BY#
S29GL-A MirrorBit™ Flash Family
13
A d v a n c e
I n f o r m a t i o n
Ordering Information–S29GL016A
S29GL016A Standard Products
Standard products are available in several packages and operating ranges. The
order number (Valid Combination) is formed by a combination of the following:
S29GL016A
10
T
A
I
R1
0
PACKING TYPE
0
2
3
= Tray
= 7-inch Tape and Reel
= 13-inch Tape and Reel
Additional Ordering Options
R1
R2
= x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL
= x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
TEMPERATURE RANGE
I
E
= Industrial (–40°C to +85°C)
= Engineering Samples (available prior to Production Release only)
PACKAGE MATERIAL SET
A
F
= Standard
= Pb-Free
PACKAGE TYPE
T
B
F
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL016A
3.0 Volt-only, 16 Megabit Page-Mode Flash Memory Manufactured on 200 nm MirrorBit™
Process Technology.
Table 1. S29GL016A Ordering Options
S29GL016A Valid Combinations
Device
Number
Speed
Option
Package, Material,
& Temperature Range
Model
Number
Packing
Type
R1, R2
0,2,3
(Note 1)
TAI,TFI
S29GL016A
90, 10
BAI,BFI
FAI,FFI
Package Description
(Notes)
TS048 (Note 2)
TSOP
VBK048 (Note 3)
Fine-Pitch BGA
LAA064 (Note 3)
Fortified BGA
Note:
1.
2.
3.
Type 0 is standard. Specify others as required: TSOP’s can be packed in Types 0 and 3; BGA’s can be packed in Types 0, 2, or 3.
TSOP package marking omits packing type designator from ordering part number.
BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this
device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
14
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Ordering Information–S29GL032A
S29GL032A Standard Products
Standard products are available in several packages and operating ranges. The
order number (Valid Combination) is formed by a combination of the following:
S29GL032A
90
T
A
I
R1
0
PACKING TYPE
0
2
3
= Tray
= 7-inch Tape and Reel
= 13-inch Tape and Reel
MODEL NUMBER
R1
R2
R3
R4
= x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#/ACC=VIL
= x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
= x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL
= x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
TEMPERATURE RANGE
I
E
= Industrial (–40°C to +85°C)
= Engineering Samples (available prior to Production Release only)
PACKAGE MATERIAL SET
A
F
= Standard
= Pb-Free
PACKAGE TYPE
T
B
F
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL032A
32 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBit™
Process Technology, 3.0 Volt-only Read, Program, and Erase
Table 2. S29GL032A Ordering Options
S29GL032A Valid Combinations
Device
Number
Speed
Option
Package, Material,
& Temperature Range
TAI,TFI
90, 10, 11
Packing
Type
R1, R2
FAI,FFI
S29GL032A
Model
Number
0,2,3
(Note 1)
TAI,TFI
BAI,BFI
R3 ,R4
FAI,FFI
Package Description
(Notes)
TS056 (Note 2)
TSOP
LAA064 (Note 3)
Fortified BGA
TS048 (Note 2)
TSOP
VBN048 (Note 3)
Fine-Pitch BGA
LAA064 (Note 3)
Fortified BGA
Notes:
1.
2.
3.
Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
TSOP package marking omits packing type designator from the ordering part number.
BGA package marking omits leading “S29” and packing type designator from the ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this
device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
15
A d v a n c e
I n f o r m a t i o n
Ordering Information–S29GL064A
S29GL064A Standard Products
Standard products are available in several packages and operating ranges. The
order number (Valid Combination) is formed by a combination of the following:
S29GL064A
90
T
A
I
R1
2
PACKING TYPE
0
2
3
= Tray
= 7” Tape and Reel
= 13” Tape and Reel
MODEL NUMBER
R1
R2
R3
R4
R5
R6
R7
R8
R9
= x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
= x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
= x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address
sectors protected when WP#/ACC=VIL
= x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
= x16, VCC=3.0-3.6V, Uniform sector device
= x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#=VIL
= x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#=VIL
= x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#=VIL, TSO48 only
= x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#=VIL, TSO48 only
TEMPERATURE RANGE
I
E
= Industrial (–40°C to +85°C)
= Engineering Samples (available prior to Production Release only)
PACKAGE MATERIAL SET
A
F
= Standard
= Pb-Free
PACKAGE TYPE
T
B
F
= Thin Small Outline Package (TSOP) Standard Pinout
= Fine-pitch Ball-Grid Array Package
= Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL064A, 64 Megabit Page-Mode Flash Memory Manufactured using 200 nm MirrorBitTM
Process Technology, 3.0 Volt-only Read, Program, and Erase
16
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 3. S29GL064A Valid Combinations
S29GL064A Valid Combinations
Device Number
Speed Option
Package, Material &
Temperature Range
TAI, TFI
S29GL064A
90, 10, 11
Model Number
Packing Type
R3, R4, R6, R7, R8, R9
R1, R2
BAI, BFI
R3, R4, R5
FAI, FFI
R1, R2, R3, R4, R5
0, 2, 3
(Note 1)
Package Description
TS048 (Note 2)
TSOP
TS056 (Note 2)
TSOP
VBN048 (Note 3)
Fine-pitch BGA
LAA064 (Note 3)
Fortified BGA
Notes:
1.
2.
3.
Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
TSOP package marking omits packing type designator from ordering part number.
BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this
device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
17
A d v a n c e
I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a
latch used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 4 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 4. Device Bus Operations
DQ8–DQ15
Operation
CE#
OE# WE# RESET#
WP#
ACC
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
DOUT
DOUT
BYTE#
= VIL
Read
L
L
H
H
X
X
AIN
Write (Program/Erase)
L
H
L
H
(Note 3)
X
AIN
(Note 4) (Note 4)
Accelerated Program
L
H
L
H
(Note 3)
VHH
AIN
(Note 4) (Note 4)
VCC ±
0.3 V
X
X
VCC ±
0.3 V
X
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
X
High-Z
High-Z
High-Z
Sector Group Protect
(Note 2)
L
H
L
VID
H
X
SA, A6 =L,
A3=L, A2=L, (Note 4)
A1=H, A0=L
X
X
Sector Group
Unprotect
(Note 2)
L
H
L
VID
H
X
SA, A6=H,
A3=L, A2=L, (Note 4)
A1=H, A0=L
X
X
Temporary Sector
Group Unprotect
X
X
X
VID
H
X
Standby
AIN
(Note 4) (Note 4)
DQ8–DQ14
= High-Z,
DQ15 = A-1
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector Group Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors
are protected (for boot sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors are
protected or unprotected as determined by the method described in Sector Group Protection and Unprotection
on page 31. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory
protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 7, on page 57).
18
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See Reading Array Data on page 43 for more information. Refer to the AC ReadOnly Operations table for timing specifications and the timing diagram. Refer to
the DC Characteristics table for the active current specification on reading array
data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed
for random locations within a page. The page size of the device is 4 words/8
bytes. The appropriate page is selected by the higher address bits A(max)–A2.
Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific
word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is deasserted and reasserted
for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the read-page addresses constant and changing the
intra-read page addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The Word Program Command
Sequence on page 44 contains details on programming data to the device using
both standard and Unlock Bypass command sequences.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
19
A d v a n c e
I n f o r m a t i o n
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 7 – 25 indicate the address space that each sector occupies.
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/
32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See Write Buffer on
page 20 for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC or ACC pin, depending on
model number. This function is primarily intended to allow faster manufacturing
throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/
ACC or ACC pin, depending on model number, returns the device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for operations
other than accelerated programming, or device damage may result. WP# contains an internal pullup; when unconnected, WP# is at VIH.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the
autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to Autoselect Mode on page 30 and Autoselect Command Sequence on page 44 for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device
is in the standby mode, but the standby current is greater. The device requires
standard access time (tCE) for read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
Refer to the DC Characteristics on page 64 for the standby current specification.
20
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available
to the system. Refer to the DC Characteristics on page 64 for the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 15,
on page 69 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output
pins are placed in the high impedance state.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
21
A d v a n c e
I n f o r m a t i o n
Table 5. S29GL016A (Model R1) Top Boot Sector Addresses
Sector
Size
Sector A19–A12
(KB/
Kwords)
SA0 000000xxx 64/32
000000h–00FFFFh
00000h–07FFFh
SA20
Sector
Size
(KB/
Kwords)
010100xxx 64/32
SA1
000001xxx
64/32
010000h–01FFFFh
08000h–0FFFFh
SA21
010101xxx
64/32
150000h–15FFFFh
A8000h–AFFFFh
SA2
000010xxx
64/32
020000h–02FFFFh
10000h–17FFFh
SA22
010110xxx
64/32
160000h–16FFFFh
B0000h–B7FFFh
SA3
000011xxx
64/32
030000h–03FFFFh
18000h–1FFFFh
SA23
010111xxx
64/32
170000h–17FFFFh
B8000h–BFFFFh
SA4
000100xxx
64/32
040000h–04FFFFh
20000h–27FFFh
SA24
011000xxx
64/32
180000h–18FFFFh
C0000h–C7FFFh
SA5
000101xxx
64/32
050000h–05FFFFh
28000h–2FFFFh
SA25
011001xxx
64/32
190000h–19FFFFh
C8000h–CFFFFh
SA6
000110xxx
64/32
060000h–06FFFFh
30000h–37FFFh
SA26
011010xxx
64/32
1A0000h–1AFFFFh
D0000h–D7FFFh
SA7
000111xxx
64/32
070000h–07FFFFh
38000h–3FFFFh
SA27
011011xxx
64/32
1B0000h–1BFFFFh
D8000h–DFFFFh
SA8
001000xxx
64/32
080000h–08FFFFh
40000h–47FFFh
SA28
011000xxx
64/32
1C0000h–1CFFFFh
E0000h–E7FFFh
SA9
001001xxx
64/32
090000h–09FFFFh
48000h–4FFFFh
SA29
011101xxx
64/32
1D0000h–1DFFFFh
E8000h–EFFFFh
SA10
001010xxx
64/32
0A0000h–0AFFFFh
50000h–57FFFh
SA30
011110xxx
64/32
1E0000h–1EFFFFh
F0000h–F7FFFh
SA11
001011xxx
64/32
0B0000h–0BFFFFh
58000h–5FFFFh
SA31
111111000
8/4
1F0000h–1F1FFFh
0F8000h–0F8FFFh
SA12
001100xxx
64/32
0C0000h–0CFFFFh
60000h–67FFFh
SA32
111111001
8/4
1F2000h–1F3FFFh
0F9000h–0F9FFFh
SA13
001101xxx
64/32
0D0000h–0DFFFFh
68000h–6FFFFh
SA33
111111010
8/4
1F4000h–1F5FFFh
0FA000h–0FAFFFh
SA14
001101xxx
64/32
0E0000h–0EFFFFh
70000h–77FFFh
SA34
111111011
8/4
1F6000h–1F7FFFh
0FB000h–0FBFFFh
SA15
001111xxx
64/32
0F0000h–0FFFFFh
78000h–7FFFFh
SA35
111111100
8/4
1F8000h–1F9FFFh
0FC000h–0FCFFFh
SA16
010000xxx
64/32
100000h–00FFFFh
80000h–87FFFh
SA36
111111101
8/4
1FA000h–1FBFFFh
0FD000h–0FDFFFh
SA17
010001xxx
64/32
110000h–11FFFFh
88000h–8FFFFh
SA37
111111110
8/4
1FC000h–1FDFFFh
0FE000h–0FEFFFh
SA18
010010xxx
64/32
120000h–12FFFFh
90000h–97FFFh
SA38
111111111
8/4
1FE000h–1FFFFFh
0FF000h–0FFFFFh
SA19
010011xxx
64/32
130000h–13FFFFh
98000h–9FFFFh
8-bit
Address
Range
16-bit
Address
Range
Sector
A19–A12
8-bit
Address
Range
16-bit
Address
Range
140000h–14FFFFh
A0000h–A7FFFh
Table 6. S29GL016A (Model R2) Bottom Boot Sector Addresses
Sector
Size
Sector A19–A12
(KB/
Kwords)
SA0 000000000
8/4
000000h–001FFFh
00000h–00FFFh
SA19
Sector
Size
(KB/
Kwords)
001100xxx 64/32
SA1
000000001
8/4
002000h–003FFFh
01000h–01FFFh
SA20
001101xxx
64/32
0D0000h–0DFFFFh
68000h–6FFFFh
SA2
000000010
8/4
004000h–005FFFh
02000h–02FFFh
SA21
001101xxx
64/32
0E0000h–0EFFFFh
70000h–77FFFh
SA3
000000011
8/4
006000h–007FFFh
03000h–03FFFh
SA22
001111xxx
64/32
0F0000h–0FFFFFh
78000h–7FFFFh
SA4
000000100
8/4
008000h–009FFFh
04000h–04FFFh
SA23
010000xxx
64/32
100000h–00FFFFh
80000h–87FFFh
SA5
000000101
8/4
00A000h–00BFFFh
05000h–05FFFh
SA24
010001xxx
64/32
110000h–11FFFFh
88000h–8FFFFh
SA6
000000110
8/4
00C000h–00DFFFh
06000h–06FFFh
SA25
010010xxx
64/32
120000h–12FFFFh
90000h–97FFFh
SA7
000000111
8/4
00E000h–00FFFFFh
07000h–07FFFh
SA26
010011xxx
64/32
130000h–13FFFFh
98000h–9FFFFh
SA8
000001xxx
64/32
010000h–01FFFFh
08000h–0FFFFh
SA27
010100xxx
64/32
140000h–14FFFFh
A0000h–A7FFFh
SA9
000010xxx
64/32
020000h–02FFFFh
10000h–17FFFh
SA28
010101xxx
64/32
150000h–15FFFFh
A8000h–AFFFFh
SA10
000011xxx
64/32
030000h–03FFFFh
18000h–1FFFFh
SA29
010110xxx
64/32
160000h–16FFFFh
B0000h–B7FFFh
8-bit
Address
Range
16-bit
Address
Range
Sector
A19–A12
8-bit
Address
Range
16-bit
Address
Range
0C0000h–0CFFFFh
60000h–67FFFh
SA11
000100xxx
64/32
040000h–04FFFFh
20000h–27FFFh
SA30
010111xxx
64/32
170000h–17FFFFh
B8000h–BFFFFh
SA12
000101xxx
64/32
050000h–05FFFFh
28000h–2FFFFh
SA31
011000xxx
64/32
180000h–18FFFFh
C0000h–C7FFFh
SA13
000110xxx
64/32
060000h–06FFFFh
30000h–37FFFh
SA32
011001xxx
64/32
190000h–19FFFFh
C8000h–CFFFFh
SA14
000111xxx
64/32
070000h–07FFFFh
38000h–3FFFFh
SA33
011010xxx
64/32
1A0000h–1AFFFFh
D0000h–D7FFFh
SA15
001000xxx
64/32
080000h–08FFFFh
40000h–47FFFh
SA34
011011xxx
64/32
1B0000h–1BFFFFh
D8000h–DFFFFh
SA16
001001xxx
64/32
090000h–09FFFFh
48000h–4FFFFh
SA35
011000xxx
64/32
1C0000h–1CFFFFh
E0000h–E7FFFh
SA17
001010xxx
64/32
0A0000h–0AFFFFh
50000h–57FFFh
SA36
011101xxx
64/32
1D0000h–1DFFFFh
E8000h–EFFFFh
SA18
001011xxx
64/32
0B0000h–0BFFFFh
58000h–5FFFFh
SA37
011110xxx
64/32
1E0000h–1EFFFFh
F0000h–F7FFFh
SA38
011111xxx
64/32
1F0000h–1FFFFFh
F8000h–FFFFFh
22
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 7. S29GL032A (Models R1, R2) Sector Addresses
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
A20-A15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
April 22, 2005 S29GL-A_00_A3
8-bit
Address
Range
16-bit
Address
Range
Sector
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
A20-A15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S29GL-A MirrorBit™ Flash Family
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
23
A d v a n c e
I n f o r m a t i o n
Table 8. S29GL032A (Model R3) Top Boot Sector Addresses
Sector
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
000000h–00FFFFh
00000h–07FFFh
010000h–01FFFFh
08000h–0FFFFh
020000h–02FFFFh
10000h–17FFFh
030000h–03FFFFh
18000h–1FFFFh
040000h–04FFFFh
20000h–27FFFh
050000h–05FFFFh
28000h–2FFFFh
060000h–06FFFFh
30000h–37FFFh
070000h–07FFFFh
38000h–3FFFFh
080000h–08FFFFh
40000h–47FFFh
090000h–09FFFFh
48000h–4FFFFh
0A0000h–0AFFFFh
50000h–57FFFh
0B0000h–0BFFFFh
58000h–5FFFFh
0C0000h–0CFFFFh
60000h–67FFFh
0D0000h–0DFFFFh
68000h–6FFFFh
0E0000h–0EFFFFh
70000h–77FFFh
0F0000h–0FFFFFh
78000h–7FFFFh
100000h–00FFFFh
80000h–87FFFh
110000h–11FFFFh
88000h–8FFFFh
120000h–12FFFFh
90000h–97FFFh
130000h–13FFFFh
98000h–9FFFFh
140000h–14FFFFh
A0000h–A7FFFh
150000h–15FFFFh
A8000h–AFFFFh
160000h–16FFFFh
B0000h–B7FFFh
170000h–17FFFFh
B8000h–BFFFFh
180000h–18FFFFh
C0000h–C7FFFh
190000h–19FFFFh
C8000h–CFFFFh
1A0000h–1AFFFFh
D0000h–D7FFFh
1B0000h–1BFFFFh
D8000h–DFFFFh
1C0000h–1CFFFFh
E0000h–E7FFFh
1D0000h–1DFFFFh
E8000h–EFFFFh
1E0000h–1EFFFFh
F0000h–F7FFFh
1F0000h–1FFFFFh
F8000h–FFFFFh
200000h–20FFFFh F9000h–107FFFh
210000h–21FFFFh 108000h–10FFFFh
220000h–22FFFFh 110000h–117FFFh
230000h–23FFFFh 118000h–11FFFFh
Sector
A20–A12
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
100100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8-bit
Address
Range
16-bit
Address
Range
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3F1FFFh
3F2000h–3F3FFFh
3F4000h–3F5FFFh
3F6000h–3F7FFFh
3F8000h–3F9FFFh
3FA000h–3FBFFFh
3FC000h–3FDFFFh
3FE000h–3FFFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
Table 9. S29GL032A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
Sector
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
24
Sector
Size
(KB/
Kwords)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
Sector
A20–A12
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
001100xxx
001101xxx
001101xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
011101xxx
011110xxx
S29GL-A MirrorBit™ Flash Family
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 9. S29GL032A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
Sector
A20–A12
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
Sector
A20–A12
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
110000xxx
110001xxx
110010xxx
110011xxx
100100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Table 10. S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 1 of 2)
Sector
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
April 22, 2005 S29GL-A_00_A3
8-bit
Address
Range
16-bit
Address
Range
Sector
A21–A15
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
S29GL-A MirrorBit™ Flash Family
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
25
A d v a n c e
I n f o r m a t i o n
Table 10. S29GL064A (Models R1, R2, R8, R9) Sector Addresses (Sheet 2 of 2)
Sector
A21–A15
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
Sector
A21–A15
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Table 11. S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 1 of 2)
Sector
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
26
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
000000h–00FFFFh
00000h–07FFFh
010000h–01FFFFh
08000h–0FFFFh
020000h–02FFFFh
10000h–17FFFh
030000h–03FFFFh
18000h–1FFFFh
040000h–04FFFFh
20000h–27FFFh
050000h–05FFFFh
28000h–2FFFFh
060000h–06FFFFh
30000h–37FFFh
070000h–07FFFFh
38000h–3FFFFh
080000h–08FFFFh
40000h–47FFFh
090000h–09FFFFh
48000h–4FFFFh
0A0000h–0AFFFFh
50000h–57FFFh
0B0000h–0BFFFFh
58000h–5FFFFh
0C0000h–0CFFFFh
60000h–67FFFh
0D0000h–0DFFFFh
68000h–6FFFFh
0E0000h–0EFFFFh
70000h–77FFFh
0F0000h–0FFFFFh
78000h–7FFFFh
100000h–00FFFFh
80000h–87FFFh
110000h–11FFFFh
88000h–8FFFFh
120000h–12FFFFh
90000h–97FFFh
130000h–13FFFFh
98000h–9FFFFh
140000h–14FFFFh
A0000h–A7FFFh
150000h–15FFFFh
A8000h–AFFFFh
160000h–16FFFFh
B0000h–B7FFFh
170000h–17FFFFh
B8000h–BFFFFh
180000h–18FFFFh
C0000h–C7FFFh
190000h–19FFFFh
C8000h–CFFFFh
1A0000h–1AFFFFh D0000h–D7FFFh
1B0000h–1BFFFFh D8000h–DFFFFh
1C0000h–1CFFFFh
E0000h–E7FFFh
1D0000h–1DFFFFh
E8000h–EFFFFh
1E0000h–1EFFFFh
F0000h–F7FFFh
1F0000h–1FFFFFh
F8000h–FFFFFh
200000h–20FFFFh F9000h–107FFFh
210000h–21FFFFh 108000h–10FFFFh
Sector
A21–A15
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
S29GL-A MirrorBit™ Flash Family
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 11. S29GL064A (Model R3) Top Boot Sector Addresses (Sheet 2 of 2)
Sector
A21–A15
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
Sector
A21–A15
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8-bit
Address
Range
16-bit
Address
Range
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F1FFFh
7F2000h–7F3FFFh
7F4000h–7F5FFFh
7F6000h–7F7FFFh
7F8000h–7F9FFFh
7FA000h–7FBFFFh
7FC000h–7FDFFFh
7FE000h–7FFFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA54
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0101111xxx
Sector
Size
(KB/
Kwords)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
April 22, 2005 S29GL-A_00_A3
8-bit
Address
Range
16-bit
Address
Range
000000h–001FFFh
00000h–00FFFh
002000h–003FFFh
01000h–01FFFh
004000h–005FFFh
02000h–02FFFh
006000h–007FFFh
03000h–03FFFh
008000h–009FFFh
04000h–04FFFh
00A000h–00BFFFh
05000h–05FFFh
00C000h–00DFFFh
06000h–06FFFh
00E000h–00FFFFFh
07000h–07FFFh
010000h–01FFFFh
08000h–0FFFFh
020000h–02FFFFh
10000h–17FFFh
030000h–03FFFFh
18000h–1FFFFh
040000h–04FFFFh
20000h–27FFFh
050000h–05FFFFh
28000h–2FFFFh
060000h–06FFFFh
30000h–37FFFh
070000h–07FFFFh
38000h–3FFFFh
080000h–08FFFFh
40000h–47FFFh
090000h–09FFFFh
48000h–4FFFFh
0A0000h–0AFFFFh
50000h–57FFFh
0B0000h–0BFFFFh
58000h–5FFFFh
0C0000h–0CFFFFh
60000h–67FFFh
0D0000h–0DFFFFh
68000h–6FFFFh
0E0000h–0EFFFFh
70000h–77FFFh
0F0000h–0FFFFFh
78000h–7FFFFh
100000h–00FFFFh
80000h–87FFFh
110000h–11FFFFh
88000h–8FFFFh
120000h–12FFFFh
90000h–97FFFh
130000h–13FFFFh
98000h–9FFFFh
2F0000h–2FFFFFh 178000h–17FFFFh
Sector
Sector
Table 12. S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
A21–A15
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA95
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
1011000xxx
S29GL-A MirrorBit™ Flash Family
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
580000h–58FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
2C0000h–2C7FFFh
27
A d v a n c e
I n f o r m a t i o n
A21–A15
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
Sector
Sector
Table 12. S29GL064A (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
A21–A15
300000h–30FFFFh 180000h–187FFFh SA96 1011001xxx
310000h–31FFFFh 188000h–18FFFFh SA97 1011010xxx
320000h–32FFFFh 190000h–197FFFh SA98 1011011xxx
330000h–33FFFFh 198000h–19FFFFh SA99 1011100xxx
340000h–34FFFFh 1A0000h–1A7FFFh SA100 1011101xxx
350000h–35FFFFh 1A8000h–1AFFFFh SA101 1011110xxx
360000h–36FFFFh 1B0000h–1B7FFFh SA102 1011111xxx
370000h–37FFFFh 1B8000h–1BFFFFh SA103 1100000xxx
380000h–38FFFFh 1C0000h–1C7FFFh SA104 1100001xxx
390000h–39FFFFh 1C8000h–1CFFFFh SA105 1100010xxx
3A0000h–3AFFFFh 1D0000h–1D7FFFh SA106 1100011xxx
3B0000h–3BFFFFh 1D8000h–1DFFFFh SA107 1100100xxx
3C0000h–3CFFFFh 1E0000h–1E7FFFh SA108 1100101xxx
3D0000h–3DFFFFh 1E8000h–1EFFFFh SA109 1100110xxx
3E0000h–3EFFFFh 1F0000h–1F7FFFh SA110 1100111xxx
3F0000h–3FFFFFh 1F8000h–1FFFFFh SA111 1101000xxx
400000h–40FFFFh 200000h–207FFFh SA112 1101001xxx
410000h–41FFFFh 208000h–20FFFFh SA113 1101010xxx
420000h–42FFFFh 210000h–217FFFh SA114 1101011xxx
430000h–43FFFFh 218000h–21FFFFh SA115 1101100xxx
440000h–44FFFFh 220000h–227FFFh SA116 1101101xxx
450000h–45FFFFh 228000h–22FFFFh SA117 1101110xxx
460000h–46FFFFh 230000h–237FFFh SA118 1101111xxx
470000h–47FFFFh 238000h–23FFFFh SA119 1110000xxx
480000h–48FFFFh 240000h–247FFFh SA120 1110001xxx
490000h–49FFFFh 248000h–24FFFFh SA121 1110010xxx
4A0000h–4AFFFFh 250000h–257FFFh SA122 1110011xxx
4B0000h–4BFFFFh 258000h–25FFFFh SA123 1110100xxx
4C0000h–4CFFFFh 260000h–267FFFh SA124 1110101xxx
4D0000h–4DFFFFh 268000h–26FFFFh SA125 1110110xxx
4E0000h–4EFFFFh 270000h–277FFFh SA126 1110111xxx
4F0000h–4FFFFFh 278000h–27FFFFh SA127 1111000xxx
500000h–50FFFFh 280000h–28FFFFh SA128 1111001xxx
510000h–51FFFFh 288000h–28FFFFh SA129 1111010xxx
520000h–52FFFFh 290000h–297FFFh SA130 1111011xxx
530000h–53FFFFh 298000h–29FFFFh SA131 1111100xxx
540000h–54FFFFh 2A0000h–2A7FFFh SA132 1111101xxx
550000h–55FFFFh 2A8000h–2AFFFFh SA133 1111110xxx
560000h–56FFFFh 2B0000h–2B7FFFh SA134 1111111000
570000h–57FFFFh 2B8000h–2BFFFFh
Sector
Size
(KB/
Kwords)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8-bit
Address
Range
16-bit
Address
Range
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7FFFFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3FFFFFh
Table 13. S29GL064A (Model R5) Sector Addresses (Sheet 1 of 2)
28
Sector
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA42
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0101010
16-bit
Address Range
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
250000–257FFF
Sector
A21–A15
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA85
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
1010101
S29GL-A MirrorBit™ Flash Family
16-bit
Address Range
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
1A8000–1AFFFF
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 13. S29GL064A (Model R5) Sector Addresses (Sheet 2 of 2)
Sector
A21–A15
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
16-bit
Address Range
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
Sector
A21–A15
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
16-bit
Address Range
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Table 14. S29GL064A (Models R6, R7) Sector Addresses (Sheet 1 of 2)
Sector
A21–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA42
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0101010
April 22, 2005 S29GL-A_00_A3
16-bit
Address
Range
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
250000–257FFF
Sector
A21–A15
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA85
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
1010101
S29GL-A MirrorBit™ Flash Family
16-bit
Address
Range
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
1A8000–1AFFFF
29
A d v a n c e
I n f o r m a t i o n
Table 14. S29GL064A (Models R6, R7) Sector Addresses (Sheet 2 of 2)
Sector
A21–A15
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
16-bit
Address
Range
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
Sector
A21–A15
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
16-bit
Address
Range
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
group protection verification, through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match
a device to be programmed with its corresponding programming algorithm.
However, the autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 15
on page 31. In addition, when verifying sector protection, the sector address
must appear on the appropriate highest order address bits (see Table 7-Table
25). Table 15 on page 31 shows the remaining address bits that are don’t care.
When all necessary bits are set as required, the programming equipment may
then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 30 on page 54 and
30
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 31 on page 55. This method does not require VID. Refer to the Autoselect
Command Sequence section for more information.
Table 15.
Description
S29GL016A
S29GL032A
S29GL064A
Manufacturer ID:
Spansion Products
Cycle 1
Cycle 2
Autoselect Codes, (High Voltage Method)
A22 A14
A8
A5 A3
CE# OE# WE# to
to A9 to A6 to to A1 A0
A15 A10
A7
A4 A2
L
L
VID
L
00
X
01h
01h
01h
22
22
X
X
7Eh
0Ch
7Eh
10h
7Eh
13h
Cycle 3
H
H
H
22
X
01h
Cycle 1
Cycle 2
L
H
L
H
H
L
22
22
X
X
7Eh
1Dh
H
H
H
22
X
00h
L
L
H
X
X
VID
VID
X
X
L
L
X
R5,
R6,
R7
H
L
X
L
R3, R4
L
H
X
X
R1, R2,
R8, R9
L
H
X
BYTE#
= VIL
L
H
L
X
BYTE#
= VIH
L
L
H
DQ7 to DQ0
Model Number
DQ8 to DQ15
X
X
Cycle 3
Cycle 1
Sector Group
Protection
Verification
Secured Silicon
Sector Indicator
Bit (DQ7), WP#
protects highest
address sector
Secured Silicon
Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector
00h (-R4, bottom boot)
01h (-R3, top boot)
01h
7Eh
1Ah
00h (-R4, bottom boot)
01h (-R3, top boot)
L
L
H
X
X
VID
X
X
X
X
L
H
22
X
C4h (-R2, bottom boot)
49h (-R1, top boot)
L
L
H
SA
X
VID
X
L
X
L
H
L
X
X
01h (protected),
00h (unprotected)
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
For S29GL064A and S29GL032A:
99h (factory locked), 19h (not factory locked)
For S29GL016A:
94h (factory locked), 14h (not factory locked)
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
For S29GL064A and S29GL032A:
89h (factory locked), 09h (not factory locked)
For S29GL016A:
84h (factory locked), 04h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase
operations in any sector group (see Tables 14 – 25). The hardware sector group
unprotection feature re-enables both program and erase operations in previously
protected sector groups. Sector group protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be
implemented either in-system or via programming equipment. Figure 2, on page
36 shows the algorithms and Figure 24, on page 80 shows the timing diagram.
This method uses standard microprocessor bus cycle timing. For sector group
unprotect, all unprotected sector groups must first be protected prior to the first
sector group unprotect write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the option of programming and protecting sector groups at its factory prior to shipping
the device through Spansion Programming Service. Contact a Spansion representative for details.
It is possible to determine whether a sector group is protected or unprotected.
See Autoselect Mode on page 30 for details.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
31
A d v a n c e
I n f o r m a t i o n
Table 16. S29GL016A (Model R1) Sector Group Protection/Unprotection Addresses
Sector
A19–A12
SA0-SA3
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
000XXXXXh
001XXXXXh
010XXXXXh
011XXXXXh
100XXXXXh
101XXXXXh
110XXXXXh
11100XXXh
11101XXXh
11110XXXh
SA28-SA30
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A19–A12
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
11111000h
11111001h
11111010h
11111011h
11111100h
11111101h
11111110h
11111111h
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
192 (3x64)
Table 17. S29GL016A (Model R2) Sector Group Protection/Unprotection Addresses
Sector
A19–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
00000000h
00000001h
00000010h
00000011h
00000100h
00000101h
00000110h
00000111h
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
Sector
A19–A12
SA8–SA10
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
00001XXXh
00010XXXh
00011XXXh
001XXXXXh
010XXXXXh
011XXXXXh
100XXXXXh
101XXXXXh
110XXXXXh
Sector/Sector
Block Size
(Kbytes)
192 (3x64)
256
256
256
256
256
256
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
Table 18. S29GL032A (Models R1, R2) Sector Group Protection/Unprotection Addresses
Sector
A20–A15
SA0
SA1
SA2
SA3
SA4–SA7
SA8–SA11
000000
000001
000010
000011
0001xx
0010xx
Sector
/Sector
Block Size
(Kbytes)
64
64
64
64
256 (4x64)
256 (4x64)
Sector
A20–A15
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
0011xx
0100xx
0101xx
0110xx
0111xx
1000xx
Sector
/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A20–A15
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
1001xx
1010xx
1011xx
1100xx
1101xx
Sector
/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A20–A15
SA56–SA59
SA60
SA61
SA62
SA63
1110xx
111100
111101
111110
111111
Sector
/Sector
Block Size
(Kbytes)
256 (4x64)
64
64
64
64
Table 19. S29GL032A (Model R3) Sector Group Protection/Unprotection Address Table
Sector
A20–A12
SA0-SA3
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32–SA35
0000XXXXXh
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh
32
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A20–A12
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52-SA55
SA56-SA59
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
111100XXXh
111101XXXh
111110XXXh
SA60-SA62
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
192 (3x64)
S29GL-A MirrorBit™ Flash Family
Sector
A20–A12
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000h
111111001h
111111010h
111111011h
111111100h
111111101h
111111110h
111111111h
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 20. S29GL032A (Model R4) Sector Group Protection/Unprotection Address Table
Sector
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
000000000h
000000001h
000000010h
000000011h
000000100h
000000101h
000000110h
000000111h
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
Sector
Sector/Sector
Block Size
(Kbytes)
A20–A12
000001XXXh
000010XXXh
000011XXXh
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
SA8–SA10
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
192 (3x64)
256
256
256
256
256
256
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
Sector
A20–A12
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
0111XXXXXh
1000XXXXXh
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
1111XXXXXh
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Table 21. S29GL064A (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses
Sector
A21–A15
SA0
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
0000000
0000001
0000010
0000011
00001xx
00010xx
00011xx
00100xx
00101xx
00110xx
Sector/
Sector
Block Size
(Kbytes)
64
64
64
64
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
00111xx
01000xx
01001xx
01010xx
01011xx
01100xx
01101xx
01110xx
01111xx
10000xx
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
10001xx
10010xx
10011xx
10100xx
10101xx
10110xx
10111xx
11000xx
11001xx
11010xx
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124
SA125
SA126
SA127
11011xx
11100xx
11101xx
11110xx
1111100
1111101
1111110
1111111
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
64
64
64
64
Table 22. S29GL064A (Model R3) Top Boot Sector Protection/Unprotection Addresses
Sector
A20–A12
00000XXXXX
00001XXXXX
00010XXXXX
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
SA56-SA59
SA60-SA63
SA64-SA67
SA12-SA15
00011XXXXX
256 (4x64)
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
256
256
256
256
256
256
256
256
256
256
Sector
A21–A12
SA0-SA3
SA4-SA7
SA8-SA11
April 22, 2005 S29GL-A_00_A3
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
Sector
A20–A12
01110XXXXX
01111XXXXX
10000XXXXX
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
SA112-SA115
SA116-SA119
SA120-SA123
SA68-SA71
10001XXXXX
256 (4x64)
SA124-SA126
SA72-SA75
SA76-SA79
SA80-SA83
SA84-SA87
SA88-SA91
SA92-SA95
SA96-SA99
SA100-SA103
SA104-SA107
SA108-SA111
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
256
256
256
256
256
256
256
256
256
256
11100XXXXX
11101XXXXX
11110XXXXX
1111100XXX
1111101XXX
1111110XXX
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
S29GL-A MirrorBit™ Flash Family
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
192 (3x64)
8
8
8
8
8
8
8
8
33
A d v a n c e
I n f o r m a t i o n
Table 23. S29GL064A (Model R4) Bottom Boot Sector Protection/Unprotection Addresses
Sector
A21–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX,
0000010XXX,
0000011XXX,
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
SA8–SA10
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
Sector/Sector
Block Size
(Kbytes)
8
8
8
8
8
8
8
8
Sector
A20–A12
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
192 (3x64)
256
256
256
256
256
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
Sector
A20–A12
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
Sector/Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA63–SA66
01110XXXXX
256 (4x64)
SA119–SA122
11100XXXXX
256 (4x64)
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
256
256
256
256
256
SA123–SA126
SA127–SA130
SA131–SA134
11101XXXXX
11110XXXXX
11111XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
(4x64)
(4x64)
(4x64)
(4x64)
(4x64)
Table 24. S29GL064A (Model R5) Sector Group Protection/Unprotection Addresses
Sector
A21–A15
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
00000
00001
00010
00011
00100
00101
00110
00111
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
01000
01001
01010
01011
01100
01101
01110
01111
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
10000
10001
10010
10011
10100
10101
10110
10111
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
11000
11001
11010
11011
11100
11101
11110
11111
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Table 25. S29GL064A (Models R6, R7) Sector Group Protection/Unprotection Addresses
Sector
A21–A15
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
00000
00001
00010
00011
00100
00101
00110
00111
34
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
01000
01001
01010
01011
01100
01101
01110
01111
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
10000
10001
10010
10011
10100
10101
10110
10111
S29GL-A MirrorBit™ Flash Family
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
Sector
A21–A15
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
11000
11001
11010
11011
11100
11101
11110
11111
Sector/
Sector
Block Size
(Kbytes)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector
groups to change data in-system. The Sector Group Unprotect mode is activated
by setting the RESET# pin to VID. During this mode, formerly protected sector
groups can be programmed or erased by selecting the sector group addresses.
Once VID is removed from the RESET# pin, all the previously protected sector
groups are protected again. Figure 1 shows the algorithm, and Figure 22, on
page 76 shows the timing diagrams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = VIL, the highest or lowest address sector remains protected for
uniform sector devices; the top or bottom two address sectors remains protected for boot sector devices).
2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
35
A d v a n c e
I n f o r m a t i o n
START
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
No
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Group Unprotect
Mode
Yes
Yes
Set up sector
group address
No
All sector
groups
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Write 60h to sector
group address with
A6–A0 = 1xx0010
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Increment
PLSCNT
No
Reset
PLSCNT = 1
Read from
sector group address
with A6–A0
= 0xx0010
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6–A0 = 1xx0010
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector group
address with
A6–A0 = 1xx0010
Data = 01h?
Yes
No
Yes
Device failed
Protect
another
sector group?
No
Yes
No
PLSCNT
= 1000?
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Group
Protect
Algorithm
Sector Group
Protect complete
Set up
next sector group
address
Data = 00h?
Yes
Last sector
group
verified?
No
Yes
Sector Group
Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
36
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables
permanent part identification through an Electronic Serial Number (ESN). The
Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector
Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is
locked when shipped from the factory. This bit is permanently set at the factory
and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer
lockable (standard shipping option) or factory locked (contact a Spansion sales
representative for ordering information). The customer-lockable version is
shipped with the Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also
contains the Secured Silicon Sector Indicator Bit permanently set to a 0. The factory-locked version is always protected when shipped from the factory, and has
the Secured Silicon Sector Indicator Bit permanently set to a 1. Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being
used to replace devices that are factory locked. Note that the ACC function and
unlock bypass modes are not available when the Secured Silicon Sector is
enabled.
The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector Address Range
x16
000000h–000007h
000008h–00007Fh
x8
000000h-00000Fh
000010h-0000FFh
Standard Factory
Locked
ExpressFlash Factory
Locked
ESN
ESN or determined by
customer
Unavailable
Determined by
customer
Customer Lockable
Determined by
customer
The system accesses the Secured Silicon Sector through a command sequence
(see Write Protect (WP#) on page 38). After the system writes the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector
by using the addresses normally occupied by the first sector (SA0). This mode
of operation continues until the system issues the Exit Secured Silicon Sector
command sequence, or until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to sending commands to sector
SA0.
Customer Lockable: Secured Silicon Sector NOT Programmed or
Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may
program and protect the 256-byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard
programming command sequence. See Command Definitions on page 43.
Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the
Secured Silicon Sector area and none of the bits in the Secured Silicon Sector
memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following
procedures:
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
37
A d v a n c e
I n f o r m a t i o n
„ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in
Figure 2, on page 36, except that RESET# may be at either VIH or VID. This
allows in-system protection of the Secured Silicon Sector without raising any
device pin to a high voltage. Note that this method is only applicable to the
Secured Silicon Sector.
„ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then use the alternate method of sector protection described in
the Sector Group Protection and Unprotection on page 31 section.
Once the Secured Silicon Sector is programmed, locked and verified, the system
must write the Exit Secured Silicon Sector Region command sequence to return
to reading and writing within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and
Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device
is shipped from the factory. The Secured Silicon Sector cannot be modified in any
way. An ESN Factory Locked device has an 16-byte random ESN at addresses
000000h–000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the
Spansion programming service (Customer Factory Locked). The devices are then
shipped from the factory with the Secured Silicon Sector permanently locked.
Contact your sales representative for details on using the Spansion programming service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or
last sector group without using VID. Write Protect is one of two functions provided by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the first or last sector group independently of whether those
sector groups were protected or unprotected. Note that if WP#/ACC is at VIL
when the device is in the standby mode, the maximum input load current is increased. See the table in DC Characteristics on page 64.
If the system asserts VIH on the WP#/ACC pin, the device reverts to
whether the first or last sector was previously set to be protected or unprotected using the method described in Sector Group Protection and
Unprotection on page 31. Note that WP# contains an internal pullup;
when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 30 on
page 54 and Table 31 on page 55 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This
protects data during VCC power-up and power-down. The command register and
38
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
all internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional
writes when VCC is greater than VLKO.
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a
write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE#
= VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Tables 26–29. To
terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 26–29. The system must write the
reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100. Alternatively, contact your sales representative for copies of these
documents.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
39
A d v a n c e
I n f o r m a t i o n
Table 26. CFI Query Identification String
Addresses
(x16)
Addresses
(x8)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Table 27.
Description
System Interface String
Addresses
(x16)
Addresses
(x8)
Data
1Bh
36h
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0007h
Reserved for future use
20h
40h
0007h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0001h
Reserved for future use
24h
48h
0005h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Description
Note: CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering
Information tables to obtain the VCC range for particular part numbers. Please consult the Erase and Programming Performance table
for typical timeout specifications.
40
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 28.
Addresses (x16)
Addresses (x8)
Device Geometry Definition
Data
Description
Device Size = 2 byte
N
27h
4Eh
00xxh
28h
29h
50h
52h
000xh
0000h
0017h = 64 Mb, 0016h = 32Mb, 0015h = 16Mb
Flash Device Interface description (refer to CFI publication 100)
0000h = x8-only bus devices
0001h = x16-only bus devices
0002h = x8/x16 bus devices
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
00xxh
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
00x0h
000xh
31h
32h
33h
34h
60h
64h
66h
68h
00xxh
0000h
0000h
000xh
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
April 22, 2005 S29GL-A_00_A3
0000h, 0020h, 0000h, 0007h = 16 Mb (-R1, -R2)
007Fh, 0000h, 0020h, 0000h = 32 Mb (-R1, -R2)
003Fh, 0000h, 0001h = 32 Mb (-R3, R4)
007Fh, 0000h, 0020h, 0000h = 64 Mb (-R1, -R2, -R8, -R9)
007Fh, 0000h, 0000h, 0001h = 64 Mb (-R3, -R4, -R5, -R6, -R7)
Erase Block Region 2 Information (refer to CFI publication 100)
0001h,
003Eh,
007Eh,
0000h,
0000h,
0000h,
0000h,
0000h,
0000h,
0000h,
0000h,
0000h,
001Eh = 16 Mb (-R1, -R2)
0001h = 32 Mb (-R1, -R2)
0001h = 64 Mb (-R1, -R2, -R8, -R9)
0000h = all others
S29GL-A MirrorBit™ Flash Family
41
A d v a n c e
Table 29.
I n f o r m a t i o n
Primary Vendor-Specific Extended Query
Addresses
(x16)
Addresses
(x8)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII
44h
88h
0033h
Minor version number, ASCII
Description
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
000xh
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in smallest sector group
48h
90h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
0004h = Standard Mode (Refer to Text)
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0001h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
00B5h
4Eh
9Ch
00C5h
4Fh
9Eh
00xxh
50h
A0h
0001h
Process Technology (Bits 7-2) 0010b = 200 nm MirrorBit
0009h = x8-only bus devices
0008h = all other devices
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
42
02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform
sectors bottom WP# protect, 05h = Uniform sectors top WP# protect
Program Suspend
00h = Not Supported, 01h = Supported
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 30 on page 54 and Table 31 on
page 55 define the valid register command sequences. Writing incorrect address
and data values or writing them in the improper sequence may place the device
in an unknown state. A reset command is then required to return the device to
reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 52 for more
information.
The system must issue the reset command to return the device to the read (or
erase-suspend-read) mode if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations–AC Characteristics on
page 66 provide the read parameters, and Figure 13, on page 67 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ignores reset commands until
the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to the
read mode. If the program command sequence is written while the device is in
the Erase Suspend mode, writing the reset command returns the device to the
erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must
be written to return to the read mode. If the device entered the autoselect mode
while in the Erase Suspend mode, writing the reset command returns the device
to the erase-suspend-read mode.
April 22, 2005 S29GL-A_00_A3
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43
A d v a n c e
I n f o r m a t i o n
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the
device was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the
system must write the Write-to-Buffer-Abort Reset command sequence to reset
the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to read several identifier codes at specific addresses:
Identifier Code
A7:A0
(x16)
A6:A-1
(x8)
Manufacturer ID
00h
00h
Device ID, Cycle 1
01h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
Secured Silicon Sector Factory Protect
03h
06h
Sector Protect Verify
(SA)02h
(SA)04h
Note: The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system may read at any address
any number of times without initiating another autoselect command sequence:
The system must write the reset command to return to the read mode (or erasesuspend-read mode if the device was previously in Erase Suspend).
Enter/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an
8-word/16-byte random Electronic Serial Number (ESN). The system can access
the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured
Silicon Sector region until the system issues the four-cycle Exit Secured Silicon
Sector command sequence. The Exit Secured Silicon Sector command sequence
returns the device to normal operation. Table 30 on page 54 and Table 31 on
page 55 show the address and data requirements for both command sequences.
See also Secured Silicon Sector Flash Memory Region on page 37 for further information. Note that the ACC function and unlock bypass modes are not available
when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 30 on page 54 and
Table 31 on page 55 show the address and data requirements for the word program command sequence, respectively.
44
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
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When the Embedded Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands
written to the device during the Embedded Program Algorithm are ignored. Note
that the Secured Silicon Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command sequence
should be reinitiated once the device returns to the read mode, to ensure data
integrity.
Programming is allowed in any sequence of address locations and across sector
boundaries. Programming to the same word address multiple times without intervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your
local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of individual words. Use of write buffer programming (see below) is strongly
recommended for general programming use when more than a few words are to
be programmed. The effective word programming time using write buffer programming is approximately four times shorter th an the single word
programming time.
Any bit in a word cannot be programmed from 0 back to a 1. Attempting
to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits
to indicate the operation was successful. However, a succeeding read shows that
the data is still 0. Only erase operations can convert a 0 to a 1.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device
faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass mode command
sequence is all that is required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time. Table 30 on page 54 and Table 31 on page 55 show the requirements for
the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/
32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer
Programming command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle containing the Write Buffer Load command
written at the Sector Address in which programming occurs. The fourth cycle
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
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A d v a n c e
I n f o r m a t i o n
writes the sector address and the number of word locations, minus one, to be
programmed. For example, if the system programs six unique address locations,
then 05h should be written to the device. This tells the device how many write
buffer addresses are loaded with data and therefore when to expect the Program
Buffer to Flash command. The number of locations to program cannot exceed
the size of the write buffer or the operation aborts.
The fifth cycle writes the first address location and data to be programmed. The
write-buffer-page is selected by address bits AMAX–A4. All subsequent address/
data pairs must fall within the selected-write-buffer-page. The system then
writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs
loaded into the write buffer. (This means Write Buffer Programming cannot be
performed across multiple write-buffer pages.) This also means that Write Buffer
Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the
operation aborts.
Note that if a Write Buffer address location is loaded multiple times, the address/
data pair counter is decremented for every data load operation. The host system
must therefore account for loading a write-buffer location more than once. The
counter decrements for each data load operation, not for each unique writebuffer-address location. Note also that if an address location is loaded more than
once into the buffer, the final data loaded for that address is programmed.
Once the specified number of write buffer locations are loaded, the system must
then write the Program Buffer to Flash command at the sector address. Any
other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6,
DQ5, and DQ1 should be monitored to determine the device status during Write
Buffer Programming.
The write-buffer programming operation can be suspended using the standard
program suspend/resume commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to execute the next
command.
The Write Buffer Programming Sequence can be aborted in the following ways:
„ Load a value that is greater than the page buffer size during the Number of
Locations to Program step.
„ Write to an address in a sector different than the one specified during the
Write-Buffer-Load command.
„ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of
the operation.
„ Write data other than the Confirm Command after the specified number of
data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address
location loaded), DQ6 = toggle, and DQ5= 0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the device for the next operation.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress.This flash device is capable of
handling multiple write buffer programming operations on the same write buffer
46
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
address range without intervening erases. For applications requiring incremental
bit programming, a modified programming method is required; please contact
your local Spansion representative. Any bit in a write buffer address range
cannot be programmed from 0 back to a 1. Attempting to do so may cause
the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate the
operation was successful. However, a succeeding read shows that the data is still
0. Only erase operations can convert a 0 to a 1.
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC
pin depending on the particular product. When the system asserts VHH on the
WP#/ACC or ACC pin. The device uses the higher voltage on the WP#/ACC or
ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at
VHH for operations other than accelerated programming, or device damage may
result. WP# contains an internal pullup; when unconnected, WP# is at VIH.
Figure 3, on page 48 illustrates the algorithm for the program operation. Refer
to the Erase and Program Operations–AC Characteristics on page 66 for parameters, and Figure 14, on page 68 for timing diagrams.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
47
A d v a n c e
I n f o r m a t i o n
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Abort Write to
Buffer Operation?
Write to a different
sector address
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
to read mode.
No
Write next address/data pair
(Note 1)
WC = WC - 1
Write program buffer to
flash sector address
Read DQ7 - DQ0 at
Last Loaded Address
DQ7 = Data?
No
Yes
No
No
DQ1 = 1?
Yes
DQ5 = 1?
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
(Note 2)
DQ7 = Data?
Yes
No
(Note 3)
FAIL or ABORT
PASS
Notes:
1.
2.
3.
4.
When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations
with data, all addresses must fall within the selected Write-Buffer Page.
DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.
If this flowchart location was reached because DQ5= 1, then the device FAILED. If this flowchart location was reached because DQ1= 1,
then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin
another operation. If DQ1= 1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5= 1, write the Reset command.
See Table 30 on page 54 and Table 31 on page 55 for command sequences required for write buffer programming.
Figure 3. Write Buffer Programming Operation
48
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
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START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 30 on page 54 and Table 31 on page 55 for program command sequence.
Figure 4. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming
operation or a Write to Buffer programming operation so that data can be read
from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation
within 15 µs maximum (5µs typical) and updates the status bits. Addresses are
not required when writing the Program Suspend command.
After the programming operation is suspended, the system can read array data
from any non-suspended sector. The Program Suspend command may also be
issued during a programming operation while an erase is suspended. In this
case, data may be read from any addresses not in Erase Suspend or Program
Suspend. If a read is needed from the Secured Silicon Sector area (One-time
Program area), then user must use the proper command sequences to enter and
exit this region. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress.
The system may also write the autoselect command sequence when the device
is in the Program Suspend mode. The system can read as many autoselect codes
as required. When the device exits the autoselect mode, the device reverts to
the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 44 for more information.
After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the
April 22, 2005 S29GL-A_00_A3
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49
A d v a n c e
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DQ7 or DQ6 status bits, just as in the standard program operation. See Write
Operation Status on page 56 for more information.
The system must write the Program Resume command (address bits are don’t
care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program
Suspend command can be written after the device resumes programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write address/data
XXXh/B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Read data as
required
No
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Done
reading?
Yes
Write address/data
XXXh/30h
Write Program Resume
Command Sequence
Device reverts to
operation prior to
Program Suspend
Figure 5. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 30 on page 54 and Table 31 on
page 55 show the address and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, the device returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2. Refer to Write Operation Status on page 56 for information on these status bits.
Any commands written during the chip erase operation are ignored. However,
note that a hardware reset immediately terminates the erase operation. If this
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occurs, the chip erase command sequence should be reinitiated once the device
returns to reading array data, to ensure data integrity.
Figure 6, on page 52 illustrates the algorithm for the erase operation. Refer to
Table 38 on page 70 for parameters, and Figure 18, on page 74 for timing
diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence
is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 30 on page 54 and
Table 31 on page 55 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded
time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase command is written. Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to the read mode. Note that the Secured Silicon
Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. The system must rewrite the command sequence and
any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the
rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector.
Refer to the Write Operation Status section for information on these status bits.
Once the sector erase operation begins, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once the device returns to reading
array data, to ensure data integrity.
Figure 6, on page 52 illustrates the algorithm for the erase operation. Refer to
Table 38 on page 70 for parameters, and Figure 18, on page 74 for timing
diagrams.
April 22, 2005 S29GL-A_00_A3
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A d v a n c e
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START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1.See Table 30 and Table 31 for program command sequence.
2.See the section on DQ3 for information on the sector erase timer.
Figure 6. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence.
The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend command is written during the
sector erase time-out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status
information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together,
to determine if a sector is actively erasing or is erase-suspended. Refer to Write
Operation Status on page 56 for information on these status bits.
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After an erase-suspended program operation is complete, the device returns to
the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word
program operation. Refer to Write Operation Status on page 56 for more
information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode on page 30 and Autoselect
Command Sequence on page 44 sections for details.
To resume the sector erase operation, the system must write the Erase Resume
command. Further writes of the Resume command are ignored. Another Erase
Suspend command can be written after the chip resumes erasing.
Note: During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were
not fully completed must be restarted. As such, if this flash device is continually issued suspend/resume
commands in rapid succession, erase progress is impeded as a function of the number of suspends. The
result is a longer cumulative erase time than without suspends. Note that the additional suspends do not
affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only
briefly. In such cases, erase performance is not significantly impacted.
April 22, 2005 S29GL-A_00_A3
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Command Definitions
Command
Sequence
(Note 1)
Command Definitions (x16 Mode, BYTE# = VIH)
Cycles
Table 30.
Bus Cycles (Notes 2–5)
First
Read (Note 5)
1
RA
Reset (Note 6)
Second
Third
Fourth
Fifth
Sixth
RD
XXX
F0
4
555
AA
2AA
55
555
90
X00
Device ID (Note 8)
6
555
AA
2AA
55
555
90
X01
227E
Device ID (Note 9)
4
555
AA
2AA
55
555
90
X01
(Note 18)
Secured Silicon Sector Factory Protect
4
555
AA
2AA
55
555
90
X03
(Note 10)
Sector Group Protect Verify
(Note 11)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
Enter Secured Silicon Sector Region
3
555
AA
2AA
55
555
88
Exit Secured Silicon Sector Region
4
555
AA
2AA
55
555
90
XXX
00
Program
4
555
AA
2AA
55
555
A0
PA
PD
Write to Buffer (Note 12)
3
555
AA
2AA
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash
1
SA
29
Write to Buffer Abort Reset (Note 13)
3
555
AA
2AA
55
555
F0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program (Note 14)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 15)
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (Note 16)
1
XXX
B0
Program/Erase Resume (Note 17)
1
XXX
30
CFI Query (Note 18)
1
55
98
Autoselect (Note 7)
1
Manufacturer ID
0001
X0E (Note 19) X0F (Note 19)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
54
See Table 4 on page 18 for description of bus operations.
All values are in hexadecimal.
Shaded cells indicate read cycles. All others are write cycles.
During unlock and command cycles, when lower address bits are 555 or 2AA as shown in table, address bits above A11 and data bits
above DQ7 are don’t care.
No unlock or command cycles required when device is in read mode.
Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in
autoselect mode, or if DQ5 goes high while device is providing status information.
Fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD and WC.
SeeAutoselect Command Sequence on page 44 for more information.
For S29GL064A and S29GL032A, Device ID must be read in three cycles.
For S29GL016A, Device ID must be read in one cycle.
Refer to Table 15 on page 31 for data indicating Secured Silicon Sector factory protect status.
Data is 00h for an unprotected sector group and 01h for a protected sector group.
Total number of cycles in command sequence is determined by number of words written to write buffer. Maximum number of cycles in
command sequence is 21, including Program Buffer to Flash command.
Command sequence resets device for next command after aborted write-to-buffer operation.
Unlock Bypass command is required prior to Unlock Bypass Program command.
Unlock Bypass Reset command is required to return to read mode when device is in unlock bypass mode.
System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command
is valid only during a sector erase operation.
Erase Resume command is valid only during Erase Suspend mode.
Command is valid when device is ready to read array data or when device is in autoselect mode.
Refer to Table 15 on page 31, for individual Device IDs per device density and model number.
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
Command Sequence
(Note 1)
Cycles
Table 31.
I n f o r m a t i o n
Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 2–5)
First
Second
Third
Addr Data Addr Data Addr Data
Read (Note 6)
1
RA
Reset (Note 7)
Fourth
Addr
Data
01
Fifth
Sixth
Addr
Data
Addr
Data
X1C
(Note 18)
X1E
(Note 18)
RD
XXX
F0
4
AAA
AA
555
55
AAA
90
X00
Device ID (Note 9)
6
AAA
AA
555
55
AAA
90
X02
7E
Device ID(Note 10)
4
AAA
AA
555
55
AAA
90
X02
(Note 11)
Secured Silicon Sector Factory
Protect
4
AAA
AA
555
55
AAA
90
X06
(Note 10)
Sector Group Protect Verify
(Note 12)
4
AAA
AA
555
55
AAA
90
(SA)X04
00/01
Enter Secured Silicon Sector Region
3
AAA
AA
555
55
AAA
88
Exit Secured Silicon Sector Region
4
AAA
AA
555
55
AAA
90
XXX
00
Write to Buffer (Note 13)
3
AAA
AA
555
55
SA
25
SA
BC
PA
PD
WBL
PD
Program Buffer to Flash
1
SA
29
Write to Buffer Abort Reset (Note 14)
3
AAA
AA
555
55
AAA
F0
Chip Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
Sector Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
SA
30
Program/Erase Suspend (Note 15)
1
XXX
B0
Program/Erase Resume (Note 16)
1
XXX
30
CFI Query (Note 17)
1
AA
98
Autoselect (Note 8)
1
Manufacturer ID
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
See Table 4 on page 18 for description of bus operations.
All values are in hexadecimal.
Shaded cells indicate read cycles. All others are write cycles.
During unlock and command cycles, when lower address bits are 555 or AAA as shown in table, address bits above A11 are don’t care.
Unless otherwise noted, address bits A21–A11 are don’t cares.
No unlock or command cycles required when device is in read mode.
Reset command is required to return to read mode (or to erase-suspend-read mode if previously in Erase Suspend) when device is in
autoselect mode, or if DQ5 goes high while device is providing status information.
Fourth cycle of autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See Autoselect Command Sequence on
page 44e or more information.
For S29GL064A and S29GL032A Device ID must be read in three cycles.
For S29GL016A, Device ID must be read in one cycle.
Refer to Table 15 on page 31, for data indicating Secured Silicon Sector factory protect status.
Data is 00h for an unprotected sector group and 01h for a protected sector group.
Total number of cycles in command sequence is determined by number of bytes written to write buffer. Maximum number of cycles in
command sequence is 37, including Program Buffer to Flash command.
Command sequence resets device for next command after aborted write-to-buffer operation.
System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command
is valid only during a sector erase operation.
Erase Resume command is valid only during Erase Suspend mode.
Command is valid when device is ready to read array data or when device is in autoselect mode.
Refer to Table 15 on page 31, for individual Device IDs per device density and model number.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
55
A d v a n c e
I n f o r m a t i o n
Write Operation Status
The device provides several bits to determine the status of a program or erase
operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 32 on page 61 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to
determine whether an Embedded Program or Erase operation is in progress or is
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Program or Erase algorithm is in progress or completed, or whether the device
is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE#
pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an
address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7
may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to
valid data on DQ7. Depending on when the system samples the DQ7 output, it
may read the status or valid data. Even if the device completed the program or
erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be
still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.
Table 32 on page 61 shows the outputs for Data# Polling on DQ7. Figure 7, on
page 57 shows the Data# Polling algorithm. Figure 19, on page 74 shows the
Data# Polling timing diagram.
56
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
START
Read DQ15–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ15–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1.
2.
VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased.
During chip erase, a valid address is any non-protected sector address.
DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 32 on page 61 shows the outputs for RY/BY#.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
57
A d v a n c e
I n f o r m a t i o n
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device
enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection onDQ7: Data# Polling on
page 56).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 32 on page 61 shows the outputs for Toggle Bit I on DQ6. Figure 8, on page
59 shows the toggle bit algorithm. Figure 20, on page 75 shows the toggle bit
timing diagrams. Figure 21, on page 75 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II on page 60.
58
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
START
Read DQ7–DQ0
Read DQ7–DQ0
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may
stop toggling as DQ5 changes to 1. See the subsections on DQ6 and DQ2 for more information.
Figure 8. Toggle Bit Algorithm
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
59
A d v a n c e
I n f o r m a t i o n
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that were
selected for erasure. (The system may use either OE# or CE# to control the read
cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 32 on page 61 to compare outputs for DQ2 and DQ6.
Figure 8, on page 59 shows the toggle bit algorithm in flowchart form, and the
section “DQ2: Toggle Bit II” explains the algorithm. See also the RY/BY#: Ready/
Busy# subsection. Figure 20, on page 75 shows the toggle bit timing diagram.
Figure 21, on page 75 shows the differences between DQ2 and DQ6 in graphical
form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8, on page 59 for the following discussion. Whenever the system
initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in
a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the
reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8,
on page 59).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a
specified internal pulse count limit. Under these conditions DQ5 produces a 1.
indicating that the program or erase cycle was not successfully completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location
that was previously programmed to 0. Only an erase operation can change
a 0 back to a 1. Under this condition, the device halts the operation, and when
the timing limit is exceeded, DQ5 produces a 1.
60
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
In all these cases, the system must write the reset command to return the device
to the reading the array (or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to
determine whether or not erasure began. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are selected for erasure, the
entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be assumed to be
less than 50 µs, the system need not monitor DQ3. See also the Sector Erase
Command Sequence section.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device accepted the
command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is 0, the device accepts additional sector
erase commands. To ensure the command is accepted, the system software
should check the status of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status check, the last command
might not have been accepted.
Table 32 on page 61 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these
conditions DQ1 produces a 1. The system must issue the Write-to-Buffer-AbortReset command sequence to return the device to reading array data. See Write
Buffer on page 20 for more details.
Table 32.
Write Operation Status
Status
Standard Mode
Program Suspend Mode
Erase Suspend Mode
Write-toBuffer
Embedded Program Algorithm
Embedded Erase Algorithm
ProgramSuspend
Read
EraseSuspend
Read
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ7#
Toggle
0
N/A
No toggle
0
0
0
Toggle
0
1
Toggle
N/A
0
Program-Suspended
Sector
1
RY/BY#
Invalid (not allowed)
1
Data
1
Non-Program
Suspended Sector
Erase-Suspended Sector
DQ1
No toggle
Non-Erase Suspended
Sector
0
N/A
Toggle
N/A
Data
1
1
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
N/A
N/A
0
Busy (Note 3)
DQ7#
Toggle
0
N/A
N/A
0
0
Abort (Note 4)
DQ7#
Toggle
0
N/A
N/A
1
0
Notes:
1.
2.
3.
4.
DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation exceeded the maximum timing limits. Refer
to the section on DQ5 for more information.
DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
DQ1 switches to 1 when the device aborts the write-to-buffer operation.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
61
A d v a n c e
I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, ACC and RESET# (Note 2) . . . . . . . . . . . . . –0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9, on
page 62. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods up to 20
ns. See Figure 10, on page 62.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During
voltage transitions, A9, OE#, ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 9, on page 62. Maximum DC input voltage on
pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0V for
periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device
reliability.
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 9. Maximum Negative Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 10. Maximum Positive Overshoot Waveform
62
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
VCC for regulated voltage range . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
VIO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC
Note:Operating ranges define those limits between which the functionality of the device is guaranteed.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
63
A d v a n c e
I n f o r m a t i o n
DC Characteristics
CMOS Compatible
Parameter
Symbol
Parameter Description (Notes)
Test Conditions
ILI
Input Load Current (Note 1)
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, ACC Input Load Current
VCC = VCC max; A9 =
12.5 V
ILR
Reset Leakage Current
VCC = VCC max; RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
VCC Initial Read Current (Notes 2, 3)
CE# = VIL, OE# =
VIH,
ICC1
Min
Typ
Max
Unit
±1.0
µA
-40°C to 0°C
250
0°C to 85°C
35
µA
35
µA
±1.0
µA
1 MHz
5
20
5 MHz
18
25
10 MHz
35
50
10 MHz
5
20
40 MHz
10
40
50
60
mA
mA
ICC2
VCC Intra-Page Read Current (Notes 2, 3)
CE# = VIL, OE# = VIH
ICC3
VCC Active Write Current (Note 3)
CE# = VIL, OE# = VIH
ICC4
VCC Standby Current (Note 3)
CE#, RESET# = VCC ± 0.3 V,
WP# = VIH
1
5
µA
ICC5
VCC Reset Current (Note 3)
RESET# = VSS ± 0.3 V, WP# = VIH
1
5
µA
ICC6
Automatic Sleep Mode (Notes 3, 5)
VIH = VCC ± 0.3 V;
-0.1< VIL ≤ 0.3 V, WP# = VIH
1
5
µA
VIL
Input Low Voltage 1 (Note 6)
–0.5
0.8
V
VIH
Input High Voltage 1 (Note 6)
0.7 VCC
VCC + 0.5
V
VHH
Voltage for ACC Program
Acceleration
VCC = 2.7 –3.6 V
11.5
12.0
12.5
V
VID
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 2.7 –3.6 V
11.5
12.0
12.5
V
VOL
Output Low Voltage (Note 6)
IOL = 4.0 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
mA
IOH = –2.0 mA, VCC = VCC min
0.85 VCC
V
IOH = –100 µA, VCC = VCC min
VCC–0.4
V
Low VCC Lock-Out Voltage (Note 7)
2.3
2.5
V
Notes:
1.
2.
3.
4.
5.
6.
7.
64
On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH.
Maximum ICC specifications are tested with VCC = VCCmax.
ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
VCC voltage requirements.
Not 100% tested.
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Test Conditions
3.3 V
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Note: Diodes are IN3064 or equivalent.
Figure 11. Test Setup
Table 33. Test Specifications
Test Condition
All Speeds
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement reference levels (See Note)
Output timing measurement reference levels
30
pF
5
ns
0.0 or VCC
0.5 VCC
V
0.5 VCC
V
V
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
VCC
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
0.5 VCC
Measurement Level
0.5 VCC
Output
0.0 V
Figure 12. Input Waveforms and Measurement Levels
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
65
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Table 34. Read-Only Operations-S29GL064A Only
Parameter
JEDEC
Description
Std.
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
tPACC
Speed Options
Test Setup
Chip Enable to Output Delay
90
10
11
Unit
Min
90
100
110
ns
CE#, OE# = VIL
Max
90
100
110
ns
OE# = VIL
Max
90
100
110
ns
Page Access Time
Max
25
30
30
ns
tGLQV
tOE
Output Enable to Output Delay
Max
25
30
30
ns
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever
Occurs First
Min
0
ns
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
tOEH
Toggle and
Data# Polling
Min
10
ns
tAXQX
Notes:
1.
2.
Not 100% tested.
See Figure 11, on page 65 and Table 33 on page 65 for test specifications
Table 35. Read-Only Operations-S29GL032A Only
Parameter
Description
JEDEC
Std.
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
tPACC
Speed Options
Test Setup
Unit
90
10
11
Min
90
100
110
ns
CE#, OE# = VIL
Max
90
100
110
ns
OE# = VIL
Max
90
100
110
ns
Page Access Time
Max
25
30
30
ns
25
30
30
ns
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
Read
Min
0
ns
tOEH
Output Enable Hold Time (Note 1)
Toggle and
Data# Polling
Min
10
ns
Notes:
1.
2.
66
Not 100% tested.
See Figure 11, on page 65 and Table 33 on page 65 for test specifications.
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 36. Read-Only Operation-S29GL016A Only
Parameter
Description
JEDEC
Std.
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
tPACC
Speed Options
Test Setup
Unit
90
10
Min
90
100
ns
CE#, OE# = VIL
Max
90
100
ns
OE# = VIL
Max
90
100
ns
Page Access Time
Max
25
30
ns
25
30
ns
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First
Min
0
ns
tOEH
Read
Min
0
ns
Output Enable Hold Time (Note 1)
Toggle and Data# Polling
Min
10
ns
Notes:
1.
2.
Not 100% tested.
See Figure 11, on page 65 and Table 33 on page 65 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 13. Read Operation Timings
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
67
A d v a n c e
I n f o r m a t i o n
Same Page
A23-A2
A1-A0*
Aa
Ab
tACC
Data Bus
Qa
Ad
Ac
tPACC
tPACC
Qb
tPACC
Qc
Qd
CE#
OE#
Note: * Figure shows device in word mode. Addresses are A1–A-1 for byte mode.
Figure 14. Page Read Timings
Table 37. Hardware Reset (RESET#)
Parameter
JEDEC
Description
Std.
All Speed Options
Unit
tReady
RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)
Max
20
µs
tReady
RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode(See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Input Low to Standby Mode (See Note)
Min
20
µs
tRB
RY/BY# Output High to CE#, OE# pin Low
Min
0
ns
Note: Not 100% tested.
68
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
tRH
RESET#
tRP
Notes:
1.
2.
3.
Not 100% tested.
See the Erase And Programming Performance on page 81 for more information.
For 1–16 words/1–32 bytes programmed.
Figure 15. Reset Timings
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
69
A d v a n c e
I n f o r m a t i o n
Table 38. Erase and Program Operations-S29GL064A
Parameter
Speed Options
Description
JEDEC
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAS
tAVWL
90
10
11
90
100
110
Unit
ns
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling Min
0
ns
tDVWH
tDS
Data Setup Time
Min
35
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
ns
tWLAX
tOEPH
OE# High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Note 2, Note 3)
Typ
240
tWHWH1
tWHWH1
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time Note 1)
Min
tBUSY
WE# High to RY/BY# Low
Min
tPOLL
Program Valid before Status Polling
Max
µs
50
90
100
4
µs
110
ns
µs
Notes:
1.
2.
3.
4.
70
Not 100% tested.
See the Erase And Programming Performance on page 81 for more information.
For 1–16 words/1–32 bytes programmed.
If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16, on page 73.
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 39. Erase and Program Operations-S29GL032A Only
Parameter
Speed Options
Description
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
35
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
ns
tOEPH
OE# High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Note 2, Note 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tBUSY
WE# High to RY/BY# Low
Min
tPOLL
Program Valid before Status Polling
Max
tWLAX
tWHWH1
tWHWH2
tWHWH1
90
10
11
90
100
110
Unit
JEDEC
90
100
4
ns
µs
110
ns
µs
Notes:
1.
2.
3.
4.
5.
Not 100% tested.
See Erase And Programming Performance on page 81 for more information
For 1–16 words/1–32 bytes programmed.
Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16, on page 73.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
71
A d v a n c e
I n f o r m a t i o n
Table 40. Erase and Program Operations-S29GL016A Only
Parameter
Speed Options
Description
Std.
tAVAV
tWC
Write Cycle Time (Note 11)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
45
ns
tAHT
Address Hold Time From CE# or OE# high during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
35
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tCEPH
CE# High during toggle bit polling
Min
20
ns
tOEPH
OE# High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
Write Buffer Program Operation (Note 2, Note 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tVHH
VHH Rise and Fall Time (Note 1)
Min
250
ns
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tBUSY
WE# High to RY/BY# Low
Min
tPOLL
Program Valid before Status Polling
Max
tWLAX
tWHWH1
tWHWH2
tWHWH1
90
10
90
100
Unit
JEDEC
90
µs
100
4
ns
ns
µs
Notes:
1.
2.
3.
4.
5.
72
Not 100% tested.
See Erase And Programming Performance on page 81 for more information
For 1–16 words/1–32 bytes programmed.
Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 16, on page 73
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tPOLL
tWP
WE#
tWPH
tCS
tDS
tWHWH1
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1.
2.
PA = program address, PD = program data, DOUT is the true data at the program address.
Illustration shows device in word mode.
Figure 16. Program Operation Timings
VHH
HH
ACC
VIL
IL or VIH
IH
VIL
IL or VIH
IH
tVHH
VHH
tVHH
VHH
Figure 17. Accelerated Program Timing Diagram
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
73
A d v a n c e
I n f o r m a t i o n
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1.
2.
SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 56.)
Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
tRC
Addresses
VA
tPOLL
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
74
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
tOE
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
DQ6 / DQ2
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
Table 41. Temporary Sector Unprotect
Parameter
JEDEC
Description
Std
tVIDR
tRSP
VID Rise and Fall Time (See Note)
RESET# Setup Time for Temporary Sector Unprotect
All Speed Options
Unit
Min
500
ns
Min
4
µs
Note: Not 100% tested.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
75
A d v a n c e
I n f o r m a t i o n
VID
RESET#
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 22. Temporary Sector Group Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
A3, A2,
A1, A0
Valid*
Valid*
Sector Group Protect or Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
76
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 42. Alternate CE# Controlled Erase and Program Operations-S29GL064A
Parameter
Speed Options
Description
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
25
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tRH
RESET# High Time Before Write
Min
50
ns
Program Valid before Status Polling (Note 4)
Max
4
µs
tWHWH1
tWHWH2
tWHWH1
tPOLL
90
10
11
90
100
110
Unit
JEDEC
ns
µs
Notes:
1.
2.
3.
4.
Not 100% tested.
See the Erase And Programming Performance on page 81 for more information.
For 1–16 words/1–32 bytes programmed.
If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 24, on page 80.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
77
A d v a n c e
I n f o r m a t i o n
Table 43. Alternate CE# Controlled Erase and Program Operations-S29GL032A
Parameter
Speed Options
Description
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
25
ns
Write Buffer Program Operation (Notes 2, 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tRH
RESET# High Time Before Write
Min
50
ns
Program Valid before Status Polling (Note 4)
Max
4
µs
tWHWH1
tWHWH2
tWHWH1
tPOLL
90
10
11
90
100
110
Unit
JEDEC
ns
µs
Notes:
1.
2.
3.
4.
78
Not 100% tested.
See Erase And Programming Performance on page 81 for more information
For 1–16 words/1–32 bytes programmed.
If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 24, on page 80.
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Table 44. Alternate CE# Controlled Erase and Program Operations-S29GL016A
Parameter
Speed Options
Description
Std.
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
25
ns
Write Buffer Program Operation (Note 2, Note 3)
Typ
240
Single Word Program Operation (Note 2)
Typ
60
Accelerated Single Word Program Operation (Note 2)
Typ
54
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
tRH
RESET# High Time Before Write
Min
50
ns
Program Valid before Status Polling (Note 4)
Max
4
µs
tWHWH1
tWHWH2
tWHWH1
tPOLL
90
10
90
100
Unit
JEDEC
ns
µs
Notes:
1.
2.
3.
4.
Not 100% tested.
See Erase And Programming Performance on page 81 for more information
For 1–16 words/1–32 bytes programmed.
If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes
(that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately
after programming resumes. See Figure 24, on page 80
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
79
A d v a n c e
PBA for program
2AA for erase
I n f o r m a t i o n
SA for program buffer to flash
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
tPOLL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
PBD for program
55 for erase
DOUT
29 for program buffer to flash
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1.
2.
3.
4.
Figure indicates last two bus cycles of a program or erase operation.
PA = program address, SA = sector address, PD = program data.
DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Illustration shows device in word mode
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
80
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Erase And Programming Performance
Typ (Note 1)
Max
(Note 2)
0.5
3.5
S29GL016A
17.5
35
S29GL032A
32
64
S29GL064A
64
128
Parameter
Sector Erase Time
Chip Erase Time
Total Write Buffer Program Time (Notes 3, 5)
240
Total Accelerated Effective Write Buffer Program Time
(Notes 4, 5)
200
Chip Program Time
Unit
sec
Comments
Excludes 00h
programming
prior to erasure
(Note 6)
µs
Excludes system
level overhead
(Note 7)
S29GL016A
16
S29GL032A
31.5
S29GL064A
63
sec
Notes:
1.
2.
3.
4.
5.
6.
7.
Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V, 10,000 cycles; checkerboard data pattern.
Under worst case conditions of 90°C; Worst case VCC, 100,000 cycles.
Effective programming time (typ) is 15 µs (per word), 7.5 µs (per byte).
Effective accelerated programming time (typ) is 12.5 µs (per word), 6.3 µs (per byte).
Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 30 on page 54 and
Table 31 on page 55 for further information on command definitions.
Table 45. TSOP Pin and BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Typ
Max
Unit
TSOP
6
7.5
pF
BGA
4.2
5.0
pF
TSOP
8.5
12
pF
BGA
5.4
6.5
pF
TSOP
7.5
9
pF
BGA
3.9
4.7
pF
Notes:
1.
2.
Sampled, not 100% tested.
Test conditions TA = 25°C, f = 1.0 MHz.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
81
A d v a n c e
I n f o r m a t i o n
Physical Dimensions
TS048—48-Pin Standard Thin Small Outline Package (TSOP)
STANDARD PIN OUT (TOP VIEW)
A2
2
0.10 C
1
N
SEE DETAIL B
-A-
-BE 5
e
9
N
+1
2
N
2
D1
D
5
A1
4
C
SEATING
PLANE
B
A
0.08MM (0.0031") M C A-B S
B
SEE DETAIL A
b
6
7
WITH PLATING
7
(c)
c1
b1
BASE METAL
R
c
e/2
SECTION B-B
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
PARALLEL TO
SEATING PLANE
L
X = A OR B
DETAIL A
Package
TS 048
Jedec
MO-142 (B) EC
Symbol
A
A1
A2
b1
b
c1
c
D
D1
E
e
L
0
R
N
82
MIN
MAX
1.20
0.15
0.05
1.05
1.00
0.95
0.20
0.23
0.17
0.27
0.22
0.17
0.16
0.10
0.21
0.10
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
0.50 BASIC
0.70
0.50
0.60
3˚
5˚
0˚
0.20
0.08
48
NOM
DETAIL B
NOTES:
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
2
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3
NOT APPLICABLE.
4
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
6
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
8
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3325 \ 16-038.10a
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
TS056—56-Pin Standard Thin Small Outline Package (TSOP)
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
2
0.10
0.10
1
A2
N
SEE DETAIL B
A
REVERSE PIN OUT (TOP VIEW)
3
B
1
N
E 5
N
+1
2
N
2
D1
0.25
9
A1
4
D
2X (N/2 TIPS)
e
5
C
SEATING
PLANE
B
A
B
N
+1
2
N
2
SEE DETAIL A
0.08MM
(0.0031")
b
M
C A-B S
6
7
WITH PLATING
7
(c)
c1
b1
SECTION B-B
BASE METAL
R
(c)
e/2
GAUGE PLANE
θ°
PARALLEL TO
SEATING PLANE
0.25MM (0.0098") BSC
L
X = A OR B
DETAIL A
Package
TS 056
Jedec
MO-142 (D) EC
Symbol
A
A1
A2
b1
b
c1
c
D
D1
E
e
L
0
R
N
MAX
1.20
0.15
0.05
1.05
1.00
0.95
0.20
0.23
0.17
0.27
0.22
0.17
0.16
0.10
0.21
0.10
19.80 20.00 20.20
18.30 18.40 18.50
13.90 14.00 14.10
0.50 BASIC
0.70
0.50
0.60
8˚
0˚
0.20
0.08
56
MIN
NOM
April 22, 2005 S29GL-A_00_A3
X
C
DETAIL B
NOTES:
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
2
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
3
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
6
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
8
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3356 \ 16-038.10c
S29GL-A MirrorBit™ Flash Family
83
A d v a n c e
I n f o r m a t i o n
LAA064—64-Ball Fortified Ball Grid Array (BGA)
84
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
VBN048—48-Ball Fine-pitch Ball Grid Array (BGA) 10x 6 mm Package
D
D1
A
e
6
e
5
7
4
+0.20
1.00 -0.50
E
SE
E1
3
2
Ø0.50
1
H
+0.20
1.00 -0.50
B
A1 ID.
6
G
Øb
F
E
D
C
SD
B
A
7
A1 CORNER
Ø0.08 M C
Ø0.15 M C A B
0.10 C
A2
A
SEATING PLANE
A1
C
0.08 C
NOTES:
PACKAGE
VBN 048
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
10.00 mm x 6.00 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.17
---
---
A2
0.62
---
0.73
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
NOTE
OVERALL THICKNESS
BALL HEIGHT
10.00 BSC.
BODY SIZE
6.00 BSC.
BODY SIZE
5.60 BSC.
BALL FOOTPRINT
E1
4.00 BSC.
BALL FOOTPRINT
MD
8
ROW MATRIX SIZE D DIRECTION
ME
6
ROW MATRIX SIZE E DIRECTION
N
48
TOTAL BALL COUNT
---
0.45
BALL DIAMETER
e
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
NONE
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
D1
0.35
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
BODY THICKNESS
D
φb
4.
DEPOPULATED SOLDER BALLS
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3425\ 16-038.25
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
85
A d v a n c e
I n f o r m a t i o n
VBK048—Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package
0.10
D
(4X)
D1
A
6
5
7
e
4
E
SE
E1
3
2
1
H
PIN A1
CORNER
INDEX MARK
6
B
10
G
F
φb
E
D
C
SD
B
A
A1 CORNER
7
φ 0.08 M C
TOP VIEW
φ 0.15 M C A B
BOTTOM VIEW
0.10 C
A2
A
SEATING PLANE
A1
C
0.08 C
SIDE VIEW
NOTES:
PACKAGE
VBK 048
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.15 mm x 6.15 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
NOTE
OVERALL THICKNESS
BALL HEIGHT
8.15 BSC.
BODY SIZE
E
6.15 BSC.
BODY SIZE
D1
5.60 BSC.
BALL FOOTPRINT
E1
4.00 BSC.
BALL FOOTPRINT
MD
8
ROW MATRIX SIZE D DIRECTION
ME
6
ROW MATRIX SIZE E DIRECTION
N
48
TOTAL BALL COUNT
0.35
---
0.43
BALL DIAMETER
e
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
---
DEPOPULATED SOLDER BALLS
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
D
φb
4.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25 \ 10.05.04
86
S29GL-A MirrorBit™ Flash Family
S29GL-A_00_A3 April 22, 2005
A d v a n c e
I n f o r m a t i o n
Revision Summary
Revision A (October 13, 2004)
Initial Release.
Revision A1 (December 17, 2004)s
Secured Silicon Sector Flash Memory Region
Updated Secured Silicon Sector address table with addresses in x8-mode.
DC Characteristics (CMOS Compatible)
ILIT re-specified over temperature.
Corrected WP#/ACC input load current footnote.
Revision A2 (January 28, 2005)
Global
Added S29GL032A information.
Revision A3 (April 22, 2005)
Added S29GL016A information.
Corrected Secured Silicon Sector Indicator Bit in Table 15.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2004 – 2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks
of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective
companies.
April 22, 2005 S29GL-A_00_A3
S29GL-A MirrorBit™ Flash Family
87