74LVX257 LOW VOLTAGE CMOS QUAD 2 CHANNEL MULTIPLEXER (3-STATE) WITH 5V TOLERANT INPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD=5.8ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 257 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVX257 is a low voltage CMOS QUAD 2 CHANNEL MULTIPLEXER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. It is composed of four independent 2-channel multiplexers with common SELECT and ENABLE (OE) INPUT. The 74LVX257 is a non-inverting SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LVX257M 74LVX257MTR 74LVX257TTR multiplexer. When the ENABLE INPUT is held "High", all outputs become in high impedance state. If SELECT INPUT is held "Low", "A" data is selected, when SELECT INPUT is "High", "B" data is chosen. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/10 74LVX257 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 SELECT 2, 5, 11, 14 1A to 4A 3, 6, 10, 13 1B to 4B 4, 7, 9, 12 1Y to 4Y 15 OE 8 16 GND VCC Common Data Select Inputs Data Inputs From Source A Data Inputs From Source B 3 State Multiplexer Outputs 3 State Output Enable Inputs (Active LOW) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OE SELECT A B Y H L L L L X L L H H X L H X X X X X L H Z L H L H X :Don‘t Care Z : High Impedance LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 OUTPUT 74LVX257 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Unit Supply Voltage (note 1) 2 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage Top Operating Temperature dt/dv Input Rise and Fall Time (note 2) (VCC = 3V) 0 to VCC V -55 to 125 °C 0 to 100 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL IOZ II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 3.0 3.6 2.0 3.0 3.6 Typ. Max. 1.5 2.0 2.4 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 2.0 2.4 0.5 0.8 0.8 Max. 1.5 2.0 2.4 0.5 0.8 0.8 V 0.5 0.8 0.8 2.0 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 2.58 Unit V V 3.0 IO=-4 mA 2.0 IO=50 µA 0.0 3.0 IO=50 µA 0.0 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 3.6 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 ±5 µA 3.6 VI = 5.5V or GND ± 0.1 ±1 ±1 µA 3.6 VI = VCC or GND 4 40 40 µA 2.48 0.1 2.4 0.1 0.1 V 3/10 74LVX257 DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP VOLV VIHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) Value TA = 25°C VCC (V) Min. 3.3 -0.5 CL = 50 pF 3.3 Typ. Max. 0.3 0.5 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. -0.3 V 2.0 3.3 0.8 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tOSLH tOSHL Parameter Propagation Delay Time A, B, to Y Propagation Delay Time SELECT to Y Output Enable Time Output Disable Time Output to Output Skew Time (note 1,2) VCC (V) CL (pF) 2.7 Value TA = 25°C Min. -40 to 85°C -55 to 125°C Typ. Max. Min. Max. Min. Max. 15 7.0 13.0 1.0 15.4 1.0 16.4 2.7 50 9.5 18.0 1.0 20.3 1.0 21.3 3.3(*) 15 5.8 9.3 1.0 11.0 1.0 12.0 3.3(*) 50 8.3 12.8 1.0 14.5 1.0 15.5 2.7 15 8.5 15.4 1.0 18.2 1.0 20.0 2.7 50 10.5 20.3 1.0 23.1 1.0 24.5 3.3(*) 15 7.0 11.0 1.0 13.0 1.0 14.0 3.3(*) 2.7 2.7 50 9.5 14.5 1.0 16.5 1.0 18.0 15 50 8.0 10.5 14.7 19.6 1.0 1.0 17.5 22.4 1.0 1.0 18.5 24.0 3.3(*) 15 6.7 10.5 1.0 12.5 1.0 13.5 3.3(*) 2.7 50 9.2 14.0 1.0 16.0 1.0 17.0 50 9.5 16.8 1.0 18.9 1.0 20.0 1.0 13.5 1.0 15.0 3.3(*) 2.7 50 8.6 12.0 50 0.5 1.0 1.5 1.5 3.3(*) 50 0.5 1.0 1.5 1.5 Unit ns ns ns ns ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 4/10 74LVX257 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD Value TA = 25°C VCC (V) Min. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Typ. Max. Max. 3.3 4 10 3.3 6 pF 3.3 23 pF 10 10 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per channel) TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VCC tPZH, tPHZ GND CL =15/50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) 5/10 74LVX257 WAVEFORM 1 : PROPAGATION DELAYS FOR INVERTING CONDITIONS (f=1MHz; 50% duty cycle)) WAVEFORM 2 : PROPAGATION DELAYS FOR NON-INVERTING CONDITIONS (f=1MHz; 50% duty cycle) 6/10 74LVX257 WAVEFORM 3 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 7/10 74LVX257 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) PO13H 8/10 74LVX257 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 9/10 74LVX257 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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