HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ MEDIUM SPEED OPERATION : 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RESPONSE OR RIPPLE CLOCKING FOR SLOW CLOCK INPUT RISE AND FALL TIMES "PRESET ENABLE" AND INDIVIDUAL "JAM" INPUTS PROVIDED BINARY OR DECADE UP/DOWN COUNTING BCD OUTPUTS IN DECADE MODE QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4029B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4029B consists of a four stage binary or BCD-decade up/down counter with provisions for look ahead carry in both counting modes. The DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4029BEY HCF4029BM1 HCF4029M013TR inputs consist of a single CLOCK, CARRY IN (CLOCK ENABLE), BINARY/DECADE, UP/ DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter advances one count at the positive transition of the clock when the CARRY-IN and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-OUT PIN CONNECTION September 2002 1/12 HCF4029B signal is normally high and the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECODE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts Up when to UP/DOWN INPUT is high, and Down when the UP/DOWN INPUT is low. Multiple packages can be connected in either a parallel clocking or a ripple clocking arrangement. Parallel clocking provides synchronous control and, hence, a faster response from all counting outputs. Ripple clocking allows for longer clock input rise and fall times. IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 15 5 CLOCK CARRY IN BINARY/ 9 DECADE 10 UP/DOWN PRESET 1 ENABLE 4, 12, 13, 3 JAM1 to JAM4 6, 11, 14, 2 Q1 to Q4 7 CARRY OUT VSS 8 16 FUNCTIONAL DIAGRAM 2/12 VDD NAME AND FUNCTION Clock Input Carry In Input Binary / Decade Select Up/Down Select Preset Enable Input Jam Input Signals Q Outputs Carry Out Outputs Negative Supply Voltage Positive Supply Voltage HCF4029B TRUTH TABLE TRUTH TABLE CLOCK TE PE J Q Q X X L L L H L H X Q Q X CONTROL INPUT BIN/DEC X L H H L H H X Q Q NC UP/DOWN X H X Q Q NC PRESET ENABLE X: Don’t Care CARRY IN LOGIC LEVEL ACTION H L H L H L H L Binary Count Decade Count Up Count Down Count Jam In No Jam No Counter Advance counter LOGIC DIAGRAM 3/12 HCF4029B TIMING CHART - Binary Mode TIMING CHART - Decade Mode 4/12 HCF4029B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 5/12 HCF4029B DC SPECIFICATIONS Test Conditions Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value IO VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 any input any input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 6/12 V V 1.5 3 4 ±1 µA V 3.5 7 11 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF HCF4029B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time (Q Outputs) tPLH tPHL Propagation Delay Time (Carry Output) tTHL tTLH Transition Time (Q Outputs, Carry Output) tW tr, tf (1) tsetup(2) tsetup fMAX Minimum Clock Pulse Width Clock Rise and Fall Time Minimum Setup Time (Carry Input) Minimum Setup Time (B/D or U/D) Maximum Clock Input Frequency VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Min. 2 4 5.5 Unit Typ. Max. 250 120 90 280 130 95 100 50 40 90 45 30 500 240 180 560 260 190 200 100 80 180 90 60 15 15 15 60 20 12 340 140 100 30 10 6 170 70 50 4 8 11 ns ns ns ns ns ns ns MHz PRESET ENABLE tPLH tPHL Propagation Delay Time (Q Outputs) tPLH tPHL Propagation Delay Time (Carry Output) tW trem(2) Minimum Preset Enable (Pulse Width) Minimum Preset Enable (Removal Time) 5 10 15 5 10 15 5 10 15 5 10 15 235 100 80 320 145 105 65 35 25 100 55 40 470 200 160 640 290 210 130 70 50 200 110 80 ns ns ns ns 7/12 HCF4029B Test Condition Symbol Parameter VDD (V) Value (*) Min. Unit Typ. Max. 170 70 50 25 15 12 100 35 30 340 140 100 50 30 25 200 70 60 PRESET ENABLE tPHL tPLH Propagation Delay Time (Carry Output) tsetup(3) thold Minimum Setup Time (Carry In) Minimum Hold Time (Carry In) 5 10 15 5 10 15 5 10 15 ns ns ns (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. (1) If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation delay at 15pF and the transition time of the carry output driving stage for the estimated capacitance load. (2) From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge. (3) From Carry In to Clock Edge. TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) 8/12 HCF4029B WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 9/12 HCF4029B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 10/12 HCF4029B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 11/12 HCF4029B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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