M74HC4094 8 BIT SIPO SHIFT LATCH REGISTER (3-STATE) ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 80 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4094 DESCRIPTION The M74HC4094 is an high speed CMOS 8 BIT SIPO SHIFT LATCH REGISTER fabricated with silicon gate C2MOS technology. This device consists of an 8 bit shift register and an 8 bit latch with 3 state output buffer. Data is shifted serially trough the shift register on the positive going transition of the clock input signal. The output of the last stage (Qs) can be used to cascade several devices. Data on the Qs output is transferred to a second output (Qs’) on the following negative transition of DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC4094B1R M74HC4094M1R T&R M74HC4094RM13TR M74HC4094TTR the clock input signal. The data of each stage of the shift register is provided with a latch, which latches data on the negative going transition of the STROBE input signal. When the STROBE input is held high, data propagates through the latch to a 3-state output buffer. This buffer is enabled when OUTPUT ENABLE input is taken high. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS January 2003 1/12 M74HC4094 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 2 3 4, 5, 6, 7, 14, 13, 12, 11 9, 10 15 8 16 STROBE SERIAL IN CLOCK Q1 to Q7 QS Q’S OE GND Vcc NAME AND FUNCTION Strobe Input Serial Input Clock Input Parallel Outputs Serial Outputs Output Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE PARALLEL OUTPUTS CK OE ST Q1 Qn Qs Qs’ H H L L Qn-1 Q7 NC H H H H Qn-1 Q7 NC H L X NC NC Q7 NC L X X Z Z NC Q8 H H H NC NC NC Q8 L X X Z Z Q7 NC X : Don’t Care Z : High Impedance NC: No Change LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/12 SERIAL OUTPUTS SI M74HC4094 TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 25 mA ± 50 mA 500(*) mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C 3/12 M74HC4094 RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time tr, tf Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II IOZ ICC 4/12 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-5.2 mA 5.68 2.0 IO=20 µA 0.0 0.1 0.1 0.1 5.8 5.63 Unit V V 5.60 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA 6.0 VI = VCC or GND 4 40 80 µA V M74HC4094 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - Qn) tPLH tPHL Propagation Delay Time (CLOCK - QS, Q’S) tPLH tPHL Propagation Delay Time (STROBE - Qn) tPZL tPZH High Impedance Output Enable Time tPHZ tPLZ High Impedance Output Disable Time fMAX Maximum Clock Frequency tW(H) tW(L) Minimum Pulse Width tW(L) Minimum Pulse Width ts ts th Minimum Set-up Time (SERIAL INPUT) Minimum Set-up Time (STROBE) Minimum Hold Time (SI, ST) VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value TA = 25°C Min. 6 30 35 Typ. Max. 30 8 7 92 26 20 65 19 15 75 20 16 58 16 13 35 16 13 16 66 80 17 7 6 28 6 6 30 7 5 45 10 8 75 15 13 200 40 34 150 30 26 160 32 27 150 30 26 150 30 26 -40 to 85°C -55 to 125°C Min. Min. Max. 95 19 16 250 50 43 190 38 32 200 40 34 190 38 32 190 38 32 4.8 24 28 75 15 13 75 15 13 75 15 13 100 20 17 0 0 0 Max. 115 23 20 300 60 51 225 45 38 240 48 41 225 45 38 225 45 38 4 20 24 95 19 16 95 19 16 95 19 16 125 25 21 0 0 0 Unit ns ns ns ns ns ns MHz 110 22 19 110 22 19 110 22 19 145 29 25 0 0 0 ns ns ns ns ns 5/12 M74HC4094 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Value TA = 25°C VCC (V) Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 140 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 10 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2(per FLIP/ FLOP) TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZL, tPLZ VCC tPZH, tPHZ GND CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) 6/12 M74HC4094 WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CLOCK), SETUP AND HOLD TIMES (CLOCK) (f=1MHz; 50% duty cycle) WAVEFORM 2 :PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (STROBE), SETUP AND HOLD TIMES (STROBE)(f=1MHz; 50% duty cycle) 7/12 M74HC4094 WAVEFORM 3 : OUTPUT ENABLE AND DISABLE TIMES(f=1MHz; 50% duty cycle) 8/12 M74HC4094 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 9/12 M74HC4094 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.004 0.008 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 8 0.024 ˚ (max.) PO13H 10/12 M74HC4094 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.60 0.0256 BSC 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 11/12 M74HC4094 Information furnished is believed to be accurate and reliable. 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