ST5481 L.O.U.I.S - LOW COST USB ISDN SOLUTION PRODUCT PREVIEW ■ COMMUNICATION DEVICE CLASS AND HARDWARE FEATURES VENDOR REQUESTS S/T ISDN Interface ■ SUPPORTS OSI LEVEL 1 IN CONFOR- ■ BUS OR SELF POWERED APPLICATION (PIN PROGRAMMABLE) MANCE WITH UIT-T I.430 FOR BASIC ACCESS AT S AND T INTERFACES (ETSI 300012/ANSI T1.605) ■ ONNOW POWER MANAGEMENT (D0,D2,D3) ■ LINE INTERFACE TRANSFORMER DIRECT ■ PIN PROGRAMMABLE HIGH/LOW POWER DRIVE ■ FULL-DUPLEX TRANSMISSION AT 192KBps ON SEPARATE TRANSMIT AND RECEIVE TWISTED PAIRS USING ALTERNATE MARK INVERSION (AMI) LINE CODING ■ 2 B CHANNELS AT 64KBps EACH PLUS 1 D CHANNEL AT 16KBps ■ ALL I.430 WIRING CONFIGURATIONS SUPPORTED INCLUDING PASSIVE BUS FOR TE’S DISTRIBUTED POINT TO POINT AND POINT TO MULTIPOINT SUSPEND MODE COMPLIANCE USB DEVICE REGISTRATION, WAKE-UP CAPABILITY, USB DEVICE IDENTIFICATION GENERAL – USB hot plug and play interface. – Control access and interrupt handling provided through the USB interface. – All FIFOS and FIFOS management needed included for USB/ISDN data processing. – Internal PLL to generate the USB 48MHz clock from a 15.36MHz crystal. ■ MULTIFRAME SUPPORT – Internal regulator for 3.3V generation from USB bus 5V. ■ ANALOG – 48 pin TQFP package. PART: INCLUDED WITH ADAPTIVE DETECTION THRESHOLD AND EQUALIZER USB Interface ■ USB 1.0 SPECIFICATION FULL COMPLIANCE, 1.1 SPECIFICATION COMPATIBILITY (1.1 POWER MANAGEMENT COMPLIANCE), 12 MBps FULL SPEED ■ ON-CHIP USB DIGITAL PLL TRANSCEIVER – 0.35 micron HCMOS 6 process. DESCRIPTION ST5481 combines ISDN link access and an USB interface to allow a very simple USB/ISDN modem design with all ISDN protocols and upper applications processed into the HOST PC. WITH ■ 6 ISOCHRONOUS ENDPOINTS FOR B1, B2, D CHANNELS ENDPOINT FOR I430 DATA.INTERRUPT ■ ISDN PROTOCOL AND DATA.CONTROL ENDPOINT FOR USB STANDARD PLUS VENDOR SPECIFIC REQUEST TQFP48 ORDERING NUMBER: ST5481 TQF7 October 2000 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/18 ST5481 applications drivers. Link Activation, deactivation protocols (I430) is managed by the device. But the full handling of the command and indicate primitives is done by the host processor accessing to dedicated registers. Call setup signalling frames through D channel are managed by the host processor. 1 - GENERAL PURPOSE The ST5481 is a single chip ISDN -BRI with USB Interface low cost controller. The purpose is a low cost ISDN modem for applications like INTERNET ACCES and FAX capabilities when the PC is ON (full operating mode). The bonus is to offer an easy and lowcost access to INTERNET at a rate of 128kbits/sec. EASY access due to plug and play features via USB bus and lowcost due to host processing concept and remote powering via USB bus features. Internal regulators can be enabled to feed the device (and external devices) via the GNDBUS, VBUS USB powering lines. They convert the USB 5 volts to 3.3 volts. The device respects the USB release 1.0 power management recommendations. When entered in suspend mode on USB side the device drop into a low power mode. An internal oscillator and a PLL provide from an external 15.36MHz crystal a 48MHz clock for USB data rate recovering and 15.36MHz clock for S interface. 2 - MAIN FUNCTIONS The device controls the S0 ISDN basic rate access (ITU normalization I430) and manages the B1, B2, D channels through the USB bus. B1, B2, D channels data flow is regulated through FIFO memories of respectively 32, 32, 16 bytes in each direction. On D, B1, B2 channels, all upper protocols than basic HDLC framing protocol are host processed from upper-datalink protocol (I440 normalization), network protocol up to The device offers one operating mode called CLOSED mode plus several test modes. In CLOSED MODE the device presents the USB interface, the S interface and 8 GPIO pins. 3 - PIN-OUT 2/18 MODE3 MODE2 MODE1 MOD0 RPSM GNDA VREGA VBUS VREGD1 GNDBUS DP DM Figure 1 : Pin-out Synoptic 12 11 10 9 8 7 6 5 4 3 2 1 LIP 13 48 GPIO7 LIN 14 47 GPIO6 IREF 15 46 GPIO5 LON 16 45 GPIO4 LOP 17 44 GNDD1 TEST13 18 43 GPIO3 42 GPIO2 ST5481 GPIO1 21 40 GPIO0 CFG1_TEST9 22 39 XTALIN SDO_TEST8 23 38 XTALOUT SCK_TEST7 24 37 FLTPLL CFG0/TEST0 35 36 GNDD2 VREGD2 32 33 34 NRESET 30 31 ID1_TEST14 28 29 ID3_TEST2 26 27 FS_TEST4 25 ID0_TEST15 41 ID2_TEST1 20 SDI_TEST10 CLK_TEST3 NCS_TEST11 DR_TEST5 19 DX_TEST6 TEST12 ST5481 3.1 - Pin List Pin Name Type Function 1 DM I/O Negative USB differential data line 2 DP I/O Positive USB differential data line 3 GNDBUS I 4 VREGD1 I/O 5 VBUS I 6 VREGA I/O 7 GNDA I Analog ground 8 RPSM I REMOTE POWER SUPPLY MODE: when tied to a logic zero value the device is self powered 9 MODE0 I Static configuration pin. Used for working modes and test modes programming 10 MODE1 I Static configuration pin. Used for working modes and test modes programming 11 MODE2 I Static configuration pin. Used for working modes and test modes programming 12 MODE3 I Static configuration pin. Used for working modes and test modes programming 13 LIP In analog Receive AMI signal differential positive inputs from the S line 14 LIN In analog Receive AMI signal differential negative input from the S line 15 IREF In analog External current reference (connected to an external resistor) 16 LON Out analog Transmit AMI signal differential negative output to the S line 17 LOP Out analog Transmit AMI signal differential positive output to the S line 18 TEST13 Out analog Analog test pin: AOPTEST1 19 TEST12 Out analog Analog test pin: AOPTEST2 20 TEST11 I/O Test pin 21 TEST10 I/O Test pin 22 TEST9 I/O Test pin 23 TEST8 I/O Test pin 24 TEST7 I/O Test pin 25 TEST6 I/O Test pin 26 TEST5 I/O Test pin 27 TEST4 I/O Test pin 28 TEST3 I/O Test pin 29 ID3_TEST2 I/O Either ID product bit 2 for USB descriptor either test pin 30 ID2_TEST1 I/O Either ID product bit 3 for USB descriptor either test pin 31 ID1_TEST14 I Either ID product bit 1 for USB descriptor either test pin 32 ID0_TEST15 I Either ID product bit 0 for USB descriptor either test pin 33 NRESET I Initialisation input pin, zero active. 34 VREGD2 I Digital input supply, must be connected to VREGD1 USB remote ground Digital input/ output regulated supply, is an input when RPSM is tied to a logic zero value USB remote positive supply 5 volts. 3.3V input/ output analog regulated supply, is an input when RPSM is tied to a logic zero value 3/18 ST5481 Pin Name Type Function 35 GNDD2 I 36 CFG0_TEST0 I/O 37 FLTPLL In analog 38 XTALOUT O Tied to 15.36MHz external crystal 39 XTALIN I Tied to 15.36MHz external crystal 40 GPIO0 I/O General purpose input-output pin 2mA 41 GPIO1 I/O General purpose input-output pin 2mA 42 GPIO2 I/O General purpose input-output pin 2mA 43 GPIO3 I/O General purpose input-output pin 2mA 44 GNDD1 I 45 GPIO4 I/O General purpose input-output pin 4mA 46 GPIO5 I/O General purpose input-output pin 4mA 47 GPIO6 I/O General purpose input-output pin 4mA 48 GPIO7 I/O General purpose input-output pin 4mA Digital ground CFG0 input for configuration when closed or open mode else test9 Used to adjust the internal PLL filter Digital ground 3.2 - PLL An internal oscillator provides a 15.36MHz clock for S interface from an external 15.36MHz crystal. From this clock, the analog block PLL provides a 48MHz clock for USB data rate recovering. 4/18 ST5481 4 - SYNOPTIC Figure 2 : Global Synoptic VREF-GEN VREF IREF TXCK_O NRESET RXCK_O S0 4 S0 interface B1, B2, D FIFOS for isochonous endpoints TXFS_O CONTROL_DATA_OUT(7-0) CONTROL_DATA_IN(7-0) RXFS_O TXDATA RXDATA CHANNEL ACCESS and FRAMING B1_W FLTPLL PLL 48MHz 15.36 15.36MHz CK48 STOP_OSC MCLK B2_W Descriptor ROM 256 bytes D_W USB Driver 4 USB Bus NLSD DEN DREQ I430 MACROCELL USB MACROCELL Endpoint 1 controller NINT SDO SDI Microwire interface SCK Endpoint 0 controller NCS CK48 CK12 TEST TEST interface TEST2-0 Power management and REGULATORS Test pins MODE(3-0) RPSM 8 power pins 5/18 ST5481 5 - ISDN ACCESS The device is directly connected to the ISDN line at S0 interface point. 4 pins are dedicated to this access: LIP, LIN: receive AMI differential signals inputs connected to the appropriate transformer LOP, LON: transmit AMI differential signals outputs connected to the appropriate transformer. The S interface access sub-function is clockfeeded by a 15.36MHz clock signal from the on-chip oscillator. I431 recommendation protocols are fully implemented. The activation / deactivation command management is done by the device. 5.1 - ISDN S Interface Synoptic See Figure 3. DP, DM for data exchange. VBUS, GNDBUS as power lines. The data transfer rate is 12 MBits. The clock is extracted from the differential lines DP, DM by a digital PLL from a 48MHz internal clock. This 48MHz clock is created from the 15.36MHz clock. The USB protocol is fully implemented following the 1.0 USB specification. 6.1 - USB Normalization This specification refers to USB normalization documents: – Universal Serial Bus Specification revision 1.0 – Universal Serial Bus Common Class Specification revision 1.0 – ST5481 belongs to the VENDOR SPECIFIC DEVICE CLASS and to a vendor specific subclass defined as ISDN MODEM DEVICE SUBCLASS. It presents ONE INTERFACE belonging to the VENDOR SPECIFIC INTERFACE CLASS and a vendor specific interface subclass defined as ISDN SOFT MODEM INTERFACE SUBCLASS. 6 - USB ACCESS The device is directly connected to the USB bus. 4 pins are dedicated to this access: It satisfies to a vendor specific control protocol called ISDN SOFT MODEM PROTOCOL. Figure 3 : S-Interface Block Diagram - Tx multiframe control - D channel monitoring Line Driver - Loopbacks - Frame construction - AMI code generation Line Signal Detector TXNUM - C/I control - Activation state machine - Master clocks generation - D & E channel processing CONTROL 6/18 - Auto threshold controller - Auto equalizer controller - Digital PLL, line synchronization - AMI decoder - Frame synchronization & polarity check - Signal ID - Multiframe control. RXNUM Pre Filter & equalizer Slicers 2x6 bits DACs Rx ST5481 7 - POWER MANAGEMENT Figure 5 : Self Powered Mode (RPSM=0) The device can be supplied by the USB bus power lines VBUS (5 volts) and GNDBUS (ground). This is enabled when RPSM (remote power supply mode) is at logic one. Then on-chip regulators bring 3.3 volts to internal analog and digital blocks. When RPSM is high, a supply is brought to external devices through pins GNDD1, VREGD1, GNDD2, VREGD2, GNDA, VREGA. 8 RPSM 5 VBUS 3 GNDBUS 4 VREGD1 44 GNDD1 34 VREGD2 35 GNDD2 From USB bus Figure 4 : Bus-Powered Mode (RPSM=1) 8 RPSM 5 VBUS 3 GNDBUS From USB bus To other digital device To other analog device From 3.3V externally regulated supplies 4 VREGD1 6 VREGA 44 GNDD1 7 GNDA 34 VREGD2 35 GNDD2 The power budgeting is done by the host when initializing the pipe: 6 VREGA 7 GNDA The needed information (maximum power consumption) is adjusted through pins CFG0, CFG1 and as well as RPSM for “remote wake up ability” information. ST 5481 ST 5481 The following mechanism is used to do "a get description device". 7/18 ST5481 The host gets back the configuration of the device either a low power device, either a high power device (max power parameter higher than 100mA). Being a high power device allows to set on a wake up ability because looking for a line signal detection consume more than 500uA allowed for a low power device when in a suspend state. – A delay of 4.5ms is introduced before distributing the clocks to the internal functions. To adjust the maximum power consumption parameter into the configuration descriptor, the logical values present on pins CFG0, CFG1, RPSM are used (see Table 1). A USB SOFTWARE RESET is done through USB bmRequest SET_DEFAULT. It brings the S interface, application registers, application state machines and fifos pointers to default state. At power on, the digital regulator is immediately ON and after 100µs the analog regulator is authorized to feed the internal oscillator. When the device goes out of SUSPEND_CLOCK state, a delay of 4.5ms is introduced before distributing the clocks to the internal functions. – Initialization and clocks management. When the device enters into a suspend mode due to inactivity on USB bus, the oscillator is stopped in order to save power except if FCONF(3) is equal to 1. – A HARDWARE PIN RESET is done through pin NRESET (active low). – A USB HARDWARE RESET is done through DP, DM pins. This reset affects the USB interface, resetting the USB core state machines. It does not affect the application (S interface, registers, fifos). Table 1 : Maximum Power Current and Wake up Ability Coding Max Power Current High/Low Power Wake Up Ability CFG1 CFG0 RPSM Bm Attributes ROM add 27 Max Power ROM add 28 100 mA LO NO 0 0 1 80 32 150 mA HI NO 0 1 1 80 96 150 mA HI YES 1 0 1 A0 96 250 mA HI YES 1 1 1 A0 F9 100 mA LO NO 0 0 0 C0 32 150 mA HI NO 0 1 0 C0 96 150 mA HI YES 1 0 0 E0 96 250 mA HI YES 1 1 0 E0 F9 8/18 ST5481 8 - DEVICE STATES The device complies with USB rev 1.1 power management requirements. It complies with requirements. I430 power management Due to inactivity on the USB bus for more than 3 ms, the device may enter into the SUSPEND mode even if Reset signalling is not done yet. The ST5481 recovers activity within the 15ms of the resume signalling issued by the host or hub. It means that S interface cannot be activated neither by the host nor by a detection of signal on line. This signal detection is disabled. The 15MHz oscillator is not addressed to MACRO-S M2: ACTIVE Mode. When the device is in S6,S7,S8,S9 states from USB point of view, the S interface may be in this state, then it can be deactivated by a PDN primitive (from host) or a hardware power down which is generated by a suspend event on USB bus If wake up is enabled and occurs, the ST5481 recovers activity within the 15ms when it initiates the resume (K state) and about the same time the host or hub initiates a Reset (SEO for 10 ms). M3: INACTIVE Mode (initial mode if CFG1 = 1). Wake up ability concerns wake up of the USB bus (resume event when the bus is in a suspend state) from the S line through a line signal detection done by the S interface. When USB is suspended, The S interface will really be in the active mode once a resume signalling has been done on USB bus after the NLSD signal became active. Interface S states and relationship with Device versus USB States. When USB is configured, a transition from this mode to ACTIVE mode is obtained with a PUP primitive (from host). M1: QUIET mode (initial mode if CFG1 = 0). The line signal detection is enabled. Then it can be activated (go to state ACTIVE) by a line signal detection. Figure 6 : S Interface States - CFG1=0 PON RESET / USB REQUEST/ PIN RESET M1 OFF S LINE ACTIVATION NOT POSSIBLE STT(5)=1 STT(5)=1 STT(5)=0 PUP or NLSD=0 M3 INACTIVE S LINE ACTIVATION POSSIBLE M2 ACTIVE PDN or PDWN=1 9/18 ST5481 If Pin CFG1 is 1, when reset (PON,USB,PIN) is active the initial state is INACTIVE. Figure 7 : S Interface States - CFG1=1 M1 OFF OFFS LINE ACTIVATION NOT POSSIBLE PON RESET / USB REQUEST/ PIN RESET STT(5)=1 STT(5)=1 STT(5)=0 PUP or NLSD=0 M3 INACTIVE S LINE ACTIVATION POSSIBLE M2 ACTIVE PDN or PDWN=1 9 - ENDPOINTS CONFIGURATION AND DEDICATION These endpoints are organized as one interface (interface 0), one configuration (configuration 1). The interface being composed of four alternate settings. Hereafter in the document RX data direction is from S line to PC and is considered as IN by USB protocol. The endpoints are: – 4 isochronous endpoints for B1 and B2 channels (fifo 32 bytes in each direction) • EP3 input endpoint for B1 channel IN(RX) on S line - associated to IN(RX) fifo 32 bytes • EP2 output endpoint for B1 channel OUT(TX) on S line - associated to OUT(TX) fifo 32 bytes • EP5 input endpoint for B2 channel IN(RX) on S line - associated to IN(RX) fifo 32 bytes • EP4 output endpoint for B2 channel OUT(TX) on S line - associated to OUT(TX) fifo 32 bytes – 2 isochronous endpoints for D channels (fifo 16 bytes in each direction) • EP7 input endpoint for D channel IN(RX) on S line - associated to IN(RX) fifo 16 bytes • EP6 output endpoint for D channel OUT(TX) on S line - associated to OUT(TX) fifo 16 bytes 10/18 – 1 control endpoint means management of USB standards, Communication Device Class (CDC) standards (unused), and vendor requests (S interface application dedicated): • EP0 - internal configuration and control registers - D, B1, B2 channels transmit commands - CI primitives to be transmitted – 1 interrupt endpoint used for vendor interrupts • EP1 - channels reception or transmission indications - CI primitives in receive direction - D, B1, B2 channel reception indications - S line status - GPIO input changes The alternate settings are: • Alternate setting 0: EP0, EP1. - initialisation configuration • Alternate setting 1: EP0, EP1, EP2, EP3, P6, EP7 - connection 64Kbits through B1 channel • Alternate setting 2: EP0, EP1, EP4, EP5, EP6, EP7 - connection 64Kbits through B2 channel • Alternate setting 3: EP0, EP1, EP2, EP3, EP4, EP5, EP6, EP7 - connection 128Kbps (144Kbits/sec) through B1 + B2 + (data into D) channels ST5481 USB Descriptors During the USB request GET DESCRIPTOR, the device returns these values from an internal 256 byte ROM. Table 2 : Device Descriptor ROM addr Offset 08 0 09 Field Size Value Description bLengh 1 12h Size of this descriptor in bytes 1 bDescriptorType 1 01h Device Descriptor type 0A 2 bcdUSB 2 0101h 0C 4 bDeviceClass 1 FFh Vendor Specific Class code 0D 5 bDeviceSubClass 1 01h Vendor specific ISDN MODEM subclass 0E 6 bDeviceProtocol 1 01h Vendor specific ISDN SOFT MODEM control protocol 0F 7 bMaxPacketSize0 1 08h Max packet size for EP0 10 8 idVendor 2 0483h ST id vendor 12 10 idProduct 2 481xh Application id product 1 14 12 bcdDevice 2 01xxh Device release 2 16 14 iManufacturer 1 00h No specific manufacturer registred 17 15 iProduct 1 01h product id String descriptor index 1 18 16 iSerialNumber 1 00h No specific serial number registred 19 17 bNumConfigurations 1 01h Number of possible configurations USB spec release number 1.1 Notes 1. This word represents the hardware-software association. The value is programmable through 4 of the 16 bits. the lower bits values are defined by pins ID3 to ID0. 2. This word represents the silicon hardware. The lower 8-bit value is defined at metal layer. The other 8 bits are written into the ROM at diffusion layer. Table 3 : Interface 0 as 0 Descriptor ROM addr Offset 20 0 21 Size Value bLengh 1 09h Size of this descriptor in bytes 1 bDescriptorType 1 02h Configuration Descriptor type 22 2 wTotalLengh 2 24 4 bNumInterface 1 01h number of interfaces supported by this configuration 25 5 bConfigurationValue 1 01h value used to select this conf. 26 6 iConfiguration 1 00h No specific string descriptor for this configuration 27 7 bmAttributes 1 XXh Self powered and remote wake-up abilities programmable 1 XXh max consumption programmable 1 28 Note 8 Field MaxPower 1 Description 00CFh Total length of data byte returned for this configuration 1. Theses words are defined by a transcoding of the pins CFG0, CFG1, RPSM : see power management section for coding of these pins. 11/18 ST5481 10 - ELECTRICAL SPECIFICATIONS Unless otherwise stated, electrical characteristics are specified over the operating range. Typical values are given for VBUS = +5V, VregA = 3.3V, VregD1 = VregD2 = 3.3V, Tamb = 25°C 10.1 - Absolute Maximum Rating Table 4 : Absolute maximum ratings Symbol VBUS Parameter 5V Power Supply Voltage Value Unit 5.5V V VREGD1 3.3V Power Supply Voltage 1 -0.3V to 3.6V V VREGD2 3.3V Power Supply Voltage 1 -0.3V to 3.6V V VREGA 3.3V Power Supply Voltage 1 -0.3V to 3.6V V -0.3 to VREGA + 0.3V V -0.3 to VREGDX + 0.3V V -0.5 to VBUS + 0.3V V 0, +70 °C -55, +125 °C °C VIA Analog Input Voltage 2 VID Digital Input Voltage VID Digital Input Voltage on RPSM Toper Operating Temperature Tstg Storage Temperature Notes GNDA = GNDD1 = GNDD2 = GNDBUS = 0V Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 1. In Remote Power Supply Mode (RPSM=0) 2. For the ISDN S side access “LOP,LON,LIP,LIN” pins the voltage level can temporary exceed the maximum rating due to the phone line conditions. To prevent any damage to the circuit, an external protection circuit must be implemented according to the application schematics. 10.2 - Nominal DC Characteristics (Ta = 0 to 70°C unless otherwise specified) Table 5 : Nominal DC characteristics Symbol VBUS Parameter Supply voltage Ivdd Supply Current (RPSM=1) Ivdds Supply Current in Suspended Mode (RPSM=1) Minimum Typical Maximum Unit 4 5 5.25 V TBD TBD mA TBD mA VREGA Analog regulated OUTPUT power supply (RPSM=1) Analog regulated INPUT power supply (RPSM=0) 3.3-5% 3.3 3.3+5% V VREGD1 Digital regulated OUTPUT power supply (RPSM=1) Digital regulated INPUT power supply (RPSM=0) 3.3-5% 3.3 3.3+5% V VREGD2 Digital regulated INPUT power supply 1 3.3-5% 3.3 3.3+5% V TBD 40 mA 40 mA TBD mA IVregA Analog regulated OUTPUT current (RPSM=1) Analog regulated INPUT current (RPSM=0) IVregD1 Digital regulated OUTPUT current (RPSM=1) Digital regulated INPUT current (RPSM=0) IVregD2 PDLP PD Note 12/18 TBD Digital regulated INPUT current 1 Low Power mode (Suspended mode) TBD mW Operating Power TBD mW 1. VREGD2 is always an analog power input, to be connected to VREGD1 ST5481 A 2.2µF decoupling polarized capacitor (tantal or chemical) is necessary as between VREGA and GNDA. A 1µF decoupling polarized capacitor (tantal or chemical) is necessary as between VREGD1 and GNDD1. A 1µF decoupling polarized capacitor (tantal or chemical) is necessary as between VREGD2 and GNDD2. Table 6 : Digital Pins (except GPIO4 to GPIO7,XTALin, XTALout, RPSM, NRESET) Symbol Parameter VIL Low level input voltage VIH High level input voltage VOL Low level input voltage (ILoad = 2mA) VOH High Level Output Voltage (Iload = -2mA) ILEAK Input Leakage Current Maximum Unit 0.2VRegD1 V V 0.4 0.85VRegD1 IOH High Level Output Current (Vohmin<Vof<VregD1) Schmitt Trigger Hysteresis -2 uA mA 2 0.8 Input Capacitance V V 1 Low level input Current (0<Vol<Volmax) CIN Typical 0.8VRegD1 IOL VHYST Minimum mA V 3 pF Table 7 : GPIO4, GPIO5, GPIO6, GPIO7. Symbol Parameter VIL Low level input voltage VIH High level input voltage VOL Low level input voltage (Iload = 2mA) VOH High Level Output Voltage (Iload = -2mA) ILEAK Input Leakage Current Low level input Current (0<Vol<Volmax) IOH High Level Output Current (Vohmin<Vof<VregD1) CIN Typical Maximum Unit 0.2VRegD1 V 0.8VRegD1 V 0.4 0.85VRegD1 Schmitt Trigger Hysteresis -4 uA mA 4 0.8 Input Capacitance V V 1 IOL VHYST Minimum mA V 3 pF Table 8 : RPSM, NRESET.(5 volt inputs compatible) Symbol VIL Low level input voltage VIH High level input voltage VHYST Note Parameter Schmitt Trigger Hysteresis Minimum Typical 0.7VBUS 1 Maximum Unit 0.3VBUS V V 1.3 V A 10ms time constant will be used (ex: 470 nF, 20 Ω) to generate an adequate pulse on NRESET pin. 13/18 ST5481 Table 9 : Crystal Oscillator (XTALin, XTALout) Symbol Parameter Minimum Typical Maximum Unit 0.2VRegD1 V VIL Low level input voltage VIH High level input voltage 0.8VRegD1 V IL Low level input Current -TBD uA IH High Level Output Current ESR CO Note TBD uA Electrical Serial Resistor 25 Ω Shunt capacitance 7 pF Typical Maximum Unit 0.35 5 ns 60 100 us Typical Maximum Unit Manufacturer example: Ref MMD A20BA1- 15.36MHz Table 10 : 48MHz Internal PLL Symbol JiTTER Lock Time Parameter Minimum Jitter peak-peak Magnitude High level input voltage 10.3 - Universal Serial Bus Interface See Chapter 7 of USB rev1.0 for complete Electrical Specification Table 11 : USB Nominal DC Characteristics (DP, DM) Symbol Parameter Minimum VDI Differential Input Sensitivity [(DP)-(DM)] 0.2 VCM Differential Common Mode Range 0.8 2.5 V VSE Single Ended Receiver Threshold 0.8 2 V VOH High Level output Static voltage (RL of 15KΩ to GND) 2.5 3.6 V VOL Low level input Static voltage (RL of 1.5KΩ to 3.6V) 0.3 V ILO Hi-Z State Data Line Leakage Current (0v <Vin <3,3V) ± 10 uA Cin Transceiver Capacitance (Pin to GND) 20 pF RD Driver Output Resistance (steady state drive) TBD kΩ TBD V See Chapter 7 of USB rev1.0 for complete Electrical Specification. Note Excludes external resistor. In order to comply with USB Specification 1.0, external series resistors of 27 Ω ±1% each on DP and DM are recommended. AC Characteristics (DP, DM) See Chapter 7.3.2 of USB rev1.0 for complete Electrical Specification. 14/18 ST5481 10.4 - Line Side Isdn S Interface Table 12 : ISDN Interface Electrical Characteristics: RIREF = 120kΩ Symbol Minimum Typical Maximum Unit 14.25 15 15.75 mA ITX TX Line Driver current with 70Ω between LOP / LON [ 70 (total)= 50 (load) + 2 x 7 (serial) + 2 x 3 (serial) ] ITX TX Line Driver current with 420Ω between LOP / LON [ 420 (total)= 400 (load) + 2 x 7 (serial) + 2 x 3 (serial) ] 3 mA ITX TX Line Driver current with 25.6Ω between LOP / LON [ 25.6(total)= 5.6 (load) + 2 x 7 (serial) + 2 x 3 (serial) ] 26 mA ZOTX ZTX ZINRX Note Parameter 6 kΩ Impedance when inactive, between LOP / LON 2.5 kΩ Receive Input impedance between LIP / LIN 2.5 kΩ Transmit Output impedance during pulse. ( 20Ω is obtained as total min value with serial resistors: [ 20(total)= ZOTX+ 7(serial) + 7(serial) ]) UIT-TI430, ETSI 300012, ANSI T1.605 standards compliance. 11 - APPLICATION SYNOPTIC 11.1 - Global Environment Figure 8 : Synoptic USB Plug B Usb cable ISDN USB dongle RJ45 NT1 ST5481 S interface 15/18 6 5 0Ω R16 VCC D+out 3 D-in GND.D1/D2 2 1 GNDA GND D+in 4 D-out U2 USBUF01W6 5 6 VCC + C7 10µF 4.7MΩ R18 C8 100nF 2 D3 SMLTV3/3 1 I/01 1 2 U3 ref1 DALC208SC6 ref2 5 I/04 3 I/02 mode3 12 15 14 13 mode2 mode1 11 10 mode0 rpsm 8 9 GndA VregA 6 7 Vbus 5 Gndbus 3 Vregd1 DP 4 DM 44 45 47 46 48 2 I/03 6 R21 510Ω 1 4 R17 120KΩ 2.2µF + C10 VCC D2 LED gpio7 4 R1 510Ω gpio6 lip D1 LED gpio5 lin D+ gpio4 iref 16 17 lon 3 43 U1 ST5481 18 10KΩ 1% R22 10KΩ 1% R23 4.7Ω R20 4.7Ω R19 19 20 21 38 23 C11 100nF 22 39 40 41 42 gpio2 D- Gndd1 lop gpio3 test12 2 gpio1 ncs/test11 USB-B gpio0 sdi/test10 L1 4.7µH xtalin cfg1/test9 test13 37 Y1 1KΩ 24 RJ45 8 7 6 8 9 4 3 2 1 J2 C9 4.7µF 5 + 7 5 4 3 2 1 C4 100nF R2 220KΩ C3 33pF 6 2:1 T60407 L526X010 2fold-Choke 2x5mH 2:1 T1 VCC C2 33pF 11 2fold-Choke 2x5mH 10 12 13 14 15 16 dx/test6 25 dr/test5 26 fs/test4 27 clk/test3 28 id2/test2 29 id3/test1 30 id1/test14 31 id0/test15 32 nreset 33 Vregd2 34 Gndd2 35 C1 47pF 15.36MHz R7 Cfg0/test0 36 fltpll 1 xtalout sd0/test8 16/18 sck/test7 J1 R15 1MΩ ST5481 11.2 - Application Schematic Figure 9 : Schematic ST5481 TQFP48 PACKAGE MECHANICAL DATA Figure 10 : 48 Pins - Full Plastic A A2 e 48 A1 37 36 12 25 E3 E1 E B 1 0,10 mm .004 inch SEATING PLANE c 24 L D3 D1 D L1 13 K 0,25 mm .010 inch GAGE PLANE Millimeter Inch Dimension Minimum Typical A Maximum Minimum Typical 1.60 A1 0.05 A2 1.35 B 0.17 C 0.09 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.22 0.27 0.007 0.009 0.011 0.20 0.004 0.008 D 9.00 0.354 D1 7.00 0.276 D3 5.50 0.216 e 0.50 0.0197 E 9.00 0.354 E1 7.00 0.276 E3 5.50 0.216 L L1 K 0.45 Maximum 0.60 0.75 0.018 1.00 0.024 0.030 0.039 0° (minimum), 7° (maximum) 17/18 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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