STMICROELECTRONICS ST62T01C

ST62T00C/T01C
ST62T03C/E01C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD, SAFE RESET AND 16 PINS
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 64bytes
■ User Programmable Options
■ 9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62T03C)
■ 3I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler
■ Digital Watchdog
■ Oscillator Safe Guard
■ Low Voltage Detector for Safe Reset
■ 8-bit A/D Converter with up to 4 analog inputs
■ On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■ Power-on Reset
■ One external Non-Maskable Interrupt
■ ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
■
■
ST62T00C
ST62T01C
1036
1836
EPROM
(Bytes)
-
ST62T03C
ST62E01C
1036
-
1836
DEVICE
OTP
(Bytes)
9
9
Analog
inputs
4
4
9
9
None
4
I/O Pins
PDIP16
PSO16
SSOP16
CDIP16W
(See end of Datasheet for Ordering Information)
Rev. 2.8
August 1999
1/70
1
Table of Contents
Document
Page
ST62T00C/T01C/ST62T03C/E01C . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
11
11
12
12
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . .
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
14
14
14
15
15
18
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
19
19
19
20
22
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
26
26
27
28
28
30
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
...
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
31
32
32
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34
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Table of Contents
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4.1.4 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
35
37
38
38
38
39
40
4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ST62P00C/P01C/P03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ST6200C/01C/03C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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ST62T00C/T01C ST62T03C/E01C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T00C,T01C,T03C and ST62E01C devices are low cost members of the ST62xx 8-bit
HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All
ST62xx devices are based on a building block approach: a common core is surrounded by a
number of on-chip peripherals.
The ST62E01C is the erasable EPROM version of
the ST62T00C,T01C,T03C and device, which
may be used to emulate the ST62T00C,T01C and
T03C device, as well as the respective
ST6200C,01C and 03C ROM devices.
OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options de-
fined in the programmable option bytes of the
OTP/EPROM versions.
OTP devices offer all the advantages of user programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit programmable prescaler,an 8-bit A/D Converter with up to
4 analog inputs and a Digital Watchdog timer,
making them well suited for a wide range of automotive, appliance and industrial applications.
Figure 1. Block Diagram
8-BIT
A/D CONVERTER
TEST/VPP
PORT A
TEST
PORT B
NMI
INTERRUP T
PROGRAM
:
MEMORY
1036 Bytes
DATA ROM
USER
SELECTAB LE
(ST62T00C,T03C)
1836 Bytes
(ST62T01C, E01C)
DATA RAM
64 Bytes
TIMER
DIGITAL
WATCHDOG
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
8 BIT CORE
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
VDD VSS
OSCILLATOR
RESET
OSCin OSCout
RESET
(*) Analog input availability depend on versions
4/70
4
PA1..PA 3 (20mA Sink)
PB0..PB1
PB3,PB5..PB 7 / Ain (*)
ST62T00C/T01C ST62T03C/E01C
1.2 PIN DESCRIPTIONS
VDD and VSS. Power is supplied to the MCU via
these two pins. VDD is the power connection and
VSS is the ground connection.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
PB0..PB1,PB3,PB5-PB7. These 6 lines are organized as one I/O port (B). Each line may be configured under software control as inputs with or
without internal pull-up resistors, interrupt generating inputs with pull-up resistors, open-drain or
push-pull outputs. PB3,PB5..-PB7 can be used as
analog inputs for the A/D converter on the
ST62T00C, T01C and E01C.
Figure 2. ST62T03C,T00C, T01C, and E01C Pin
Configuration
RESET. The active-low RESET pin is used to restart the microcontroller. Internal pull-up is provided at this pin.
TEST/VPP. The TEST must be held at VSS for normal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM
programming Mode is entered.
NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. The user can select as option the availability of an on-chip pull-up at this pin.
PA1-PA3. These 3 lines are organized as one I/O
port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs. PA1PA3 can also sink 20mA for direct LED driving.
VSS
VDD
1
16
OSCin
2
15
PA1/20 mA Sink
OSCout
3
14
PA2/20 mA Sink
NMI
4
13
PA3/20 mA Sink
VPP/TEST
5
12
PB0
RESET
6
11
PB1
Ain*/PB7
7
10
PB3/Ain*
Ain*/PB6
8
9
PB5/Ain*
*Analog input availability depend on device
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ST62T00C/T01C ST62T03C/E01C
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Briefly, Program space contains user program
code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for subroutine and interrupt service routine nesting.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
DATA SPACE
0000h
000h
RAM / EEPROM
BANKING AREA
0-63
PROGRAM
MEMORY
03Fh
040h
DATA READ-ONLY
MEMORY WINDOW
07Fh
080h
081h
082h
083h
084h
DATA READ-ONLY
MEMORY
WINDOW SELECT
DATA RAM
BANK SELECT
0FFh
ACCUMULATOR
INTERRUPT &
RESET VECTORS
6/70
6
RAM
0C0h
0FF0h
0FFFh
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
ST62T00C/T01C ST62T03C/E01C
MEMORY MAP (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate addressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register)Program Memory Protection.
The Program Memory in OTP or EPROM devices
can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be accepted.
Figure 4. Program Memory Map
ST62T03C,T00C
0000h
ST62T01C, E01C
0000h
NOT IMPLEMENTED
NOT IMPLEMENTED
07FFh
0800h
RESERVED *
087Fh
0880h
0AFFh
0B00h
0B9Fh
RESERVED *
USER
PROGRAM MEMORY
(OTP/EPROM)
1824 BYTES
0BA0h
USER
PROGRAM MEMORY
(OTP)
1024 BYTES
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED *
INTERRUPT VECTORS
RESERVED
NMI VECTOR
USER RESET VECTOR
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED *
INTERRUPT VECTORS
RESERVED
NMI VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
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7
ST62T00C/T01C ST62T03C/E01C
MEMORY MAP (Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space comprises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
1.3.3.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently contains the program code to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
1.3.3.2 Data RAM
In ST6200C/01C/03C devices, the data space includes 60 bytes of RAM, the accumulator (A), the
indirect registers (X), (Y), the short direct registers
(V), (W), the I/O port registers, the peripheral data
and control registers, the interrupt option register
and the Data ROM Window register (DRW register).
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 1. ST6200C/01C/03C Data Memory Space
RESER VED
000h
03Fh
040h
DATA ROM WINDOW AREA
64 BYTES
07Fh
X REGISTER
080h
Y REGISTER
081h
V REGISTER
W REGISTER
082h
083h
DATA RAM 60 BYTES
084h
0BFh
PORT A DATA REGISTE R
0C0h
PORT B DATA REGISTE R
0C1h
RESER VED
0C2h
RESER VED
0C3h
PORT A DIRECTION REGISTE R
PORT B DIRECTION REGISTE R
0C4h
0C5h
RESER VED
0C6h
RESER VED
0C7h
INTERRUPT OPTION REGISTER
0C8h*
DATA ROM WINDOW REGISTER
0C9h*
RESER VED
0CAh
0CBh
PORT A OPTION REGISTER
PORT B OPTION REGISTER
0CCh
0CDh
RESER VED
0CEh
RESER VED
0CFh
A/D DATA REGISTER(except ST62T03C)
0D0h
A/D CONTROL REGISTER (except ST62T03C)
0D1h
TIMER PRESCALER REGISTER
0D2h
TIMER COUNTE R REGISTE R
0D3h
TIMER STATU S CONTROL REGISTER
0D4h
0D5h
RESER VED
0D6h
WATCH DOG REGISTER
0D8h
0D7h
RESER VED
ACCUMULATOR
* WRITE ONLY REGISTER
8/70
8
0D9h
0FEh
0FFh
ST62T00C/T01C ST62T03C/E01C
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program
memory can therefore be used to store either instructions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only register and therefore cannot be accessed using singlebit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrated in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be
written to prior to the first access to the Data readonly memory window area.
Data Window Register (DWR)
Address: 0C9h — Write Only
7
0
-
-
DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 6, 7 = Not used.
Bit 5-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data readonly memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while executing an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an interrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
13 12
DATA ROM
WINDOW REGISTER 7 6
CONTENTS
(DWR)
11 10 9
8
7
6
5
2
1
0
4
3
5
4
3
2
1
0 PROGRAM SPACE ADDRESS
READ
5
4
3
2
1
0
0
1
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
0
0
1
DATA SPACE ADDRESS
:
40h-7Fh
IN INSTRUCTION
Example:
DWR=28h
ROM
ADDRESS:A19h
1
1
0
0
1
1
0
0
DATA SPACE ADDRESS
:
59h
VR01573C
9/70
9
ST62T00C/T01C ST62T03C/E01C
1.4 PROGRAMMING MODES
1.4.1 Option Bytes
The two Option Bytes allow configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when
the chip reset is activated.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the programmer.
The option bytes are located in a non-user map.
No address has to be specified.
EPROM Code Option Byte (LSB)
7
0
PROOSCIL
TECT
-
-
NMI
PULL
-
WDACT
OSGEN
EPROM Code Option Byte (MSB)
15
-
8
-
-
-
-
-
EXTCNTL
LVD
D15-D11. Reserved. Must be cleared
D10. Reserved. Must be set to 1.
EXTCNTL. External STOP MODE control.. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one.. When
EXTCNTL is low, STOP mode is not available with
the watchdog active.
10/70
10
LVD. LVD RESET enable.When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.
PROTECT. Readout Protection. This bit allows the
protection of the software contents against piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.
OSCIL. Oscillator selection. When this bit is low,
the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.
D5. Reserved. Must be cleared to zero.
D4. Reserved. Must be set to one.
NMI PULL. NMI Pull-Up. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.
D2. Reserved. Must be set to 1.
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.
OSGEN. Oscillator Safe Guard. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
The Option byte is written during programming either by using the PC menu (PC driven Mode) or
automatically (stand-alone mode)
ST62T00C/T01C ST62T03C/E01C
PROGRAMMING MODES (Cont’d)
1.4.2 Program Memory
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/VPP pin. The
programming flow of the ST62T00C,T01C,T03C
and E01C is described in the User Manual of the
EPROM Programming Board.
Table 2. ST62T00C, T03C Program Memory Map
Device Address
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFF h
Description
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 3. ST62T01C,E01C Program Memory Map
Device Address
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFF h
Description
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Note: OTP/EPROM devices can be programmed
with the development tools available from STMicroelectronics (ST62E2X-EPB or ST622X-KIT).
1.4.3 EPROM Erasing
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prevent unintentional erasure problems when testing the application in such an environment.
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 30Wsec/cm2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet
lamp with 12000µW/cm 2 power rating. The
ST62E01C should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.
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11
ST62T00C/T01C ST62T03C/E01C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other register of the data space.
Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct registers as any other register of the data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Figure 6. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin
OSCout
INTERRUPTS
CONTROLLER
DATA SPACE
OPCODE
FLAG
VALUES
CONTROL
SIGNALS
DATA
ADDRESS /READ LINE
2
RAM/EEPR OM
PROGRAM
ADDRESS 256
DECODER
ROM/EPRO M
A-DATA
B-DATA
DATA
ROM/EPROM
DEDICAT IONS
ACCUMULATOR
12
Program Counter
and
6 LAYER STACK
FLAGS
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
12/70
12
ST62T00C/T01C ST62T03C/E01C
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
The PC value is incremented after reading the address of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt
PC=Interrupt vector
- Reset
PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZNMI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI instruction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context
switching and thus retain their status.
The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also participates in the rotate left instruction.
The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.
Switching between the three sets of flags is performed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumulator, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subroutine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are executed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
lFigure 7. ST6 CPU Programming Mode
INDEX
REGISTER
b11
b7
X REG. POINTER
b0
b7
Y REG. POINTER
b0
b7
V REGISTER
b7
W REGISTER
b0
b7
ACCUM ULATO R
b0
PROGRAM COUNTER
SHORT
DIRECT
ADDRESSING
MODE
b0
b0
SIX LEVELS
STACK REGISTER
NORMAL FLAGS
C
Z
INTERRUPT FLAGS
C
Z
NMI FLAGS
C
Z
VA000423
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13
ST62T00C/T01C ST62T03C/E01C
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor
(RNET). In addition, a Low Frequency Auxiliary Oscillator (LFAO) can be switched in for security reasons, to reduce power consumption, or to offer the
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automatically limits the internal clock frequency (f INT) as a
function of VDD, in order to guarantee correct operation. These functions are illustrated in Figure 9,
Figure 10, Figure 11 and Figure 12.
Figure 8 illustrates various possible oscillator configurations using an external crystal or ceramic resonator, an external clock input, an external resistor
(RNET), or the lowest cost solution using only the
LFAO. CL1 an CL2 should have a capacitance in the
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
The internal MCU clock frequency (fINT) is divided
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.
With an 8MHz oscillator frequency, the fastest machine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillator configuration may be specified by selecting theappropriate option.When the CRYSTAL/
RESONATORoption isselected, itmustbeusedwith
a quartz crystal, a ceramic resonator or an external
signal providedonthe OSCinpin.When theRC NETWORK option is selected, the system clock is generated by an external resistor.
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator is automatically started.
Figure 8. Oscillator Configurations
CRYSTAL/RES ONATOR CLOCK
CRYSTAL/RESON ATOR option
ST6xxx
OSCin
OSCout
CL1n
C L2
EXTERNAL CLOCK
CRYSTAL/RESON ATOR option
ST6xxx
OSCin
OSCout
NC
RC NETW ORK
RC NETW ORK option
ST6xxx
OSCin
OSCout
NC
RNET
INTEGRA TED CLOCK
CRYSTAL/RESON ATOR option
OSG ENABLED option
ST6xxx
OSCin
OSCout
NC
14/70
14
ST62T00C/T01C ST62T03C/E01C
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
the software instruction at fLFAO clock frequency.
3.1.2 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provided, main oscillator switched off...).
User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced fLFAO frequency. The A/D converter accuracy is decreased, since the internal frequency is below 1MHz.
At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.
ADCR
Address: 0D1h — Read/Write
7
ADCR ADCR ADCR ADCR ADCR
7
6
5
4
3
0
OSC
OFF
ADCR ADCR
1
0
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register . These bits are not used.
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
3.1.3 Oscillator Safe Guard
The Oscillator Safe Guard (OSG) affords drastically increased operational integrity in ST62xx devices. The OSG circuit provides three basic func-
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide a fixed frequency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
supply voltage, in order to ensure correct operation even if the power supply should drop.
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
whose cross-over frequency is device dependent.
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
9). In all cases, when the OSG is active, the maximum internal clock frequency, fINT, is limited to
fOSG, which is supply voltage dependent. This relationship is illustrated in Figure 12.
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator may be accessed. This oscillator starts operating after the first missing edge of
the main oscillator (see Figure 10).
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock frequency of the device is kept within the range the
particular device can stand (depending on VDD),
and below fOSG: the maximum authorised frequency with OSG enabled.
Note. The OSG should be used wherever possible
as it provides maximum safety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency
to fOSG.
Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and is not accurate.
For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.
It should also be noted that power consumption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature).
15/70
15
ST62T00C/T01C ST62T03C/E01C
CLOCK SYSTEM (Cont’d)
Figure 9. OSG Filtering Principle
(1)
(2)
(3)
(4)
(1) Maximum Frequency for the device to work correctly
(2) Actual Quartz Crystal Frequency at OSCin pin
(3) Noise from OSCin
(4) Resulting Internal Frequency
VR001932
Figure 10. OSG Emergency Oscillator Principle
Main
Oscillator
Emergency
Oscillator
Internal
Frequency
VR001933
16/70
16
ST62T00C/T01C ST62T03C/E01C
CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram
POR
Core
: 13
OSG
TIMER 1
M
U
X
MAIN
OSCILLATOR
fINT
Watchdog
: 12
LFAO
:1
Main Oscillator off
Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)
Maximum FREQU ENCY (MHz)
8
4
FUNCTIONALITY IS NOT
GUARANTEED
IN THIS AREA
7
6
5
4
3
3
fOSG
2
fOSG Min
2
1
1
2.5
3
3.6
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD )
VR01807
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guaranteed at a frequency of at least fOSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a fOSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at fOSG.
17/70
17
ST62T00C/T01C ST62T03C/E01C
3.2 RESETS
The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog peripheral timing out.
– by Low Voltage Detection (LVD)
3.2.1 RESET Input
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET pin are acceptable, provided VDD has
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization sequence is executed following expiry of the internal
delay period.
If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
3.2.2 Power-on Reset
The function of the POR circuit consists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to
allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence
18/70
18
is executed immediately following the internal delay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from
0V.
As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy
(presenting oscillation) VDD supplies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performances.
Figure 13. Reset and Interrupt Processing
RESET
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
SELECT
NMI MODE FLAGS
PUT FFEH
ON ADDRESS BUS
YES
IS RESET STILL
PRESENT?
NO
LOAD PC
FROM RESET LOCATIONS
FFE/FFF
FETCH INSTRUCTION
VA000427
ST62T00C/T01C ST62T03C/E01C
RESETS (Cont’d)
3.2.3 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst other things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-
ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start’s running and
sinking current on the supply.
As long as the supply voltage is below the reference value, there is a internal and static RESET
command. The MCU can start only when the supply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figure 14, that represents a powerup, power-down sequence.
Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage Detector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
VDD
VUp
Vdn
RESET
RESET
time
VR02106A
3.2.5 Application Notes
No external resistor is required between VDD and
the Reset pin, thanks to the built-in pull-up device.
Direct external connection of the pin RESET to
VDD must be avoided in order to ensure safe behaviour of the internal reset sources (AND.Wired
structure).
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ST62T00C/T01C ST62T03C/E01C
RESETS (Cont’d)
3.2.6 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The initialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced.
Figure 15. Reset and Interrupt Processing
RESET
JP
JP:2 BYTES/4 CYCLES
RESET
VECTOR
INITIALIZATION
ROUTINE
RETI: 1 BYTE/2 CYCLES
RETI
VA00181
Figure 16. Reset Block Diagram
VDD
fOSC
COUNTER
RPU
RESD1)
RESET
ST6
INTERNA L
RESET
CK
AND. Wired
RESET
RESET
POWER ON RESET
WATCHD OG RESET
LVD RESET
VR02107A
1) Resistive ESD protection. Value not guaranteed.
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ST62T00C/T01C ST62T03C/E01C
RESETS (Cont’d)
Table 4. Register Reset Status
Register
Oscillator Control Register
Address(es)
0DCh
Status
Comment
fINT = fOSC; OSG disabled
Port Data Registers
0C0h to 0C1h
Port Direction Register
0C4h to 0C5h
Port Option Register
0CCh to 0CDh
Interrupt Option Register
0C8h
Interrupt disabled
TIMER Status/Control
X, Y, V, W, Register
0D4h
080H TO 083H
TIMER disabled
Accumulator
0FFh
Data RAM
084h to 0BFh
Data ROM Window Register
0C9h
A/D Result Register
TIMER Counter Register
0D0h
0D3h
FFh
TIMER Prescaler Register
0D2h
7Fh
Watchdog Counter Register
0D8h
FEh
A/D Control Register
0D1h
40h
I/O are Input with pull-up
00h
Undefined
I/O are Input with pull-up
I/O are Input with pull-up
As written if programmed
Max count loaded
A/D in Standby (When available)
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ST62T00C/T01C ST62T03C/E01C
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usually caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be reloaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 5).
In the SOFTWARE option, the Watchdog is disabled until bit C of the DWDR register has been set.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
In the HARDWARE option, the Watchdog is permanently enabled. Since the oscillator will run continuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then governed by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP instruction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU enters STOP mode.
When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its
activity.
Table 5. Recommended Option Choices
Functions Required
Stop Mode & Watchdog
Stop Mode
Watchdog
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Recommended Options
“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
“SOFTWARE WATCHDOG”
“HARDWARE WATCHDOG”
ST62T00C/T01C ST62T03C/E01C
Figure 17. Watchdog Counter Control
D0
C
D1
SR
D2
D3
D4
D5
WATCHDOG COUNTER
WATCHDOG CONTROL REGISTER
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, location 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watchdog timer period. This time period can be set to the
user’s requirements by setting the appropriate value for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which generates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Reset.
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the associated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this register. The relationship between the DWDR register
bits and the physical implementation of the Watchdog timer downcounter is illustrated in Figure 17.
Only the 6 most significant bits may be used to define the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer periods ranging from 384µs to 24.576ms).
RESET
T5
T4
T3
T2
D6
T1
D7
T0
÷28
OSC ÷12
VR02068A
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ST62T00C/T01C ST62T03C/E01C
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
Address: 0D8h — Read/Write
Reset status: 1111 1110b
7
T0
0
T1
T2
T3
T4
T5
SR
C
Bit 0 = C: Watchdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is selected, the Watchdog function is activated by setting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
When C is kept low the counter can be used as a
7-bit timer.
This bit is cleared to “0” on Reset.
Bit 1 = SR: Software Reset bit
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0: Downcounter bits
It should be noted that the register bits are reversed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
These bits are set to “1” on Reset.
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3.3.2 Application Notes
The Watchdog plays an important supporting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog related options should be selected on the basis of a
trade-off between application security and STOP
mode availability.
When STOP mode is not required, hardware activation without EXTERNAL STOP MODE CONTROL should be preferred, as it provides maximum security, especially during power-on.
When STOP mode is required, hardware activation and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP mode to be entered when the MCU
is idle.
The NMI pin can be connected to an I/O line (see
Figure 18) to allow its state to be controlled by software. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been unexpectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH
ST62T00C/T01C ST62T03C/E01C
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are executed after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
It should be noted that when the GEN bit is low (interrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
Figure 18. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
SWITCH
NMI
I/O
VR02002
Figure 19. Digital Watchdog Block Diagram
RESET
Q
RSFF
R
S
-27
DB 1.7 LOAD SET
DB0
-2 8
SET
-12
OSCILLATOR
CLOCK
8
WRITE
RESET
DATA BUS
VA00010
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ST62T00C/T01C ST62T03C/E01C
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source is associated with a specific Interrupt Vector which contains a Jump instruction to the associated interrupt
service routine. These vectors are located in Program space (see Table 6).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the interrupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt service routine, thus servicing the interrupt.
Interrupt sources are linked to events either on external pins, or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the highest priority and can interrupt any interrupt routine
at any time; the other four interrupts cannot interrupt each other. If more than one interrupt request
is pending, these are processed by the processor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Table 6. Interrupt Vector Map
Interrupt Source
Interrupt source #0
Interrupt source #1
Interrupt source #2
Interrupt source #3
Interrupt source #4
Priority
1
2
3
4
5
Vector Address
(FFCh-FFDh)
(FF6h-FF7h)
(FF4h-FF5h)
(FF2h-FF3h)
(FF0h-FF1h)
ically reset by the core at the beginning of the nonmaskable interrupt service routine.
Interrupt request from source #1 can be configured either as edge or level sensitive by setting accordingly the LES bit of the Interrupt Option Register (IOR).
Interrupt request from source #2 are always edge
sensitive. The edge polarity can be configured by
setting accordingly the ESB bit of the Interrupt Option Register (IOR).
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine before being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Storage of interrupt requests is not available in level sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execution.
At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropriate interrupt service routine is executed instead.
Table 7. Interrupt Option Register Description
GEN
SET
CLEARED
SET
3.4.1 Interrupt request
All interrupt sources but the Non Maskable Interrupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, including the Non Maskable Interrupt source, can restart the MCU from STOP/WAIT modes.
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
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ESB
CLEARED
SET
LES
CLEARED
OTHERS
NOT USED
Enable all interrupts
Disable all interrupts
Rising edge mode on interrupt source #2
Falling edge mode on interrupt source #2
Level-sensitive mode on interrupt source #1
Falling edge mode on interrupt source #1
ST62T00C/T01C ST62T03C/E01C
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
The interrupt procedure is very similar to a call procedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a result, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The following list summarizes the interrupt procedure:
MCU
– The interrupt is detected.
– The C and Z flags are replaced by the interrupt
flags (or by the NMI flags).
– The PC contents are stored in the first level of
the stack.
– The normal interrupt lines are inhibited (NMI still
active).
– The first internal latch is cleared.
– Theassociated interrupt vectoris loaded inthe PC.
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL mode and especially during the execution of an ”ldi IOR, 00h” instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the ”ldi” instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
User
– User selected registers are saved within the interrupt service routine (normally on a software
stack).
– The source of the interrupt is found by polling the
interrupt flags (if more than one source is associated with the same vector).
– The interrupt is serviced.
– Return from interrupt (RETI)
MCU
– Automatically the MCU switches back to the normal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt routine usually begins by the identifying the device which generated the interrupt request (by polling). The user should save the registers which are used within the interrupt routine in a
software stack. After the RETI instruction is executed, the MCU returns to the main routine.
Figure 20. Interrupt Processing Flow Chart
INS TRU CTION
FETCH
INS TRU CTION
EXEC UTE
IN STRUC TION
WAS
THE INS TRU CTION
A RE TI ?
LOAD PC FROM
INT ERR UP T VEC TOR
NO
(FFC/FFD)
YES
YES
IS THE CORE
ALREADY IN
NORMAL MODE?
?
SET
INTER RU PT MASK
NO
C LEAR
INT ERR UP T MASK
SELECT
PROGRAM FLAGS
PUSH THE
PC IN TO THE STACK
SELECT
IN TER NA L MODE FLAG
”POP”
THE STACK ED PC
C HEC K IF THER E IS
AN IN TER RUP T R EQUEST
AN D INTE RRU PT MASK
NO
?
YES
VA000014
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ST62T00C/T01C ST62T03C/E01C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to enable/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
7
-
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is active but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
0
LES
ESB
GEN
-
-
-
-
Interrupt sources available on the ST62E01C/
T01C are summarized in the Table 8 with associated mask bit to enable/disable the interrupt request.
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 8. Interrupt Requests and Mask Bits
Peripheral
Register
Address
Register
Mask bit
Masked Interrupt Source
GENERAL
IOR
C8h
GEN
All Interrupts, excluding
NMI
TIMER
A/D CONVERTER(*)
Port PAn
Port PBn
TSCR
ADCR
ORPA-DRPA
ORPB-DRPB
D4h
D1h
C4h-CCh
C5h-CDh
ETI
EAI
ORPAn-DRPAn
ORPBn-DRPBn
TMZ: TIMER Overflow
EOC: End of Conversion
PAn pin
PBn pin
*Except ST62T03C
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28
Interrupt
vector
Vector 3
Vector 4
Vector 1
Vector 2
ST62T00C/T01C ST62T03C/E01C
INTERRUPTS (Cont’d)
Figure 21. Interrupt Block Diagram
VDD
FF
CLK
Q
CLR
NMI
INT #0 - NMI (FFC,D)
I0 Start
FF
PBE
PORT A
0
CLK
Q
CLR
INT #1 (FF6,7)
MUX
FROM REGIST ER
SINGLE BIT ENABLE
PORT A,B
I1 Start
PBE
1
RESTART FROM
STOP/WAI T
IOR REG. C8H, bit 6
VDD
PORT B
Bits
PBE
FF
CLK
PBE
INT #2 (FF4,5)
Q
CLR
IOR REG. C8H, bit 5
I2 Start
TIMER
TMZ
ETI
INT #3 (FF2,3)
ADC(*)
EAI
EOC
INT #4 (FF0,1)
GEN
VA0426T
(*)Except on ST62T03C
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ST62T00C/T01C ST62T03C/E01C
3.5 POWER SAVING MODES
The WAIT and STOP modes have been implemented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
described in the following paragraphs.
In addition, the Low Frequency Auxiliary Oscillator
(LFAO) can be used instead of the main oscillator
to reduce power consumption in RUN and WAIT
modes.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen”
state where the core stops processing the program instructions, the RAM contents and peripheral registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still active.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capability of monitoring external events. The active oscillator (main oscillator or LFAO) is not stopped in
order to provide a clock signal to the peripherals.
Timer counting may be enabled as well as the
Timer interrupt, before entering the WAIT mode:
this allows the WAIT mode to be exited when a
Timer interrupt occurs. The same applies to other
peripherals which use the clock signal.
If the power consumption has to be further reduced, the Low Frequency Auxiliary Oscillator
(LFAO) can be used in place of the main oscillator,
if its operating frequency is lower. If required, the
LFAO must be switched on before entering the
WAIT mode.
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If the WAIT mode is exited due to a Reset (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset procedure. If an interrupt is generated during WAIT
mode, the MCU’s behaviour depends on the state
of the processor core prior to the WAIT instruction,
but also on the kind of interrupt request which is
generated. This is described in the following paragraphs. The processor core does not generate a
delay following the occurrence of the interrupt, because the oscillator clock is still available and no
stabilisation period is necessary.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is available. When in STOP mode, the MCU is placed in
the lowest power consumption mode. In this operating mode, the microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and peripheral registers are preserved as long as the
power supply voltage is higher than the RAM retention voltage, and the ST62xx core waits for the
occurrence of an external interrupt request or a
Reset to exit the STOP state.
If the STOP state is exited due to a Reset (by activating the external pin) the MCU will enter a normal reset procedure. Behaviour in response to interrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is generated.
This case will be described in the following paragraphs. The processor core generates a delay after occurrence of the interrupt request, in order to
wait for complete stabilisation of the oscillator, before executing the first instruction.
ST62T00C/T01C ST62T03C/E01C
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an interrupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable interrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
Interrupts do not affect the oscillator selection,
consequently, when the LFAO is used, the user
program must manage oscillator selection as soon
as normal RUN mode is resumed.
3.5.3.1 Normal Mode
If the MCU was in the main routine when the WAIT
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt occurs; the related interrupt routine is executed and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, providing no other interrupts are pending.
3.5.3.2 Non Maskable Interrupt Mode
If the STOP or WAIT instruction has been executed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STOP or WAIT instruction is executed, and the MCU remains in non-maskable interrupt mode, even if another interrupt has been
generated.
3.5.3.3 Normal Interrupt Mode
If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt occurs. Nevertheless, two cases must be considered:
– If the interrupt is a normal one, the interrupt routine in which the WAIT or STOP mode was en-
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance with their priority.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is processed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal interrupt mode.
Notes:
To achieve the lowest power consumption during
RUN or WAIT modes, the user program must take
care of:
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic levels);
– placing all peripherals in their power down
modes before entering STOP mode;
– selecting the Low Frequency Auxiliary Oscillator
(provided this runs at a lower frequency than the
main oscillator).
When the hardware activated Watchdog is selected, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruction will be executed in its place.
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an interrupt, it will stop it generating a wake-up signal.
The WAIT and STOP instructions are not executed if an enabled interrupt request is pending.
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ST62T00C/T01C ST62T03C/E01C
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the following
input or output configurations:
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
– Push-pull output
– Open drain output
The lines are organised as bytewise Ports.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associated with the PA0 line of Port A).
The DATA registers (DRx), are used to read the
voltage level values of the lines which have been
configured as inputs, or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
be also written by user software, in conjunction
with the related option registers, to select the different input mode options.
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will directly affect the Port data register causing an undesired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O registers are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
Figure 22. I/O Port Block Diagram
SIN CONTROLS
RESET
VDD
DATA
DIRECTION
REGISTE R
VDD
INPUT /OUTPUT
DATA
REGISTE R
SHIFT
REGIST ER
OPTION
REGISTE R
SOUT
TO INTERRU PT
TO ADC
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VA00413
ST62T00C/T01C ST62T03C/E01C
I/O PORTS (Cont’d)
4.1.1 Operating Modes
Each pin may be individually programmed as input
or output with various configurations.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and Option registers (OR). Table 9 illustrates the various port
configurations which can be selected by user software.
4.1.1.1 Input Options
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-impedance state.
4.1.1.2 Interrupt Options
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The interrupt trigger modes (falling edge, rising edge and
low level) can be configured by software as described in the Interrupt Chapter for each port.
4.1.1.3 Analog Input Options
Some pins can be configured as analog inputs by
programming the OR and DR registers accordingly. These analog inputs are connected to the onchip 8-bit Analog to Digital Converter. ONLY ONE
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively shorted.
Table 9. I/O Port Option Selection
DDR
OR
DR
Mode
0
0
0
Input
With pull-up, no interrupt
Optio n
0
0
1
Input
No pull-up, no interrupt
0
1
0
Input
With pull-up and with interrupt
0
1
1
Input
Analog input (when available)
1
0
X
Output
Open-drain output (20mA sink when available)
1
1
X
Output
Push-pull output (20mA sink when available)
Note: X = Don’t care
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ST62T00C/T01C ST62T03C/E01C
I/O PORTS (Cont’d)
4.1.2 Safe I/O State Switching Sequence
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recommended safe transitions are illustrated in Figure
23. All other transitions are potentially risky and
should be avoided when changing the I/O operating mode, as it is most likely that undesirable sideeffects will be experienced, such as spurious interrupt generation or two pins shorted together by the
analog multiplexer.
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data register latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data register:
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning: Care must also be taken to not use instructions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by software (AND instruction).
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power consumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturbance to
the conversion.
Figure 23. Diagram showing Safe I/O State Transitions
Interrupt
pull-up
010*
011
Input
Analog
Input
pull-up (Reset
state)
000
001
Input
Output
Open Drain
100
101
Output
Open Drain
Output
Push-pull
110
111
Output
Push-pull
Note *. xxx = DDR, OR, DR Bits respectively
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ST62T00C/T01C ST62T03C/E01C
I/O PORTS (Cont’d)
4.1.3 I/O Port Option Registers
ORA/B (CCh PA, CDh PB) Read/Write
7
Px7
Px6
Px5
Px4
Px3
Px2
Px1
4.1.5 I/O Port Data Registers
DRA/B (C0h PA, C1h PB) Read/Write
0
7
Px0
Px7
Bit 7-0 = Px7 - Px0: Port A and B Option Register
bits.
4.1.4 I/O Port Data Direction Registers
DDRA/B (C4h PA, C5h PB) Read/Write
7
Px7
0
Px6
Px5
Px4
Px3
Px2
Px1
Px0
Bit 7-0 = Px7 - Px0: Port A and B Data Registers
bits.
Note: X = Don’t care
0
Px6
Px5
Px4
Px3
Px2
Px1
Px0
Bit 7-0 = Px7 - Px0: Port A and B Data Direction
Registers bits.
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ST62T00C/T01C ST62T03C/E01C
I/O PORTS (Cont’d)
Table 10. I/O Port Option Selections
MODE
AVAILABLE ON (1)
SCHEMATIC
PA1-PA3
Input
PB0,PB1,PB3,PB5-PB7
Data in
Interrupt
Input
with pull up
PA1-PA3
PB0,PB1,PB3,PB5-PB7
Data in
Interrupt
Input
with pull up
PA1-PA3
PB0,PB1,PB3,PB5-PB7
Data in
with interrupt
Interrupt
Analog Input
PB3,PB5-PB7
(Except ST62T03C)
ADC
Open drain output
5mA
PB0,PB1,PB3,PB5-PB7
Data out
Open drain output
PA1-PA3
20mA
Push-pull output
5mA
PB0,PB1,PB3,PB5-PB7
Data out
Push-pull output
20mA
PA1-PA3
Note 1. Provided the correct configuration has been selected.
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ST62T00C/T01C ST62T03C/E01C
4.2 TIMER
The prescaler input is the internal frequency (fINT)
divided by 12. The prescaler decrements on the
rising edge. Depending on the division factor programmed by PS2, PS1 and PS0 bits in the TSCR
(see Figure 11), the clock input of the timer/counter register is multiplexed to different sources. For
division factor 1, the clock input of the prescaler is
also that of timer/counter; for factor 2, bit 0 of the
prescaler register is connected to the clock input of
TCR. This bit changes its state at half the frequency of the prescaler input clock. For factor 4, bit 1 of
the PSC is connected to the clock input of TCR,
and so forth. The prescaler initialize bit, PSI, in the
TSCR register must be set to allow the prescaler
(and hence the counter) to start. If it is cleared, all
the prescaler bits are set and the counter is inhibited from counting. The prescaler can be loaded
with any value between 0 and 7Fh, if bit PSI is set.
The prescaler tap is selected by means of the
PS2/PS1/PS0 bits in the control register.
Figure 25 illustrates the Timer’s working principle.
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit programmable prescaler, giving a maximum count of 215.
Figure 24 shows the Timer Block Diagram. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, which can be addressed in Data space as a RAM location at address 0D3h. The state of the 7-bit prescaler can be
read in the PSC register at address 0D2h. The
control logic device is managed in the TSCR register as described in the following paragraphs.
The 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can
be loaded and read under program control. When
it decrements to zero then the TMZ (Timer Zero)bit
in the TSCR is set. If the ETI (Enable Timer Interrupt) bit in the TSCR is also set, an interrupt request is generated. The Timer interrupt can be
used to exit the MCU from WAIT mode.
Figure 24. Timer Block Diagram
DATA BUS
PSC
fINT
12
8
8
6
5
4
3
2
1
0
8-BIT
COUNTER
SELECT
1 OF 7
8
b7 b6
b5
b4
b3 b2
b1
b0
STATUS/CONTROL
REGISTER
TMZ ETI D5
D4 PSI PS2 PS1 PS0
3
INTERRUPT
LINE
VR02070A
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ST62T00C/T01C ST62T03C/E01C
TIMER (Cont’d)
4.2.1 Timer Operation
The Timer prescaler is clocked by the prescaler
clock input (fINT ÷ 12).
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high.
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request associated with Interrupt Vector
#3 is generated. When the counter decrements to
zero, the TMZ bit in the TSCR register is set to
one.
4.2.3 Application Notes
TMZ is set when the counter reaches zero; however, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is loaded with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
Figure 25. Timer Working Principle
7-BIT PRESCALER
BIT0
CLOCK
0
BIT1
1
BIT2
2
BIT3
BIT4
3
4
8-1 MULTIPLEXER
BIT5
BIT6
6
5
7
PS0
PS1
PS2
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
8-BIT COUNTER
VA00186
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ST62T00C/T01C ST62T03C/E01C
TIMER (Cont’d)
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
PSI=“0” both counter and prescaler are not running.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Select. These bits select the division ratio of the prescaler register.
Table 11. Prescaler Division Factors
PS2
0
0
0
0
1
1
1
1
4.2.4 Timer Registers
Timer Status Control Register (TSCR)
Address: 0D4h — Read/Write
7
TMZ
0
ETI
D5
D4
PSI
PS2
PS1
PS0
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit
must be cleared by user software before starting a
new count.
Bit 6 = ETI: Enable Timer Interrup
When set, enables the timer interrupt request
(vector #3). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is generated.
Bit 5 = D5: Reserved
Must be set to “1”.
Bit 4 = D4
Do not care.
Bit 3 = PSI: Prescaler Initialize Bit
Used to initialize the prescaler and inhibit its counting. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescaler is enabled to count downwards. As long as
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
Divided by
1
2
4
8
16
32
64
128
Timer Counter Register TCR
Address: 0D3h — Read/Write
7
D7
0
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: Counter Bits.
Prescaler Register PSC
Address: 0D2h — Read/Write
7
D7
0
D6
D5
D4
D3
D2
D1
D0
Bit 7 = D7: Always read as ”0”.
Bit 6-0 = D6-D0: Prescaler Bits.
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ST62T00C/T01C ST62T03C/E01C
4.3 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converter with analog inputs as alternate I/O
functions (the number of which is device dependent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock frequency
of 8MHz).
The ADC converts the input voltage by a process
of successive approximations, using a clock frequency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is decreased.
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Option and Data registers (refer to I/O ports description for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input simultaneously, to avoid device malfunction.
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control register, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This automatically clears (resets to “0”) the End Of Conversion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before completing the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a logical “0”.
The A/D converter features a maskable interrupt
associated with the end of conversion. This interrupt is associated with interrupt vector #4 and occurs when the EOC bit is set (i.e. when a conversion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
The power consumption of the device can be reduced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control register to “0”. If PDS=“1”, the A/D is powered and enabled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
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sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automatically disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
Figure 26. ADC Block Diagram
Ain
CONVERTER
INTERRUPT
CLOCK
RESET
AVSS
AVDD
CONTROL REGISTER
RESULT REGISTER
8
8
CORE
CONTROL SIGNALS
CORE
VA00418
4.3.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire conversion cycle. Voltage variation should not exceed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during conversion.
When selected as an analog channel, the input pin
is internally connected to a capacitor Cad of typically 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conversion. In the worst case, conversion starts one instruction (6.5 µs) after the channel has been selected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated using the following formula:
6.5µs = 9 x Cad x ASI
(capacitor charged to over 99.9%), i.e. 30 kΩ including a 50% guardband. ASI can be higher if Cad
has been charged for a longer period by adding instructions before the start of conversion (adding
more than 26 CPU cycles is pointless).
ST62T00C/T01C ST62T03C/E01C
A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the microprocessor, the user should not switch heavily loaded output signals during conversion, if high precision is required. Such switching will affect the supply voltages used as analog references.
The accuracy of the conversion depends on the
quality of the power supplies (V DD and VSS). The
user must take special care to ensure a well regulated reference voltage is present on the VDD and
VSS pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
suitable decoupling capacitor is used at the VDD
pin.
The converter resolution is given by::
V DD – V SS
--------------------------256
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Conversion resolution can be improved if the power supply voltage (VDD ) to the microcontroller is
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switching. Nevertheless, the WAIT instruction should be
executed as soon as possible after the beginning
of the conversion, because execution of the WAIT
instruction may cause a small variation of the VDD
voltage. The negative effect of this variation is minimized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
The best configuration, from an accuracy standpoint, is WAIT mode with the Timer stopped. Indeed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.
A/D Converter Control Register (ADCR)
Address: 0D1h — Read/Write
7
EAI
0
EOC
STA
PDS
D3
D2
D1
D0
Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
Bit 6 = EOC: End of conversion. Read Only. This
read only bit indicates when a conversion has
been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
Bit 5 = STA: Start of Conversion. Write Only. Writing a “1” to this bit will start a conversion on the selected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Bit 4 = PDS: Power Down Selection. This bit activates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (idle
mode).
Bit 3-0 = D3-D0. Not used
A/D Converter Data Register (ADR)
Address: 0D0h — Read only
7
D7
0
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.
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ST62T00C/T01C ST62T03C/E01C
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Program space, Data space, and Stack space. Program space contains the instructions which are to
be executed, plus the data for immediate mode instructions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and constants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the immediate addressing mode is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter).
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Direct addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the opcode. Short direct addressing is a subset of the direct addressing mode. (Note that 80h and 81h are
also indirect registers).
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
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bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is twobyte long.
Program Counter Relative. The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is
executed. The relative addressing mode instruction is one-byte long. The opcode is obtained in
adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to
obtain the address of the branch.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the address of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Bit Test & Branch. The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and
branch instruction is three-byte long. The bit identification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Program space. The third byte is the jump displacement, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the indirect registers, X or Y (80h,81h). The indirect register is selected by the bit 4 of the opcode. A register indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
ST62T00C/T01C ST62T03C/E01C
5.3 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following paragraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Load & Store. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.
Table 12. Load & Store Instructions
Instruction
LD
LD
LD
LD
LD
A, X
A, Y
A, V
A, W
X, A
LD Y, A
LD V, A
LD W, A
LD A, rr
LD rr, A
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Addressing Mode
Bytes
Cycles
Direct
Direct
Direct
Direct
Direct
1
1
1
1
1
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
1
1
1
2
2
1
1
1
1
2
3
Short
Short
Short
Short
Short
Flags
4
4
4
4
4
Z
∆
∆
∆
∆
∆
C
*
*
*
*
*
4
4
4
4
4
4
4
4
4
4
4
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
*
*
*
*
*
*
*
*
*
*
*
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆ . Affected
* . Not Affected
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ST62T00C/T01C ST62T03C/E01C
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while
the other can be either a data space memory con-
tent or an immediate value in relation with the addressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always
the accumulator.
Table 13. Arithmetic & Logic Instructions
Instruction
ADD A, (X)
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
CLR r
COM A
CP A, (X)
CP A, (Y)
CP A, rr
CPI A, #N
DEC X
DEC Y
DEC V
DEC W
DEC A
DEC rr
DEC (X)
DEC (Y)
INC X
INC Y
INC V
INC W
INC A
INC rr
INC (X)
INC (Y)
RLC A
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
Addressing Mode
Indirect
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
Inherent
Indirect
Indirect
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
Inherent
Inherent
Indirect
Indirect
Direct
Immediate
Bytes
Cycles
1
1
2
2
1
1
2
2
2
3
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
2
2
1
1
1
2
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register
44/70
44
Flags
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
∆
∆
∆
∆
∆
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
∆
∆
∆
∆
∆
∆
ST62T00C/T01C ST62T03C/E01C
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the selected condition is met.
Control Instructions. The control instructions
control the MCU operations during program execution.
Bit Manipulation Instructions. These instructions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Table 14. Conditional Branch Instructions
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Instruction
JRC e
JRNC e
JRZ e
JRNZ e
JRR b, rr, ee
JRS b, rr, ee
Branch If
C=1
C=0
Z=1
Z=0
Bit = 0
Bit = 1
Bytes
Cycles
1
1
1
1
3
3
2
2
2
2
5
5
Notes :
b.
3-bit address
e.
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
Flags
Z
*
*
*
*
*
*
C
*
*
*
*
∆
∆
rr. Data space register
∆ . Affected. The tested bit is shifted into carry.
* . Not Affected
Table 15. Bit Manipulation Instructions
Instruction
SET b,rr
RES b,rr
Addressing Mode
Bit Direct
Bit Direct
Bytes
Cycles
2
2
4
4
Notes:
b.
3-bit address;
rr. Data space register;
Flags
Z
*
*
C
*
*
* . Not<M> Affected
Table 16. Control Instructions
Instruction
NOP
RET
RETI
STOP (1)
WAIT
Addressing Mode
Inherent
Inherent
Inherent
Inherent
Inherent
Bytes
Cycles
1
1
1
1
1
2
2
2
2
2
Flags
Z
*
*
∆
*
*
C
*
*
∆
*
*
Notes:
1.
This instruction is deactivated<N>and a WAI T is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*.
Not Affected
Table 17. Jump & Call Instructions
Instruction
CALL abc
JP abc
Addressing Mode
Extended
Extended
Bytes
Cycles
2
2
4
4
Flags
Z
C
*
*
*
*
Notes:
abc. 12-bit address;
* . Not Affected
45/70
45
ST62T00C/T01C ST62T03C/E01C
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW
0
0000
HI
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
RNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
1
0001
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
Abbreviations for Addressing Modes:
dir
Direct
sd
Short Direct
imm Immediate
inh
Inherent
ext
Extended
b.d
Bit Direct
bt
Bit Test
pcr
Program Counter Relative
ind
Indirect
46/70
46
2
0010
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
3
0011
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
JRR
b0,rr,ee
bt
JRS
b0,rr,ee
bt
JRR
b4,rr,ee
bt
JRS
b4,rr,ee
bt
JRR
b2,rr,ee
bt
JRS
b2,rr,ee
bt
JRR
b6,rr,ee
bt
JRS
b6,rr,ee
bt
JRR
b1,rr,ee
bt
JRS
b1,rr,ee
bt
JRR
b5,rr,ee
bt
JRS
b5,rr,ee
bt
JRR
b3,rr,ee
bt
JRS
b3,rr,ee
bt
JRR
b7,rr,ee
bt
JRS
b7,rr,ee
bt
4
0100
2
5
0101
6
0110
JRZ
2
e
1
2
#
pcr
JRZ 4
e
1
2
e
x
e
sd 1
2
#
sd 1
2
#
pcr
JRZ 4
e
1
2
e
y
e
1
2
sd 1
2
#
e
sd 1
2
#
pcr
JRZ 4
e
1
2
1
2
sd 1
2
e
1
2
a,v
e
sd 1
2
#
pcr
JRZ 4
e
1
2
e
w
e
1
Legend:
#
Indicates Ill egal Instructions
e
5 Bit Displacement
b
3 Bit Address
rr
1byte dataspace address
nn
1 byte immediate data
abc
12 bit address
ee
8 bit Displacement
prc 1
JRC 4
e
sd 1
2
#
pcr
JRZ 4
e
prc 2
JRC 4
1
INC 2
pcr 1
JRZ
1
2
prc 1
JRC 4
e
pcr 1
JRZ
1
2
prc
JRC 4
1
LD 2
prc 2
JRC 4
e
1
LD 2
a,w
pcr 1
prc 1
JRC
e
sd 1
Cycle
Addressing Mode
AND
a,(x)
ind
ANDI
a,nn
imm
SUB
a,(x)
ind
SUBI
a,nn
imm
DEC
(x)
ind
2
2
0010
3
0011
4
0100
5
0101
6
0110
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
JRC
Mnemonic
e
1
1
0001
#
prc
Operand
Bytes
ind
#
e
pcr
JRZ 4
LD
prc 1
JRC
0
0000
7
0111
(x),a
e
#
a,nn
imm
CP
a,(x)
ind
CPI
a,nn
imm
ADD
a,(x)
ind
ADDI
a,nn
imm
INC
(x)
ind
prc
JRC 4
1
INC 2
pcr 1
JRZ
ind
LDI
#
e
v
e
prc 1
JRC
e
pcr 1
JRZ
1
2
prc 2
JRC 4
1
LD 2
a,y
e
prc 1
JRC 4
e
pcr
JRZ 4
e
prc 2
JRC 4
1
INC 2
pcr 1
JRZ
1
2
prc 1
JRC 4
e
pcr 1
JRZ
e
prc 2
JRC 4
1
LD 2
a,x
1
2
a,(x)
e
pcr
JRZ 4
HI
LD
prc 1
JRC 4
e
pcr 1
JRZ
1
2
e
1
2
JRC 4
1
INC 2
LOW
7
0111
prc
ST62T00C/T01C ST62T03C/E01C
Opcode Map Summary (Continued)
LOW
8
1000
HI
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
RNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
JRNZ
e
pcr
9
1001
4
A
1010
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
4
ext 1
JP 2
abc
2
ext 1
Abbreviations for Addressing Modes:
dir
Direct
sd
Short Direct
imm Immediate
inh
Inherent
ext
Extended
b.d
Bit Direct
bt
Bit Test
pcr
Program Counter Relative
ind
Indirect
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
B
1011
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
RES
b0,rr
b.d
SET
b0,rr
b.d
RES
b4,rr
b.d
SET
b4,rr
b.d
RES
b2,rr
b.d
SET
b2,rr
b.d
RES
b6,rr
b.d
SET
b6,rr
b.d
RES
b1,rr
b.d
SET
b1,rr
b.d
RES
b5,rr
b.d
SET
b5,rr
b.d
RES
b3,rr
b.d
SET
b3,rr
b.d
RES
b7,rr
b.d
SET
b7,rr
b.d
C
1100
2
D
1101
JRZ 4
e
1
2
pcr 3
JRZ 4
e
1
2
pcr 1
JRZ 4
e
1
2
e
1
2
E
1110
LDI 2
rr,nn
imm
DEC
x
sd
COM
a
pcr
JRZ 4
e
1
2
pcr 1
JRZ 2
sd 1
RETI 2
pcr 1
JRZ 4
inh 1
DEC 2
y
pcr 1
JRZ 2
sd 1
STOP 2
pcr 1
JRZ 4
inh 1
LD 2
1
2
y,a
e
#
e
v
e
pcr 1
JRZ 2
sd 1
RET 2
pcr 1
JRZ 4
inh 1
DEC 2
2
JRC
prc 1
JRC 4
prc 2
JRC 4
e
w
prc 1
JRC 4
e
pcr 1
JRZ 2
sd 1
WAIT 2
pcr 1
JRZ 4
inh 1
LD 2
prc 2
JRC 4
e
e
Legend:
#
Indicates Ill egal Instructions
e
5 Bit Displacement
b
3 Bit Address
rr
1byte dataspace address
nn
1 byte immediate data
abc
12 bit address
ee
8 bit Displacement
prc 2
prc 2
JRC 4
e
e
1
prc 1
JRC 4
e
v,a
e
1
2
prc 2
JRC 4
inh 1
LD 2
e
1
2
prc 1
JRC 4
sd 1
RCL 2
a
e
1
2
prc 2
JRC 4
e
pcr 1
JRZ 4
1
2
prc 1
JRC 4
1
DEC 2
pcr 1
JRZ 4
1
2
dir
ADD
a,(y)
ind
ADD
a,rr
dir
INC
(y)
ind
INC
rr
dir
LD
(y),a
ind
LD
rr,a
dir
AND
a,(y)
ind
AND
a,rr
dir
SUB
a,(y)
ind
SUB
a,rr
dir
DEC
(y)
ind
DEC
rr
dir
e
pcr
JRZ 4
1
2
prc 2
JRC 4
sd 1
2
w,a
pcr 1
prc 1
JRC 4
e
sd 1
Cycle
Operand
Bytes
ind
CP
a,rr
e
pcr 1
JRZ
1
2
a,(y)
e
e
dir
CP
prc 1
JRC 4
e
e
1
2
e
e
e
ind
LD
a,rr
e
e
1
2
a,(y)
prc 2
JRC 4
1
LD 2
HI
LD
prc 1
JRC 4
e
x,a
1
2
JRC 4
1
2
LOW
F
1111
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Mnemonic
e
1
prc
Addressing Mode
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47
ST62T00C/T01C ST62T03C/E01C
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, however it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than V DD.
Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD
or VSS).
Symbol
VDD
Parameter
Supply Voltage
Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained
from:
Tj=TA + PD x RthJA
Where:TA = Ambient Temperature.
RthJA =Package thermal resistance (junction-to ambient).
PD = Pint + Pport.
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).
Value
Unit
-0.3 to 7.0
V
(1)
V
V
VI
Input Voltage
V SS - 0.3 to VDD + 0.3
VO
Output Voltage
V SS - 0.3 to VDD + 0.3 (1)
80
mA
100
mA
150
°C
-60 to 150
°C
IV DD
Total Current into VDD (source)
IVSS
Total Current out of VSS (sink)
Junction Temperature
Tj
TSTG
Storage Temperature
Notes:
- Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.
48/70
48
ST62T00C/T01C ST62T03C/E01C
6.2 RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Test Condition s
Min.
Typ.
Max.
Unit
TA
Operating Temperature
6 Suffix Version
1 Suffix Version
3 Suffix Version
-40
0
-40
85
70
125
°C
VDD
Operating Supply Voltage
f OSC = 4MHz, 1 & 6 Suffix
f OSC = 4MHz, 3 Suffix
fosc= 8MHz , 1 & 6 Suffix
fosc= 8MHz , 3 Suffix
3.0
3.0
3.6
4.5
6.0
6.0
6.0
6.0
V
0
0
0
0
4.0
4.0
8.0
4.0
MHz
V DD =
V DD =
V DD =
V DD =
2)
3.0V, 1 & 6 Suffix
3.0V , 3 Suffix
3.6V , 1 & 6 Suffix
3.6V , 3 Suffix
fOSC
Oscillator Frequency
IINJ+
Pin Injection Current (positive)
V DD = 4.5 to 5.5V
+5
mA
IINJ-
Pin Injection Current (negative) V DD = 4.5 to 5.5V
-5
mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.
2.An oscillator frequency above 1MHz is recommended for reliable A/D results
Figure 27. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
Maximum FREQU ENCY (MHz)
1 & 6 Suffix version
8
FUNCTIONALITY IS NOT
3 Suffix version
GUARANTEED IN
7
THIS AREA
6
5
4
3
2
1
2.5
3
3.6
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD)
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.
49/70
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ST62T00C/T01C ST62T03C/E01C
6.3 DC ELECTRICAL CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Symbol
VIL
VIH
V Hys
Vup
V dn
VOL
VOH
R PU
IIL
IIH
IDD
Retention
Parameter
Test Conditions
Input Low Level Voltage
All Input pins
Input High Level Voltage
All Input pins
Hysteresis Voltage (1)
All Input pins
50
Typ.
Max.
VDD x 0.3
VDD= 5V
VDD= 3V
LVD Threshold in power-on
LVD threshold in powerdown
Low Level Output Voltage
VDD= 5.0V; IOL = +10µA
All Output pins
VDD= 5.0V; IOL = + 3mA
VDD= 5.0V; IOL = +10µA
Low Level Output Voltage
VDD= 5.0V; IOL = +7mA
20 mA Sink I/O pins
VDD= 5.0V; IOL = +15mA
High Level Output Voltage
VDD= 5.0V; IOH = -10µA
All Output pins
VDD= 5.0V; IOH = -3.0mA
All Input pins
Pull-up Resistance
RESET pin
Input Leakage Current
VIN = VSS (No Pull-Up configured)
All Input pins but RESET
VIN = VDD
Input Leakage Current
VIN = VSS
VIN = VDD
RESET pin
Supply Current in RESET
VRESET=VSS
Mode
fOSC=8MHz
Supply Current in
VDD=5.0V fINT=8MHz
RUN Mode (2)
Supply Current in WAIT
VDD=5.0V fINT=8MHz
Mode (3)
Supply Current in WAIT
VDD=3V fINT=32K
Mode (4)
Supply Current in STOP
ILOAD=0mA
Mode, with LVD disabled(3) VDD=5.0V
Supply Current in STOP
ILOAD=0mA
Mode, with LVD enabled(3) VDD=5.0V
EPROM Data Retention
TA = 55°C
Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by + option byte programmed (except LVD)
(4) Characterized but not tested; option byte programmed except LVD
50/70
Value
Min.
Unit
V
VDD x 0.7
V
0.2
0.2
V
3.5
4.1
3.8
4.3
0.1
0.8
0.1
0.8
1.3
4.9
3.5
40
150
-8
V
V
100
350
350
900
0.1
1.0
-16
-30
10
ΚΩ
µA
3.5
mA
3.5
mA
500
µA
30
µA
20
µA
500
10
years
ST62T00C/T01C ST62T03C/E01C
DC ELECTRICAL CHARACTERISTICS (Cont’d)
(TA = -40 to +85°C unless otherwise specified))
Symbol
Parameter
Vup
V dn
LVD Threshold in power-on
LVD threshold in powerdown
Low Level Output Voltage
All Output pins
VOL
Low Level Output Voltage
20 mA Sink I/O pins
VOH
IDD
High Level Output Voltage
All Output pins
Supply Current in STOP
Mode, with LVD disabled(*)
Test Conditions
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = + 5mA
VDD= 5.0V; IOL = + 10mAv
VDD= 5.0V; IOL = +10µA
VDD= 5.0V; IOL = +10mA
VDD= 5.0V; IOL = +20mA
VDD= 5.0V; IOL = +30mA
VDD= 5.0V; IOH = -10µA
VDD= 5.0V; IOH = -5.0mA
ILOAD=0mA
VDD=5.0V
Value
Min.
Typ.
Max.
Vdn +50 mV
3.6
4.1
3.8
4.3
Vup -50 mV
0.1
0.8
1.2
0.1
0.8
1.3
2.0
4.9
3.5
Unit
V
V
V
V
µA
10
Note:
(*) All Peripherals in stand-by.
6.4 AC ELECTRICAL CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Symbol
Parameter
Test Conditions
Value
Min.
tREC
Supply Recovery Time (1)
100
fLFAO
Internal frequency with LFAO active
200
fOSG
Internal Frequency with OSG
enabled 2)
VDD = 3V
VDD = 3.6V
VDD = 4.5V
Unit
Typ.
Max.
400
800
kHz
fOSC
MHz
5.8
3.5
900
MHz
MHz
kHz
ms
2
2
4
fRC
VDD=5.0V
Internal frequency with RC oscillator R=47kΩ
R=100kΩ
and OSG disabled 2) 3)
R=470kΩ
CIN
Input Capacitance
All Inputs Pins
10
pF
Output Capacitance
All Outputs Pins
10
pF
C OUT
4
2.7
800
5
3.2
850
Notes:
1. Period for which VDD has to be connected at 0V to allow internal Reset function at next power-up.
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.
51/70
51
ST62T00C/T01C ST62T03C/E01C
6.5 A/D CONVERTER CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Symbol
Res
ATOT
tC
Parameter
Total Accuracy (1) (2)
Conversion Time
Zero Input Reading
FSR
Full Scale Reading
ACIN
Value
Typ.
8
Min.
Resolution
ZIR
AD I
Test Conditions
fOSC > 1.2MHz
fOSC > 32kHz
fOSC = 8MHz (TA < 85°C)
fOSC = 4 MHz
Conversion result when
VIN = VSS
Conversion result when
VIN = VDD
Max.
Unit
Bit
±2
±4
70
140
LSB
µs
00
Hex
Analog Input Current During
VDD= 4.5V
Conversion
Analog Input Capacitance
2
FF
Hex
1.0
µA
5
pF
Notes:
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.
6.6 TIMER CHARACTERISTICS
(TA = -40 to +125°C unless otherwise specified)
Symbol
52/70
Parameter
fIN
Input Frequency on TIMER Pin
tW
Pulse Width at TIMER Pin
Test Conditions
Min.
Value
Typ.
Max.
IINT
---------4
VDD = 3.0V
VDD >4.5V
1
125
Unit
MHz
µs
ns
ST62T00C/T01C ST62T03C/E01C
Figure 28.. RC frequency versus Vcc
Frequency
10
R=47K
]
+
0
R=100K
1
R=470K
0.1
3
3.5
4
4.5
VDD (volts)
5
5.5
6
Figure 29. LVD thresholds versus temperature
53/70
ST62T00C/T01C ST62T03C/E01C
Idd WAIT (mA)
Figure 30. Idd WAIT versus Vcc at 8 Mhz for OTP devices
1.2
1
0.8
0.6
0.4
0.2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Idd WAIT (µA)
Figure 31. Idd STOP versus Vcc for OTP devices
8
6
4
2
0
-2
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 32. Idd STOP versus Vcc for ROM devices
Idd STOP (µA)
2
1.5
T = -40°C
T = 25°C
T = 95°C
T = 125°C
1
0.5
0
-0.5
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
54/70
54
ST62T00C/T01C ST62T03C/E01C
Idd WAIT (mA)
Figure 33. Idd WAIT versus Vcc at 8Mhz for ROM devices
0.8
T=
T=
T=
T=
0.6
0.4
0.2
-40°C
25°C
95°C
125°C
0
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Idd Wait (µA)
Figure 34. Idd WAIT (µA) Fosc=32KHz (option byte programmed to 00h)
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
T = -40C
T = 25C
T = 95C
T = 125C
2.5
3
3.5
4
4.5
5
5.5
6
Vdd (volts)
This curves represents typical variations and is given for guidance only
Figure 35. Idd RUN versus Vcc at 8 Mhz for ROM and OTP devices
Idd RUN (mA)
5
4
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3
2
1
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
55/70
55
ST62T00C/T01C ST62T03C/E01C
Figure 36. Vol versus Iol on all I/O port at Vdd=5V
8
Vol (V)
6
T = -40°C
T = 25°C
T = 95°C
T = 125°C
4
2
0
0
10
20
Iol (mA)
30
40
This curves represents typical variations and is given for guidance only
Figure 37. Vol versus Iol on all I/O port at T=25°C
Vol (V)
8
Vdd
Vdd
Vdd
Vdd
6
4
2
= 3.0V
= 4.0V
= 5.0V
= 6.0V
0
0
10
20
Iol (mA)
30
40
This curves represents typical variations and is given for guidance only
Figure 38. Vol versus Iol for High sink (20mA) I/Oports at T=25°C
5
Vol (V)
4
Vdd = 3.0V
Vdd = 4.0V
3
2
Vdd = 5.0V
Vdd = 6.0V
1
0
0
20
30
Iol (mA)
This curves represents typical variations and is given for guidance only
56/70
56
10
40
ST62T00C/T01C ST62T03C/E01C
Figure 39. Vol versus Iol for High sink (20mA) I/O ports at Vdd=5V
5
Vol (V)
4
T=
T=
T=
T=
3
2
1
-40°C
25°C
95°C
125°C
0
0
10
20
Iol (mA)
30
40
This curves represents typical variations and is given for guidance only
Figure 40. Voh versus Ioh on all I/O port at 25°C
Voh (V)
6
Vdd
Vdd
Vdd
Vdd
4
2
0
= 3.0V
= 4.0V
= 5.0V
= 6.0V
-2
0
10
20
Ioh (mA)
30
40
This curves represents typical variations and is given for guidance only
Figure 41. Voh versus Ioh on all I/O port at Vdd=5V
6
Voh (V)
4
T=
T=
T=
T=
2
0
-40°C
25°C
95°C
125°C
-2
0
10
20
Ioh (mA)
30
40
This curves represents typical variations and is given for guidance only
57/70
57
ST62T00C/T01C ST62T03C/E01C
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 42. 16-Pin Plastic Dual In Line Package (B), 300-mil Width
Dim.
mm
Min
Typ
A
Min
Typ
5.33
A1
0.38
A2
2.92
b
0.36
b2
Max
0.210
0.015
3.30
4.95 0.115 0.130 0.195
0.56 0.014
0.022
1.52
1.78
0.25
0.36 0.008 0.010 0.014
0.060 0.070
c
0.20
D
18.67 19.18 19.69 0.735 0.755 0.775
e
PDIP16
inches
Max
2.54
0.100
E1
6.10
6.35
7.11 0.240 0.250 0.280
L
2.92
3.30
3.81 0.115 0.130 0.150
Number of Pins
N
16
Figure 43. 16-Pin Ceramic Side-Brazed Dual In-Line Package
Dim.
mm
Min
Typ
A
Min
Typ
3.78
0.38
B
0.36 0.46 0.56 0.014 0.018 0.022
B1
0.015
1.14 1.37 1.78 0.045 0.054 0.070
C
0.20 0.25 0.36 0.008 0.010 0.014
D
19.86 20.32 20.78 0.782 0.800 0.818
E1
e
17.78
0.700
7.04 7.49 7.95 0.277 0.295 0.313
2.54
0.100
G
6.35 6.60 6.86 0.250 0.260 0.270
G1
9.47 9.73 9.98 0.373 0.383 0.393
G2
L
1.02
0.040
2.92 3.30 3.81 0.115 0.130 0.150
S
1.27
0.050
Ø
4.22
0.166
Number of Pins
N
58/70
58
Max
0.149
A1
D1
CDIP16W
inches
Max
16
ST62T00C/T01C ST62T03C/E01C
PACKAGE MECHANICAL DATA (Cont’d)
Figure 44. 16-Pin Plastic Small Outline Package (M), 300-mil Width
Dim.
mm
Min
A
2.35
A1
0.10
B
0.33
Typ
Min
Typ
2.65 0.0926
Max
0.1043
0.0040
0.51
C
0.013
0.020
0.32
0.0125
D
10.10
10.50 0.3977
0.4133
E
7.40
7.60 0.2914
0.2992
e
1.27
0.050
H
10.01
10.64 0.394
0.419
h
0.25
0.74
0.010
0.029
K
0°
8°
0°
8°
L
0.41
1.27
0.016
0.050
G
SO16
inches
Max
0.10
0.004
Number of Pins
N
16
Figure 1. 16-Pin Plastic Shrink Small Outline Package, 0.209” Width
Dim.
mm
Min
Typ
A
1.73
A1
inches
Min
Typ
Max
1.86 1.99
0.068
0.073
0.078
0.05
0.13 0.21
0.002
0.005
0.008
B
0.25
0.38
0.010
C
0.09
0.20
0.004
D
6.07
6.20 6.33
0.239
0.244
0.249
E
7.65
7.80 7.90
0.301
0.307
0.311
E1
5.20
5.30 5.38
0.205
0.209
0.212
e
Max
0.65
G
0°
L
0.63
4°
0.008
0.026
0.076
K
0.015
0.003
8°
0.75 0.95
0°
4°
8°
0.025
0.030
0.037
Number of Pins
SSOP16
N
16
59/70
59
ST62T00C/T01C ST62T03C/E01C
7.2 ORDERING INFORMATION
Table 18. OTP/EPROM VERSION ORDERING INFORMATION
Sales Type
ST62T00CB6
ST62T00CM6
ST62T01CB6
ST62T01CM6
ST62T01CN6
ST62T03CB6
ST62T03CM6
ST62T01CB3
ST62T01CM3
ST62T01CN3
ST62E01CF1
60/70
60
I/O
Program
Memory (Bytes)
Analog
input
Temperature Range
-40 to +125°C
PDIP16
PSO16
PDIP16
PSO16
SSOP16
PDIP16
PSO16
PDIP16
PSO16
0 to +70°C
SSOP16
CDIP16W
1036 (OTP)
4
1836 (OTP)
9
1036 (OTP)
-40 to + 85°C
None
1836 (OTP)
1836(EPROM)
4
Package
ST62P00C/P01C/P03C
8-BIT FASTROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD , SAFE RESET AND 16 PINS
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
Data RAM: 64bytes
9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62P03C)
3 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
8-bit Timer/Counter with 7-bit programmable
prescaler
Digital Watchdog
Oscillator Safe Guard
Low Voltage Detector for Safe Reset
8-bit A/D Converter with up to 4 analog inputs
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
PDIP16
PSO16
SSOP16
(See end of Datasheet for Ordering Information)
DEVICE SUMMARY
DEVICE
ST62P00C
ST62P01C
ST62P03C
ROM
(Bytes)
1036
1836
1036
I/O Pins
Analog
inputs
9
9
9
4
4
None
Rev. 2.8
August 1999
61/70
61
ST62P00C/P01C/P03C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62P00C/P01C & P03C are the Factory Advanced Service Technique ROM (FASTROM) versions of ST62T00C,T01C and T03C OTP devices.
They offer the same functionality as OTP devices,
selecting as FASTROM options the options defined in the programmable option byte of the OTP
version.
1.2 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
1.2.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to STMicroelectronics using the correctly filled OPTION
LIST appended.
1.2.2 Listing Generation and Verification
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the ROM con-
tents and options which will be used to produce
the specified MCU. The listing is then returned to
the customer who must thoroughly check, complete, sign and return it to STMicroelectronics. The
signed listing forms a part of the contractual agreement for the production of the specific customer
MCU.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on contractual points.
Table 1. ROM Memory Map for ST62P00C,P03C
Device Address
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Description
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 2. ROM Memory Map for ST62P01C
Device Address
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Description
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 3. FASTROM version Ordering Information
Sales Type
ST62P00CB1/XXX
ST62P00CB6/XXX
ST62P00CB3/XXX (*)
ST62P00CM1/XXX
ST62P00CM6/XXX
ST62P00CM3/XXX (*)
ST62P01CB1/XXX
ST62P01CB6/XXX
ST62P01CB3/XXX (*)
ST62P01CM1/XXX
ST62P01CM6/XXX
ST62P01CM3/XXX (*)
ST62P01CN1/XXX
ST62P01CN6/XXX
ST62P01CN3/XXX (*)
ST62P03CB1/XXX
ST62P03CB6/XXX
ST62P03CB3/XXX (*)
ST62P03CM1/XXX
ST62P03CM6/XXX
ST62P03CM3/XXX (*)
(*) Advanced information
62/70
62
ROM
Analog inpu ts
1036 Bytes
4
1836 Bytes
1036 Bytes
None
Temperature Range
0 to +70°C
-40 to + 85°C
-40 to + 125°C
0 to +70°C
-40 to + 85°C
-40 to + 125°C
0 to +70°C
-40 to + 85°C
-40 to + 125°C
0 to +70°C
-40 to + 85°C
-40 to + 125°C
0 to +70°C
-40 to + 85°C
-40 to + 125°C
0 to +70°C
-40 to + 85°C
-40 to + 125°C
0 to +70°C
-40 to + 85°C
-40 to + 125°C
Package
PDIP16
PSO16
PDIP16
PSO16
SSOP16
PDIP16
PSO16
ST62P00C/P01C/P03C
ST62P00C/P01C/P03C FASTROM MICROCONTROLLER OPTION LIST
Customer
Address
. . ... ... . .. .. . .. .. .. . .. ... . ..
. . ... ... . .. .. . .. .. .. . .. ... . ..
. . ... ... . .. .. . .. .. .. . .. ... . ..
Contact
. . ... ... . .. .. . .. .. .. . .. ... . ..
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST62P00C [ ] ST62P01C
[ ] ST62P03C
Package:
[ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
[ ] Shrink Small Outline Plastic
Temperature Range:
[ ] 0°C to + 70°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
Readout Protection:
[ ] Disabled
[ ] Enabled
External STOP Mode Control[ ] Enabled
LVD Reset
[ ] Enabled
NMI pin pull-up
[ ] Enabled
OSG
[ ] Enabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
. . ... ... . .. .. . .. .. .. . .. ... . ..
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date
. . ... ... . .. .. . .. .. .. . .. ... . ..
63/70
63
ST62P00C/P01C/P03C
Notes:
64/70
64
ST6200C/01C/03C
8-BIT ROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD , SAFE RESET AND 16 PINS
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
Data RAM: 64bytes
9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST6203C)
3 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
8-bit Timer/Counter with 7-bit programmable
prescaler
Digital Watchdog
Oscillator Safe Guard
Low Voltage Detector for Safe Reset
8-bit A/D Converter with up to 4 analog inputs
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
PDIP16
PSO16
SSOP16
(See end of Datasheet for Ordering Information)
DEVICE SUMMARY
DEVICE
ST6200C
ST6201C
ST6203C
ROM
(Bytes)
1036
1836
1036
I/O Pins
9
9
9
Analog
inputs
4
4
None
Rev. 2.8
August 1999
65/70
65
ST6200C/01C/03C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
1.2 ROM READOUT PROTECTION
The ST6200C/01C and 03C are mask programmed ROM version of ST62T00C,T01C and
T03C OTP devices.
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version.
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to prevent any access to the program memory content.
In case the user wants to blow this fuse, high voltage must be applied on the TEST pin.
Figure 1. Programming wave form
Figure 2. Programming Circuit
TEST
0.5s min
5V
15
14V typ
10
47mF
100nF
5
VSS
TEST
VDD
150 µs typ
PROTECT
14V
TEST
100mA
max
100nF
ZPD15
15V
VR02003
4mA typ
t
VR02001
Note: ZPD15 is used for overvoltage protection
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ST6200C/01C/03C
ST6200C/01C/03C MICROCONTROLLER OPTION LIST
Customer
Address
. . ... ... . .. .. . .. .. .. . .. ... . ..
. . ... ... . .. .. . .. .. .. . .. ... . ..
. . ... ... . .. .. . .. .. .. . .. ... . ..
Contact
. . ... ... . .. .. . .. .. .. . .. ... . ..
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST6200C
[ ] ST6201C
[ ] ST6203C
Package:
[ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
[ ] Shrink Small Outline Plastic
Temperature Range:
[ ] 0°C to + 70°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
Special Marking:
[ ] No
[ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count: DIP16:
9
SO16:
6
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
Note:
No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.
External STOP Mode Control[ ] Enabled
LVD Reset
[ ] Enabled
NMI pin pull-up
[ ] Enabled
OSG
[ ] Enabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
. . ... ... . .. .. . .. .. .. . .. ... . ..
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date
. . ... ... . .. .. . .. .. .. . .. ... . ..
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ST6200C/01C/03C
1.3 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
1.3.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file generated by the development tool. All unused bytes
must be set to FFh.
The selected mask options are communicated to
STMicroelectronics using the correctly filled OPTION LIST appended.
1.3.2 Listing Generation and Verification
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
part of the contractual agreement for the creation
of the specific customer mask.
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The STMicroelectronics Sales Organization will be
pleased to provide detailed information on contractual points.
Table 4. ROM Memory Map for ST6200C,03C
Device Address
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Description
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 5. ROM Memory Map for ST6201C
Device Address
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Description
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
ST6200C/01C/03C
ORDERING INFORMATION (Cont’d)
Table 6. ROM version Ordering Information
Sales Type
ROM
Analog inpu ts
Temperature Range
Package
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PDIP16
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO16
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PDIP16
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO16
ST6201CN1/XXX
ST6201CN6/XXX
ST6201CN3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
SSOP16
ST6203CB1/XXX
ST6203CB6/XXX
ST6203CB3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PDIP16
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO16
ST6200CB1/XXX
ST6200CB6/XXX
ST6200CB3/XXX
1036 Bytes
ST6200CM1/XXX
ST6200CM6/XXX
ST6200CM3/XXX
ST6201CB1/XXX
ST6201CB6/XXX
ST6201CB3/XXX
ST6201CM1/XXX
ST6201CM6/XXX
ST6201CM3/XXX
4
1836 Bytes
1036 Bytes
ST6203CM1/XXX
ST6203CM6/XXX
ST6203CM3/XXX
None
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ST6200C/01C/03C
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved.
Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
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Sweden - Switzerland - United Kingdom - U.S.A.
http:// www.st.com
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