ST70137 UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER ST70137 HARDWARE FEATURES DESCRIPTION ■ SUPPORT DIGITAL SIGNAL PROCESSING ST70137 is STMicroelectronics UNICORNTM chipset ADSL DMT transceiver for controllerless ADSL CPE modem. REQUIREMENTS FOR ONE ADSL CPE CHANEL (ITU-R) ■ COMPLIANT WITH ITU 992.1 (ADSL FULL RATE) ANNEXE A (ADSL OVER POTS) AND ANNEXE B (ADSL OVER ISDN) AND ITU 922.2 (G.LITE) AND ANSI T1.413. ■ DIRECT INTERFACE TO PCI BUS (PCI RELEASE 2.2 AND COMPLIANT WITH MICROSOFT PC99 & PC2001 SPECIFICATION) UNICORNTM allows to develop easily and quickly low cost ADSL CPE modem for PC environment. UNICORNTM is made of two devices, ST70137 and ST70136 or ST70134 (CPE ADSL Analog Front End). ST70137 provides PCI and USB interface. PCI is used to build ADSL CPE modem bundled in the PC, USB interface is used to build external bus powered ADSL modem. (USB ST70137 is compliant with ITU 992.1 Annexe A and B, with ITU 992.2 and with ANSI T1.413. ■ DIRECT INTERFACE TO THE EXTERNAL UNICORNTM chipset is delivered with a complete PC software suite for Microsoft Windows 98, Windows 2000 and Windows NT. NDIS5.0 PCI driver and USB driver with ADSL modem control and ATM device driver are provided assuring full ATM support. Configuration and diagnostic tools are also provided. ■ DIRECT INTERFACE TO USB RELEASE 1.1 SPECIFICATION) SERIAL MEMORY TO SUPPORT PCI/USB USER’S CONFIGURATION ■ DIRECT ANALOG FRONT END INTERFACE FOR ST70136 OR ST70134 ■ 4 TO 8 GPIO DEPENDING ON SELECTED AFE AND EXTERNAL MEMORY CONFIGURATION USED UNICORNTM chipset and PC software ensure interoperability with the most deployed DSLAM. ■ CLOCK & RESET INTERFACE ■ 1.8V AND 3.3V POWER SUPPLY ■ TTL LOGIC LEVELS (DEPENDING ON PADS) COMPATIBLE ■ POWER MANAGEMENT ■ LOW POWER CONSUMPTION : 0.4W ■ TQFP 144 ST70137 SOFTWARE FEATURES ■ RFC 2364 PPP OVER ATM ■ UNI 3.0, 3.1, 4.0 SIGNALING TQFP144 ORDER CODE: ST70137TQFP ■ UBR, CBR ■ AAL0, AAL5 ■ NDIS5.0 PCI DRIVER AND USB DRIVER September 2001 1/22 ST70137 TYPICAL APPLICATION PC PCI or ST70137 DMT ST70136 AFE or ST70134 POTS Line LINE I/F USB ST70137 ADSL MODEM ST70136 or ST70134 POTS Line USB Dongle Modem or PCI Board BLOCK DIAGRAM USB IF USB_BRIDGE Bridge PCI_IF MEM IF PCI_BRIDGE CFG_MEMs CFG_SEL CLK USB_PCIN_sel SWITCHER ATM FIFOs OBC FIFOs Utop FSM TGB REGs PERIPHERAL RST GPIO IF OBC_IF ADSL uP TOSCA v. 2.0 TAP AFE IF OBC: On Board Controller TGB: Time Generation Block TAP: Test Access Protocol Utop FSM: Utopia Finite State Machine 2/22 ST70137 SOFTWARE ARCHITECTURE User Applications: Netscape, NetMeeting, etc. Trace Tools Ring 3: User Mode NDIS 5 Data Control Win32 kernel Modem SW Hw Abstraction Layer USB Driver PCI Driver Registry USBD SYS - MS Bus Driver UHCD.SYS OHCD.SYS UHCI (Intel) OHCI (NEC and Others) Ring 0: Kernel Level Hardware USB Device 3/22 PCI Device ST70137 VSS VSS VSS AFERST VSS AFETXD[0] AFETXD[1] AFETXD[2] AFETXD[3] VSS AFERXD[0] AFERXD[1] AFERXD[2] AFERXD[3] VDD1.8 COMP_ROUT VSS MCLK VDD3.3 CLWD AFEWR/ GPIO[5] CTRLDOUT CTRLDIN/ GPIO[4] VSS VSS VDD1.8 TDI TDO TMS TCK TRSTB VSS A_VDD_PLL A_VSS_PLL D_VDD_PLL D_VSS_PLL PIN CONNECTIONS 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125124 123 122 121120 119 118 117116 115 114 113 112 111 110 109 VDD 3.3 1 108 VDD3.3 GPIO[0] 2 107 ACTD GPIO[1] 3 106 PWDN GPIO[2] 4 105 SUSPENDN GPIO[3] 5 104 SUSPEND VSS 6 103 LD_PWDN DMINUS 7 102 VSS DPLUS 8 101 AFESEL VSS 9 100 USB_PCIN_SEL RSTN 10 99 CFG_MEM_SEL CFG_SCE 11 98 VAUX_D_USB_SP CFG_SCK/ GPIO[6] 12 97 VDD1.8 CFG_SDI 13 96 VR50 CFG_SDO/GPIO[7] 14 95 PCI_AD[0] VDD 1.8 15 94 PCI_AD[1] C_EXT 16 93 PCI_AD[2] VSS 17 92 VDD3.3 VDD 3.3 18 91 PCI_AD[3] VR50F 19 90 PCI_AD[4] PCI_INTAN 20 89 VSS PCI_RSTN 21 88 PCI_AD[5] VSS 22 87 PCI_AD[6] PCI_CLK 23 86 VDD3.3 PCI_GNTN 24 85 PCI_AD[7] VDD 3.3 25 84 PCI_CBE0N PCI_REQN 26 83 VSS PCI_PMEN 27 82 PCI_AD[8] VSS 28 81 PCI_AD[9] PCI_AD[31] 29 80 VDD3.3 PCI_AD[30] 30 79 PCI_AD[10] VDD 3.3 31 78 PCI_AD[11] PCI[AD29] 32 77 VSS PCI_AD[28] 33 76 PCI_AD[12] VSS 34 75 PCI_AD[13] PCI_AD[27] 35 74 VDD3.3 PCI_AD[26] 36 73 PCI_AD[14] ST70137 PCI_AD[15] VSS PCI_CBE1N PCI_PAR VDD3.3 SERRN PERRN VSS PCI_STOPN PCI_DEVSELN VDD3.3 PCI_TRDYN PCI_IRDYN VSS PCI_FRAMEN PCI_CBE2N VDD1.8 VDD3.3 PCI_AD[16] PCI_AD[17] VSS PCI_AD[18] PCI_AD[19] VDD3.3 PCI_AD[20] PCI_AD[21] VSS PCI_AD[22] PCI_AD[23] VDD3.3 PCI_IDSEL PCI_CBE3N VSS PCI_AD[24] VDD3.3 PCI_AD[25] 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 4/22 ST70137 PIN LIST PIN NAME TYPE DRIVE 1 VDD3.3 P 2 GPIO[0] I/O 4mA 3 GPIO[1] I/O 4mA 4 GPIO[2] I/O 4mA 5 GPIO[3] I/O 4mA 6 VSS 7 DATA_MINUS I/O 8 DATA_PLUS I/O DESCRIPTION Power supply pins 3.3V for I/O pads (not PCI) P Ground 9 VSS P 10 RSTN I 11 CFG_SCE O 4mA 12 CFG_SCK/GPO[ 6] O 4mA 13 CFG_SDI I 14 CFG_SDO/GPO[ 7] O 15 VDD 1.8 P Power supply pins 1.8V for Core 16 C_EXT P External Capacitor to reduce ripple of the internal DC regulator 1 17 VSS 18 VDD3.3 P Power supply pins 3.3V for PCI I/O pads ESD protection 19 VR50F P Power Supply for DC regulator (3.3V) 20 PCI_INTAN 21 PCI_RSTN I 22 VSS P 23 PCI_CLK I 24 PCI_GNTN I 25 VDD3.3 P 26 PCI_REQN O 8mA 27 PCI_PMEN OD 8mA 28 VSS 29 PCI_AD[31] I/O 8mA 30 PCI_AD[30] I/O 8mA 31 VDD3.3 32 PCI_AD[29] I/O 8mA 33 PCI_AD[28] I/O 8mA 34 VSS Note 10nF 5/22 Ground 4mA Ground OD 8mA Ground Power supply pins 3.3V for PCI I/O pads ESD protection P 1. Pin C_EXT must be connected: 1µF Ground P P Low, High Impendance Power supply pins 3.3V for PCI I/O pads Ground ST70137 PIN LIST (continued) PIN NAME TYPE DRIVE DESCRIPTION 35 PCI_AD[27] I/O 8mA 36 PCI_AD[26] I/O 8mA 37 VDD3.3 38 PCI_AD[25] I/O 8mA 39 PCI_AD[24] I/O 8mA 40 VSS 41 PCI_CBE_N[3] 42 PCI_IDSEL 43 VDD3.3 44 PCI_AD[23] I/O 8mA 45 PCI_AD[22] I/O 8mA 46 VSS 47 PCI_AD[21] I/O 8mA 48 PCI_AD[20] I/O 8mA 49 VDD3.3 50 PCI_AD[19] I/O 8mA 51 PCI_AD[18] I/O 8mA 52 VSS 53 PCI_AD[17] I/O 8mA 54 PCI_AD[16] I/O 8mA 55 VDD3.3 P Power supply pins 3.3V for PCI I/O pads 56 VDD1.8 P Power supply pins 1.8V for Core 57 PCI_CBE_N[2] I/O 8mA 58 PCI_FRAMEN I/O 8mA 59 VSS 60 PCI_IRDYN I/O 8mA 61 PCI_TRDYN I/O 8mA 62 VDD3.3 63 PCI_DEVSELN I/O 8mA 64 PCI_STOPN I/O 8mA 65 VSS 66 PCI_PERRN I/O 8mA 67 PCI_SERRN I/O 8mA 68 VDD3.3 69 PCI_PAR I/O 8mA 70 PCI_CBE_N[1] I/O 8mA 71 VSS 72 PCI_AD[15] I/O 8mA 73 PCI_AD[14] I/O 8mA P Power supply pins 3.3V for PCI I/O pads ESD Protection P I/O Ground 8mA I P Power supply pins 3.3V for PCI I/O pads ESD Protection P Ground P Power supply pins 3.3V for PCI I/O pads ESD Protection P Ground P Ground P Power supply pins 3.3V for PCI I/O pads ESD Protection P Ground P Power supply pins 3.3V for PCI I/O pads ESD Protection P Ground 6/22 ST70137 PIN LIST (continued) PIN NAME TYPE DRIVE P DESCRIPTION 74 VDD3.3 75 PCI_AD[13] I/O 8mA Power supply pins 3.3V for PCI I/O pads ESD Protection 76 PCI_AD[12] I/O 8mA 77 VSS 78 PCI_AD[11] I/O 8mA 79 PCI_AD[10] I/O 8mA 80 VDD3.3 81 PCI_AD[9] I/O 8mA 82 PCI_AD[8] I/O 8mA 83 VSS 84 PCI_CBE_N[0] I/O 8mA 85 PCI_AD[7] I/O 8mA 86 VDD3.3 87 PCI_AD[6] I/O 8mA 88 PCI_AD[5] I/O 8mA 89 VSS 90 PCI_AD[4] I/O 8mA 91 PCI_AD[3] I/O 8mA 92 VDD3.3 93 PCI_AD[2] I/O 8mA 94 PCI_AD[1] I/O 8mA 95 PCI_AD[0] I/O 8mA 96 VR50 P 3.3V Power supply for DC regulator 97 VDD1.8 P Power 98 VAUX_D/USB_SP I 99 CFG_MEM_SEL I 100 USB_PCIN_sel I 101 AFESEL I 102 VSS P 103 LPDWDN O 4mA 104 SUSPEND O 4mA 105 SUSPENDN O 4mA 106 PWDN O 4mA 107 ACTD I 108 VDD3.3 P 109 TEST P Ground P Power supply pins 3.3V for PCI I/O pads ESD Protection P Ground P Power supply pins 3.3V for PCI I/O pads P Ground P Power supply pins 3.3V for PCI I/O pads ESD Protection Ground Power supply pins 3.3V for I/O pads (not PCI) I/O Test Reserved - Must be fixed to ground 110 TEST I/O Test Reserved - Must be fixed to ground 111 TEST I/O Test Reserved - Must be fixed to ground 112 AFERST O 7/22 4mA ST70137 PIN LIST (continued) PIN NAME TYPE DRIVE DESCRIPTION 113 VSS P 114 AFETXD[0] O 8mA Ground 115 AFETXD[1] O 8mA 116 AFETXD[2] O 8mA 117 AFETXD[3] O 8mA 118 VSS P 119 AFERXD[0] I 120 AFERXD[1] I 121 AFERXD[2] I 122 AFERXD[3] I 123 VDD1.8 P Power supply pins 1.8V for Core 124 COMP_CELL O Compensation cell resistor 1 125 VSS P Ground 126 MCLK I 127 VDD3.3 P 128 CLWD I 129 AFEWR/GPIO[5] I/O 4mA 130 CTRLDOUT O 4mA 131 CTRLDIN/GPIO[4] I/O 4mA 132 VSS P 133 TEST I/O 134 VDD1.8 P 135 TDI I 136 TDO O 137 TMS I 138 TCK I 139 TRSTB I 140 VSS P 141 VDD_APLL P PLL Analog power supply 1.8V 142 VSS_APLL P PLL Analog Ground 143 VDD_DPLL P PLL digital power supply 1.8V 144 VSS_DPLL P PLL digital Ground Ground Power supply pins 3.3V for I/O pads (not PCI) Ground Test Reserved - Must be fixed to ground Power supply pins 1.8V for Core 4mA Ground Note 1. COMP_CELL 100KΩ ± 1% Note: PCI section from pin 16 to pin 96 (included): all the power supply pins (at 3.3V) included in this section are intented for PCI I/O pads. 8/22 ST70137 PIN DESCRIPTION Signal Name Direction Init Status Polarity I - - Signal Description PCI INTERFACE PCI_CLK PCI Clock. (33 MHz) The rising edge of this signal is the reference upon which all the other PCI signals are based except for PCI_RSTN and PCI_INTAN. The maximum PCI_CLK frequency for ST70137 is 33MHz and the minimum is DC. PCI_RSTN I I L PCI Reset Reset bring ST70137 in a known state: - All PCI bus output signal tri-stated - All open drain signals floated - All registers set to their factory defaults - All FIFOs emptied - GPIO signals tri-stated - Sachem Macrocell initialized - Clock of Adsl_Up stopped - AFE set in Power down mode PCI_REQN O H L PCI Request This signal is sourced by an agent wishing to become a bus master. It is a point to point signal and each master has its own PCI_REQN. PCI_GNTN I I L PCI Grant The PCI_GNTN signal is a dedicated, point-to-point signal provided to each potential bus master and signifies that access to the bus has been granted. PCI_AD[31:0] I/O I - PCI Multiplexed Address/Data Bus Address and data are multiplexed on the same PCI bus pins. A PCI bus transaction consists of an address phase followed by the one or more data phase. An address phase occurs on the PCLK cycle in which PCI_FRAMEN is asserted. A data phase occurs on PCLK cycles in which PCI_IRDYN and PCI_TRDYN are both asserted. 9/22 ST70137 PIN DESCRIPTION (continued) Signal Name PCI_CBE_N[3:0] Direction Init Status Polarity I/O I L Signal Description PCI Multiplexed Bus Command Mode Bus command and byte enables are multiplexed on the same pins. These pins define the current bus command during an address phase. During a data phase, these pins are used as Byte Enables, with PCI_CBE_N[0] (LSB) enabling byte 0 and PCI_CBE_N[3] enabling byte 3 (MSB). C/BE[3:0]=Command Type 0000 = Interrupt Acknowledge 0001 = Special Cycle 0010 = I/O Read 0011 = I/O Write 0100 = Reserved 0101 = Reserved 0110 = Memory Read 0111 = Memory Write 1000 = Reserved 1001 = Reserved 1010 = Configuration Read 1011 = Configuration Write 1100 = Memory Read Multiple 1101 = Memory Write Multiple 1110 = Memory Read line 1111 = Memory Write and Invalidate PCI_PAR I/O I H PCI Parity (even) Parity is always driven as even from all PCI_AD[31:0] and PCI_CBE[3:0] signals. The parity is valid during the clock following the address phase and is driven by the bus master. During a data phase for write transactions, the bus master sources this signal on the clock following PCI_IRDYN active; during data phase for read transactions, this signal is driven by the target and is valid on the clock following PCI_TRDYN active. The PCI_PAR signal has the same timing as PCI_AD[], delayed by one clock. PCI_FRAMEN I/O I L PCI Cycle Frame This signal is driven by current bus master to indicate the beginning and duration of a bus transaction. When PCI_FRAMEN is first asserted, it indicates a bus transaction is beginning with a valid addresses and bus command present on PCI_AD[31:0] and PCI_CBE[3:0]. Data transfer continue until PCI_FRAMEN is asserted. PCI_FRAMEN de-assertion indicates the transaction is in final data phase or has completed. PCI_DEVSELN I/O I L PCI Device Select This signal is driven by a target decoding and recognizing its bus address. This signal informs a bus master whether an agent has decoded a current bus cycle. PCI_IRDYN I/O I L PCI Initiator Ready This signal is always driven by the bus master to indicate its ability to complete the current data phase. During write transactions it indicates PCI_AD[] contains valid data. PCI_IDSEL I I H PCI Initializatio n Device Select This pin is used as chip select during configuration read or write transactions. 10/22 ST70137 PIN DESCRIPTION (continued) Signal Name Direction Init Status Polarity Signal Description PCI_TRDYN I/O I L PCI Target Ready This signal is driven by the select target to indicate the target is able to complete the current data phase. During read transactions, it indicates PCI_AD[] contains valid data. Wait states occur until both PCI_TRDYN and PCI_IRDYN are asserted togheter. PCI_PERRN I/O I L PCI Parity Error Only for reporting data parity errors for all bus transactions except for special cycles. It is driven by the agent receiving data two clock cycles after the parity was detected as an error. This signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition. PCI_SERRN O Z L PCI System Error Used to report address and data parity errors on special cycle commands and any other error condition having a catastrophic system impact. PCI_INTAN O Z L PCI Interrupt A This signal is defined as optional and level sensitive. Driving it low will interrupt to the host. The PCI_INTAN interrupt is to be used for any single function device requiring an interrupt capability. PCI_PMEN O Z L PCI Power Management Event This signal is used to indicate that a power management event has been detected. The PCI_PMEN signal is asynchronous with respect to the PCI clock; it is set (if enabled) by the low to high transition of the ACTD signal. PCI_STOPN I/O I L PCI Stop This signal indicates the current target is requesting the master to stop the current transaction. DPLUS I/O I + Differential positive USB data input/output. DMINUS I/O I - Differential negative USB data input/output. I/O I - General Purpose I/O Bus These signals are controlled by internal registers located inside ADSL uP block. At the Power-up, Hardware or Software Reset the input direction is chosen. CFG_MEM_SEL I I - Select Internal [1] or External [0] PCI/USB configuration memory. USB_PCIN_sel I I - Select PCI [0] or USB [1] Interface Selecting USB interface and if all Test Pins are set to default value, all the PCI Pads are deactivated. The power supply for this section can be not provided. The PCI section is frozen. Selecting PCI interface the DMINUS and DPLUS has to be set to the low level (reset mode). The PLL is in power down and no any clock will be provided to the USB section. VAUX_D / USB_SP I I - VAUX Detect when USB_PCIN_sel = [0] or USB SELF POWERED when USB_PCIN_sel = [1]. USB INTERFACE MISCELLANEOUS INTERFACE GPIO[3:0] 11/22 ST70137 PIN DESCRIPTION (continued) Signal Name Direction Init Status Polarity Signal Description CLOCK & RESET INTERFACE MCLK I I - 35.328 MHz Master Input Clock. RSTN I I L Asynchronous Master USB_PCI_SEL = ‘1’). AFETXD[3:0] O L - AFE Transmit Data Nibble Bus The signal changes are synchronized to the rising edge of MCLK clock signal. AFERXD[3:0] I I - AFE Receive Data Nibble Bus The signal changes are synchronized to the rising edge of MCLK clock signal. CLWD I I H Start of word indication This signal is the word clock used to enable shift of data. It occurs on CTRLDOUT signal to indicate the first data of the nibble sequence. The CLWD frequency is equal to MCLK/4. CTRLDOUT O H L Transmit Control Word Data to AFE The data is shifted out from internal register on the rising edge of MCLK during CLWD assertion. AFESEL I I - Select ST-70136 [0] or ADSL_C [1]. AFERST O L L AFE Reset This signal is connected to the internal PCFW (USB_PCIN_SEL = [0]) or UCFW registers (USB_PCIN_SEL = [1]) if AFESEL = [0], or to the Sachem GPOUT register if AFESEL = [1]. Not usable in USB mode. AFEWR / GPIO[ 5] I/O I L/- AFE Write control output signal (AFESEL = 0), or General Purpose I/O pin. The selection is performed writing the proper bit in the PCFW or UCFW (depending on status of USB_PCIN_SEL pin) registers. At the power-on or hardware reset the GPIO[5] function is selected. CTRLDIN / GPIO[4] I I L/- Receive Control word data from AFE (AFESEL = 0), or General Purpose I/O pin. The selection is performed writing the proper bit in the PCFW or UCFW (depending on status of USB_PCIN_SEL pin) registers. At the power-on or hardware reset the GPIO[4] function is selected ACTD I I H Activation Tone Detect [1] (or Wake Up signal). When PCI IF has been selected, the Low to High transition of ACTD asserts the PCI_PMEN signal (if this last has been enabled) and generates an interrupt event. When USB IF has been selected, the Low to High transition of ACTD de-asserts the SUSPEND signal and re-enable the internal ST70137 activity. SUSPEND O L H Suspend Mode Indication. SUSPENDN O H L Suspend Mode Indication Negated. PWDN O H H AFE Power Down. LDPWDN O H H Line Driver Power Down [1]. Input Reset (active if AFE INTERFACE 12/22 ST70137 PIN DESCRIPTION (continued) Signal Name Direction Init Status Polarity Signal Description CFG_MEM INTERFACE CFG_SCE O L H Chip Enable This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol. This pin has to be connected directly to the EEPROM’s chip select pin. CFG_SCK/GPO[ 6] O L - Serial Clock or General Purpose Output Pin 6 depending on the internal selection. The selection is performed writing the proper bit inside the PCFW or UCFW register. At the power-on or hardware reset the CFG_CLK functionality is selected. This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol. CFG_SDI I I H Serial Data Input Data going into this pin has to be generated on the rising edge of CFG_SCK. This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol. CFG_SDO/GPO[ 7] O L - Serial Data/Address Output General Purpose Output Pin 7 depending on the internal selection. The selection is performed writing the proper bit inside the PCFW or UCFW register. At the power-up or hardware reset the CFG_SDO functionality is selected. The CFG_SDO data change is synchronous with the falling edge of CFG_SCK. This pin is designed to directly interface to a serial EEPROM that use the 93C66 EEPROM interface protocol. TDI I IH - JTAG Test Data Input. TDO O - - JTAG Test Data Output. TMS I IH L JTAG Test Mode Select. TCK I IL - JTAG Test Clock. TRSTB I IL L JTAG Reset (active Low). JTAG INTERFACE TEST CONDITION All Ouputs have been loaded with. Outputs Minimum Maximum Unit PCI 0 50 pF USB * 0 50 pF Others 0 15 pF * See text scheme at page 20. 13/22 ST70137 TIMING SPECIFICATION MCLK Master Clock Symbol Parameter F Clock frequency T Clock Period Th Clock Duty cycle Minimum Typical Maximum Unit 35.328 MHz 28.3 ns 40 60 % AFE IF Transmit & Receive Signals MCLK T Th1 AFERXD Ts1 AFETXD Tv1 Th2 CLWD Ts2 Tv2 CTRLDOUT AFEWR Tv3 Ts3 CTRLDIN Th3 AFE IF Transmit & Receive signals Ts1 Data Setup Time 5 ns Th1 Data Hold Time 7 ns Tv1 Data Valid Time Ts2 Th2 Tv2 Ts3 Th3 Data Setup Time 5 ns Data Hold Time 6 ns Tv3 13 Data Valid Time 18 ns ns Data Setup Time 20 ns Data Hold Time 1 ns Data Valid Time 18 ns 14/22 ST70137 CFG_MEM IF Signals with PCI = 30.3ns CFG_SCK Tsclk CFG_SDO Tv1 Th CFG_SDI Ts CFG_SCE Tv2 CFG_MEM IF signals with PCI = 30.3ns * Symbol Parameter Minimum Typical Maximum Unit Ts Data Setup Time 45 ns Th Data Hold Time 0 ns Tv1 Data Valid Time 970 ns Tv2 Data Valid Time 160 ns Tsck SCK Clock period: - USB 48MHz USB_CLK / 64 - PCI 33MHz PCI_CLK / 64 ns * PCI conditions are more restrictive than USB conditions. GPIO IF PCI_CLK Tv GPIO OUTPUT GPIO IF Symbol Tv 15/22 Parameter Output Data Valid from PCI_CLK Minimum Typical Maximum Unit 22 ns ST70137 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Description Minimum Typical Maximum Units VDD 3.3 Supply Voltage 3.0 3.3 3.6 V VDD 1.8 Supply Voltage 1.62 1.8 1.98 V 450 mW 0 70 °C -65 +150 °C Ptot Total Power Dissipation Tamb Ambient Temperature 1.5ml airflow Tstg Storage Temperature VESD ESD Protection (HBM) 2000 V PCI Interface DC Specifications Parameter Description Condition Minimum Typical Maximum Units Vilp Input LOW Voltage -0.5 0.3V DD V Vihp Input HIGH Voltage 0.5VDD VDD+0.5 V -10 10 µA 0.1V DD V lip Input Leakage Current 0<Vin<V DD Volp Output LOW Voltage Iout = 1.5mA Vohp Output HIGHT Voltage Iout = 0.5mA Cinp Input Pin Capacitance * Cclkp CLK Pin Capacitance * Cidsel IDSEL Pin Capacitance * Lpinp Pin Inductance * V 0.9VDD 5 N/A 10 pF 12 pF 8 pF 20 nH Maximum Units * Guaranted by design. USB Interface DC Specifications Nominal DC Characteristics (DPLUS, DMINUS) Parameter Description Minimum Typical VDI Differential Input Sensitivity [(D+) - (D-)] 0.2 VCM Differential Common Mode Range 0.8 2.5 V V SE Single Ended Receiver Threshold 0.8 2 V VOH V OL High Level Output Static Voltage (RL of 15KΩ to GND Low Level Output Static Voltage (RL of 1.5KΩ to 3.6V) 2.8 3.6 0.3 V V ILO Hi-Z State Data Line Leakage Current (0V < Vin < 3.3V) 30 µA CIN Transceiver Capacitance (Pin to GND) * 10 pF RD Driver Output Resistance (steady state drive) 44 Ω 28 V * Guaranted by design. 16/22 ST70137 Other Signals DC Characteristics The values presented in the following table apply for all inputs and/or outputs unless otherwise specified. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device. Symbol Parameter Test Condition Minimum Typical Maximum Units IIN Input Leakage Current Vin = VSS, VDD no pull up/pull down -4 +4 µA I OZ Tristate Leakage Current Vin = VSS, VDD no pull up/pull down -4 +4 µA I PU Pull Up Current Vin = VSS -15 -40 -125 µA I PD Pull Down Current Vin = VDD +15 +30 +125 µA Minimum Typical Maximum Units Suspend Mode Current Consumption Symbol Parameter Test Condition I518 Suspend Mode Current Consumption on 1.8V Temperature = 25°C 350 µA I533 Suspend Mode Current Consumption on 3.3V Temperature = 25°C 150 µA AC Specifications PCI Signaling AC Specifications Symbol Ioh Parameter Switching Current High Test Condition 0 < Vout ≤ 0.3VDD Minimum Typical Maximum -12V DD mA -32VDD Vout = 0.7VDD Iol Switching Current Low VDD > Vout ≥ 0.6VDD Units 16V DD mA mA 38VDD Vout = 0.18VDD mA Icl Low Clamp Current * -3 < Vin ≤ -1V Ich High Clamp Current * VDD + 4 > Vin ≥ VDD + 1 25 + (Vin - VDD - 1) / 0.015 Tr Unloaded Output Rise Time * 0.2VDD to 0.6VDD 1 4 V/ns Tf Unloaded Output Fall Time * 0.6VDD to 0.2VDD 1 4 V/ns -25 + (Vin + 1) / 0.015 mA mA * Guaranted by design. Timing Specifications PCI Clock Specifications Symbol Parameter Test Condition Minimum Typical Maximum Units 50 ns Tc Clock Cycle Time 30 Th Clock High Time 11 ns TI Clock Low Time 11 ns Clock Slew Rate * 1 * Guaranted by design. 17/22 4 V/ns ST70137 PCI Clock Waveform 5V 2.4V 2.0V 1.5V 0.8V 0.4V Th TI Tc PCI Clock Waveform 3.3V 0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD Th TI Tc PCI Timings Symbol Parameter Minimum Typical Maximum Units Tval Clock to Signal Valid Delay (bused signals) 2 11 ns Tval(ptp) Clock to Signal Valid Delay (point to point) 2 12 ns Ton Float to Active Delay 2 Toff Active to Float Delay Tsu Input Set up Time to Clock (bused signals) 7 ns Tsu(ptp) Input Set up Time to Clock (point to point) * 10, 12 * ns ns 28 ns Th Input Hold Time from Clock 0 ns Trst Reset Active Time after Power Stable 1 ms Trst-clk Reset Active Time after CLK Stable ** 100 µs Trst-off Reset Active to Output Float Delay ** 40 ns * PCI REQN and GNTN are point-to-point signals and have different output valid delay and input setupt times than do bused signals. REQN has set up of 12ns and GNTN of 10ns. All other signals are bused. ** Guaranted by design. 18/22 ST70137 CLK Tsu Th Input Tval Output Tri-state Output Ton Toff USB Interface AC Specifications (1.1 version) AC Characteristics (D+, D-) Symbol Parameter Test Conditio n Minimum Typical Maximum Units 11.97 12.03 Mbps tDR Average bit rate (12 M/s ±0.05%) tR Rise Time between 10% and 90% (see Figure Rise and Fall Time Measures) 4 20 ns tF Fall Time 10% and 90% (see Figure Rise and Fall Time Measures) 4 20 ns 1.3 2 V VCRS Output Signal Crossover Voltage USB Test Scheme Test 2 Test 1 50pF 19/22 50pF ST70137 Rise and Fall Time Measures TR TF 90% 90% 10% 10% Input / Output TTL Generic Characteristics The value presented in the following table apply for all TTL inputs and/or outputs unless otherwise specified. Symbol Parameter V IL Low Level Input Voltage VIH High Level Input Voltage Test Condition Minimum Typical Maximum Units 0.8 V 2.0 V VILHY Low Level Threshold, falling * Slow edge < 1V/µs 0.9 1.35 V VIHHY Low Level Threshold, rising * Slow edge < 1V/µs 1.3 1.9 V VHY Schmitt Trigger Hysteresis * Slow edge < 1Vµs 0.4 0.7 V VOL Low Level Output Voltage IOUT = XmA (see Note) 0.4 V VOH High Level Output Voltage IOUT = XmA (see Note) 2.4 V * Guaranted by design. Note: The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8mA. 20/22 ST70137 PACKAGE MECHANICAL DATA (TQFP144 - 20 x 20 x 1.40 mm) A A2 A1 e 144 109 0,076 mm 0.03 inch 108 36 73 SEATING PLANE E3 E1 E B 1 c L 72 D3 D1 D L1 37 K Millimeters 0,25 mm .010 inch GAGE PLANE Inches Dimension Minimum Typical A Minimum Typical 1.60 A1 0.05 A2 1.35 B 0.17 C 0.09 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.22 0.27 0.0067 0.0087 0.011 0.20 0.0035 0.008 22.00 0.866 D1 20.00 0.787 D3 17.50 0.689 e 0.50 0.020 E 22.00 0.866 E1 20.00 0.787 E3 17.50 0.689 L1 K 0.45 Maximum 0.063 D L 21/22 Maximum 0.60 0.75 0.018 1.00 0.024 0.039 0° (Min.), 7° (Max.) 0.030 ST70137 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http ://www.st.com 22/22 ST70137.PDF STMicroelectronics GROUP OF COMPANIES