ST72681 USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ USB 2.0 Interface compatible with Mass Storage Device Class – Integrated USB 2.0 PHY – Supports USB High Speed and Full Speed – Suspend and Resume operations Mass Storage Controller Interface (MSCI) – Supports all type of NAND Flash devices – Reed-Solomon Encoder/Decoder for MLC NAND Flash support: on-the-fly correction (4 bytes of a 512-byte block) – Flash identification support – 10MB/s for read and 8MB/s for write operations with one single NAND Flash device – 10MB/s for read and 10MB/s for write operations in multi mode NAND Flash device topology Embedded ST7 8-bit MCU Supply Management – 3.3V operation – Integrated 3.3V-1.8V voltage regulator Very low power consumption – Less than 100mA during write operation with two NAND Flash devices – Less than 500µA in suspend mode Clock Management – Integrated PLL for generating core and USB 2.0 clock sources using an external 12 MHz crystal Up to two configurable LED outputs – Blinking on USB specific activity (idle, suspend, data access) Features USB interface # of NAND devices supported R/W speed Operating Supply Operating Temperature Packages TQFP48 ■ ■ ■ ■ ■ ■ Data Protection – Write protect switch control – Password-based security for data protection Bootability support Flexibility – Configurable Vendor ID/Product ID (VID/PID) with production tool – Patch code support with external EEPROM device TQFP48 7x7 lead-free package Development Support – Complete reference design including schematics, BOM and gerber files Supports Windows ME, Windows 2K, Windows XP, Linux and MacOS. Drivers available for Windows 98 SE ST72681 USB 2.0 up to 4 10MBps/8MBps (single NAND) / 10MBps/10MBps (multi NAND) 3.0V to 3.6V 0°C to +70°C TQFP48 7x7 / Die form Rev. 1.1 May 2005 1/12 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1 ST72681 1 INTRODUCTION The ST72681 is a USB 2.0 high-speed Flash Drive controller. The USB 2.0 high-speed interface including PHY and function supports USB 2.0 Mass Storage Device Class. The Mass Storage Controller Interface combined with the Reed-Solomon Encoder/Decoder on-thefly correction (4-byte on 512-byte data blocks) provides a flexible, high transfer rate solution for interfacing a wide of range NAND Flash memory device types. The internal 60 MHz PLL driven by the 12MHz oscillator is used to generate the 480MHz frequency for the USB 2.0 PHY. The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data and patch code are stored in internal RAM. I/O ports provide functions for EEPROM connection, LEDs and write protect switch control. The internal 3.3V to 1.8V voltage regulator provides the 1.8V supply voltage to the digital part of the circuit. Figure 1. Device Block Diagram 8-bit CPU 12 MHz OSC USB 2.0 PHY USB 2.0 Function 3.3V to 1.8V Voltage Regulator 2/12 1 ROM RAM Mass Storage Controller Interface ReedSolomon Error Correction GPIO NAND I/F ST72681 2 PIN DESCRIPTION NAND D[5] NAND D[4] NAND D[3] NAND D[2] NAND D[1] NAND D[0] NC* NAND D[6] NAND D[7] NAND RnB NAND WP READ ONLY EEPROM SCL VSS_2 VDD33_2 NC* NC* RESET LED2 LED1 NAND ALE/EEPROM SDA VSS_3 NC* VDD33_3 VDDOUSB VSSBL VDDBL NAND CLE USBDM NAND WE VDD3 USBDP ST72681 NAND RE VDDC NAND CE1 VSSC NAND CE2 RREF NAND CE3 VSSA NAND CE4 OSCOUT VDD33_4 OSCIN 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS_4 VDDA VDD33_1 VSS_1 Figure 2. 48-Pin TQFP Package Pinout * must remain NOT connected in the application 3/12 1 ST72681 PIN DESCRIPTION (Cont’d) Legend / Abbreviations for tables: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with Schmitt trigger Output level: D8 = 8mA drive D4 = 4mA drive D2 = 2mA drive Port and control configuration: – Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt – Output: OD = pseudo open drain, PP = push-pull The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Pin Type Table 1. Power Supply Pin Name Description 48 VSS_1 S Ground 47 VDD33_1 S IOs and Regulator supply voltage 33 VSS_2 S Ground 32 VDD33_2 S IOs and Regulator supply voltage 25 VSS_3 S Ground 24 VDD33_3 S IOs and Regulator supply voltage 14 VSS_4 S Ground 15 VDD33_4 S IOs and Regulator supply voltage 13 VDDOUSB S USB2 PHY, OSC and PLL power supply output (1.8V) Table 2. Control & System 29 RESET 4/12 I/O 3.3 CT Output Input Pin Name Power Level Type TQFP48 Pin Description Reset input with filter with internal pull-up ST72681 PIN DESCRIPTION (Cont’d) Table 3. USB 2.0 Interface Pin Name Type TQFP48 Pin Description 12 VDDBL S Supply voltage for buffers and deserialisation flip flops (1.8V) 11 VSSBL S Ground for buffers and deserialisation flip flops (1.8V) 10 USBDM I/O USB2 DATA - 9 USBDP I/O USB2 DATA + 8 VDD3 S Supply voltage for the FS compliance (3.3V) 7 VDDC S Supply voltage for DLL & xor tree (1.8V) 6 VSSC S Ground for DLL & XOR tree (1.8V) 5 RREF I/O Ref. resistor for integrated impedance process adaptation (11.3 kOhms 1% Pull Down) Table 4. USB 2.0 and core Clock System Pin Name Type TQFP48 Pin Description 4 VSSA S Ground for osc & PLL (1.8V) 3 OSCOUT O 12MHz oscillator output 2 OSCIN I 12MHz oscillator input 1 VDDA S Supply voltage for osc & PLL (1.8V) 5/12 ST72681 PIN DESCRIPTION (Cont’d) Table 5. General Purpose IO Ports / Mass Storage IOs Level Alternate function 45 NAND D[0] I/O TT D4 NAND DATA [0] 44 NAND D[1] I/O TT D4 NAND DATA [1] 43 NAND D[2] I/O TT D4 NAND DATA [2] 42 NAND D[3] I/O TT D4 NAND DATA [3] 41 NAND D[4] I/O TT D4 NAND DATA [4] 40 NAND D[5] I/O TT D4 NAND DATA [5] 39 NAND D[6] I/O TT D4 NAND DATA [6] 38 NAND D[7] I/O TT D4 NAND DATA [7] 26 NAND ALE / EEPROM SDA I/O TT D8 NAND ADDRESS LATCH ENABLE EEPROM SERIAL DATA 22 NAND CLE O TT D8 NAND COMMAND LATCH ENABLE 21 NAND WE O TT D8 NAND WRITE ENABLE 20 NAND RE O TT D8 NAND READ ENABLE 19 NAND CE1 O TT D4 NAND ENABLE 1 18 NAND CE2 O TT D4 NAND ENABLE 2 17 NAND CE3 O TT D4 NAND ENABLE 3 16 NAND CE4 O TT D4 NAND ENABLE 4 37 NAND RnB I TT D2 NAND READY/BUSY TQFP48 Outputs Main function (after reset) Input Type Pin Pin Name 36 NAND WP O TT D2 NAND WRITE PROTECT 35 READ ONLY I TT D2 READ ONLY SWITCH 34 EEPROM SCL O TT D2 EEPROM SERIAL CLOCK 28 LED2 O TT D8 GREEN LED (USB ACCESS) 27 LED1 O TT D8 RED LED (NAND ACCESS) 6/12 ST72681 3 NAND FLASH DEVICE SUPPORT Type Samsung K9F2808U0C-Y Samsung K9F5608U0C-Y Samsung K9F1208U0A-Y Toshiba TC58512FT Toshiba TC58DVM92A Toshiba TC58DVG02A Toshiba TC58DVG04B1FT00 Toshiba TC58DVG14B1FT00 ST NAND128W3A ST NAND256W3A ST NAND512W3A ST NAND01GW3A Hynix HY27US08281M Hynix HY27US08561M Hynix HY27US08121M Samsung K9F1G08U0M-Y Samsung K9F2G08U0M-Y Samsung K9K2G08U0M-Y Samsung K9K4G08U0M-Y Samsung K9W4G08U1 Samsung K9W8G08U1 Toshiba TH58NVG0S3 Toshiba TH58NVG1S3 Toshiba TH58NVG2S3 ST NAND01GW3B ST NAND02GW3B Hynix HY27UA081G1M Micron 29F2G08AA Memory size 16M x 8b 32M x 8b 64M x 8b 64M x 8b 64M x 8b 128M x 8b 128M x 8b 256M x 8b 16M x 8b 32M x 8b 64M x 8b 128M x 8b 16M x 8b 32M x 8b 64M x 8b 128M x 8b 256M x 8b 256M x 8b 512M x 8b 512M x 8b 1G x 8b 128M x 8b 256M x 8b 512M x 8b 128M x 8b 256M x 8b 128M x 8b 256M x 8b Program Page Size (in Bytes) 528 528 528 528 528 528 528 528 528 528 528 528 528 528 528 2112 2112 2112 2112 2112 2112 2112 2112 2112 2112 2112 2112 2112 7/12 ST72681 4 APPLICATION SCHEMATICS Figure 3. Application Schematic Sheet 1/2 1 2 3 4 5 6 8 7 D D V33 V33 C12 10nF USB_V5 U1 1 2 3 Vin C13 10nF C14 10nF C15 10nF 5 Vout GND + C8 4.7uF 4 INHIBIT BYPASS LD3985M33R_SOT23-5L C1 10nF C10 220nF D[7..0] NAND_WP NAND_RnB NAND_ALE NAND_CLE NAND_WE NAND_RE V33 C NAND_CE4 NAND_RnB NAND_CE2 NAND_CE1 R1 4.7K C NAND_CE3 D5 D6 D7 D0 D1 D2 D3 D4 NAND NAND Sheet NAND_VCC B DP DM V33 J1 VBUS DD+ GND 1 2 3 4 V18_USB C16 10nF C17 10nF C18 10nF LED2 LED1 NAND ALE/EEPROM SDA VSS_3 EEPROM_SCL NAND_WP NAND_RnB NAND_ALE NAND_CLE NAND_WE NAND_RE NAND_CE4 NAND_CE3 NAND_CE2 NAND D[5] NAND D[6] NAND D[7] NAND RnB RO C3 U3 100nF 13 14 15 USB CON V33 RESET 28 27 PE2 PE3 26 25 NAND_ALE NAND_VCC E0 VCC E1 nWC E2 SCL VSS SDA R6 18K B NAND_ALE M24C32W_TSSOP8 PE2 11.3K 1% ST72681 PE3 R3 18pF 36 35 34 33 32 31 30 29 R4 220 R5 220 23 24 1uF NAND CE4 NAND CE3 NAND CE2 NAND CE1 NAND RE NAND WE NAND CLE C19 100nF VDDA OSCIN OSCOUT VSSA RREF VSSC VDDC VDD3 USBDP USBDM VSSBL VDDBL 16 17 18 19 20 21 22 C21 C2 1 2 3 4 5 6 7 8 9 10 11 12 10K NAND WP READ ONLY EEPROM SCL VSS_2 VDD33_2 NC NC RESET XT1 CRYSTAL 12MHz_M49-12.000 VDDOUSB VSS_4 VDD33_4 18pF V18_USB R2 NC VDD33_3 C20 NAND D[0] NAND D[1] NAND D[2] NAND D[3] NAND D[4] VSS_1 VDD33_1 NC V18_USB USB_V5 NAND_CE1 40 39 38 37 45 44 43 42 41 48 47 46 NAND_WP S1 Read Only U2ST72 C22 470nF LED1 RED LED NAND_CE4 NAND_CE3 NAND_CE2 NAND_CE1 NAND_RE NAND_WE NAND_CLE V33 LED2 GREEN LED V33 A A Title PFD/Ref 1B CPU Size Number 1 8/12 2 3 4 5 6 Revision Release 1 A3 Date: File: Drawn By: Sheet 1 of 2 20-May-2005 7 8 1B ST72681 Figure 4. Application Schematic Sheet 2/2 D C B A 1 1 2 NAND_RnB 2 0 0 3 D7 D6 D5 D4 C4 100nF C6 100nF NAND_WP NAND_RE NAND_WE NAND_CLE NAND_ALE D3 D2 D1 D0 4 U4 NAND_FLASH_TSOP48 NAND_CE1 NAND_CE2 NAND_CE3 NAND_CE4 D[7..0] On Board Flash1 NAND_CE1 NAND_CE2 NAND_CE3 NAND_CE4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V33 V33 NAND_WP NAND_RE NAND_WE NAND_CLE NAND_ALE 4 D7 D6 D5 D4 C5 100nF C7 100nF D3 D2 D1 D0 6 U5 On Board Flash2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V33 V33 6 NC/#RES NC NC NC NC NC NC NC NC I/O 7 GND/RB2/NC I/O 6 #R/B I/O 5 #RE I/O 4 #CE NC NC/#CE2 NC NC NC/PRE VCC VCC VSS VSS NC NC NC NC CLE NC ALE I/O 3 #WE I/O 2 #WP I/O 1 NC I/O 0 NC NC NC NC NC NC NC NC 5 5 1 2 3 4 5 NAND_RnB2 6 7 NAND_RnB NAND_RE 8 NAND_CE2 9 NAND_CE4 10 11 12 13 14 15 NAND_CLE 16 NAND_ALE 17 NAND_WE 18 NAND_WP 19 20 21 22 23 24 NC/#RES NC NC NC NC NC NC NC NC I/O 7 GND/RB2/NC I/O 6 #R/B I/O 5 #RE I/O 4 #CE NC NC/#CE2 NC NC NC/PRE VCC VCC VSS VSS NC NC NC NC CLE NC ALE I/O 3 #WE I/O 2 #WP I/O 1 NC I/O 0 NC NC NC NC NC NC NC NC D[7..0] R_Samsung W_config R_SW R_Toshiba_config R_T NAND_RnB 3 1 2 3 4 5 GND/NAND_RnB2 6 7 NAND_RnB NAND_RE 8 NAND_CE1 9 NAND_CE3 10 11 12 13 14 15 NAND_CLE 16 NAND_ALE 17 NAND_WE 18 NAND_WP 19 20 21 22 23 24 NAND_FLASH_TSOP48 Title A3 Size 7 Release 1 PFD/Ref NAND Number 7 Date: 11-May-2005 Drawn By: 8 Sheet 2of2 8 Revision 1B D C B A 9/12 ST72681 5 PACKAGE MECHANICAL DATA Figure 5. 48-Pin Thin Quad Flat Package Dim. mm Min Typ inches Max Min Typ A A D1 A2 A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 C 0.09 A1 b E1 e E c L1 L θ 1.60 0.063 0.15 0.002 0.006 0.20 0.004 0.008 D 9.00 0.354 D1 7.00 0.276 0.354 E 9.00 E1 7.00 0.276 e 0.50 0.020 θ 0° 3.5° L 0.45 0.60 L1 7° 0° 3.5° N 7° 0.75 0.018 0.024 0.030 1.00 0.039 Number of Pins 10/12 Max D 48 ST72681 6 REVISION HISTORY Table 6. Revision History Date May-2005 Revision 1.1 Description of Changes Changed status of the document Changed description on 1st page Removed unconnected pins in Table 5 on page 6 Changed Table 4, “USB 2.0 and core Clock System,” on page 5 Changed pin 5 description in Table 3, “USB 2.0 Interface,” on page 5 Changed section 3 on page 7 Changed Figure 3 and Figure 4 11/12 ST72681 Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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