ST7282A5 - ST7282B5
ROM FROM EPROM
PRELIMINARY DATASHEET
■
■
ST72-Core
Controller/Driver for max. 20 × 16, 28 × 8
or 32 × 4
■
LCD segments (ST7LCD4)
■
56 bytes LCD-RAM
■
864 bytes data RAM
■
512 bytes EEPROM (eep2a)
■
32Kbytes program ROM
■
24 digital I/O (ST7 IO3) with pull up,
interrupt input, analog input, push-pull/
open drain output
■
36 LCD/IO combi pins (ST7 LCIO1) with
pull-up, interrupt input, push-pull, open
drain output, LCD output
■
16 bit reload timer (ST7TIM4)
■
Watchdog Timer (ST7 WD2)
■
8 bit synchronous serial I/O (ST7SIO)
■
8 bit A/D Converter (ST7ADC2)
■
RDS Demodulator (ST7 RDS BD)
■
Group & Block Sync Module for RDS (ST7
RDS GB)
■
RDS filter (ST7 RDS FI)
■
LCD Synchro IN / Out
■
System Frequency 8.55 MHz
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1 GENERAL DESCRIPTION
T IM E R 1 6 b it
S T 7 T IM 4
ST7 LCIO
S IO
G R P & B LK S Y N C
ST 7 R D S G B
R D S F ilte r
ST 7 R DS F I
ST 72 CO R E
LCD RAM
5 6B y te
O S C IL L A T O R
S T 7 O S C IL L A T O R
LCD C O N TR OL
S eg . D rv ./P or t E
VD D
VS S
V P P /T E S T
R E SE T
MPX
R D S F IL
RDS REF
O S C IN
8 .5 5 M H z
O S C O U T /S T O P
S 2 2 /P E 5
S 2 1 /P E 4 /R D S C O M P
O s c - O p tio n
S20/PE3
S19/PE2
S18/PE1
S17/PE0
S T 7 L C IO
VLCD 1/5
VLCD 2/5
VLCD 3/5
VLCD
VLCD 4/5
S T7 LC D 4
BP1/PH0
BP3/PH2
BP4/PH3
BP5/S-12/PH4
BP6/S-11/PH5
BP7/S-10/PH6
BP8/S-9/PH7
PO R T H
S T 7 L C IO
P A 0 /C P 1/A IN
P A 1 /C P 2/A IN
P A 2 /A IN
P A 3 /A IN
P A 4 /A IN
P A 5 /A IN
P A 6 /A IN
P A 7 /A IN
R D S C O M P /P E 4 /S 2 1
RDS DEM OD.
ST 7 R DS B D
3 2K R O M
RA M 864
ST7 IO3
AD C
ST 7 A DC 2
ST7 LCIO
Seg. Drv. PORT G
PORT A
E E P R O M 51 2
W A TC H D O G
ST 7 W D 2
B P 1 6 /S 0 /P G 7
B P 1 5 /S - 1/P G 6
B P 1 4 /S - 2/P G 5
B P 1 3 /S - 3/P G 4
B P 1 2 /S - 4/P G 3
B P 1 1 /S - 5/P G 2
B P 1 0 /S - 6/P G 1
B P 9 /S -7 /P G 0
PO RT B
S T 7 IO 3
S T 7 IO 3
BP2/PH1
Seg. Drv. PORT D
S 8 /P F 7
S 7 /P F 6
S 6 /P F 5
S 5 /P F 4
S 4 /P F 3
S 3 /P F 2
S 2 /P F 1
S 1 /P F 0
PO R T C
ST7 LCIO
S 1 6 /P D 7
S 1 5 /P D 6
S 1 4 /P D 5
S 1 3 /P D 4
S 1 2 /P D 3
S 1 1 /P D 2
S 1 0 /P D 1
S 9 /P D 0
Seg. Drv. PORT F
VDDP
VSSP
VDDA
VSSA
PC0/AIN
PC1/AIN
PC2/AIN
PC3/AIN
PC4/AIN
PC5/AIN
PC6/AIN
PC7/AIN
PB0/AIN
PB1/AIN
PB2/AIN
PB3/AIN
PB4/AIN
PB5/AIN
PB6/AIN
PB7/AIN
Figure 1. Block Diagram
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1.1 Quick Reference
The ST7282A5/B5 is a 32K ROM version of the
ST72 family, using the ST72CORE and N-Well
technology.
It is derived from EPROM M4 version replacing
EPROM by ROM.
Two different commercial products are supported
by this device : ST7282A5 (no LCD driver) functionnality described in specification SD70KL1618
ed. F) and ST7282B5 (LCD driver) functionnality
described in specification 96096 ed. B).
It contains an LCD controller/driver with 20 segment and 16 backplane outputs able to drive up to
20 x 16 = 320 segments.
The LCD control logic reads automatically data
from the LCD-RAM independently from the
ST7282 B5.
Further it contains up to 62 I/O pins, 24 of them
can be used as analog inputs to the 8 bit analogdigital converter. Each digital I/O pin can individually be defined by software to work in one of the
following modes: open-drain output, push pull output, input, input with pull-up (23 pins only) or inter-
rupt input with pull up (23 pins only). 3 of the digital
I/O pins serve as interface to the SIO. On pin PA4
the pull-up resistor is desactivated.
Port pins PD, PE, PF, PG and PH are multiplexed
with LCD Segment and backplane pins.
A 512 byte EEPROM for non volatile storage of
data is available. The programming voltage for
that device is generated on chip without external
components. So no extra supply is necessary. 16
bytes are protected against external readout.
One interrupt vector is connected to the I/O ports.
Five more interrupt vectors are available for the
timer, the ADC, the serial I/O interface and the
Group & Block Sync module (2). The watchdog
can be set by the user in 64 increments from
2.8msec to 182msec ( fOSC = 8.55 MHz ).
A synchronous 8 bit serial interface for serial data
IN/OUT is also implemented.
RDS signals can be decoded with the help of RDS
filter, RDS demodulator and Group & Block Sync
module.
1.2 Parameters
The values below substitute the corresponding values in the specifications of dedicated functions.
1.2.1 Absolute maximum ratings
Supply voltage
Input voltage*
Output voltage*
Input current
Output current*
Power dissipation
Storage temperature
Operation temperature
Display voltage
Output voltage Seg+COM
ESD
LU susceptibility
( VDD - VSS )
VIN
VOUT
Iin
IOUT
PD
Tstg
Tamb
(VLCD - VSS)
VOUT
ESD
LU
-0.3 ... +7V
VSS-0.3V...VDD +0.3V
VSS-0.3V ... VDD+0.3V
-10 ... +10mA
-10 ... + 10mA
tbd
-55 ... +125°C
-40 ... +85°C
VDD ... 7V
VSS-0.3V ... VLCD+0.3V
2500V
VDDA, Pin 52 - Class C
1.2.2 Recommended operating conditions
Supply voltage
Supply votage difference
(VDD - VSS)
4.5 ... 5.5V
(VDD, VDDP, VDDA)
50mV
(VSS, VSSP, VSSA)
The maximum accumulated current of all I/O pins
should not exceed 40 mA for VDDP and 40 mA for
VSSP.
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* except LCD pins
** MIL 883B Mode, 100pF through 1.5k
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1.2.3 Electrical Characteristics
The values given in the specifications of dedicated functions are generally not applicable for chips. Therefore, only the limits listed below are valid for the product. T = -40 ... +85°C, VDD - VSS = 5V unless otherwise
specified.
PARAMETER
SYMBOL
VDD
IDD
Supply voltage
Supply current Run Mode
CONDITION
fOSC=8.55MHz
MIN
TYP
MAX
UNIT
4.5
-
5.5
V
-
10
20
mA
-
3
5
mA
no output load
IDD
Supply current Wait Mode
fOSC=8.55MHz
WD, Timer, LCD active
Supply current slow wait mode
IDD
no output load
-
0.7
2
mA
Supply current halt mode
IDD
no output load
-
-
100
µA
Supply current Reset Mode
IDD
VRESET=VSS
-
10
15
mA
VDD
-
7
V
-
-
50
mV
9.00
pF
f=8.55MHz
Display voltage
Supply voltage differences
VLCD
VD
(VDD, VDDP, VDDA)
(VSS, VSSP, VSSA)
OSCILLATOR:
Input/output cap Cin, Cout
Oscillation frequency
1)
Built up time 2)
fOSC
VDD = 4.5V
tBU
VDD=5.0V
8.55
8.55
8.55
MHz
-
8
20
ms
+50
+100
µA
+10
+20
µA
-
1
mA
-
-
V
-
0.2VDD
V
-
10
ms
C1=C2=22pF
Crystal
RESET:
3)
Input current
Input current 4)
-IR
VR=VSS
IR
VR=VDD
Input current 5)
IR
VR=VDD
Input voltage high
VR
Input voltage low
VR
0.7VDD
POWER-ON RESET
tr
Supply rise time
6)
10%-90%
.01
trec
10
-
-
ms
Trigger level on
Vtlon
1.4
.-
-
V
Trigger level off
Vtloff
-
-
3
V
Supply recovery time
RDS FILTER:
Center frequency
fc
56.5
57
57.5
KHz
3dB Bandwith
BW
Vin = 3mVRMS
2.5
3
3.5
KHz
Gain
G
57 KHz, Vin = 3mVRMS
18
20
22
dB
Attenuation
A
∆f = ±4 KHz
18
22
-
dB
f = 38 KHz
50
80
-
dB
f = 67 KHz
35
50
-
dB
Input impedance
RI
100
160
200
KΩ
Load impedance
RL
1
-
-
MΩ
MPX input signal
VIN
170
250
600
mVRMS
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ST7282A5 - ST7282B5 - ROM FROM EPROM
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
I/O PORTS:
Input leakage current 7)
IIL
V=VSS
-
-
10
µA
Input leakage current
IIH
V=VDD
-
-
10
µA
Input voltage high
VIH
leading edge
0.7VDD
-
-
V
Input voltage low
VIL
trailing edge
-
-
0.2VDD
V
Output voltage high
VOH
I=5mA, VDD=4.5V
3.0
-
-
V
(PA,PB,PC)
VOH
I=1.0mA, VDD=4.5V
4.1
-
-
V
Output voltage high
VOH
I=2.5mA, VDD=4.5V
3.0
-
-
V
(PD, PE, PF, PG, PH)
VOH
I=0.5mA, VDD=4.5V
4.1
-
-
V
Output voltage low
VOL
I=-5mA, VDD=4.5V
-
-
1.0
V
(PA, PB, PC, PD, PE, PF, PG,
PH)
VOL
I=-1.6mA, VDD=4.5V
-
-
0.4
V
Output voltage slope
dVO/dt
CL=50pF
-
0.25
-
V/ns
Output current slope
dIO/dt
CL=50pF
-
2.5
-
mA/ns
Noise amplitude
VN
20MHz-250MHz
-
100
-
µV
VIN=VSS
-
-
-
-
Pullup Resistor Current
IRPU
-
50
-
µA
ADC:
Resolution
VA1
Total Error
tcon
Conversion time
fOSC=8.55MHz 8)
-
-
bit
fOSC=8.55MHz 8)
-
+2
LSB
fOSC=8.55MHz
34
35
µs
-
5
pF
-
30
KΩ
8.55
-
MHz
Input capacitance
RVA
Analog source impedance
Osc. frequency range
LCD DRIVER:
Frame frequency
fF
fOSC=8.55MHz
-
132
Hz
DC offset voltage 9)
VOS
VLCD=VDD, no load
-
50
mV
COM output voltage high
VOH
I=50µA
-
-
V
COM output voltage low
VOL
I=50µA
-
0.5
V
SEG output voltage high
VOH
I=25µA
-
-
V
SEG output voltage low
VOL
I=25µA
-
0.5
V
tW
VDD=4.5V
-
10
ms
EEPROM:
Write time
1)Operation below 30 KHz Mis possible but requires increased supply current
2)Time to build up the oscillation amplitude to 90% VDD
3)Pull-up resistor
4)WD not active
5)WD generating a reset
6)Period for which VDD has to be disconnected or at OV to allow internal reset function at next power
up
7)pull up off
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ST7282A5 - ST7282B5 - ROM FROM EPROM
8) noise at VDD, VSS < 10 mV
9)The DC offset voltage refers to all segment and common outputs. It is the difference between the
measured voltage value and nominal voltage value for every voltage level. Rin of voltage meter
must be > 10 MΩ.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1.3 ST7282A5/B5 ADDRESS MAPPING
ADDR.
USER
$0000
Port A Data Reg.
$0001
Port A Data Direction Reg.
$0002
Port A Option Reg.
$0003
Port A Pin status
$0004
Port B Data Reg.
$0005
Port B Data Direction Reg.
$0006
Port B Option Reg.
$0007
Port B Pin status
$0008
Port C Data Reg.
$0009
Port C Data Direction Reg.
$000A
Port C Option Reg.
$000B
Port C Pin status
$000C
Port D Data Reg.
$000D
Port D Data Direction Reg.
$000E
Port D Option Reg.
$000F
Port D Pin status
$0010
ADC Control Reg.
$0011
ADC Data Reg.
$0012
Watchdog Reg.
$0013
LCD Ctrl. 1
$0014
EECR1
$0015
EECR2
$0016
SIO Data Reg.
$0017
SIO Interrupt Disable
$0018
Timer Reg. 1
$0019
Timer Reg. 2
$001A
Timer Reg. 3
$001B
Timer Reg. 4
$001C
Timer Reg. 5
$001D)
(Not to be used **
--------)
(-----
$0023)
(from $001D to $0023
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ST7282A5 - ST7282B5 - ROM FROM EPROM
$0024
CRC Test Reg. ( ST use )
$0025
CRC Test Reg. ( ST use )
$0026
Misc. Reg.
$0027
LCD Ctrl. 2
$0028
reserved
$0029
reserved
$002A
Filter Reg. 1
$002B
Filter Reg. 2
$002C
RDS_R0
$002D
RDS_R1
$002E
RDS_R2
$002F
reserved
$0030
RDS_BD_H
$0031
RDS_BD_L
$0032
RDS_CORRP
$0033
RDS_QU
$0034
RDS_INT
$0035
reserved
$0036
reserved
$0037
reserved
$0038
reserved
$0039
reserved
$003A
reserved
$003B
reserved
$003C
reserved
$003D
reserved
$003E
reserved
$003F
reserved
$0040
LCD RAM 8 Byte MUX8
-----
SEG.-7-0 = Byte 40 ... 47
$0047
BP1 ... BP8 = Bit0 ... Bit7
$0048
LCD RAM 24 Byte MUX8,11,16
-----
SEG. 1 - 24 = Byte 48 ... 5F
$005F
BP1 ... BP8 = Bit0 ... Bit7
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ST7282A5 - ST7282B5 - ROM FROM EPROM
$0060
LCD RAM 4 Byte Mux 4
-----
Seg -8, -9, -10, -11
$0063
BP1 ... BP4 = Bit0 ... Bit3
$0064
$0065
$0066
$0067
LCD RAM
not used
for display
$0068
LCD RAM 24 Byte MUX 11, 16
-----
SEG. 1-24 = Byte 68 ... 7F
$007F
BP9 ... BP16 = Bit0 ... Bit7
$0080
-----
reserved
$008F
$0090
Port E Data Register
$0091
Port E Data Direction Register
$0092
Port E Option Register
$0093
Port E Pin Status
$0094
Port F Data Register
$0095
Port F Data Direction Register
$0096
Port F Option Register
$0097
Port F Pin Status
$0098
Port G Data Register
$0099
Port G Data Direction Register
$009A
Port G Option Register
$009B
Port G Pin Status
$009C
Port H Data Register
$009D
Port H Data Direction Register
$009E
Port H Option Register
$009F
Port H Pin Status
$00A0
-----
RAM 864 Stack = 300-3FF
$03FF
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ST7282A5 - ST7282B5 - ROM FROM EPROM
$0400
-----
reserved
$0DFF
$0E00
-----
EEPROM read out protected
$0E0F
$0E10
-----
EEPROM 512
$0FFF
$1000
-----
not available (test area)
$1FFF
$2000
-----
reserved
$7FFF
$8000
-----
ROM 32k
$FFDF
$FFE0
-----
reserved (ST Routram area)
$FFEF
$FFF0
-----
user vectors
$FFFF
“Not to be used” is mandatory. Any access would modify the functionality.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2 IMPLEMENTATION REMARKS OF THE DEDICATIONS
In this chapter the options of the dedications, which are implemented are described. The dedications are
described in detail in the target specs of the dedications. In case of discrepancies between this specification and the specs. of the dedications, this specification is valid.
2.1 Core
2.1.1 Oscillator
The oscillator can be used with quartz or ceramic resonator. The pins OSCIN and OSCOUT permit connection to the on chip clock oscillator circuit. OSCIN is the input, OSCOUT the clock oscillator output. A
quartz or a ceramic resonator can be connected to these pins. Two external ceramic capacitors of 22pF
connect the oscillator pins to ground. Also an external system clock can be applied to the oscillator input
OSCIN.
2.1.2 External reset input RESET
Low level active external reset input with Schmitt-Trigger characteristic. A pull-up resistor of typically
300kΩ ( 200kΩ - 500kΩ ) is integrated. This pin is resetting the I/O ports immediately without any need of
a clock.
2.1.3 Stack
The Stack is located at 3FFH and may go down to 300H.
2.1.4 Interrupts
I1 is connected to IOPorts A ... H (start address FFFAH )
I2 is connected to RDS GRP & BLK SYNC (block interrupt) ( start address FFF8H )
I3 is connected to SIO ( start address FFF6H )
I4 is connected to Timer ( start address FFF4H )
I5 is connected to ADC (start address FFF2H )
I6 is connected to RDS GRP & BLK SYNC (bit interrupt) (start address FFF0H )
If more then 1 input pin of a group, connected to the same interrupt, is selected as interrupt input with pullup, all selected inputs are "AND" connected.
WARNING :
Read modify write instructions may clear interrupt flags of dedications unintentionally if the interrupt flag is
set after the read and before the write. Operations on control registers of dedications should be done with
sufficient timing distance to interrupt events.
2.1.5 Miscellaneous register( 0026h )
Read/Write
Reset Value: 0000 0000 ( 00h )
This register is a various 8-Bit register where only 3 bits are used for interrupt and slow mode.
– b6 = INTP: Interrupt Positive allows to select the I1 line triggering mode in conjunction with INTN. It can
only be modified when the I bit of the CCR is set.
– b5 = INTN: Interrupt Negative allows to select the I1 line triggering mode in conjunction with INTP. It can
only be modified when the I bit of the CCR is set.
– b1 = SM: Slow Mode. Setting this bit to "1" enables Slow Mode, thus reducing power consumption. In
this mode, an extra divider by 64 is added in the clock circuitry. In Halt Mode SM bit is automatically
reset.Registers of all RDS-Modules should not be accessed during slow mode.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 2. External Interrupt Options
INTP
INTN
I1 External Interrupt Options
0
0
Negative edge and Low level sensitive
0
1
Negative edge only
1
0
Positive edge only
1
1
Positive and negative edge sensitive
2.2 LCD controller/driver
The LCD module contains an LCD controller/driver with 20 segment and 16 backplane outputs able to
drive up to 20 x 16 = 320 segments. The LCD control logic reads automatically data from the LCD-RAM
independently from the ST72 core.
Two signals (LCF32K,LCSYNCHINOUT) can be activated on pins PC0, PC1 to connect a slave display
chip for expanding the number of segments. To activate these pins as LCF32K, LCSYNCHINOUT, bit0 of
register LCD Ctrl.2 (0027H) has to be set. During reset this bit is cleared.
VLCD must never be below VDD.
2.2.1 Address mapping of the picture elements
The LCD-RAM is located in the address region of the ST72 data space from address 40H - 7FH.
The LCD forms a matrix of 20 segment lines ( columns ) and 16 backplane lines ( rows ). Each bit of the
LCD-RAM is mapped to one dot of the LCD matrix according to fig. 1. If a bit is set, the corresponding LCD
segment is switched on, if it is reset, the segment is switched off.
After reset, the LCD-RAM is not initialized and contains arbitrary information. As the LCD control register
is cleared, the LCD is completely switched off.
In halt mode no clock for the LCD module is available from the main oscillator. The LCD module is
switched off in halt mode.
The input frequency of the LCD controller is fOSC/2 (4.275MHz).
A 32kHz stand by oscillator is not available. Therefore the mode FEXT (C5, C4, C3 = 001) of LCD control
register cannot be used.
In any case a missing LCD clock ( no oscillator active, broken crystal etc. ) is detected by a clock supervisor circuit which switches all segment and common lines to ground to avoid destructive DC levels at the
LCD.
If the LCD clock is not missing but far too slow (e.g. due to incorrect setting of C5, C4, C3 in LCD control
register) the LCD is switched off periodically. This situation has to be avoided.
A division factor of +256 is recommended for the prescaler (C5, C4, C3 = 110; fOUT = 16.699KHz). With
this setting of the predevider, frame frequencies of 132.2Hz, 66.1Hz, 44.1Hz and 33.1Hz can be generated.
The frequency out of the prescaler must not be below 15KHz in order not to switch off the display through
the LCD oscillator supervisor.
To activate segments and backplanes, data and option register bits of the corresponding combiport pins
have to be set to 1. During reset data and option register bits of combiports are set to 1.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2.2.2 External Divider Chain
The different display voltage levels are supplied by an external resistor chain as shown in fig. below.
Two different configurations with five or four display voltage levels can be chosen.
The resistors have to have a good matching within < 1% to avoid DC voltage levels on the liquid crystal
device.
DC levels trigger electrode reactions on the liquid crystal cell, deteriorating display quality rapidly.
Figure 3. External Divider Chain
VLCD
VLCD
R5
R4
C4
C3
VLCD45
VLCD45
R4
C3
R3
VLCD35
VLCD35
C2
R3
C2
VLCD25
VLCD25
R2
R2
C1
C1
VLCD15
VLCD15
R1
R1
GND
GND
ST6LCD3 4.DS4
C1 = C2 = C3 = C4 = 0.1 ... 0.3µF
R1 = R2 = R3 = R4 = R5 = 1 ... 200kΩ
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2.2.2.1 Working with 1/5 Bias
Figure 4. Waveform on common and on segment output working with 1/5 Bias
VLCD
VLCD
4/5
4/5
3/5
3/5
2/5
2/5
1/5
1/5
GND
GND
0
1
0
1
0
1
0
1
BACKPLANE OFF
BACKPLANE SELECTED
ST6LC352.DS4
VLCD
VLCD
4/5
4/5
3/5
3/5
2/5
2/5
1/5
1/5
GND
GND
0
1
0
1
0
SEGMENT SELECTED
1
0
1
SEGMENT OFF
ST6LC351.DS4
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ST7282A5 - ST7282B5 - ROM FROM EPROM
2.2.2.2 Working with 1/4 Bias
Depending on the selected display material, the
operating mode and the display voltage VLCD, it is
possible to reduce the LCD resistor chain to 4 resistors, and operate with the 1/4 bias method.
If VLCD35 and VLCD25 are connected to the
same voltage, the segment and backplane drivers
will work in the same way as with 1/5 bias, but the
resulting waveforms will look a bit different :
Figure 5. Waveform on common and on segment output working with Bias 1/4
VLCD
VLCD
4/5
4/5
3/5
3/5
2/5
2/5
1/5
1/5
GND
GND
0
1
0
1
0
SEGMENT SELECTED
1
0
1
SEGMENT OFF
ST6LC351.DS4
VLCD
VLCD
3/4
3/4
2/4
2/4
1/4
1/4
GND
GND
0
1
0
1
0
SEGMENT SELECTED
1
0
1
SEGMENT OFF
ST6LC362.DS4
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 6. Address Mapping of the LCD-RAM MUX16
BP1
bit0
BP2
bit1
BP3
bit2
BP4
bit3
BP5
bit4
BP6
bit5
BP7
bit6
BP8
bit7
BP1
bit0
BP2
bit1
BP3
bit2
BP4
bit3
BP5
bit4
BP6
bit5
BP7
bit6
BP8
bit7
ADRESSES
48
49
--
4F
50
--
--
--
--
5E
5F
40 ... 47
and 60 ... 67
not used
68
69
S
E
--
6F
70
--
7B
--
--
7E
7F
S
S
S
S
S
E
E
E
E
E
(SEG21 ... SEG24
G
G
G
G
G
G
are not available)
1
2
8
8
20
24
Figure 7. Address Mapping of the LCD-RAM MUX8
BP1
bit0
BP2
bit1
BP3
bit2
BP4
bit3
BP5
bit4
BP6
bit5
BP7
bit6
BP8
bit7
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40
41
--
47
48
49
--
--
--
--
5E
5F
ADRESSES
60 ... 7F
not used
S
S
S
S
S
S
E
E
E
E
E
E
(SEG21 ... SEG24
G
G
G
G
G
G
are not available)
-7
-6
0
1
2
24
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 8. Address Mapping of the LCD-RAM MUX4
BP1
bit0
BP2
bit1
BP3
bit2
BP4
bit3
ADRESS
ES
64 ... 7F
60
61
62
63
40
41
S
S
S
S
S
E
E
E
E
G
G
G
-11
-10
-9
--
--
--
--
5E
5
F
not used
(SEG21
... SEG24
47
48
49
S
S
S
S
S
E
E
E
E
E
E
G
G
G
G
G
G
G
-8
-7
-6
0
1
2
24
are not
available)
2.3 TIMER 4
16 bit autoreload timer with 2 capture inputs connected to PA0, PA1 (see spec. ST7TIM4). The in-
put clock of the timer is fosc divided by 2.
2.4 WATCHDOG
The WD2 is used to reset the ST7282 B5 after a
certain period of time in the range of 2.8 msec up
to 184 msec when fOSC = 8.55 MHz is used.
WD2 will be activated, if bit0 in Watchdog Reg.
(Adr. 12h) is set ("1"). Once WD2 is running, any
software access to bit0 in Watchdog Reg. will NOT
influence WD2. However, a RESET signal (either
externally or caused by WD2) will reset bit0 of
Watchdog Reg.
After a RESET, WD2 is deactivated and set to it's
longest period ( 184 msec for fOSC = 8.55 MHz ).
WD2 is able to produce a SW-Reset ( bit0 set to
"1", bit1 to "0" ).
Dedication address of WD2 is 12h .
If WD2 is enabled, any stop instruction will generate a reset. However, the use of a stop instruction
(HALT) is not recommended in this case.
2.5 I/O PORTS
Pins PD0 ... PD7, PE0 ... PE3, PF0 ... PF7, PG0 ...
PG7 and PH0 ... PH7 are of type LCIO.
Pins PA0 ... PA7, PB0 ... PB7 and PC0 ... PC7 are
of type IO3 and can also be used as analog inputs.
The interrupt outputs of PORT A, PORT B, PORT
C, PORT D, PORT E, PORT F, PORT G and
PORT H are anded and connected to the interrupt
input I1 of core ( start address FFFAH ). So every
port pin which is programmed as an input with interrupt enabled can generate an interrupt. If more
than one port pin is programmed as an interrupt input, overlapping interrupts cannot be detected due
to the AND function.
PA0, PA1 are also used as CP1, CP2 inputs of
TIMER 4.
The pins PA5 ... PA7 are also used by the serial
I/O ( see fig. 2 ). PA5 is connected with SCL (
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clock input ), PA6 is connected with SDA ( data input ) and PA7 is connected with DOUT ( data output ) of the SIO.
For serial input operation PA5 and PA6 have to be
programmed as inputs. For serial output PA7 has
to be programmed as open drain output ( DDR = 1,
OPR = 0 ). In this operation mode the output of the
SIO shift register instead of the port data register is
connected to the port buffer. When PA7 is programmed as push pull output
( DDR = 1, OPR
= 1 ), the port data register is connected to the port
buffer.
When the SIO pins are not used PA5 ... PA7 can
be used as any other I/O pin (PA7 not in open
drain output mode).
After reset ports PA0 ... PA7, PB0 ... PB7 and PC0
... PC6 are in input mode with pull up resistors
switched on and interrupt disabled.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
PA4 does not have a pull-up resistor.
Ports PD0 ... PD7, PE0 ... PE3, PF0 ... PF7, PG0
... PG7 and PH0 ... PH7 are in the "LCD Output
mode" (all pins switched to VSS).
PC7 is switched to analog input mode during reset
( data register and option register bits are set ).
PC0, PC1 may optionally be used to "cascade" the
LCD (refer to: 2. LCD CONTROLLER/DRIVER).
2.6 ADC
The reference voltage inputs of the ADC1N are
connected to VDDA, VSSA. Therefore special care
has to be taken to stabilize VDDA, VSSA and to
avoid switching of I/O pins during conversion. Analog inputs may be multiplexed from pins PA0 ...
PA7, PB0 ... PB7 and PC0 ... PC7. Up to 24 analog inputs can be multiplexed.
Selection of an analog input is done by programming the corresponding pin of a port as analog input ( DDR = 0, DR = 1, OPR = 1 ). Be sure that
only one port pin is programmed as analog input at
a time. Otherwise the analog sources are shorted
by the analog multiplexer. Conversion time for an
8.55 MHz clock is 34 µsec (i.e. 288 clocks + 0...6
clocks of fOSC) because the ADC is supplied with
a clock signal of fOSC : 6 that is also available dur-
ing WAIT. The ADC interrupt is connected to level
sensitive interrupt input I5 of the core ( start address FFF2H ). So the interrupt has to be cleared
before the interrupt service routine is left.
A stop instruction will stop the clock of the ADC
and will switch off its comparator to achieve minimum power consumption. This can also be done
by clearing bit 5 ( SC ) of ADC control register (
10H ).
A rising edge on EOC-bit sets the interrupt flipflop.
To remove the interrupt, a write operation to ADCControl register has to be executed, to clear the interrupt flipflop. After the reset, the interrupt flipflop
is also cleared.
2.7 SERIAL I/O
The 8 bit SIO generates an interrupt after the falling edge of the eight external clock pulse. The interrupt signals to the ST72 to read or write the SIO
via an 8 bit register ( adr. 26H ).
The SIO uses the input/output structure of Port A (
PA5 : SCL, PA6 : SDA, PA7 : DOUT ) (see fig. 2).
The 3 pins can be operated in the following ways:
directly by software, as an S-BUS, as an I2C-BUS
and as a standard SIO ( clock, data, enable ).
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To operate the SIO PA5 and PA6 have to be programmed as inputs, PA7 as open drain output.
The SIO interrupt ( active low ) is connected to the
interrupt input I3 of the core ( address FFF6H ).
After reset all ports are in input mode with pull up
resistors switched on and the SIO interrupt is disabled.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Figure 9. Peripheral Interface Configuration of Serial I/O
PP / OD
MUX
DOUT / PA7
0
1
OPR
DR
OUT
IN
SDA / PA6
SERIAL
I/O
DR
CLOCK
SCL / PA5
DR
INTERFA C.DS4
2.8 RAM
The RAM is located in the address range A0H3FFH.
300H-3FFH may be used as Stack area.
2.9 EEPROM
The 512 bytes EEPROM is located at addresses
0E00 - 0FFF. 2 cells of 256 bytes each or one cell
of 512 bytes may be used. EEPROM control register EECR (adr. 014H) is used to control the different operation modes of the range 0E00H - 0EFFH,
EEPROM control register EECR2 (adr. 015H) that
of range 0F00H - 0FFFH. Some of its bits are read
only, some are write only. So no single bit instructions are allowed.
To avoid destruction of data during power up or
down, the reset pin directly desactivates the
chargepump of EEPROM cells.
The EEPROM can be used for data storage only,
no program execution and no read modify write in-
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structions (single bit, increment, decrement) are
possible.
After bit E2LAT of EECR goes to low, there should
not be a read operation during the next 20 µsec.
A parallel programming mode for 8 bytes is available. No clear is needed before a write.
Two cells of 256 bytes are used, parallel programming of bytes in each cell is possible. This should
be avoided however, to keep software compatitility
between all future versions and ROM versions,
that have only one physical register, that will be
addressed through two different addresses 14H
and 15H.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
Before access to one area, also the control register of the other area should be checked and access done only, if both areas allow the required access.
SGS-THOMSON may implement a single or double register version in future ROM or EPROM versions.
EEAREA
0E00
Adr. 14H
Reg
0EFF
future
0E00
Reg
Adr. 15H
0F00
Adr. 15H
EEAREA
Adr. 14H
Reg
0FFF
0FFF
PADD.DS4
2.10 32K ROM
The 32K ROM is located at addresses 8000H-FFFFH.
16 bytes ( FFE0H - FFEFH ) are reserved for SGS-Thomson test vectors.
2.11 RDS
Modules ( see separate specs )
Registers of all RDS-Modules should not be accessed ( read or write ) during slow mode of CPU.
2.12 OSCILLATOR
The ST7 Oscillator allows operation with a crystal
or external input. The corresponding mode is defined by a metal option. In case of external input
the clock amplitude into OSCI may not be lower
then 50mV. The pin OSCO/STOP then is serving
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as output for the stop signal to synchronize with
external clock sources.
In the present version, the device works with a
dedicated crystal.
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ST7282A5 - ST7282B5 - ROM FROM EPROM
3 TESTING
Pin VPP/TEST is used for testing the device. For
normal operation pin VPP/TEST has to be connected to VSS or has to be left open. An internal
pull down resistor of about 100k is integrated to
select normal operation mode if pin VPP/TEST is
not connected.
The testmodes are for SGS THOMSON internal
use only!
4 PIN DESCRIPTION
4.1 Connection diagram
ST7
PB2/AIN
PB3/AIN
PB4/AIN
PB5/AIN
PB6/AIN
PB7/AIN
GND
VDD
GNDP
VDDP
PC0/LCF32K/AIN
PC1/LCSYNC/AIN
PC2/AIN
PC3/AIN
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
PB1/AIN
PC7/AIN
2
63
PB0/AIN
STOP/OSCOUT
3
62
PA7/DOUT/AIN
OSCIN
4
61
PA6/SDA/AIN
S16/PD7
5
60
PA5/SCL/AIN
S15/PD6
6
59
PA4/AIN
S14/PD5
7
58
PA3/AIN
S13/PD4
8
57
PA2/AIN
S12/PD3
9
56
PA1/CP2/AIN
S11/PD2
10
55
PA0/CP1/AIN
S10/PD1
11
54
RESET
S09/PD0
12
53
VSSA
VPP/TEST
13
52
VDDA
S8/PF7
14
51
RDSREF
S7/PF6
15
50
MPX
S6/PF5
16
49
RDSFIL
S5/PF4
17
48
PE5/S22
S4/PF3
18
47
RDSCOMP/PE4/S21
S3/PF2
19
46
S20/PE3
S2/PF1
20
45
S19/PE2
S1/PF0
21
44
S18/PE1
BP16/S-0/PG7
22
43
S17/PE0
BP15/S-1/PG6
23
42
VLCD1/5
BP14/S-2/PG5
24
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VLCD2/5
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VLCD4/5
VLCD
BP1/PH0
BP2/PH1
BP3/PH2
BP4/PH3
BP5/S-12/PH4
BP6/S-11/PH5
BP7/S-10/PH6
BP8/S-9/PH7
BP9/S-7/PG0
BP10/S-6/PG1
BP11/S-5/PG2
BP12/S-4/PG3
ST 7282 B5
VLCD3/5
PC6/AIN
BP13/S-3/PG4
Family
PC4/AIN
PC5/AIN
Figure 10. Connection Diagram ( top view ) for the 80 pin quad flat pack
CONDIAG.DS4
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ST7282A5 - ST7282B5 - ROM FROM EPROM
4.2 P I N
DESCRIPTION
Ports A, B, C, D, E, F, G are described on page 18
STOP/OSCOUT
Oscillator pins
STOP/OSCIN
VPP/TEST
Test pin
VLCD
VLCD 4/5
VLCD 3/5
Voltage levels for the LCD module
VLCD 2/5
VLCD 1/5
NC
(not connected) - must be left open
RDSCOMP
RDSFIL
MPX
I/O Pins for the RDS module (see seperate spec)
RDSREF
VSSA
Analog voltages for the ADC and filter module
VDDA
VDD
Supply voltage
GND
VDDP
Peripheral supply voltage
GNDP
Reset
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Reset pin - active low
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ST7282A5 - ST7282B5 - ROM FROM EPROM
5 RELATED DOCUMENTS
ST7 IO3 - SD 70K L136 ed. B
ST7 LCD4 - SD 70K L140 ed. B
ST7 TIM4 - SD 70K L130 ed. A
ST7 WD2 - SD 70K L137 ed. A
ST7 EEPROMeep2a
ST7 ADC2- SD 70K L138 ed. A
ST7 RDS BD - SD 70K L145 ed. B
ST7 RDS GB - SD 70K L144 ed. B
ST7 RDS FI - SD 70K L129 ed. C
ST7 SIO - # 96098 ed. B
ST7 OSCILLATOR - SD 70K L163 ed. A
ST7 LCIO1 - SD 70K L135 ed. C
6 HISTORIC
Below, the differences between the original specification # 96096 ed. B (ST7282B5) and the present
specification # 97115 ed. B:
Page # modified in
original spec 96096
Modifications
New page
1
Block diagram : S21, S22
2
2
Quick reference : 2 commercial products
3
VLCD changed from target of 10V to < 7V
3
3
LU on all pins changed from target of class A to class A on all pins except
pin VDDA (52) class C
Islow changed from target of 1mA to 2mA;
4
Ihalt changed from target of 10µA to 100µA ;
4-5
VLCD changed from target of 10V to 7V.
7
21
23
Address mapping : TIMER
7 - 8 - 9 - 10
EEPROM : 2 bank 256 bytes
19
Oscillator
20
Connection diagram : S21, S22
21
Related documents, sales types
23
7 ORDERING INFORMATION
SALES TYPE
OPTIONS
ST7282A5Q6B/XXX
NO LCD
ST7282B5Q6B/XXX
WITH LCD
TEMP RANGE
-40°C to 85°C
The user code to be delivered to SGS-THOMSON
must be in Motorola S.format (.S19) and must
PACKAGE
PQFP80
NOT include EEPROM content.
n
n
n
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