STMICROELECTRONICS STLC5464

STLC5464
MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED
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32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH
AUTOMATIC RESTART IN CASE OF TX
FRAME ABORT
32 RxHDLCs INCLUDING ADDRESS RECOGNITION
16 COMMAND/INDICATE CHANNELS (4 OR
6-BIT PRIMITIVE)
16 MONITOR CHANNELS PROCESSED IN
ACCORDANCE WITH GCI OR V*
DESCRIPTION
The STLC5464 is a Subscriber line interface card
controller for Central Office, Central Exchange,
NT2 and PBX capable of handling :
- 16 U Interfaces or
- 2 Megabits line interface cards or
- 16 SLICs (Plain Old Telephone Service) or
- Mixed analogue and digital Interfaces (SLICs or
U Interfaces) or
- 16 S Interfaces
- Switching Network with centralized processing
256 x 256 SWITCHING MATRIX WITHOUT
BLOCKING AND WITH TIME SLOT SEQUENCE INTEGRITY AND LOOPBACK PER
BIDIRECTIONAL CONNECTION
DMA CONTROLLER FOR 32 Tx CHANNELS
AND 32 Rx CHANNELS
HDLCs AND DMA CONTROLLER ARE CAPABLE OF HANDLING A MIX OF LAPD, LAPB,
SS7, CAS AND PROPRIETARY SIGNALLINGS
EXTERNAL SHARED MEMORY ACCESS BETWEEN DMA CONTROLLER AND MICROPROCESSOR
SINGLE MEMORY SHARED BETWEEN
n x MULTI-HDLCs AND SINGLE MICROPROCESSOR ALLOWS TO HANDLE n x 32
CHANNELS
BUS ARBITRATION
INTERFACE FOR VARIOUS 8,16 OR 32 BIT
MICROPROCESSORS
PQFP160
(Plastic Quad Flat Pack)
ORDER CODE : STLC5464
RAM CONTROLLER ALLOWS TO INTERFACE UP TO :
-16 MEGABYTES OF DYNAMIC RAM OR
-1 MEGABYTE OF STATIC RAM
INTERRUPT CONTROLLER TO STORE
AUTOMATICALLY EVENTS IN SHARED
MEMORY
PQFP160 PACKAGE
May 1997
1/83
STLC5464
CONTENTS
Page
I
PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
I.1
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
I.2
I.3
I.3.1
I.3.2
I.3.3
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
13
13
13
13
II
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
III
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
III.1
III.1.1
III.1.2
III.1.3
III.1.4
III.1.5
III.1.5.1
III.1.5.2
III.1.6
III.1.6.1
III.1.6.2
III.1.6.3
III.2
III.2.1
III.2.1.1
III.2.1.2
III.2.1.3
III.2.2
III.2.3
III.2.4
III.2.4.1
III.2.4.2
III.2.4.3
III.2.5
III.2.6
III.2.6.1
III.2.6.2
III.3
III.3.1
III.3.2
III.3.3
III.3.4
III.3.5
III.4
III.4.1
III.4.2
THE SWITCHING MATRIX N x 64 KBits/S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture of the Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Back Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delay through the Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sequence Integrity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Access to Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Access to Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Format of the HDLC Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Composition of an HDLC Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description and Functions of the HDLC Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSMA/CR Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time Slot Assigner Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Storage Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transparent Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command of the HDLC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I AND MONITOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCI and V* Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of the Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CI and Monitor Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CI and Monitor Transmission/Reception Command . . . . . . . . . . . . . . . . . . . . . . . . . . .
MICROPROCESSOR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of the Interface for the different microprocessors . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
15
17
17
17
21
21
21
21
21
21
21
21
23
23
24
24
24
24
24
26
26
26
26
26
26
27
27
27
27
28
28
28
2/83
STLC5464
CONTENTS (continued)
Page
III.5
III.5.1
III.5.2
III.5.3
III.5.4
III.5.4.1
III.5.4.2
III.5.5
III.5.5.1
III.5.5.2
III.5.5.3
III.6
III.7
III.7.1
III.7.2
III.8
III.8.1
III.8.2
III.8.3
III.8.4
III.8.5
III.9
MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Choice of memory versus microprocessor and capacity required . . . . . . . . . . . . . . . . .
Memory Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18K x n SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
512K x n SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
256K x n DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1M x n DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4M x n DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUS ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLOCK SELECTION AND TIME SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . .
Clock Distribution Selection and Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCXO Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERRUPT CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Interrupts (INT0 Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time Base Interrupts (INT1 Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Emergency Interrupts (WDO Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
32
32
32
32
32
33
33
33
34
34
34
35
35
35
35
35
35
36
III.10
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
IV
DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
V
CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
V.1
V.2
SYNCHRONIZATION SIGNALS DELIVERED BY THE SYSTEM . . . . . . . . . . . . . . . . .
TDM SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
V.3
GCI INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
V.4
V* INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
VI
MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
VI.1
VI.2
DYNAMIC MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STATIC MEMORIEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
44
VII
VII.1
MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST9 FAMILY MOD0=1, MOD1=0, MOD2=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
46
VII.2
80C188 MOD0=1, MOD1=1, MOD2=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
VII.3
VII.4
80C186 MOD0=1, MOD1=1, MOD2=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68000 MOD0=0, MOD1=0, MOD2=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
52
VII.5
TOKEN RING TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
VII.6
MASTER CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
3/83
STLC5464
CONTENTS (continued)
Page
VIII
VIII.1
INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDENTIFICATION AND DYNAMIC COMMAND REGISTER . . . . . . . . . . . IDCR (00)H
55
55
VIII.2
VIII.3
GENERAL CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCR (02)H
INPUT MULTIPLEX CONFIGURATION REGISTER 0 . . . . . . . . . . . . . . . IMCR0 (04)H
55
57
VIII.4
INPUT MULTIPLEX CONFIGURATION REGISTER 1 . . . . . . . . . . . . . . . IMCR1 (06)H
57
VIII.5
OUTPUT MULTIPLEX CONFIGURATION REGISTER 0 . . . . . . . . . . . . OMCR0 (08)H
57
VIII.6
VIII.7
OUTPUT MULTIPLEX CONFIGURATION REGISTER 1 . . . . . . . . . . . OMCR1 (0A)H
SWITCHING MATRIX CONFIGURATION REGISTER. . . . . . . . . . . . . . . SMCR (0C)H
58
58
VIII.8
CONNECTION MEMORY DATA REGISTER. . . . . . . . . . . . . . . . . . . . . . CMDR (0E)H
59
VIII.9
VIII.10
CONNECTION MEMORY ADDRESS REGISTER . . . . . . . . . . . . . . . . . . CMAR (10)H
SEQUENCE FAULT COUNTER REGISTER . . . . . . . . . . . . . . . . . . . . . . SFCR (12)H
60
61
VIII.11
TIME SLOT ASSIGNER ADDRESS REGISTER . . . . . . . . . . . . . . . . . . . TAAR (14)H
61
VIII.12
VIII.13
TIME SLOT ASSIGNER DATA REGISTER . . . . . . . . . . . . . . . . . . . . . . . TADR (16)H
HDLC TRANSMIT COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . HTCR (18)H
62
62
VIII.14
HDLC RECEIVE COMMAND REGISTER . . . . . . . . . . . . . . . . . . . . . . . . HRCR (1A)H
64
VIII.15
VIII.16
ADDRESS FIELD RECOGNITION ADDRESS REGISTER . . . . . . . . . . AFRAR (1C)H
ADDRESS FIELD RECOGNITION DATA REGISTER . . . . . . . . . . . . . . AFRDR (1E)H
65
66
VIII.17
FILL CHARACTER REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FCR (20)H
66
VIII.18
VIII.19
GCI CHANNELS DEFINITION REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . GCIR0 (22)H
GCI CHANNELS DEFINITION REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . GCIR1 (24)H
66
67
VIII.20
GCI CHANNELS DEFINITION REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . GCIR2 (26)H
67
VIII.21
VIII.22
GCI CHANNELS DEFINITION REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . GCIR3 (28)H
TRANSMIT COMMAND / INDICATE REGISTER. . . . . . . . . . . . . . . . . . . . TCIR (2A)H
67
68
VIII.23
TRANSMIT MONITOR ADDRESS REGISTER . . . . . . . . . . . . . . . . . . . . TMAR (2C)H
69
VIII.24
VIII.25
TRANSMIT MONITOR DATA REGISTER . . . . . . . . . . . . . . . . . . . . . . . . TMDR (2E)H
TRANSMIT MONITOR INTERRUPT REGISTER. . . . . . . . . . . . . . . . . . . . TMIR (30)H
70
70
VIII.26
MEMORY INTERFACE CONFIGURATION REGISTER . . . . . . . . . . . . . . MICR (32)H
70
VIII.27
VIII.28
INITIATE BLOCK ADDRESS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . IBAR (34)H
INTERRUPT QUEUE SIZE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . IQSR (36)H
72
72
VIII.29
INTERRUPT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IR (38)H
73
VIII.30
VIII.31
INTERRUPT MASK REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR (3A)H
TIME REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR (3C)H
74
74
VIII.32
TEST REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TR (3E)H
74
4/83
STLC5464
CONTENTS (continued)
Page
IX
IX.1
EXTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NITIALIZATION BLOCK IN EXTERNAL MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
75
IX.2
IX.2.1
IX.2.2
IX.2.3
IX.3
IX.3.1
IX.3.2
IX.3.3
IX.4
IX.5
IX.5.1
IX.5.2
IX.6
IX.6.1
IX.6.2
RECEIVE DESCRIPTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bits written by the Rx DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSMIT DESCRIPTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bits written by the Rx DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE & TRANSMIT HDLC FRAME INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE COMMAND / INDICATE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Command / Indicate Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Command / Indicate Interrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE MONITOR INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Monitor Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Monitor Interrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
76
76
76
77
77
78
78
78
79
79
80
80
80
81
X
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
5/83
STLC5464
LIST OF FIGURES
Page
I
PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
II
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Figure 1
: General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Switching Matrix Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unidirectional and Bidirectional Connections . . . . . . . . . . . . . . . . . . . . . .
Loop Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Variable Delay through the matrix with ITDM = 1 . . . . . . . . . . . . . . . . . . .
Variable Delay through the matrix with ITDM = 0 . . . . . . . . . . . . . . . . . . .
Constant Delay through the matrix with SI = 1 . . . . . . . . . . . . . . . . . . . . .
HDLC and DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Structure of the Receive Circular Queue . . . . . . . . . . . . . . . . . . . . . . . . .
Structure of the Transmit Circular Queue . . . . . . . . . . . . . . . . . . . . . . . . .
D, C/I and Monitor Channel Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-HDLC connected to µP with multiplexed buses . . . . . . . . . . . . . . . .
Multi-HDLC connected to µP with non-multiplexed buses . . . . . . . . . . . .
Microprocessor Interface for INTEL 80C188 . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface for INTEL 80C186 . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface for MOTOROLA 68000 . . . . . . . . . . . . . . . . . . .
Microprocessor Interface for ST9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . .
512K x 8 SRAM Circuit Memory Organization . . . . . . . . . . . . . . . . . . . . .
256K x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . .
1M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4M x 16 DRAM Circuit Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chain of n Multi-HDLC Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MHDLC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCXO Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Three Circular Interrupt Memories . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
17
18
19
20
22
25
25
28
29
29
29
29
30
30
32
32
32
33
33
33
34
35
36
IV
DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
V
CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Clocks received and delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . .
Synchronization Signals received by the Multi-HDLC . . . . . . . . . . . . . . . .
GCI Synchro Signal delivered by the Multi-HDLC . . . . . . . . . . . . . . . . . . .
V* Synchronization Signal delivered by the Multi-HDLC . . . . . . . . . . . . . .
38
39
40
41
MEMORY TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Dynamic Memory Read Signals from the Multi-HDLC . . . . . . . . . . . . . . .
Dynamic Memory Write Signals from the Multi-HDLC . . . . . . . . . . . . . . .
Static Memory Read Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . .
Static Memory Write Signals from the Multi-HDLC . . . . . . . . . . . . . . . . . .
42
43
44
45
III
Figure 27
Figure 28
Figure 29
Figure 30
VI
Figure 31
Figure 32
Figure 33
Figure 34
6/83
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
STLC5464
LIST OF FIGURES (continued)
Page
VII
MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35 : ST9 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 36 : ST9 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 37 : 80C188 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 38 : 80C188 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 39 : 80C186 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 40 : 80C186 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 41 : 68000 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 42 : 68000 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 43 : Token Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 44 : Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
46
47
48
49
50
51
52
53
54
54
VIII
INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
IX
EXTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
X
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
7/83
STLC5464
I - PIN INFORMATION
DM0
ADM14
ADM13
ADM12
ADM11
ADM10
VSS
VDD
ADM9
ADM8
ADM7
ADM6
ADM5
ADM4
ADM3
ADM2
ADM1
ADM0
VSS
VDD
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
D2
93
29
VDD
D1
92
30
VSS
D0
91
31
DOUT0
VSS
90
32
DOUT1
VDD
89
33
DOUT2
A23/ADM18
88
34
DOUT3
A22/ADM17
87
35
DOUT4
A21/ADM16
86
36
DOUT5
A20/ADM15
85
37
DOUT6
A19
84
38
DOUT7
A18
83
39
NDIS
A17
82
40
NTRST
A16
81
8/83
80
DIN8
A15/AD15
94
28
79
D3
A14/AD14
DIN7
78
95
27
A13/AD13
D4
77
DIN6
A12/AD12
96
26
76
D5
A11/AD11
DIN5
75
97
25
A10/AD10
98
D6
74
D7
DIN4
VSS
DIN3
24
73
23
VDD
99
72
D8
A9/AD9
DIN2
71
100
22
A8/AD8
D9
70
DIN1
A7/AD7
101
21
69
D10
A6/AD6
DIN0
68
102
20
A5/AD5
D11
67
PSS
A4/AD4
103
19
66
D12
A3/AD3
FSCV
65
104
18
A2/AD2
D13
64
FSCG
A1/AD1
105
17
63
D14
A0/AD0
FS
62
106
16
VSS
D15
61
VSS
VDD
107
15
60
VDD
MOD2
VDD
59
108
14
MOD1
VSS
58
FRAMEB
57
109
13
MOD0
TRI
NDS/NRD
FRAMEA
56
110
12
R/W / NWR
TRO
55
CLOCKB
NAS/ALE
111
11
54
NWE
READY
CLOCKA
53
112
10
NDTACK
NOE
52
DCLK
NBHE/NUDS
113
9
51
NRAS0/NCE0
NLDS
VCXO OUT
50
114
8
INT1
NCAS0/NCE1
49
VCXO IN
INT0
115
7
48
NRAS1/NCE2
NCS1
EC
47
116
6
NCS0
NCAS1/NCE3
46
CB
VSS
117
5
45
NRAS2/NCE4
44
WDO
VDD
118
4
TCK
NCE5
43
XTAL2
TDO
119
3
42
120
NRAS3/NCE6
41
NCE7
XTAL1
TDI
NRESET
2
TMS
1
5464-01.EPS
DM1
140
DM5
147
DM2
DM6
148
141
DM7
149
DM3
DM8
150
142
DM9
151
DM4
DM10
152
143
DM11
153
144
DM12
154
VSS
DM13
155
VDD
DM14
156
145
DM15
157
146
VSS
VDD
158
NTEST
159
160
I.1 - Pin Connections
STLC5464
I - PIN INFORMATION (continued)
I.2 - Pin Description
Pin N°
Symbol
Type
Function
POWER PINS (all the power and ground pins must be connected)
14
VDD1
Power
DC supply
15
VSS1
Ground
DC ground
29
VDD2
Power
DC supply
30
VSS2
Ground
DC ground
45
VDD3
Power
DC supply
46
VSS3
Ground
DC ground
61
VDD4
Power
DC supply
62
VSS4
Ground
DC ground
73
VDD5
Power
DC supply
74
VSS5
Ground
DC ground
89
VDD6
Power
DC supply
DC ground
90
VSS6
Ground
107
VDD7
Power
DC supply
108
VSS7
Ground
DC ground
121
VDD8
Power
DC supply
DC ground
122
VSS8
Ground
133
VDD9
Power
DC supply
134
VSS9
Ground
DC ground
145
VDD10
Power
DC supply
146
VSS10
Ground
DC ground
158
VDD11
Power
DC supply
159
VSS11
Ground
DC ground (Total 22)
2
XTAL1
I
Crystal 1. A clock pulse at fMin. = 32000kHz can be applied to this input (or one pin
of two crystal pins) with : -50.10-6 < ∆f < +50.10-6.
3
XTAL2
O
Crystal 2. If the internal crystal oscillator is used, the second crystal pin is applied
to this output.
7
VCXO IN
O4
VCXO input signal. This signal is compared to clock A(or B) selected inside the
Multi-HDLC.
8
VCXO OUT
I3
VCXO error signal. This pin delivers the result of the comparison.
10
CLOCKA
I3
Input Clock A (4096kHz or 8192kHz)
CLOCKS
11
CLOCKB
I3
Input Clock B (4096kHz or 8192kHz)
12
FRAMEA
I3
Clock A at 8kHz
13
FRAMEB
O8
Clock B at 8kHz
9
DCLK
O8
Data Clock issued from Input Clock A (or B). This clock is delivered by the circuit
at 4096kHz (or 2048kHz). DOUT0/7 are transmitted on the rising edge of thissignal.
DIN0/7 are sampled on the falling edge of this signal.
17
FSCG
O8
Frame synchronization for GCI at 8kHz. This clock is issued from FRAME A (or B).
18
FSCV*
I3
Frame synchronization for V Star at 8kHz
16
FS
O8
Frame synchronization.This signal synchronizes DIN0/7 and DOUT0/7.
19
PSS
I3
Programmable synchronization Signal. The PS bit of connection memory is read
in real time.
Type : I1 = Input TTL ;
I2 = I1 + Pull-up ;
O4 = Output CMOS 4mA ;
O4T = O4 + Tristate ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = Output CMOS 8mA, Tristate
I3 = I1 + Hysteresis ;
I4 = I3 + Pull-up ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate ;
9/83
STLC5464
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
TIME DIVISION MULTIPLEXES (TDM)
20
DIN0
I1
TDM0 Data Input 0
21
DIN1
I1
TDM1 Data Input 1
22
DIN2
I1
TDM2 Data Input 2
23
DIN3
I1
TDM3 Data Input 3
24
DIN4
I1
TDM4 Data Input 4
25
DIN5
I1
TDM5 Data Input 5
26
DIN6
I1
TDM6 Data Input 6
27
DIN7
I1
TDM7 Data Input 7
TDM8 Data Input 8
28
DIN8
I1
31
DOUT0
O8DT
TDM0 Data Output 0
32
DOUT1
O8DT
TDM1 Data Output 1
33
DOUT2
O8DT
TDM2 Data Output 2
34
DOUT3
O8DT
TDM3 Data Output 3
35
DOUT4
O8DT
TDM4 Data Output 4
36
DOUT5
O8DT
TDM5 Data Output 5
37
DOUT6
O8DT
TDM6 Data Output 6
38
DOUT7
O8DT
39
NDIS
I1
5
CB
O8D
6
EC
I1
Echo. Wired at VSS if not used.
I4
Reset for boundary scan
TDM7 Data Output 7
DOUT 0/7 Not Disable. When this pin is at 0V, the Data Output 0/7 are at high
impedance. Wired at VDD if not used.
Contention Bus for CSMA/CR
BOUDARY SCAN
40
NTRST
41
TMS
I2
Mode Selection for boundary scan
42
TDI
I2
Input Data for boundary scan
43
TDO
O4
Output Data for boundary scan
44
TCK
I4
Clock for boundary scan
MICROPROCESSOR INTERFACE
58
MOD0
I1
1101
59
MOD1
I1
1100
60
MOD2
I1
0110
1
NRESET
I3
Circuit Reset
47
NCS0
I3
Chip Select 0 : internal registers are selected
48
NCS1
I3
Chip Select 1 : external memory is selected
49
INT0
O4
Interrupt generated by HDLC, RxC/I or RxMON. Active high.
50
INT1
O4
Interrupt1.This pin goes to 5V when the selected clock A (or B) has disappeared ;
250µs after reset this pin goes to 5V also if clock A is not present.
4
WDO
O4
Watch Dog Output.This pin goes to 5V during 1ms when the microprocessor has not
reset the Watch Dog during the programmable time.
80C188 80C186 68000 ST9
Type : I1 = Input TTL ;
I2 = I1 + Pull-up ;
O4 = Output CMOS 4mA ;
O4T = O4 + Tristate ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = Output CMOS 8mA, Tristate
10/83
I3 = I1 + Hysteresis ;
I4 = I3 + Pull-up ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate ;
STLC5464
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
MICROPROCESSOR INTERFACE (continued)
51
NLDS
I3
Lower Data Strobe (68000)
52
NUDS
I3
Bus High Enable (Intel) / Upper Data Strobe (68000)
53
NDTACK
O8D
Data Transfer Acknowledge (68000)
54
READY
O8T
Data Transfer Acknowledge (Intel)
55
NAS/ALE
I3
Address Strobe(Motorola) / Addresss Latch Enable(Intel)
56
R/W / NWR
I3
Read/Write (Motorola) / Write(Intel)
57
NDS/NRD
I3
Data Strobe (Motorola) /Read Data (Intel)
63
A0/AD0
I/O
Address bit 0 (Motorola) / Address/Data bit 0 (Intel)
64
A1/AD1
I/O
Address bit 1 (Motorola) / Address/Data bit 1 (Intel)
65
A2/AD2
I/O
Address bit 2 (Motorola) / Address/Data bit 2 (Intel)
66
A3/AD3
I/O
Address bit 3 (Motorola) / Address/Data bit 3 (Intel)
67
A4/AD4
I/O
Address bit 4 (Motorola) / Address/Data bit 4 (Intel)
68
A5/AD5
I/O
Address bit 5 (Motorola) / Address/Data bit 5 (Intel)
69
A6/AD6
I/O
Address bit 6 (Motorola) / Address/Data bit 6 (Intel)
70
A7/AD7
I/O
Address bit 7 (Motorola) / Address/Data bit 7 (Intel)
71
A8/AD8
I/O
Address bit 8 (Motorola) / Address/Data bit 8 (Intel)
72
A9/AD9
I/O
Address bit 9 (Motorola) / Address/Data bit 9 (Intel)
75
A10/AD10
I/O
Address bit 10 (Motorola) / Address/Data bit 10 (Intel)
76
A11/AD11
I/O
Address bit 11 (Motorola) / Address/Data bit 11 (Intel)
77
A12/AD12
I/O
Address bit 12 (Motorola) / Address/Data bit 12 (Intel)
78
A13/AD13
I/O
Address bit 13 (Motorola) / Address/Data bit 13 (Intel)
79
A14/AD14
I/O
Address bit14 (Motorola) / Address/Data bit 14 (Intel)
80
A15/AD15
I/O
Address bit15 (Motorola) / Address/Data bit 15 (Intel)
81
A16
I1
Address bit16 (Motorola) / Address bit 16 (Intel)
82
A17
I1
Address bit17 (Motorola) / Address bit 17 (Intel)
83
A18
I1
Address bit18 (Motorola) / Address bit 18 (Intel)
84
A19
I1
Address bit19 (Motorola) / Address bit 19 (Intel)
85
A20/ADM15
I/O
Address bit 20 from µP (input) / Address bit 15 for SRAM (output)
86
A21/ADM16
I/O
Address bit 21 from µP (input) / Address bit 16 for SRAM (output)
87
A22/ADM17
I/O
Address bit 22 from µP (input) / Address bit 17 for SRAM (output)
88
A23/ADM18
I/O
Address bit 23 from µP (input) / Address bit 18 for SRAM (output)
91
DO
I/O
Data bit 0 for µP if not multiplexed (see Note 1).
92
D1
I/O
Data bit 1 for µP if not multiplexed
93
D2
I/O
Data bit 2 for µP if not multiplexed
94
D3
I/O
Data bit 3 for µP if not multiplexed
95
D4
I/O
Data bit 4 for µP if not multiplexed
96
D5
I/O
Data bit 5 for µP if not multiplexed
97
D6
I/O
Data bit 6 for µP if not multiplexed
98
D7
I/O
Data bit 7 for µP if not multiplexed
99
D8
I/O
Data bit 8 for µP if not multiplexed
Type : I1 = Input TTL ;
I2 = I1 + Pull-up ;
O4 = Output CMOS 4mA ;
O4T = O4 + Tristate ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = Output CMOS 8mA, Tristate
I3 = I1 + Hysteresis ;
I4 = I3 + Pull-up ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate ;
11/83
STLC5464
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
MICROPROCESSOR INTERFACE (continued)
100
D9
I/O
Data bit 9 for µP if not multiplexed
101
D10
I/O
Data bit 10 for µP if not multiplexed
102
D11
I/O
Data bit 11 for µP if not multiplexed
103
D12
I/O
Data bit 12 for µP if not multiplexed
104
D13
I/O
Data bit 13 for µP if not multiplexed
105
D14
I/O
Data bit 14 for µP if not multiplexed
106
D15
I/O
Data bit 15 for µP if not multiplexed
Token Ring Input (for use Multi-HDLCs in cascade)
MEMORY INTERFACE
109
TRI
I3
110
TRO
O4
111
NWE
O4T
Write Enable for memory circuits
112
NOE
O4T
Control Output Enable for memory circuits
113
NRAS0/NCE0
O4T
Row Address Strobe Bank 0 / Chip Enable 0 for SRAM
114
NCAS0/NCE1
O4T
Column Address Strobe Bank 0 / Chip Enable1 for SRAM
115
NRAS1/NCE2
O4T
Row Address Strobe Bank 1 / Chip Enable 2 for SRAM
116
NCAS1/NCE3
O4T
Column Address Strobe Bank 1 / Chip Enable 3 for SRAM
117
NRAS2/NCE4
O4T
Row Address Strobe Bank 2 / Chip Enable 4 for SRAM
118
NCE5
O4T
Chip Enable 5 for SRAM
119
NRAS3/NCE6
O4T
Row Address Strobe Bank 3 / Chip Enable 6 for SRAM
120
NCE7
O4T
Chip Enable 7 for SRAM
123
ADM0
O8T
Address bit 0 for SRAM and DRAM
124
ADM1
O8T
Address bit 1 for SRAM and DRAM
125
ADM2
O8T
Address bit 2 for SRAM and DRAM
126
ADM3
O8T
Address bit 3 for SRAM and DRAM
127
ADM4
O8T
Address bit 4 for SRAM and DRAM
128
ADM5
O8T
Address bit 5 for SRAM and DRAM
129
ADM6
O8T
Address bit 6 for SRAM and DRAM
130
ADM7
O8T
Address bit 7 for SRAM and DRAM
131
ADM8
O8T
Address bit 8 for SRAM and DRAM
132
ADM9
O8T
Address bit 9 for SRAM and DRAM
135
ADM10
O8T
Address bit 10 for SRAM and DRAM
136
ADM11
O8T
Address bit 11 for SRAM only
137
ADM12
O8T
Address bit 12 for SRAM only
138
ADM13
O8T
Address bit 13 for SRAM only
139
ADM14
O8T
Address bit 14 for SRAM only
Token Ring Output (for use Multi-HDLCs in cascade)
Type : I1 = Input TTL ;
I2 = I1 + Pull-up ;
O4 = Output CMOS 4mA ;
O4T = O4 + Tristate ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = Output CMOS 8mA, Tristate
12/83
I3 = I1 + Hysteresis ;
I4 = I3 + Pull-up ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate ;
STLC5464
I - PIN INFORMATION (continued)
I.2 - Pin Description (continued)
Pin N°
Symbol
Type
Function
MEMORY INTERFACE (continued)
140
DM0
I/O
Memory Data bit 0
141
DM1
I/O
Memory Data bit 1
142
DM2
I/O
Memory Data bit 2
143
DM3
I/O
Memory Data bit 3
144
DM4
I/O
Memory Data bit 4
147
DM5
I/O
Memory Data bit 5
148
DM6
I/O
Memory Data bit 6
149
DM7
I/O
Memory Data bit 7
150
DM8
I/O
Memory Data bit 8
151
DM9
I/O
Memory Data bit 9
152
DM10
I/O
Memory Data bit 10
153
DM11
I/O
Memory Data bit 11
154
DM12
I/O
Memory Data bit 12
155
DM13
I/O
Memory Data bit 13
156
DM14
I/O
Memory Data bit 14
157
DM15
I/O
Memory Data bit 15
160
NTEST
I2
Test Control. When this pin is at 0V each output is high impedance except XTAL2 Pin.
Type : I1 = Input TTL ;
I2 = I1 + Pull-up ;
O4 = Output CMOS 4mA ;
O4T = O4 + Tristate ;
O8D = Output CMOS 8mA, Open Drain ;
O8T = Output CMOS 8mA, Tristate
I3 = I1 + Hysteresis ;
I4 = I3 + Pull-up ;
O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ;
O8DT = Output CMOS 8mA, Open Drain or Tristate ;
Note : D0/15 input/output pins must be connected to one single external pull up resistor if not used.
I.3 - Pin Definition
I.3.1 - Input Pin Definition
I1
: Input 1 TTL
I2
: Input 2 TTL + pull-up
I3
: Input 3 TTL + hysteresis
I4
: Input 4 TTL + hysteresis +pull-up
I.3.2 - Output Pin Definition
O4
: Output CMOS 4mA
O4T : Output CMOS 4mA, Tristate
O8
: Output CMOS 8mA
O8T : Output CMOS 8mA,Tristate
O8D : Output CMOS 8mA,Open Drain
O8DT : Output CMOS 8mA,Open Drain or Tristate (Programmable pin)
Moreover, each output is high impedance when the NTEST Pin is at 0 volt except XTAL2 Pin.
I.3.3 - Input/Output Pin Definition
I/O : Input TTL/ Output CMOS 8mA.
N.B. XTAL1 : this input is CMOS.
XTAL2 : NTEST pin at 0 has no effect on this pin.
13/83
STLC5464
II - BLOCK DIAGRAM
The top level functionalities of Multi-HDLC appear on the general block diagram.
0
1
2
3
4
5
6
GCI1
GCI0
DIN6 26
DIN7 27
SWITCHING MATRIX
n x 64 kb/s
Pseudo
Random
Sequence
Analyser
7
DOUT6
DOUT7
FRAME B
CLOCK B
36
37
38 12 10 13
11
GCI0
Pseudo
Random
Sequence
Generator
CLOCK A
DOUT5
35
0
1
2
3
4
5
6
7
FRAME A
DOUT4
32 33 34
DOUT2
DOUT3
39 31
25 24 23 22 21 20
DOUT1
DOUT0
NDIS
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
Figure 1 : General Block Diagram
GCI1
V10
CLOCK
SELECTION
18 FSCV*
17 FSCG
To
Internal
Circuit
D7
9
DCLK
16 FS
DIN8 28
5
CB
6
EC
V10
TIME SLOT ASSIGNER FOR MULTIHDLC
7
8
XTAL1
2
GCI CHANNEL DEFINITION
COUNTER
XTAL
XTAL2
3
WDO
4
µP Bus
WATCHDOG
µP
INTERFACE
32 Rx HDLC
with Adress
Recognition
32 Rx DMAC
32 Tx HDLC
with CSMA CR
for Content. Bus
16 Rx
C/I
16 Rx
MON
16 Tx
C/I
16 Tx
MON
32 Tx DMAC
Rx
C/I
Rx
MON
Tx
C/I
Tx
MON
49 INT0
INTERRUPT
CONTROLLER
50 INT1
RAM
INTERFACE
Internal Bus
RAM
Bus
BUS ARBITRATION
STLC5464
There are :
- The switching matrix,
- The time slot assigner,
- The 32 HDLC transmitters with associated DMA
controllers,
- The 32 HDLC receivers with associated DMA
controllers,
- The 16 Command/Indicate and Monitor Channel
transmitters belonging to two General Component Interfaces(GCI),
14/83
- The 16 Command/Indicate and Monitor Channel
receivers belonging to two General Component
Interfaces (GCI),
- The memory interface,
- The microprocessor interface,
- The bus arbitration,
- The clock selection and time synchronization
function,
- The interrupt controller,
- The watchdog,
5464-02.EPS
VCX IN
VCX OUT
STLC5464
III - FUNCTIONAL DESCRIPTION
III.1 - The Switching Matrix N x 64 KBits/S
III.1.1 - Function Description
The matrix performs a non-blocking switch of 256
time slots from 8 Input Time Division Multiplex
(TDM) at 2 Mbit/s to 8 output Time Division Multiplex. A TDM is composed of 32 Time Slots (TS) at
64 kbit/s. The matrix is designed to switch a 64
kbit/s channel (Variable delay mode) or an hyperchannel of data (Sequence integrity mode). So, it
will both provide minimum throughput switching
delay for voice applications and time slot sequence
integrity for data applications on a per channel
basis.
The requirements of the Sequence Integrity (n*64
kbit/s) mode are the following:
All the time slots of a given input frame must be put
out during a same output frame.
The time slots of an hyperchannel (concatenation
of TS in the same TDM) are not crossed together
at output in different frames.
In variable delay mode, the time slot is put out as
soon as possible. (The delay is two or three time
slots minimum between input and output).
For test facilities, any time slot of an Output TDM
(OTDM) can be internally looped back into the
same Input TDM number (ITDM) at the same time
slot number.
A Pseudo Random Sequence Generator and a
Pseudo Random Sequence Analyzer are implemented in the matrix. They allow the generation a
sequence on a channel or on a hyperchannel, to
analyse it and verify its integrity after several
switching in the matrix or some passing of the
sequence across different boards.
The Frame Signal (FS) synchronises ITDM and
OTDM but a programmable delay or advance can
be introducedseparatelyon each ITDM and OTDM
(a half bit time, a bit time or two bit times).
An additional pin (PSS) permits the generation of
a programmable signal composed of 256 bits per
frame at a bit rate of 2048 kbit/s.
An external pin (NDIS) asserts a high impedance
on all the TDM outputs of the matrix when active
(during the initialization of the board for example).
III.1.2 - Architecture of the Matrix
The matrix is essentially composed of buffer data
memories and a connection memory.
The received serial data is first convertedto parallel
by a serial to parallelconverterand stored consecutively in a 256 position Buffer Data Memory (see
Figure 2 on Page 16).
To satisfy the Sequence Integrity (n*64 kbit/s) requirements, the data memory is built with an even
memory, an odd memory and an output memory.
Two consecutive frames are stored alternatively in
the odd and even memory. During the time an input
frame is stored, the one previously stored is transferred into the output memory according to the
connectionmemoryswitching orders. Aframe later,
the output memory is read and data is convertedto
serial and transferred to the output TDM.
III.1.3 - Connection Function
Two types of connections are offered :
- unidirectional connection and
- bidirectional connection.
An unidirectionalconnectionmakes only the switch
of an input time slot through an output one whereas
a bidirectionalconnectionestablishesthe link in the
other direction too. So a double connection can be
achieved by a single command (see Figure 3 on
Page 17).
III.1.4 - Loop Back Function
Any time slot of an Output TDM can be internally
looped back on the time slot which has the same
TDM number and the same TS number
(OTDMi, TSj) ----> (ITDMi, TSj).
In the case of a bidirectional connection, only the
one specified by the microprocessor is concerned
by the loop back (see Figure 4 on Page 17).
15/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 2 : Switching Matrix Data Path
PRSG : Pseudo Random Sequence Generator
From Connection
PRSA : Pseudo Random Sequence Analyzer
Memory
OTSV : Output Time Slot Validated
INS : Insert
DIN 0/7
CM : Connection Memory (from CMAR Register)
BIT SYNCHRO
D7
Tx
HDLC
DIN’ 0/7
HDLCM
D4/5
ME : Message Enable
IMTD : Increased Min Throughtput Delay
SGV : Sequence Generator Validated
SAV : Sequence Analyzer Validated
Rx
GCI
From SMCR Register
1
PRSG
SGV
1
LOOP
1
PSEUDO RANDOM
SEQUENCE
GENERATOR
211 - 1
Rec. O.152
S/P
1
DATA
MEMORIES
IMTD
CM
(when Read)
A
D
CONNECTION
MEMORY
D
Sequence Integrity,
LOOP, PRSA, PRSG,
INS, OTSV
64kb/s and
n x 64kb/s
Sequence
Integrity
Internal
Bus
CM
CMDR
Data
Register
1
CMAR
INS
1
PRSG
ME
GCIR
SAV
PSEUDO RANDOM
SEQUENCE
ANALYZER
211 - 1
Rec. O.152
1
P/ S
Tx
GCI
PRSA
D4/5
D7
Rx
HDLC
Address
Register
SFDR
Sequence Fault
Counter Register
1
D0/7
BIT SYNCHRO
From Connection Memory
OTSV (per channel)
From Disable Pin
(for all multiplexes)
DOUT 0/7
16/83
5464-03.EPS
From OMCR Register
OMV (per multiplex)
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 3 : Unidirectional and Bidirectional Connections
OTSy, OTDMq
ITSx,ITDMp
DATA
MEMORY
n x 64kb/s
DOWN STREAM
DOWN STREAM
Unidirectional Connection
ITSx,ITDMp
DATA
MEMORY
n x 64kb/s
DOWN STREAM
ITSy, ITDMq
DOWN STREAM
OTSx, OTDMp
DATA
MEMORY
n x 64kb/s
UP STREAM
UP STREAM
Bidirectional Connection
5464-04.EPS
OTSy, OTDMq
p, q = 0 to 7
x, y = 0 to 31
Figure 4 : Loop Back
OTSV
OTSy, OTDMq
DOWN STREAM
ITSy, ITDMq
DATA
MEMORY
n x 64kb/s
DATA
MEMORY
n x 64kb/s
ITSx,ITDMp
DOWN STREAM
OTSx, OTDMp
UP STREAM
Loop
Loopback per channel relevant if bidirectional connection has been done.
III.1.5 - Delay through the Matrix
III.1.5.1 - Variable Delay Mode
In the variable delay mode, the delay through the
matrix dependson the relative positionsof the input
and output time slots in the frame.
So, some limits are fixed :
- the maximum delay is a frame + 2 time slots,
- the minimum delay is programmable.
Three time slots if IMTD = 1, in this case n = 2 in
the formula hereafter or two time slots if
IMTD = 0, in this case n = 1 in the same formula
(see Paragraph ”Switching Matrix Configuration
Reg SMCR (0C)H” on Page 60).
All the possibilities can be ranked in three cases :
a) If OTSy > ITSx + n then the variable delay is :
OTSy - ITSx Time slots
5464-05.EPS
UP STREAM
p, q = 0 to 7
x, y = 0 to 31
b) If ITSx < OTSy < ITSx + n then the variable delay
is :
OTSy - ITSx + 32 Time slots
c) OTSy < ITSx then the variable delay is :
32 - (ITSx - OTSy) Time slots.
N.B. Rule b) and rule c) are identical.
For n = 1 and n = 2, see Figure 5 on Page 18.
III.1.5.2 - Sequence Integrity Mode
In the sequence integrity mode (SI = 1, bit located
in the Connection Memory), the input time slots are
put out 2 frames later (see Figure 6 on Page 19).
In this case, the delay is definedby a singleexpression :
Constant Delay = (32 - ITSx) + 32 + OTSy
So, the delay in sequence integrity mode varies
from 33 to 95 time slots.
17/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 5 : Variable Delay through the matrix with ITDM = 1
1) Ca s e : If OTS y > ITS x + 2, the n Va ria ble De la y is : OTS y - ITSx Time S lots
F ra me n
Inpu t
Fra m e
ITS0
Outpu t
Fra m e
OTS 0
ITS x ITS x+1 ITSx+2
Fra me n + 1
ITS31 ITS0
ITS 31
y>x+2
OTS 31
OTS y
Variable De lay
(OTS y - ITSx)
2) Ca s e : If ITS x ≤ OTS y ≤ ITS x + 2, the n Variab le De la y is : O TS y - ITS x + 32 Tim eS lots
F ra me n
Fra me n + 1
Inpu t
Fra m e
ITS0
Outpu t
Fra m e
OTS 0
ITS x ITS x+1 ITSx+2
ITS31 ITS0
ITSx
ITS 31
x≤y≤x+2
OTS 31
OTS y
OTS y
32 Time S lots
Va riable De lay : OTS y - ITSx + 32 Time S lots
3) Ca s e : If OTS y < ITS x, the n Va ria ble De lay is : 32 - (ITSx - OTS y) Tim eS lots
F ra me n
Inpu t
Fra m e
ITS0
Outpu t
Fra m e
OTS 0
ITS x
Fra me n + 1
ITS x
ITS31 ITS0
ITS 31
y<x
OTS 31
Variable De lay : 32 - (ITSx - OTS y) Time S lots
32 TimeS lots
18/83
OTS y
5464-06.EPS
OTS y
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 6 : Variable Delay through the matrix with ITDM = 0
1) Case : If OTSy > ITSx + 1, then Variable Delay is : OTSy - ITSx TimeSlots
Frame n
Input
Frame
ITS0
Output
Frame
OTS0
ITSx ITSx+1 ITSx+2
Frame n + 1
ITS31 ITS0
ITS31
y>x+1
OTS31
Variable Delay
OTSy
(OTSy - ITSx)
2) Case : If ITSx ≤ OTSy ≤ ITSx + 1, then Variable Delay is : OTSy - ITSx + 32 TimeSlots
Frame n
Frame n + 1
Input
Frame
ITS0
Output
Frame
OTS0
ITSx ITSx+1 ITSx+2
ITS31 ITS0
ITS31
ITSx
x ≤ y≤ x +1
OTS31
OTSy
32 TimeSlots
OTSy
Variable Delay : OTSy - ITSx + 32 TimeSlots
3) Case : If OTSy < ITSx, then Variable Delay is : 32 - (ITSx - OTSy) TimeSlots
Frame n
Input
Frame
ITS0
Output
Frame
OTS0
ITSx
Frame n + 1
ITSx
ITS31 ITS0
ITS31
y<x
OTS31
Variable Delay : 32 - (ITSx - OTSy) TimeSlots
OTSy
5464-07.EPS
OTSy
32 TimeSlots
19/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 7 : Constant Delay through the matrix with SI = 1
Co ns ta nt Delay = (32 -ITSx) + 32 + OTS y
0 ≤ x ≤ 31
0 ≤ y ≤ 31
ITS : Input Time S lot
OTS : Output TimeS lot
ITS0
Frame n + 1
ITS31
ITS0
Frame n + 2
ITS31
Min. Constant Delay = 33TS
1
+
32 Time S lots
ITS0
ITS31
OTS0
OTS 31
+0
= 33
Time S lots
OTS 31
Max. Constant Delay = 95 Time Slots
32 - 0
(32 - ITSx)
20/83
+ 32
+ 32
+ 31
+ OTS y
= 95
Time S lots
= Cons tant
Delay
5464-08.EPS
Frame n
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.1.6 - Connection Memory
III.1.6.1 - Description
The connection memory is composed of 256 locations addressed by the number of OTDM and TS
(8x32).
Each location permits :
- to connect each input time slot to one output time
slot (If two or more output time slots are connected to the same input time slot number, there
is broadcasting).
- to selectthe variable delay mode or the sequence
integrity mode for any time slot.
- to loop back an output time slot. In this case the
contents of an input time slot (ITSx, ITDMp) is the
same as the output time slot (OTSx,OTDMp).
- to output the contents of the corresponding connection memory instead of the data which has
been stored in data memory.
- to output the sequence of the pseudo random
sequence generator on an output time slot: a
pseudo random sequence can be inserted in one
or several time slots (hyperchannel) of the same
Output TDM ; this insertion must be enabled by
the microprocessor in the configuration register
of the matrix.
- to define the source of a sequenceby the pseudo
random sequence analyzer: a pseudo random
sequence can be extracted from one or several
time slots (hyperchannel)of the same Input TDM
and routed to the analyzer; this extraction can be
enabled by the microprocessor in the configuration register of the matrix (SMCR).
- to assert a high impedance level on an output
time slot (disconnection).
- to deliver a programmable 256-bit sequence during 125 microsecondson the Programmable synchronization Signal pin (PSS).
- Connection Memory Address Register (CMAR).
III.1.6.2 - Access to Connection Memory
Supposing that the Switching Matrix Configuration
Register (SMCR) has been already written by the
microprocessor, it is possible to access to the connection memory from microprocessor with the help
of two registers :
- Connection Memory Data Register (CMDR) and
- Connection Memory Address Register (CMAR).
Data (optional)
III.1.6.3 - Access to Data Memory
To extract the contents of the data memory it is
possible to read the data memory from microprocessor with the help of the two registers :
- Connection Memory Data Register (CMDR) and
III.2 - HDLC Controller
III.2.1 - Function Description
The internal HDLC controller can run up to 32
channels in a conventional HDLC mode or in a
transparent (non-HDLC) mode (configurable per
channel).
Each channel bit rate is programmable from 4kbit/s
to 64kbit/s. All the configurations are also possible
from 32 channels (from 4 to 64 kbit/s) to one
channel at 2 Mbit/s.
In reception,the HDLC time slots can directly come
from the input TDM DIN8 (direct HDLC Input) or
from any other TDM input after switching towards
the output 7 of the matrix (configurable per time
slot).
In transmission, the HDLC frames are sent on the
output DOUT6 and on the output CB (with or without contention mechanism), or are switched towards the other TDM output via the input 7 of the
matrix (see Figure 8 on Page 22 and Paragraph
III.2.2 on Page 23).
III.2.1.1 - Format of the HDLC Frame
The format of anHDLC frame isthe same in receive
and transmit direction and shown here after.
III.2.1.2 - Composition of an HDLC Frame
Opening Flag
Address Field (first byte)
Address Field (second byte)
Command Field (first byte)
Command Field (second byte)
Data (first byte)
Data (last byte)
FCS (first byte)
FCS (second byte)
Closing Flag
- Opening Flag
- One or two bytes for address recognition (reception) and insertion (transmission)
- Data bytes with bit stuffing
- Frame Check Sequence: CRC with polynomial
G(x) = x16 +x12+x5+1
- Closing Flag.
21/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 8 : HDLC and DMA Controller Block Diagram
DOUT 6
Direct HDLC O utput
F rom Output 7
of the Matrix
From Output 6
of the Matrix
DIN 8
Dire ct HDLC Input
Conte ntion
Bus
To Input 7 of the Matrix
TIME S LOT AS S IGNE R
22/83
32 CS MA-CR
32 ADDRE S S
RECOGNITION
32 Tx HDLC
32 Rx FIFO ’s
32 Tx FIFO ’s
32 Rx DMAC
32 Rx DMAC
Echo
RAM
INTERFACE
5464-09.EPS
µP
INTERFACE
32 Rx HDLC
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.2.1.3 - Description and Functions of the
HDLC Bytes
- FLAG
The binary sequence 01111110marks the beginning and the end of the HDLC Frame.
Note : In reception, three possible flag configurations are allowed and correctly detected :
- two normal consecutive flags :
...0111111001111110...
- two consecutive flags with a ”0” common :
...011111101111110...
- a global common flag : ...01111110...
this flag is the closing flag for the current frame
and the opening flag for the next frame
- ABORT
The binary sequence 1111111 marks an Abort
command.
In reception,seven consecutive1’s, inside a message, are detected as an abort command and
generates an interrupt to the host.
In transmit direction, an abort is sent upon command of the micro-processor. No ending flag is
expected after the abort command.
- BIT STUFFING AND UNSTUFFING
This operation is done to avoid the confusion of
a data byte with a flag.
In transmission, if five consecutive 1’s appear in
the serial stream being transmitted,a zero isautomatically inserted (bit stuffing) after he fifth ”1”.
In reception, if five consecutive ”1” followed by a
zero are received, the ”0” is assumed to have
been inserted and is automatically deleted (bit
unstuffing).
- FRAME CHECK SEQUENCE
TheFrame Check Sequenceiscalculatedaccording
to the recommendationQ921 of the CCITT.
- ADDRESS RECOGNITION
In the frame, one or two bytes are transmitted to
indicate the destination of the message.
Two types of addresses are possible :
- a specific destination address
- a broadcast address.
In reception, the controller compares the receive
addresses to internal registers, which contain the
address message. 4 bits in the receive command
register (HRCR) inform the receiver of which
registers, it has to take into account for the comparison. The receiver compares the two address
bytes of the message to the specific board address and the broadcast address. Upon an address match, the address and the data following
are written to the data buffers; upon an address
mismatch, the frame is ignored. So, it authorizes
the filtering of the messages. If no comparison is
specified, each frame is received whatever its
address field.
In Transmission, the controller sends the frame including the destination or broadcastaddresses.
III.2.2 - CSMA/CR Capability
An HDLC channel can come in and go out by any
TDM input on the matrix. For time constraints,
direct HDLC Access is achieved by the input TDM
(DIN 8) and the output TDM (DOUT6).
In transmission, a time slot of a TDM can be shared
between different sources in Multi-point to point
configuration (different subscriber’s boards for example). The arbitration system is the CSMA/CR
(Carrier Sense Multiple access with Contention
Resolution).
The contention is resolved by a bus connected to
the CB pin (Contention Bus). This bus is a 2Mbit/s
wire line common to all the potential sources.
If a Multi-HDLC has obtained the access to the bus,
the data to transmit is sent simultaneouslyon the CB
line and the outputTDM. Theresult of the contention
is readbackon the Echoline.If a collisionisdetected,
the transmission is stopped immediately. A contentionon a bit basisis so achieved. Each message to
be sent with CSMA/CR has a priority class (PRI = 8,
10) indicated by the Transmit Descriptor and some
rules are implemented to arbitrate the access to the
line. The CSMA/CR Algorithm is given. When a
request to send a message occurs, the transmitter determines if the shared channel is free. The
Multi-HDLC listens to the Echo line. If C or more
consecutive ”1” are detected (C depending on the
message’s priority), the Multi-HDLC begins to send
its message. Each bit sent is sampled back and
compared with the original value to send. If a bit is
different, the transmission is instantaneously
stopped (before the end of this bit time) and will
restart as soon as the Multi-HDLC will detect thatthe
channel is free without interrupting the microprocessor.
After a successful transmission of a message, a
programmablepenalty PEN(1 or 2) isapplied to the
transmitter (see Paragraph HDLC Transmit Command Register on Page 65). It guaranteesthat the
same transmitterwill not take the bus another time
before a transmitter which has to send a message
of same priority.
In case of a collision, the frame which has been
aborted is automatically retransmitted by the DMA
controller without warning the microprocessor of
this collision. The frame can be located in several
buffers in external memory. The collision can be
detected from the second bit of the opening frame
to the last but one bit of the closing frame.
23/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.2.3 - Time Slot Assigner Memory
Each HDLC channel is bidirectional and configurate by the Time Slot Assigner (TSA).
The TSAis a memoryof 32 words (one per physical
Time Slot) where all of the 32 input and output time
slots of the HDLC controllers can be associated
to logical HDLC channels. Super channels are
created by assigning the same logical channel
number to several physical time slots.
The following features are configurate for each
HDLC time slot :
- Time slot used or not
- One logical channel number
- Its source : (DIN 8 or the output 7 of the matrix)
- Its bit rate and concerned bits (4kbit/s to
64kbit/s). 4kbit/s correspond to one bit transmitted each two frames. This bit must be present in
two consecutive frames in reception, and repeated twice in transmission.
- Its destination :
- direct output on DOUT6
- direct output on DOUT6 and on the Contention
Bus (CB)
- on another OTDM via input 7 of the matrix and
on the Contention Bus (CB)
III.2.4 - Data Storage Structure
Data associated with each Rx and Tx HDLC channel is stored in externalmemory; The data transfers
between the HDLC controllers and memory are
ensuredby 32 DMAC(Direct Memory AccessController) in reception and 32 DMAC in transmission.
The storage structure chosen in both directions is
composed of one circular queue of buffers per
channel. In such a queue, each data buffer is
pointed to by a Descriptor located in external memory too. The main information contained in the
Descriptor is the address of the Data Buffer, its
length and the address of the next Descriptor; so
the descriptors can be linked together.
This structure allows to :
- Store receive frames of variable and unknown
length
- Read transmit frames stored in external memory
by the host
- Easily perform the frame relay function.
24/83
III.2.4.1 - Reception
At the initialization of the application, the host has
to prepare an Initialization Block memory, which
contains the first receive buffer descriptor address
for each channel, and the receive circular queues.
At the opening of a receive channel, the DMA
controller reads the address of the first buffer descriptor corresponding to this channel in the initialization Block. Then, the data transfer can occur
without intervention of the processor (see Figure 9
on Page 25).
A new HDLC frame always begins in a new buffer.
A long frame can be split between several buffers
if the buffer size is not sufficient. All the information
concerning the frame and its location in the
circular queue is included in the Receive Buffer
Descriptor :
- The Receive Buffer Address (RBA),
- The size of the receive buffer (SOB),
- The number of byteswritten into the buffer (NBR),
- The Next Receive Descriptor Address (NRDA),
- The status concerning the receive frame,
- The control of the queue.
III.2.4.2 - Transmission
In transmission, the data is managed by a similar
structure as in reception (see Figure 10 on
Page 25).
By the same way, a frame can be split up between
consecutive transmit buffers.
The main information contained in the Transmit
Descriptor are :
- transmit buffer address (TBA),
- numberof bytes to transmit(NBT) concerningthe
buffer,
- next transmit descriptor address (NTDA),
- status of the frame after transmission,
- control bit of the queue,
- CSMA/CR priority (8 or 10).
III.2.4.3 - Frame Relay
The principle of the frame relay is to transmit a
frame which has been received without treatment.
A new heading is just added. This will be easily
achieved, taking into account that the queue structure allows the transmission of a frame split between several buffers.
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 9 : Structure of the Receive Circular Queue
Initialization Block
up to 32 channels
Initial Receive
Descriptor
0
1
RDA
RDA
31
RDA
RECEIVE
DMA
CONTROLLER
Receive
Descriptor 2
NRDA
RBA
NRDA
RBA
Receive
Buffer 1
Receive
Buffer 2
Receive
Descriptor n
Receive
Descriptor 3
NRDA
RBA
NRDA
RBA
5464-10.EPS
Receive
Buffer 3
Receive
Buffer n
One receive circular queue by channel
Figure 10 : Structure of the Transmit Circular Queue
Initialization Block
up to 32 channels
0
1
TDA
TDA
31
TDA
TRANSMIT
DMA
CONTROLLER
Transmit
Descriptor 2
Initial Transmit
Descriptor
NTDA
TBA
NTDA
TBA
Transmit
Buffer 1
Transmit
Buffer 2
Transmit
Descriptor n
Transmit
Descriptor 3
NTDA
TBA
NTDA
TBA
Transmit
Buffer 3
5464-11.EPS
Transmit
Buffer n
One transmit circular queue by channel
25/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.2.5 - Transparent Modes
In the transparentmode, the Multi-HDLC transmits
data in a completely transparent manner without
performing any bit manipulation or Flag insertion.
The transparent mode is per byte function.
Two transparent modes are offered :
- First mode : for the receive channels, the
Multi-HDLC continuously writes received bytes
into the external memory as specified in the current receive descriptor without taking intoaccount
the Fill Character Register.
- Secondmode: the Fill CharacterRegister specifies
the ”fill character”which must be taken into account.
In reception,the ”fill character”will not betransferred
to theexternalmemory. Thedetectionof ”Fill character” marks the end of a message and generates an
interruptifBINT=1 (see TransmitDescriptoronPage
78). When the ”Fill character”is not detected a new
message is receiving.
As for the HDLC mode the correspondence
between the physical time slot and the logical
channel is fully defined in the Time Slot Assigner
memory (Time slot used or not used, logical channel number, source, destination).
III.2.6 - Command of the HDLC Channels
The microprocessor is able to control each HDLC
receive and transmit channel. Some of the commands are specific to the transmission or the reception but others are identical.
III.2.6.1 - Reception Control
The configuration of the controller operating mode
is: HDLC mode or Transparent mode.
The control of the controller: START, HALT, CONTINUE, ABORT.
- START : On a start command, the RxDMA controller reads the address of the first descriptor in
the initialization block memory and is ready to
receive a frame.
- HALT : For overloading reasons, the microprocessor can decide to halt the reception. The DMA
controller finishes transfer of the current frame to
external memory and stops. The channel can be
restarted on CONTINUE command.
- CONTINUE : The reception restarts in the next
descriptor.
- ABORT: On an abort command, the reception is
instantaneously stopped. The channel can be
restarted on a START or CONTINUE command.
Reception of FLAG (01111110) or IDLE (11111111)
between Frames.
Address recognition. The microprocessor defines
26/83
the addressesthat the Rx controller has to take into
account.
In transparent mode: ”fill character” register selected or not.
III.2.6.2 - Transmission Control
The configuration of the controller operating mode
is : HDLC mode or Transparent mode.
The control of the controller : START, HALT, CONTINUE, ABORT.
- START : On a start command, the Tx DMAcontroller reads the address of the first descriptor in the
initialization block memory and tries to transmit the
first frame if End Of Queue is not at ”1”.
- HALT : The transmitter finishes to send the current frame and stops.The channel can be restarted on a CONTINUE command.
- CONTINUE : if the CONTINUE command occurs
after HALT command, the HDLC Transmitter restarts by transmitting the next buffer associated
to the next descriptor.
If the CONTINUE command occurs after an
ABORT command which has occurred during a
frame, the HDLC transmitter restarts by transmitting the frame which has been effectively aborted
by the microprocessor.
- ABORT: On an abort command, the transmission
of the current frame is instantaneously stopped,
an ABORT sequence ”1111111” is sent, followed
by IDLE or FLAG bytes. The channel can be
restarted on a START or CONTINUE command.
Transmission of FLAG (01111110 ) or IDLE
(111111111)between frames can be selected.
CRC can be generated or not. If the CRC is not
generated by the HDLC Controller, it must be located in the shared memory.
In transparentmode: ”fill character” register can be
selected or not.
III.3 - C/I and Monitor
III.3.1 - Function Description
The Multi-HDLC is able to operate both GCI and V*
links. The TDM DIN/DOUT 4 and 5 are internally
connected to the CI and Monitor receivers/transmitters. Since the controllershandle up to 16CI and
16 Monitor channels simultaneously, the MultiHDLC can manage up to 16 level 1 circuits.
The Multi-HDLC can be used to support the CI and
monitor channels based on the following protocols :
- ISDN V* protocol
- ISDN GCI protocol
- Analog GCI protocol.
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.3.2 - GCI and V* Protocol
A TDM can carry 8 GCI channels or V* channels. The monitor and S/C bytes always stand at the same
position in the TDM in both cases.
CGI Channel 0
CGI Channel 7
TS0
TS1
TS2
TS3
B1
B2
MON
S/C
CGI Channel 1 to Channel 6
The GCI or V* channels are composed of 4 bytes
and have both the same general structure.
B1
B2
MON
S/C
B1, B2 : Bytes of data. Those bytes are not
affected by the monitor and CI protocols.
MON : Monitor channel for operation and
maintenance information.
S/C
: Signalling and control information.
Only Monitor handshakes and S/C bytes are different in the three protocols :
ISDN V* S/C byte
D
C/I 4 bits
T
TS28
TS29
TS30
TS31
B1
B2
MON
S/C
III.3.3 - Structure of the Treatment
GCI/V* TDM’s are connected to DIN 4 and DIN 5.
The D channels are switched through the matrix
towards the output 7 and the HDLC receiver. The
Monitor and S/C bytes are multiplexed and sent to
the CI and Monitor receivers (see Figure 11 on
Page 28).
In transmission, the S/C and Monitor bytes are
recombined by multiplexing the information provided by the Monitor,C/I and the HDLCTransmitter.
Like in reception,the D channelis switched through
the matrix.
E
III.3.4 - CI and Monitor Channel Configuration
ISDN GCI S/C byte
D
C/I 4 bits
A
E
Monitor channel data is located in a time slot ; the
CI and monitor handshakebits are in the next time
slot.
A
E
Each channel can be defined independently. A
table with all the possible configurations is presented hereafter (Table 13).
Analog GCI S/C byte
C/I 6 bits
CI : The Command/Indicate channel is used for
activation/deactivation of lines and control
functions.
D : These 2 bits carry the 16 kbit/s ISDN basic
access D channel.
In GCI protocol, A and E are the handshake bits
and are used to control the transfer of information
on monitor channels.The E bit indicates the transfer of each new byte in one direction and the A bit
acknowledges this byte transfer in the reverse direction.
In V* protocol, there isn’t any handshakemode.The
transmitter has only to mark the validity of the
Monitor byte by positioning the E bit (T is not used
and is forced to ”1”).
For more information about the GCI and V*, refer
to the General Interface Circuit Specification (issue1.0, march 1989) and the France Telecom
Specification about ISDN Basic Access second
generation (November 1990).
Table 13 : C/I and MON Channel Configuration
C/I validated or not
Monitor validated
or not
CI For analog subscriber (6 bits)
CI For ISDN subscriber (4 bits)
Monitor V*
Monitor GCI
Note : A mix of V* and GCI monitoring can be performed for two
distinct channels in the same application.
III.3.5 - CI and Monitor Transmission/Reception
Command
The reception of C/I and Monitor messages are
managed by two interrupt queues.
In transmission, a transmit command register is
implemented for each C/I and monitor channel (16
C/I transmit command registers and 16 Monitor
transmit command registers). Those registers are
accessible in read and write modes by the microprocessor.
27/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 11 : D, C/I and Monitor Channel Path
DIN 5
GCI1
DIN 4
DOUT 4
GCI0
D Channels
from Tx HDLC
0
1
2
3
4
5
6
7
SWITCHING
MATRIX
0
1
2
3
4
5
6
7
GCI0
DOUT 5
GCI1
D Cha nnels
to Rx HDLC
GCI CHANNEL DEFINITION
16 Rx
C/I
16 Rx
MON
16 Tx
C/I
16 Tx
MON
5464-12.EPS
INTERRUPT
CONTR OLLER
Internal Bus
III.4 - Microprocessor Interface
III.4.1 - Description
The Multi-HDLC circuit can be controlledby severa
types of microprocessors (ST9, Intel/Motorola 8 or
16 data bits interfaces) such as :
- ST9 family
- INTEL 80C188 8 bits
- INTEL 80C186 16 bits
- MOTOROLA 68000 16 bits
During the initialization of the Multi-HDLC circuit,
the microprocessor interface is informedof the type
of microprocessor that is connectedby polarisation
of three external pins MOD 0/2).
Two chip Select (CS0/1)pins are provided.CS0 will
select the internal registers and CS1 the external
memory.
28/83
Table 14 : Microprocessor Interface Selection
MOD2
Pin
0
1
1
0
0
MOD1
Pin
1
1
0
0
0
MOD0
Pin
1
1
0
0
1
Microprocessor
80C188
80C186
68000
Reserved
ST9
III.4.2 - Definition of the Interface for the different microprocessors
The signals connectedto the microprocessor interface are presented on the following figures for the
different microprocessor (see Figures 12, 13, 14,
15, 16 and 17 on Pages 29-30).
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 12 : Multi-HDLC connected to µP with multiplexed buses
MULTI-HDLC
Multiplex
Address/Da ta Bus
Address Bus
µP
INTER FACE
Inte rnal Bus
R AM
INTER FACE
Data Bus
STATIC or
DYNAMIC RAM
(organize d
by 16 bits )
5464-13.EPS
µP ST9
IINTEL
MOTOROLA
8/16 BITS
BUS ARBITRATION
Figure 13 : Multi-HDLC connected to µP with non-multiplexed buses
MULTI-HDLC
Address Bus
Address Bus
µP
INTERFACE
Internal Bus
RAM
INTERFACE
Data Bus
Data Bus
STATIC or
DYNAMIC RAM
(organized
by 16 bits)
5464-14.EPS
µP
IINTEL
MOTOROLA
8/16 BITS
BUS ARBITRATION
Figure 14 : Microprocessor Interface for INTEL 80C188
INT0/1
WDO
NRES ET
CS 0/1
ARDY
INTEL
80C188
µP
INTERFACE
NWR
NR D
ALE
5464-15.EPS
A8/19
AD0/7
Figure 15 : Microprocessor Interface for INTEL 80C186
INT0/1
WDO
NRES ET
CS 0/1
NBHE
ARDY
NWR
µP
INTERFACE
NR D
ALE
A16/19
5464-16.EPS
INTEL
80C186
AD0/15
29/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 16 : Microprocessor Interface for MOTOROLA 68000
INT0/1
WDO
NRES ET
CS 0/1
NDTACK
R/NW
MOTOROLA
68000
µP
INTERFACE
NUDS
NLDS
NAS
5464-15.EPS
A1/23
AD0/15
Figure 17 : Microprocessor Interface for ST9
INT0/1
WDO
NRE S ET
C S 0/1
WAIT
ST9
R/NW
µP
INTERFACE
NDS
AD0/7
30/83
5464-19.EPS
NAS
A8/15
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.5 - Memory Interface
III.5.1 - Function Description
The memory interface allows the connection of
Static or Dynamic RAM. The memory space addressable in the two configurationsis not thesame.
In the case of dynamic memory (DRAM), the memory interface will address up to 16 Megabytes. In
caseof staticmemory(SRAM) only 1 Megabytewill
be addressed. The memory location is always organized in 16 bits.
The memory is shared between the Multi-HDLC
and the microprocessor. Theaccess to the memory
is arbitrated by an internal function of the circuit:
the bus arbitration.
III.5.2 - Choice of memory versus microprocessor and capacity required
The memory interface depends on the memory
chips which are connected. As the memory chips
will be chosen versus the microprocessor and the
wanted memory space, the Table 22 presents the
different configurations.
Example 1 : if the applicationrequires 16 bit mProcessor and 1 Megaword Shared memory size, three
capabilities are offered :
- 4 DRAM Circuits (256Kx16) or
- 4 DRAM Circuits (1Mx4) or
- 1 DRAM Circuit (1Mx16).
Example 2 : if the application requires 8 bit mProcessor and 1 Megabyte Shared memory size, three
capabilities are offered:
- 2 DRAM Circuits (256Kx16) or
- 8 SRAM Circuits (128Kx8) or
- 2 SRAM Circuits (512kx8).
Example 3 : for small applications it is possible to
connect 2 SRAM Circuits (128Kx8) to obtain 256
Kilobytes shared memory.
III.5.3 - Memory Cycle
For SRAM and DRAM, the different cycles are
programmable (see Paragraph ”Memory Interface
Configuration Register MICR (32)H” on Page 71).
Each cycle is equal to : p x 1/f
with f the frequencyof signal applied to the Crystal
1 input and p selected by the user.
Table 22 : DRAM and SDRAM Selection versus µP
Microprocessor and
shared memory
Shared memory size required by the application
8 bits
µProcessor
Number of
Megabytes
0.5
1
2
4
8
16
16 bits
µProcessor
Number of
Megawords
0.25
0.5
1
2
4
8
1(256Kx16)
2(256Kx16)
4(256Kx16)
DRAM Circuits proposed
Capacity
Organization
4 Megabits
256Kx16
1Mx4
4(1Mx4)
8(1Mx4)
16(1Mx4)
16 Megabits
1Mx16
1(1Mx16)
2(1Mx16)
4(1Mx16)
64 Megabits
4Mx4
4(4Mx4)
8(4Mx4)
4Mx16
1(4Mx16)
2(4Mx16)
SRAM Circuits proposed
Capacity
Organization
1 Megabits
128Kx8
4 Megabits
512kx8
Not possible
4(128Kx8)
8(128Kx8)
2(512kx8)
31/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 19 : 512K x 8 SRAM Circuit Memory
Organization
III.5.4 - SRAM interface
A19
1
1
1
1
0
0
0
0
A18
1
1
0
0
1
1
0
0
A0 or equiv.
1
0
1
0
1
0
1
0
512K x 16
512K x 8
III.5.5.1 - 256K x n DRAM Signals
Signals
NRAS3
NRAS2
NRAS1
NRAS0
NCAS1
NCAS0
Figure 18 : 128K x 8 SRAM Circuit Memory
Organization
128K x 16
128K x 8
NCE 6
6
NCE 5
5
NCE 4
4
DM0/7
III.5.5 - DRAM Interface
In DRAM, the memory space can achieve up to 16
megabytes organized by 16 bits. Eleven address
wires, four NRAS and two NCAS are needed to
select any byte in the memory. One NRAS signal
selects 1 bank of 4 and the NCAS signals select the
bytes concerned by the transfer (1 or 2 selecting a
byte or a word). The DRAM memory interface is
then defined. The ”RAS only” refresh cycles will
refresh all memory locations. The refresh is programmable. The frequency of the refresh is fixed
by the memory requirements.
III.5.4.1 - 18K x n SRAM
The Address bits delivered by the Multi-HDLC for
128K x n SRAM circuits are :
ADM0/14 and ADM15/16 (17 bits) corresponding
with A1/17 delivered by the µP.
7
0
NCE0
DM8/15
The SRAM space achieves 1 Mbyte max. It is
always organized in 16 bits. The structure of the
memory plane is shown in the following figures.
Because of the different chips usable, 19 address
wires and 8 NCE (Chip Enable) are necessary to
address the 1 Mbyte. The NCE selects the Most or
Least Significant Byte versus the value of A0 delivered by the µP and the location of chip in the
memory space.
NCE 7
1
NCE1
5464-21.EPS
Signals
NCE7
NCE6
NCE5
NCE4
NCE3
NCE2
NCE1
NCE0
A20
1
1
0
0
A19
1
0
1
0
A0 or equiv.
1
0
The Address bits delivered by the Multi-HDLC for
256K x n DRAM circuits are :
ADM0/8 (2 x 9 = 18 bits) corresponding with A1/18
delivered by the µP.
Figure 20 : 256K x 16 DRAM Circuit Organization
NCE 3
3
NCE 2
CAS1
2
CAS0
NCE 1
1
NCE 0
DM8/15
0
DM0/7
5464-20.EPS
256K x 16
RAS 3
7
6
RAS 2
5
4
RAS 1
3
2
RAS 0
1
0
Signals
NCE1
NCE0
A0 or equiv.
1
0
The Address bits delivered by the Multi-HDLC for
512K x n SRAM circuits are :
ADM0/14 and ADM15/18 (19 bits) corresponding
with A1/19 delivered by the µP.
32/83
DM8/15
DM0/7
ADM0/8, NWE, NOE a re conne cte d to e a ch circuit.
5464-22.EPS
III.5.4.2 - 512K x n SRAM
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.5.5.2 - 1M x n DRAM Signals
Signals
A22
A20
NRAS3
1
1
NRAS2
1
0
NRAS1
0
1
NRAS0
0
0
Figure 22 : 4M x 16 DRAM Circuit Organization
A0 or equiv.
NCAS 1
NCAS 0
NCAS1
1
NCAS0
0
NRAS1
3
2
NRAS0
1
0
DM8/15
DM0/7
ADM0/10, NWE, NOE a re conne cte d to e a ch circuit
The Address bits delivered by the Multi-HDLC for
1M x n DRAM circuits are :
ADM0/9 (2 x 10 = 18 bits) correspondingwith A1/20
delivered by the µP.
Figure 21 : 1M x 16 DRAM Circuit Organization
NCAS1
NCAS0
NRAS3
7
6
NRAS2
5
4
NRAS1
3
2
NRAS0
1
0
DM8/15
DM0/7
ADM0/9, NWE, NOE a re connected to each circuit
5464-23.EPS
1M x 16
III.6 - Bus Arbitration
The Bus arbitration function arbitrates the access
to the bus between different entities of the circuit.
Those entities which can call for the bus are the
following :
- The receive DMA controller,
- The microprocessor,
- The transmit DMA controller,
- The Interrupt controller,
- The memory interface for refreshing the DRAM.
This list gives the memory access priorities per
default.
If the treatment of more than 32 HDLC channels is
required by the application, it is possible to chain
several Multi-HDLC components.That is done with
two external pins (TRI, TRO) and a token ring
system.
The TRI, TRO signals are managed by the bus
arbitration function too. When a chip has finished
its tasks, it sends a pulse of 30 ns to the next chip.
Figure 23 : Chain of n Multi-HDLC Components
III.5.5.3 - 4M x n DRAM Signals
Signals
A23
NRAS1
1
NRAS0
0
5464-24.EPS
4M x 16
TRI
A0 or equiv.
MHDLC 0
µP
RAM
TRO
TRI
MHDLC 1
1
NCAS0
0
The Address bits delivered by the Multi-HDLC for
4M x n DRAM circuits are :
ADM0/10 (2 x 11 = 22 bits) corresponding with
A1/22 delivered by the µP.
TRO
TRI
MHDLC n
µP Bus
5464-25.EPS
NCAS1
TRO
RAM Bus
33/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Depending on the applications, three different signals of synchronization (GCI, V* or Sy) can be
provided to the component. The clock A/B frequency can be a 4096 or 8192kHz clock. The
component is informed of the synchronization and
clocks that are connectedby software.The timings
of the different synchronization are given Page 38.
III.7 - Clock Selection and Time Synchronization
III.7.1 - Clock Distribution Selection
and Supervision
Two clock distributions are available : Clock at
4.096MHzor 8.192MHz and a synchronizationsignal at 8kHz. The component has to select one of
these two distributions and to check its integrity
(see Figure 25 and Paragraph ”General Configuration Register GCR (02)H” on Page 57).
DCLK, FSCGCI and FSCV* are output on three
external pins of the Multi-HDLC. DCLK is the clock
selected between Clock A and Clock B. FSCGCI
and FSCV* are functions of the selected distribution and respect the GCI and V* frame synchronization specifications.
The supervision of the clock distribution consists of
verifying its availability. The detection of the clock
absence is done in less than 250µs. In case the
clock is absent, an interrupt is generated with a
4kHz recurrence. Then the clock distribution is
switched by the microprocessor. This change of
clock occurs on a falling edge of the new selected
distribution.
III.7.2 - VCXO Frequency Synchronization
An external VCXO can be used to provide a clock
to the transmission components. This clock is controlled by the main clock distribution (Clock A or
Clock B at 4096kHz). As the clock of the transmission component is 15360 or 16384kHz,a configurable function is necessary.
The VCXO frequency is divided by P (30 or 32) to
provide a common sub-multiple (512kHz) of the
reference frequency CLOCKA or CLOCKB
(4096kHz). The comparison of these two signals
gives an error signal which commands the VCXO.
Two external pins are needed to perform this function : VCXO-IN and VCXO-OUT (see Figure 26 on
Page 35).
Figure 24 : MHDLC Clock Generation
REF. CLOCK
RES ET
INT1
Clock Lack
De te ction
from 250µs
FRAME A
CLOCK A
FS CV*
Fra me
CLOCK S ELECTION
CLOCK
FS CGCI
ADAP TATION
CLOCK B
S elect A or B
(S ELB)
Clock
S upervision
De a ctivation
(CS D)
A or B
S e lecte d
(BS EL)
Clock
HCL
DCLK
S YN1
GENERAL CONFIGURATION REGISTER (GCR)
34/83
S YN0
To the interna l
MHDLC
5464-26.EPS
At RES ET
FRAME A a nd CLOCK A
a re s elected
FRAME B
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 25 : VCXO Frequency Synchronization
VCXO
f = 15 360kHz
or 16384kHz
LOW P ASS
F ILTER
/p
7
VCXO IN
OUX
8
VCXO OUT
/8
Re f =
409 6kHz
III.8 - Interrupt Controller
III.8.1 - Description
Three external pins are used to manage the interrupts generated by the Multi-HDLC. The interrupts
have three main sources :
- The operating interrupts generated by the HDLC
receivers/transmitters, the CI receivers and the
monitor transmitters/receivers. INT0 Pin is reserved for this use.
- The interrupt generatedby an abnormal working of
theclockdistribution.INT1Pinisreservedforthisuse.
- The non-activity of the microprocessor (Watchdog). WDO Pin is reserved for this use.
III.8.2 - Operating Interrupts (INT0 Pin)
There are five main sources of operating interrupts
in the Multi-HDLC circuit :
- The HDLC receiver,
- The HDLC transmitter,
- The CI receiver,
- The Monitor receiver,
- The Monitor transmitter.
When an interrupt is generated by one of these
functions, the interrupt controller :
- Collects all the information about the reasons of
this interrupt,
- Stores them in external memory,
- Informs the microprocessor by positioning the
INT0 pin in the high level.
Three interrupt queues are built in external memory
to store the information about the interrupts :
- A single queue for the HDLC receivers and transmitters,
- One for the CI receivers,
- One for the monitor receivers.
The microprocessor takes the interrupts into account by reading the Interrupt Register (IR) of the
interrupt controller.
MHDLC
5464-27.EPS
if f = 153 60kHz, p = 30
if f = 163 84kHz, p = 32
EVM
This register informs the microprocessor of the
interrupt source. The microprocessor will have information about the interruptsource by readingthe
corresponding interrupt queue (see Paragraph ”Interrupt Register IR (38)H” on Page 74).
On an overflow of the circular interrupt queues and
an overrun or underrun of the different FIFO, the
INT0 Pin is activated and the origin of the interrupt
is stored in the Interrupt Register.
A 16 bits register is associated with the Tx Monitor
interrupt. It informs the microprocessor of which
transmitter has generated the interrupt (see Paragraph ”Transmit Monitor Interrupt Register TMIR
(30)H” on Page 71).
III.8.3 - Time Base Interrupts (INT1 Pin)
The Time base interrupt is generated when an
absence or an abnormal working of clock distribution is detected. The INT1 Pin is activated.
III.8.4 - EmergencyInterrupts (WDO Pin)
The WDO signal is activated by an overflow of the
watchdog register.
III.8.5 - Interrupt Queues
There are three different interrupt queues :
- Tx and Rx HDLC interrupt queue,
- Rx C/I interrupt queue,
- Rx Monitor interrupt queue.
Their length can be defined by software.
For debugging function, each interrupt word of the
CI interruptqueue and monitor interrupt queue can
be followed by a timestamped word. It is composed
of a counter which runs in the range of 250µs. The
counter is the same as the watchdog counter.
Consequently,the watchdogfunctionisn’t available
at the same time.
35/83
STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
Figure 26 : The Three Circular Interrupt Memories
IBA + 256
INITIALIZATION
HDLC (Tx a nd Rx)
BLOC K
INTER RUPT QUEUE
IBA + 256
+ HDLC
Que ue Size
MON (Rx)
INTER RUP TQUEUE
IBA + 256
+ HDLC
Que ue S ize
+ MON
Que ue S ize
C/I (Rx)
INTER RUP T QUEUE
5464-28.EPS
IBA
IBA + 254
III.9 - Watchdog
This function is used to control the activity of the
application. It is composed of a counter which
counts down from an initial value loaded in the
Timer register by the microprocessor.
If the microprocessor doesn’t reset this counter
before it is totally decremented, the external Pin
WDO is activated ; this signal can be used to reset
the microprocessor and all the application.
The initial time value of the counter is programmable from 0 to 15s in increments of 0.25ms.
At the reset of the component,the counter is automatically initialized by the value corresponding to
512ms which are indicated in the Timer register.
36/83
The microprocessor must put WDR (IDCR Register) to”1” to reset this counter and to confirm that
the application started correctly.
In the reverse case, the WDO signal could be used
to reset the board a second time.
III.10 - Reset
There are two possibilities to reset the circuit :
- by software,
- by hardware.
Each programmable register receives its default
value. After that, the default value of each data
register is stored in the associatedmemory except
for Time slot Assigner memory.
STLC5464
IV - DC SPECIFICATIONS
Absolute Maximum Ratings
Symbol
Parameter
Value
5V Power Supply Voltage
VDD
Input or Output Voltage
-0.5, 6.5
V
-0.5, VDD + 0.5
V
-55, +125
°C
Storage Temperature
Tstg
Unit
Power Dissipation
Symbol
P
Parameter
Power Consumption
Test Conditions
Min.
VDD = 5V
Typ.
Max.
400
Unit
mW
Recommended DC Operating Conditions
Symbol
Parameter
VDD
5V Power Supply Voltage
Toper
Operating Temperature
Test Conditions
Min.
Typ.
Max.
Unit
4.75
5.25
V
0
+70
°C
Max.
Unit
Note 1 : All the following specifications are valid only within these recommended operating conditions.
TTL Input DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
IIL
Low Level Input Current
VI = 0V
1
µA
IIH
High Level Input
VI = VDD
-1
µA
0.7
1
V
2
2.4
Vhyst
SchmittTrigger hysteresis
VT+
Positive Trigger Voltage
VT-
Negative Trigger Voltage
CIN
Input Capacitance (see Note 2)
C OUT
Output Capacitance
CI/O
Bidirextional I/O Capacitance
0.8
2.0
0.4
0.6
f = 1MHz @ 0V
V
V
0.8
2
V
V
4
pF
Max.
Unit
4
4
8
Note 2 : Excluding package
CMOS Output DC Electrical Characteristics
Symbol
Parameter
Test Conditions
VOL
Low Level Output Voltage
IOL = X mA (see Note 3)
VOH
High Level Output Voltage
IOH = -X mA (see Note 3)
Note 3 :
Min.
Typ.
0.4
VDD5-0.4
V
V
X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
X = 4 or 8mA.
Protection
Symbol
VESD
Parameter
Electrostatic Protection
Test Conditions
C = 100pF, R = 1.5kΩ
Min.
2000
Typ.
Max.
Unit
V
37/83
STLC5464
V - CLOCK TIMING
V.1 - Synchronization Signals delivered by the system
For one of three different input synchronizations which is programmed, FSCG and FSCV* signals
delivered by the Multi-HDLC are in accordance with the figure hereafter.
Figure 27 : Clocks received and delivered by the Multi-HDLC
CLOCK B
t2
t5h
t1
t5l
CLOCK A
3
4
5
6
7
0
1
1) S y Mode
F ra me A (or B)
t3
t4
t3
t4
t3
t4 CGI
2) G CI Mode
F ra me A (or B)
3) V*Mod e
F ra me A (or B)
DIN 0/8, ECHO
DO UT 0/7, CB
if F S = F S CG
Bit3
Bit4
Bit5
Bit6
Bit7
Bit0
Time S lot 31
TDM0/7
Bit1
Time S lot 0
F S CG delivere d
by the circuit
5464-29.EPS
F S CV* de livere d
by the circuit
The four Multiplex Configura tion Registers are a t zero (no de lay).
Symbol
Parameter
Min.
Typ.
Max.
Unit
t1
Clock Period if 4096kHz
Clock Period if 8192kHz
239
120
244
122
249
125
ns
ns
t2
Delay between Clock A and Clock B
- 60
0
+60
ns
t3
Set up time Frame A (or B)/CLOCK A (or B)
10
t1-10
ns
Hold time Frame A (or B)/CLOCK A (or B)
10
10
t1-10
125000 - (t1 - 10)
ns
Clock ratio t5h/t5l
75
125
%
t4
t4GCI
t5
38/83
100
STLC5464
V - CLOCK TIMING (continued)
V.2 - TDM Synchronization
Figure 28 : Synchronization Signals received by the Multi-HDLC
CLOCK A (o r B)
t1
t2
DCLK de live re d by
the Multi-HDLC
t3
FSCG d e livere d by
the Multi-HDLC
t4
t5
t6
DOUT0/7, CB
Bit 7, Time S lot 31
Bit 0, Time Slot 0
t7
t7
DIN0/8
t9
t8
5464-30.EPS
ECHO
The four Multiplex Configura tion Re giste rs a re a t z e ro (no de lay be twe e n FS a nd Multiplexe s).
Symbol
Parameter
Min.
Typ.
Max.
Unit
Id CLOCKA or B
244
488
Id CLOCKA or B
ns
ns
5
30
ns
t1
Clock Period if 4096kHz
Clock Period if 2048kHz
t2
Delay between CLOCK A or B and DCLK (30pF)
t3
Set-up Time FS/DCLK
20
t4
Hold Time FS/DCLK
20
t5
Duration FS
244
t6
DCLK to Data 50pF
DCLK to Data 100pF
t7
Set-up Time Data/DCLK
20
t7
Hold Time Data/DCLK
20
t8
Set-up Echo/DCLK (rising edge)
t9
Hold Time Echo/DCLK (rising edge)
t1-20
125000-244
ns
50
100
ns
ns
ns
155
205
ns
ns
ns
ns
39/83
STLC5464
V - CLOCK TIMING (continued)
V.3 - GCI Interface
Figure 29 : GCI Synchro Signal delivered by the Multi-HDLC
125 µs
FS re ce ived by
the Multi-HDLC
CH0
CH1
CH7
DIN4/5
DOUT4/5
GCI Ch a nn e l
B1
B2
MON
D
C/I AE
t1
DCLK de livered by
the Multi-HDLC
t3
t3
FS CG de livered by
the Multi-HDLC
t6
DOUT0/7, CB
if FSCG is connected to FS
Bit 0, Time S lot 0
t7
t7
5464-31.EPS
DIN0/8
The four Multiplex Configura tion Registers a re a t ze ro (no de lay betwee n FS and Multiplexes ).
Symbol
Parameter
Min.
Typ.
Max.
Unit
CLOCKA/B Tmin
244
488
CLOCKA/B Tmax
ns
ns
20
ns
125000-244
ns
50
100
ns
ns
t1
Clock Period if 4096kHz
Clock Period if 2048kHz
t3
DCLK to FSCG
t5
Duration FS
t6
DCLK to Data 50pF
DCLK to Data 100pF
t7
Set-up Time Data/DCLK
20
ns
t7
Hold Time Data/DCLK
20
ns
40/83
244
STLC5464
V - CLOCK TIMING (continued)
V.4 - V* Interface
Figure 30 : V* Synchronization Signal delivered by the Multi-HDLC
125 µs
FS re ce ived by
th e Multi-HDLC
CH0
CH1
CH7
DIN4/5
DOUT4/5
GCI Ch a nn e l
B1
B2
MON
D
C/I AT
t1
DCLK de livere d by
th e Multi-HDLC
t3
t3
FSCV* de live re d by
th e Multi-HDLC
DOUT0/7, CB
if FSCG is conne cte d to FS
Bit 3, Time S lot 31
t7
t7
5464-32.EPS
DIN0/8
Th e four Multiple x Configura tion Re giste rs a re a t z e ro (no de la y be twe e n FS a nd Multiple xe s ).
Symbol
Parameter
Min.
Typ.
Max.
244
Unit
t1
Clock Period 4096kHz
t3
DCLK to FSCV*
ns
t5
Duration FSCV*
t6
Clock to Data 50pF
Clock to Data 100pF
t7
Set-up Time Data/DCLK
20
ns
t7
Hold Time Data/DCLK
20
ns
20
244
ns
ns
50
100
ns
nS
41/83
STLC5464
VI - MEMORY TIMING
VI.1 - Dynamic Memories
Figure 31 : Dynamic Memory Read Signals from the Multi-HDLC
NDS fro m µP
(or e quivalent)
T
Total Re ad Cycle
1/f
a
a
a
a
a
MASTERCLOCK
a pplied to XTAL1 P in
NRAS 0/3
a
HZ
Tu
HZ
Tv
NCAS 0/1
Tw
Tz
NWE
Tv/2
ADM0/10
Tw + Tz /2
NOE
Ts
Th
DM0/15 from
DRAM Circuit
Symbol
HZ
HZ
E ach s ignal from the MHDLC is high
impe dance outside this time if MBL = 0
Parameter
T
Delay between Data Strobe from the mP and beginning of cycle
a
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
Min.
5464-33.EPS
Note : S e e
MBL De finition
Typ.
Max.
Unit
2/f
20
ns
Tw
Delay between NCAS Falling Edge and NCAS rising Edge
1/f
2/f
ns
Tz
Delay between NCAS Rising Edge and end of cycle
1/f
2/f
ns
Ts
Set-up Time Data /NCAS Rising Edge
20
ns
Th
Hold Time Data/NCAS Rising Edge
0
ns
42/83
STLC5464
VI - MEMORY TIMING (continued)
Figure 32 : Dynamic Memory Write Signals from the Multi-HDLC
NDS fro m µP
(or equivalent)
T
Tota l Write Cycle
1/f
a
a
a
a
a
MASTE RCLOCK
a pplied to XTAL1 P in
NRAS 0/3
a
Tu
HZ
HZ
Tv
NCAS 0/1
Tw
Tz
NWE
Tv/2
ADM0/10
Td
DM0/15
NOE
HZ
Symbol
HZ
Ea ch s ignal from the MHDLC is high
impe dance outside this time if MBL = 0
Max.
Unit
1/f
f : Masterclock Frequency
32
33
MHz
Tu
Delay between beginning of cycle and NRAS Falling Edge
1/f
2/f
ns
Tv
Delay between NRAS Falling Edge and NCAS Falling Edge
1/f
2/f
ns
Tw
Delay between NCAS Falling Edge and NWE Rising Edge
1/f
2/f
ns
Tz
Delay between NWE Rising Edge and end of cycle
1/f
2/f
ns
Delay between NRAS Falling Edge and address change
1/2f
1/f
ns
Data Valid after beginning of cycle (30 pF)
1/f
1/f
ns
Tv/2
Td
Parameter
Min.
Typ.
5464-34.EPS
No te : S e e
MBL Definition
Note : Total Cycle : Tu + Tv + Tw + Tz
43/83
STLC5464
VI - MEMORY TIMING (continued)
VI.2 - Static Memories
Figure 33 : Static Memory Read Signals from the Multi-HDLC
NDS fro m µP
(or equivalent)
T
Tota l Rea d Cycle
1/f
a
MASTERCLOCK
applied to XTAL1 P in
ADM0/18
a
a
a
HZ
HZ
NCE0/7
NWE
NOE
Twz
HZ
HZ
Ts
Th
Note : S e e
MBL De finition
Symbol
5464-35.EPS
DM0/15 from
S RAM Circuit
Each s igna l de livere d by the MHDLC
is high impeda nce outside this time
Parameter
T
Delay between Data Strobe delivered by the mP and beginning of
cycle
1/f
f: Masterclock frequency
Min.
Typ.
Max.
Unit
2/f
Total read cycle: Twz + 1/f
a
Twz
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
20
NOE width
1/f
Ts
Set-up Time Data /NOE Rising Edge
20
Th
Hold Time Data /NOE Rising Edge
0
44/83
ns
4/f
ns
ns
1/f
ns
STLC5464
VI - MEMORY TIMING (continued)
Figure 34 : Static Memory Write Signals from the Multi-HDLC
NDS from µP
(or equivalent)
T
1/f
a
a
MASTERCLOCK
applied to XTAL1 Pin
ADM0/18
Total Write Cycle
a
a
a
HZ
HZ
Tuv
NCE0/7
NWE
NOE
DM0/15
HZ
Symbol
Parameter
T
Delay between Data Strobe delivered by the µP and beginning of
cycle
1/f
f : Masterclock frequency
a
Delay between Masterclock and Edge of each signal delivered by the
MHDLC (30pF)
Tuv
NCE width
HZ
Each signal delivered by the MHDLC
is high impedance outside this time
Min.
5464-36.EPS
Note : See
MBL Definition
Typ.
Max.
Unit
2/f
20
1/f
ns
4/f
ns
Note : Total Write Cycle : Tuv + 1/f
45/83
STLC5464
VII - MICROPROCESSOR TIMING
VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2=0
Figure 35 : ST9 Read Cycle
NCS0/1
t1
t2
t3
READY
t4
NAS/ALE
t12
t11
NDS/NRD
t5
t6
AD0/7
A0/7
t7
t8
D0/7
R/W / NWR
Symbol
5464-37.EPS
t10
t9
Parameter
Min.
Typ.
Max.
Delay Ready / Chip Select (if t3 > t1), (30pF)
0
t2
Hold Time Chip Select /Data Strobe
14
t3
Delay Ready / NAS (if t1 > t3), (30pF)
0
t4
Width NAS
20
ns
t5
Set-up Time Address / NAS
9
ns
t6
Hold Time Address / NAS
9
ns
t7
Data Valid before Ready
0
ns
t8
Data Valid after Data Strobe (30pF)
0
ns
t9
Set-up Time R/W /NAS
15
ns
t10
Hold Time R/W / Data Strobe
15
ns
t11
Width NDS when immediate access
50
ns
t12
Delay NDS / NCS
5
ns
46/83
30
Unit
t1
ns
ns
30
ns
STLC5464
VII - MICROPROCESSOR TIMING (continued)
Figure 36 : ST9 Write Cycle
NCS0/1
t1
t2
t3
READY
t4
NAS/ALE
t12
t11
NDS/NRD
t7
t5
t8
t6
AD0/7
D0/7
A0/7
t10
5464-38.EPS
t9
R/W / NWR
Symbol
Parameter
Min.
Typ.
Max.
30
Unit
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
0
t2
Hold Time Chip Select / Data Strobe
14
ns
t3
Delay Ready / NAS (if t1 > t3), (30pF)
0
t4
Width NAS
20
ns
t5
Set-up Time Address / NAS
9
ns
t6
Hold Time Address / NAS
9
ns
t7
Set-up Time Data / Data Strobe
-15
ns
t8
Hold Time Data / Data Strobe
15
ns
ns
30
ns
t9
Set-up Time R/W / NAS
15
ns
t10
Hold Time R/W / Data Strobe
15
ns
t11
Width NDS when immediate access
50
ns
t12
Delay NDS / NCS
5
ns
47/83
STLC5464
VII - MICROPROCESSOR TIMING (continued)
VII.2 - 80C188 MOD0=1, MOD1=1, MOD2=0
Figure 37 : 80C188 Read Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
t6
AD0/7
A0/7
t7
t8
D0/7
5464-39.EPS
t5
R/W / NWR
Symbol
Parameter
Min.
Typ.
Max.
Unit
20
ns
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
0
t2
Hold Time Chip Select / NRD
10
t3
Delay Ready / ALE (if t1 > t3), (30pF)
0
t4
Width ALE
20
ns
t5
Set-up Time Address / ALE
5
ns
t6
Hold Time Address / ALE
5
ns
t7
Data Valid before Ready
0
ns
t8
Data Valid after NRD (30pF)
0
ns
t12
Delay NDS / NCS
0
ns
48/83
ns
20
ns
STLC5464
VII - MICROPROCESSOR TIMING (continued)
Figure 38 : 80C188 Write Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
AD0/7
D0/7
A0/7
t7
R/W / NWR
Symbol
t8
t6
5464-40.EPS
t5
Parameter
Min.
Typ.
Max.
Unit
20
ns
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
0
t2
Hold Time Chip Select / NWR
10
t3
Delay Ready / ALE (if t1 > t3), (30pF)
0
t4
Width ALE
20
ns
t5
Set-up Time Address / ALE
5
ns
t6
Hold Time Address / ALE
5
ns
t7
Set-up Time Data / NWR
-15
ns
t8
Hold Time Data / NWR
15
ns
t12
Delay NWR / NCS
0
ns
ns
20
ns
49/83
STLC5464
VII - MICROPROCESSOR TIMING (continued)
VII.3 - 80C186 MOD0=1, MOD1=1, MOD2=1
Figure 39 : 80C186 Read Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
t5
t6
AD0/15
t7
t8
D0/15
A0/15
R/W / NWR
t10
NBHE
A16/19
NBHE A16/19
Symbol
Parameter
t11
5464-41.EPS
t9
NBHE
Min.
Typ.
Max.
Unit
20
ns
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
0
t2
Hold Time Chip Select / NRD
10
t3
Delay Ready / ALE (if t1 > t3), (30pF)
0
t4
Width ALE
20
ns
t5
Set-up Time Address / ALE
5
ns
t6
Hold Time Address / ALE
5
ns
t7
Data Valid before Ready
-15
ns
t8
Data Valid after NRD (30pF)
0
ns
t9
Set-up Time NBHE-Address A16/19 / ALE
5
ns
t10
Hold Time Address A1619 / NRD
10
ns
t11
Hold Time NBHE- / NRD
10
ns
t12
Delay NRD / NCS
0
ns
50/83
ns
20
ns
STLC5464
VII - MICROPROCESSOR TIMING (continued)
Figure 40 : 80C186 Write Cycle
NCS0/1
t1
t2
READY
t3
t4
NAS/ALE
NDS/NRD
t12
t5
AD0/15
t8
t6
D0/15
A0/15
t7
R/W / NWR
NBHE A16/19
Symbol
t10
NBHE
A16/19
Parameter
t11
5464-42.EPS
t9
NBHE
Min.
Typ.
Max.
Unit
20
ns
t1
Delay Ready / Chip Select (if t3 > t1), (30pF)
0
t2
Hold Time Chip Select / NWR
10
t3
Delay Ready / ALE (if t1 > t3), (30pF)
0
t4
Width ALE
20
ns
t5
Set-up Time Address / ALE
5
ns
t6
Hold Time Address / ALE
5
ns
t7
Set-up Time Data / NWR
-15
ns
t8
Hold Time Data / NWR
15
ns
t9
Set-up Time NBHE-Address A16/19 / ALE
5
ns
t10
Hold Time Address 16/19 / ALE
10
ns
t11
Hold Time NBHE- / NWR
10
ns
t12
Delay NWR / NCS
0
ns
ns
20
ns
51/83
STLC5464
VII - MICROPROCESSOR TIMING (continued)
VII.4 - 68000 MOD0=0, MOD1=0, MOD2=1
Figure 41 : 68000 Read Cycle
NCS0/1
t1
NDTACK
t2
t3
t12
t4
NAS/ALE
SIZE0/NLDS
SIZE1/NUDS
t6
t5
A1/23
R/W / NWR
A1/23
t8
5464-43.EPS
t7
D0/15
Symbol
t1
Parameter
Min.
Typ.
Max.
Unit
30
ns
ns
14
ns
0
30
ns
ns
30
ns
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
0
t2
Hold Time Chip Select / NLDS-NUDS
t3
Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
t4
Delay NDTACK / NLDS-NUDS Rising Edge
0
t5
Set-up Time Address / NAS
9
ns
t6
Hold Time Address / NLDS-NUDS
9
ns
t7
Data Valid before NDTACK Falling Edge (30pF)
0
ns
t8
Data Valid after NLDS-NUDS Rising Edge (30pF)
0
ns
t12
Delay NDS / NCS
0
ns
52/83
STLC5464
VII - MICROPROCESSOR TIMING (continued)
Figure 42 : 68000 Write Cycle
NCS0/1
t1
NDTACK
t2
t3
t12
t4
NAS/ALE
SIZE0/NLDS
SIZE1/NUDS
t6
t5
A1/23
R/W / NWR
A1/23
t9
5464-44.EPS
t10
D0/15
Symbol
t1
Parameter
Min.
Max.
Unit
30
ns
ns
14
ns
0
30
ns
ns
Delay NDTACK / NCS0/1 (if t3 > t1), (30pF)
Delay when immediate access
0
t2
Hold Time Chip Select / NLDS-NUDS
t3
Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF)
Delay when immediate access
Typ.
t4
Delay NDTACK / NLDS-NUDS Rising Edge
t5
Set-up Time Address / NAS
9
ns
ns
t6
Hold Time Address / NLDS-NUDS
9
ns
ns
t9
Set-up Time Data / NLDS-NUDS
15
t10
Hold Time Data / NLDS-NUDS
15
ns
t12
Delay NDS / NCS
0
ns
53/83
STLC5464
VII - MICROPROCESSOR TIMING (continued)
VII.5 - Token Ring Timing
Figure 43 : Token Ring
1/f
MASTER CLOCK
(applied to XTAL1 P in)
a
a
TRO
tH
5464-47.EPS
tS
TRI
Symbol
Parameter
Min.
1/f
f : Masterclock frequency
a
Delay between Masterclock Rising Edge and Edges of TRO Pulse
delivered by the MHDLC (10pF)
tS
Set-up Time TRI/Masterclock Masterclock Falling Edge
5
tH
Hold Time TRI/Masterclock Falling Edge
5
Typ.
Max.
32.768
Unit
MHz
25
ns
ns
0
ns
VII.6 - Master Clock Timing
Figure 44 : Master Clock
1/f
tH
5464-48.EPS
MASTER CLOCK
(applied to XTAL1 Pin)
tL
Symbol
f
Parameter
Masterclock Frequency
Min.
Typ.
Max.
Unit
30
32.768
33
MHz
30.3
30.5
33.3
1/f
Masterclock Period
tH
Masterclock High
12
ns
tL
Masterclock Low
12
ns
54/83
ns
STLC5464
VIII - INTERNAL REGISTERS
‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not
recommended.
‘Reserved’ bits are not implemented in the circuit. However, it is not recommended to use this address.
VIII.1 - Identification and Dynamic Command Register - IDCR (00)H
bit15
C15
C14
C13
C12
C11
C10
C9
bit8
bit7
C8
C7
bit 0
C6
C5
C4
C3
C2
C1
C0
When this register is read by the microprocessor, the circuit code C0/15 is returned. Reset has no effect
on this register.
C0/3 indicates the version.
C4/7 indicates the revision.
C8/11 indicates the foundry.
C12/15 indicates the type.
Example : this code is (0010)H for the first sample.
When this register is written by the microprocessor then :
bit15
Nu
Nu
Nu
Nu
Nu
Nu
Nu
bit8
bit7
Nu
Nu
bit 0
Nu
Nu
Nu
Nu
RSS
WDR
TL
TL
: TOKEN LAUNCH
When TL is set to 1 by the microprocessor, the token pulse is launched from the TRO pin (Token
Ring Output pin). This pulse is provided to the TRI pin (Token Ring Input pin) of the next circuit
in the applications where several Multi-HDLCs are connected to the same shared memory.
WDR : WATCHDOG RESET.
When the bit 1 (WDR) of this register is set to 1 by the microprocessor, the watchdog counter is
reset.
RSS : RESET SOFTWARE
When the bit 2 (RSS) of this register is set to 1 by the microprocessor, the circuit is reset (Same
action as reset pin).
After writing this register, the values of these three bits return to the default value.
VIII.2 - General Configuration - GCR (02)H
bit15
Nu
bit8
MBL
AFAB
SCL
BSEL SELB
CSD
HCL
bit7
SYN1 SYN0 D7
bit 0
EVM
TSV
TRD
PMA
WDD
After reset (0000)H
WDD
PMA
TRD
: Watch Dog Disable
WDD = 1, the Watch Dog is masked : WDO pin stays at ”0”.
WDD = 0, the Watch Dog generates an ”1” on WDO pin if the microprocessor has not reset the
Watch Dog during the duration programmed in Timer Register.
: Priority Memory Access
PMA = 1, if the token ring has been launched it is captured and kept in order to authorize
memory accesses.
PMA = 0, memory is accessible only if the token is present; after one memory access the token
is re-launched from TRO pin of the current circuit to TRI pin of the next circuit.
: Token Ring Disable
TRD = 1, if the token has been launched, the token ring is stopped and destroyed ; memory
accesses are not possible. The token will not appear on TRO pin.
TRD = 0, the token ring is authorized ; when the token will be launched,it will appearon TRO pin.
55/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
TSV
EVM
D7
: Time Stamping Validated
TSV = 1, the time stamping counter becomes a free binary counter and counts down from 65535
to 0 in step of 250ms (Total = 16384ms). So if an event occurs when the counter indicates A and
if the next event occurs when the counter indicates B then : t = (A-B) x 250ms is the time which
haspassedbetweenthe two eventswhich have beenstored in memoryby the InterruptController
(for Rx C/I and Rx MON CHANNEL only).
TSV = 0, the counter becomes a decimal counter.The Timer Register and this decimal counter
constitute a Watch Dog or a Timer.
: EXTERNAL VCXO MODE
EVM=1,VCXO Synchronization Counter is divided by 32.
EVM=0,VCXO Synchronization Counter is divided by 30.
: HDLC connected to MATRIX
D7 = 1, the transmit HDLC is connected to matrix input 7, the DIN7 signal is ignored.
D7 = 0, the DIN7 signal is taken into account by the matrix, the transmit HDLC is ignored by the
matrix.
SYN0/1: SYNCHRONIZATION
SYN0/1 : these two bits define the signal applied on FRAMEA/B inputs. For more details, see
”Synchronization signals delivered by the system. 7.1.
HCL
SYN1
SYN0
0
0
SYIinterface
Signal applied on FRAMEA/B inputs
0
1
GCI Interface (the signal defines the first bit of the frame)
1
0
Vstar Interface (the signal defines thrid bit of the frame)
1
1
Not used
: HIGH BIT CLOCK
This bit defines the signal applied on CLOCKA/B inputs.
HCL = 1, bit clock signal is at 8192kHz
HCL= 0, bit clock signal is at 4096kHz
CSD : Clock Supervision Deactivation
CSD = 1, the lack of selected clock is not seen by the microprocessor; INT1 is masked.
CSD = 0, when the selected clock disappears the INT1 pin goes to 5V, 250ms after this
disappearance.
SELB : SELECT B
SELB = 1, FRAME B and CLOCK B must be selected.
SELB = 0, FRAME A and CLOCK A must be selected.
BSEL : B SELECTED (this bit is read only)
BSEL = 1, FRAME B and CLOCK B are selected.
BSEL = 0, FRAME A and CLOCK A are selected.
SCL
: Single Clock
This bit defines the signal delivered by DCLK output pin.
SCL = 1, Data Clock is at 2048kHz.
SCL = 0, Data Clock is at 4096kHz.
AFAB : Advanced Frame A/B Signal
AFAB = 1, the advance of Frame A Signal and Frame B Signal is 0.5 bit time versus the signal
frame A (or B) drawn in Figure 27.
AFAB = 0, Frame A Signal and Frame B Signal are in accordance with the clock timing
(see : Synchronization signals delivered by the Figure 27).
56/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
MBL
: Memory Bus Low impedance
MBL = 1, the shared memory bus is at low impedance between two memory cycles.
The memory bus includes Control bits, Data bits, Address bits. One Multi-HDLC is connected to
the shared memory.
MBL = 0, the shared memory bus is at high impedance between two memory cycles.
Several Muti-HDLCs can be connected to the shared memory. One pull up resistor is
recommended on each wire.
VIII.3 - Input Multiplex Configuration Register 0 - IMCR0 (04)H
bit15
bit8
bit7
bit 0
LP3 DEL3 ST(3)1 ST(3)0 LP2 DEL2 ST(2)1 ST(2)0 LP1 DEL1 ST(1)1 ST(1)0 LP0 DEL0 ST(0)1 ST(0)0
After reset (0000)H
See definition in next Paragraph.
VIII.4 - Input Multiplex Configuration Register 1 - IMCR1 (06)H
bit15
bit8
bit7
bit 0
LP7 DEL7 ST(7)1 ST(7)0 LP6 DEL6 ST(6)1 ST(6)0 LP5 DEL5 ST(5)1 ST(5)0 LP4 DEL4 ST(4)1 ST(4)0
After reset (0000)H
ST(i)0 : STEP0 for each Input Multiplex i(0 ≤ i ≤ 7), delayed or not.
ST(i)1 : STEP1 for each Input Multiplex i(0 ≤ i ≤ 7), delayed or not.
DEL(i); : DELAYED Multiplex i(0 ≤ i ≤ 7).
DEL (i) ST (i) 1 ST (i) 2
STEP for each Input Multiplex 0/7 delayed or not
X
0
0
Each received bit is sampled at 3/4 bit-time without delay.
First bit of the frame is defined by Frame synchronization Signal.
1
0
1
Each received bit is sampled with 1/2 bit-time delay.
1
1
0
Each received bit is sampled with 1 bit-time delay.
1
1
1
Each received bit is sampled with 2 bit-time delay.
0
0
1
Each received bit is sampled with 1/2 bit-time advance.
0
1
0
Each received bit is sampled with 1 bit-time advance
0
1
1
Each received bit is sampled with 2 bit-time advance.
When IMTD = 0 (bit of SMCR), DEL = 1 is not taken into account by the circuit.
LP (i)
: LOOPBACK 0/7
LPi = 1, Output Multiplex i is put instead of Input Multiplex i (0 ≤ i ≤ 7). LOOPBACKis transparent
or not in accordance with OMVi (bit of Output Multiplex Configuration Register).
LPi = 0, Normal case, Input Multiplex i(0 ≤ i ≤ 7) is taken into account.
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.5 - Output Multiplex Configuration Register 0 - OMCR0 (08)H
bit15
bit8
bit7
bit 0
OMV3 DEL3 ST(3)1 ST(3)0 OMV2 DEL2 ST(2)1 ST(2)0 OMV1 DEL1 ST(1)1 ST(1)0 OMV0 DEL0 ST(0)1 ST(0)0
After reset (0000)H
See definition in next Paragraph.
57/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H
bit15
bit8
bit7
bit 0
OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0
After reset (0000)H
ST(i)0 : STEP0 for each Output Multiplex i(0 ≤ i ≤ 7), delayed or not.
ST(i)1 : STEP1 for each Output Multiplex i(0 ≤ i ≤ 7), delayed or not.
DEL(i); : DELAYED Multiplex i(0 ≤ i ≤ 7).
DEL (i) ST (i) 1 ST (i) 2
STEP for each Output Multiplex 0/7 delayed or not
X
0
0
Each bit is transmitted on the rising edge of the double clock without delay.
Bit 0 is defined by Frame synchronization Signal.
1
0
1
Each bit is transmitted with 1/2 bit-time delay.
1
1
0
Each bit is transmitted with 1 bit-time delay.
1
1
1
Each bit is transmitted with 2 bit-time delay.
0
0
1
Each bit is transmitted with 1/2 bit-time advance.
0
1
0
Each bit is transmitted with 1 bit-time advance
0
1
1
Each bit is transmitted with 2 bit-time advance.
When IMTD = 0 (bit of SMCR), DEL = 0 is not taken into account by the circuit.
OMV (i) : Output Multiplex Validated 0/7
OMVi =1, condition to have DOUTi pin active (0 ≤ i ≤ 7).
OMVi =0, DOUTi pin is High Impedance continuously (0 ≤ i ≤ 7).
N.B. If DIN4 and DIN5 are GCI Multiplexes : then ST(4)1 = ST(4)0 = 0 and ST(5)1 = ST(5)0 = 0 normally.
VIII.7 - Switching Matrix Configuration Register - SMCR (0C)H
bit15
Nu
Nu
Nu
Nu
Nu
Nu
Nu
bit8
bit7
Nu
Nu
bit 0
ME
SGC
SAV
SGV
TS1
TS0
IMTD
After reset (0000)H
IMTD
TS0
TS1
SGV
SAV
SGC
58/83
: Increased Minimum Throughput Delay
When SI = 0 (bit of CMDR, variable delay mode) :
IMTD = 1, the minimum delay through the matrixmemoryis three time slots whateverthe selected
TDM output.
IMTD = 0, the minimum delay through the matrix memory is two time slots whatever the selected
TDM output.
: Tristate 0
TS0 = 1, the DOUT0/3 and DOUT6/7 pins are tristate : ”0” is at low impedance, ”1” is at low
impedance and the third state is high impedance.
TS0 = 0, the DOUT0/3 and DOUT6/7 pins are open drain : ”0” is at low impedance, ”1” is at high
impedance.
: Tristate 1
TS1 = 1, the DOUT4/5 pins are tristate : ”0” is at low impedance, ”1” is at low impedance and
the third state is high impedance.
TS1 = 0, the DOUT4/5 pins are open drain : ”0” is at low impedance, ”1” is at high impedance.
: Pseudo Random Sequence Generator Validated
SGV = 1,PRS Generator is validated.The Pseudo Random Sequence is transmitted during the
related time slot(s).
SGV = 0, PRS Generator is reset.”0” are transmitted during the related time slot.
: Pseudo Random Sequence analyzer Validated
SAV = 1, PRS analyzer is validated.
SAV = 0, PRS analyzer is reset.
: Pseudo Random Sequence Generator Corrupted
When SGC bit goes from 0 to 1, one bit of sequence transmitted is corrupted.
When the corrupted bit has been transmitted, SGC bit goes from 1 to 0 automatically.
STLC5464
VIII - INTERNAL REGISTERS (continued)
ME
Nu
: MESSAGE ENABLE
ME = 1 The contents of Connection Memory is output on DOUT0/7 continuously.
ME = 0 The contents of Connection Memory acts as an address for the Data Memory.
: Not used.
VIII.8 - Connection Memory Data Register - CMDR (0E)H
CONTROL REGISTER (CTLR)
SOURCE REGISTER (SRCR)
bit15
Nu
PS
PRSA
PRSG
INS
OTSV LOOP
bit8
bit7
SI
IM2
bit 0
IM1
IM0
ITS 4 ITS 3 ITS 2 ITS 1 ITS 0
After reset (0000)H
This 16 bit register is constituted by two registers :
SOURCE REGISTER (SRCR) and CONTROL REGISTER (CTLR) respectively 8 bits and 7 bits.
SOURCE REGISTER (SRCR) has two use modes depending on CM (part of CMAR).
CM = 1, access to connection memory (read or write)
- PRSG = 0, ITS 0/4 and IM0/2 bits are defined hereafter :
ITS 0/4 : Input time slot 0/4 define ITSx with : 0 ≤ x ≤ 31;
IM0/2 : Input Time Division Multiplex 0/2 define ITDMp with : 0 ≤ p ≤ 7.
- PRSG = 1, the Pseudo Random Sequence Generator is validated, SRCR is not significant.
CM = 0, access to data memory (read only). SRC is the data register of the data memory.
CONTROL REGISTER (CTLR) defines each Output Time Slot OTSy of each Output Time Division Multiplex OTDMq :
SI
: SEQUENCE INTEGRITY
SI = 1, the delay is always : (31 - ITSx) + 32 + OTSy(constant delay).
SI = 0, the delay is minimum to pass through the data memory (variable delay).
LOOP : LOOPBACK per channelrelevant if two connectionshas been established (bidirectional or not).
LOOP = 1, OTSy, OTDMq is taken into account instead of ITSy, ITDMq.
OTSV = 1, transparentMode LOOPBACK.
OTSV = 0, not Transparent Mode LOOPBACK.
OTSV : OUTPUT TIME SLOT VALIDATED
OTSV = 1, OTSy OTDMq is enabled.
OTSV = 0, OTSy OTDMq is High Impedance.
(OTSy : Output Time slot with 0 ≤ y ≤ 31; OTDMq : Output Time Division Multiplex with 0 ≤ q ≤ 7).
INS
: INSERT
INS = 1 The transfer from PRS Generator or Connection Memory to DOUT0/7 is validated.
INS = 0 The transfer from Data Memory to DOUT0/7 is validated.
PRSG : Pseudo Random Sequence Generator
This bit has effect only if INS = 1.
If PRSG = 1, Pseudo Random Sequence Generator delivers eight bits belonging to the same
Sequence. Hyperchannel at n x 64 Kb/s is possible.
If PRSG = 0, Connection Memory delivers eight bits D0/7.
PRSA : Pseudo Random Sequence analyzer
If PRSA = 1, PRS analyzer is enabled during OTSy OTDMq and receives data :
INS = 0, data comes from Data Memory.
INS = 1 AND PRSG=1, Data comes from PRS Generator (Test Mode).
If PRSA = 0, PRS analyzer is disabled during OTSy OTDMq.
PS
: Programmable Synchronization
If PS = 1, Programmable Synchronization Signal Pin is at ”1” during the bit time defined by OTSy
and OTDMq.
For OTSy and OTDMq with y = q = 0, PSS pin is at ”1” during the first bit of the frame defined
by the Frame synchronization Signal (FS).
If PS = 0, PSS Pin is at ”0” during the bit time defined by OTSy and OTDMq.
59/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.9 - Connection Memory Address Register - CMAR (10)H
ACCESS MODE REGISTER (AMR)
bit15
Nu
DESTINATION REGISTER (DSTR)
bit8
Nu
TC
CACL CAC
Nu
CM
bit7
READ OM2
bit 0
OM1
OM0 OTS4 OTS3 OTS2 OTS1 OTS0
After reset (0800)H
This 16 bit register is constitutedby two registers : DESTINATIONREGISTER (DSTR) and ACCESSMODE
REGISTER (AMR) respectively 8 bits and 6 bits.
Remark : It is mandatory for this specific register to write successively :
- first DSTR
- then AMR
DESTINATION REGISTER (DSTR)
When DSTR Register is written by the microprocessor, a memory access is launched. DSTR has two use
modes depending on CM (bit of CMAR).
CM = 1, access to connection memory (read or write) ;
When CM = 1, OTS 0/4 and OM 0/2 bits are defined hereafter :
OTS 0/4 : Output time slot 0/4 define OTSy with : 0 ≤ y ≤ 31,
OM0/2 : Output Time Division Multiplex 0/2 define OTDMq with : 0 ≤ q ≤ 7.
- CAC = CACL = 0, DSTR is the Address Register of the Connection Memory;
- CAC or CACL = 1, DSTR is used to indicate the current address for the Connection Memory ; its contents
is assigned to the outputs.
CM = 0, access to data memory (read only) ;
- DSTR is the Address Register of the Data Memory; its contents is assigned to the inputs.
ACCESS MODE REGISTER (AMR)
READ : READ MEMORY
READ = 1, Read Connection Memory (or Data Memory in accordance with CM).
READ = 0, Write Connection Memory.
CM
: CONNECTION MEMORY
CM = 1, Write or Read Connection Memory in accordance with READ.
CM = 0, Read only Data Memory (READ = 0 has no effect).
CAC : CYCLICAL ACCESS
CAC = 1
if Write Connection Memory, an automatic data write from Connection Memory Data Register
(CMDR) up to 256 locations of ConnectionMemory occurs. The first address is indicated by the
register DSTR, the last is (FF)H.
if Read Connection Memory, an automatic transfer of data from the location indicated by the
register (DSTR) into Connection Memory Data Register (CMDR) after reading by the
microprocessor occurs. The last location is (FF)H.
CAC = 0, Write and Read Connection Memory in the normal way.
CACL : CYCLICAL ACCESS LIMITED
CACL = 1
If Write Connection Memory, an automatic data write from Connection Memory Data Register
(CMDR) up to 32 locations of Connection Memory occurs. The first location is indicated by OTS
0/4bits of the register (DSTR) related to OTDMq as defined by OM0/2 occurs. The last location
is q +1 F(H).
If Read Connection Memory, an automatic transfer of data from Connection Memory into
Connection Memory Data Register (CMDR) after reading this last by the microprocessor
occurs.The first location is indicated by OTS 0/4 bits of the register (DSTR) related to OTDMq
as defined by OM0/2. The last location is q +1 F(H).
CACL = 0, Write and Read Connection Memory in the normal way.
60/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
TC
: Transparent Connection
TC = 1, if READ = 0 :
CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR bits
are ignored (Destination and Source are identical). The contents of Input time slot i - Input
multiplex j is switched into Output time slot i - Output multiplex j.
CAC = 0 and CACL = 1. Up to 32 ”Transparent Connections” are set up.
CAC = 1 and CACL = 0. Up to 256 ”Transparent Connections” are set up.
TC = 0, Write and Read Connection Memory in the normal way.
VIII.10 - Sequence Fault Counter Register - SFCR (12)H
bit15
F15
F14
F13
F12
F11
F10
F9
bit8
bit7
F8
F7
bit 0
F6
F5
F4
F3
F2
F1
F0
After reset (0000)H
This register is read only.
When this register is read by the microprocessor, this register is reset (0000)H.
F0/15 : FAULT0/15
Number of faults detected by the Pseudo Random Sequence analyzer if the analyzer has been
validated and has recovered the receive sequence.
When the Fault Counter Register reaches (FFFF)H it stays at its maximum value.
VIII.11 - Time Slot Assigner Address Register - TAAR (14)H
bit15
TS4
TS3
TS2
TS1
TS0
READ
Nu
bit8
bit7
HDI
r
bit 0
e
s
e
r
v
e
d
After reset (0100)H
READ : READ MEMORY
READ = 1, Read Time slot Assigner Memory.
READ = 0, Write Time slot Assigner Memory.
TS0/4 : TIME SLOTS0/4
These five bits define one of 32 time slots in which a channel is set-up or not.
HDI
: HDLC INIT
HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset
within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except
CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner
Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4
bits of Time slot Assigner Address Register.
HDI = 0, Normal state.
N.B.
After software reset (bit 2 of IDCR Register) or pin reset the automate above-mentioned is working.
The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.
61/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.12 - Time Slot Assigner Data Register - TADR (16)H
bit15
V11
V10
V9
V8
V7
V6
V5
bit8
bit7
V4
V3
bit 0
V2
V1
CH4
CH3
CH2
CH1
CH0
After reset (0000)H
CH0/4 : CHANNEL0/4
These five bits define one of 32 channels associated to TIME SLOT defined by the previous
Register (TAAR).
V1/8 : VALIDATION
The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit
V9
: VALIDATION SUBCHANNEL
V 9 = 1, each V1/8 bit is taken into account once every 250ms.
In transmit direction, data is transmitted consecutively during the time slot of the current frame
and during the same time slot of the next frame.Id est.: the same data is transmitted in two
consecutive frames.
In receive direction, HDLC controller fetches data during the time slot of the current frame and
ignores data during the same time slot of the next frame.
V 9 = 0, each V1/8 bit is taken into account once every 125ms.
V10
: DIRECT MHDLC ACCESS
If V10 = 1, the Rx HDLC Controller receives data issued from DIN8 input during the current time
slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC
Controller.
If V10 = 0, the Rx HDLC Controller receives data issued from the matrix output 7 during the
current time slot ; DOUT6 output delivers data issued from the matrix output 6 during the same
current time slot.
N.B : If D7 = 1, (see ”General Configuration Register GCR (02)H”) the Tx HDLC controller is
connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e.
DOUT0 to DOUT7).
V11
: VALIDATION of CB pin
This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register).
if CSMA = 0 :
V11 = 1, Contention Bus pin is validated and Echo pin (which is an input) is not taken into
account.
V11 = 0, ContentionBus pin is high impedance during the current time slot (This pin is an open
drain output).
VIII.13 - HDLC Transmit Command Register - HTCR (18)H
bit15
CH4
CH3
CH2
CH1
CH0
READ
Nu
bit8
bit7
CF
PEN
bit 0
CSMA
After reset (0000)H
READ : READ COMMAND MEMORY
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
CH0/4 : These five bits define one of 32 channels.
62/83
NCRC
F
P1
P0
C1
C0
STLC5464
VIII - INTERNAL REGISTERS (continued)
C1/C0 : COMMAND BITS
P0/1
C1
C0
Commands Bits
0
0
ABORT ; if this command occurs during the current frame, HDLC Controller transmits seven ”1”
immediately, afterwards HDLC Controller transmits ”1” or flag in accordance with F bit, generates
an interrupt and waits new command such as START orn CONTINUE.
If this command occurs after transmitting a frame, HDLC Controller generates an interrupt and
waits a new command such as START or CONTINUE.
0
1
START ; Tx DMA Controller is now going to transfer first frame from buffer related to initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
1
0
CONTINUE ; Tx DMA Controller is now going to transfer next frame from buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already transmitted.
1
1
HALT ; after transmitting frame, HDLC Controller transmits ”1” or flag in accordance with F bit,
generates an interrupt and is waiting new command such as START or CONTINUE.
: PROTOCOL BITS
P1
P0
Transmission Mode
0
0
HDLC
0
1
Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.
1
0
Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.
1
1
Reserved
F
: Flag
F = 1 ; flags are transmitted betweenclosing flag of currentframe and opening flag of next frame.
F = 0 ; ”1” are transmitted between closing flag of current frame and opening flag of next frame.
NCRC : CRC NOT TRANSMITTED
NCRC = 1, the CRC is not transmitted at the end of the frame.
NCR C =0, the CRC is transmitted at the end of the frame.
CSMA : Carrier Sense Multiple Access with Contention Resolution
CSMA = 1, CB output and the Echo Bit are taken into account during this channel transmission
by the Tx HDLC.
CSMA = 0, CB output and the Echo Bit are defined by V11 (see ” Time slot Assigner Data
Register TADR (16)H”).
PEN : CSMA PENALTY significant if CSMA = 1
PEN = 1, the penalty value is 1 ; a transmitter which has transmitted a frame correctly will count
(PRI +1) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the buffer descriptor related to the frame.
PEN = 0, the penalty value is 2 ; a transmitter which has transmitted a frame correctly will count
(PRI +2) logic one received from Echo pin before transmitting next frame. (PRI, priority class 8
or 10 given by the transmit descriptor related to the frame).
CF
: Common flag
CF = 1, the closing flag of previous frame and opening flag of next frame are identical if the next
frame is ready to be transmitted.
CF = 0, the closing flag of previous frame and opening flag of next frame are distinct.
63/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.14 - HDLC Receive Command Register - HRCR (1A)H
bit15
CH4
CH3
CH2
CH1
CH0
READ
AR21
bit8
bit7
AR20
AR11
bit 0
AR10
CRC
Nu
P1
P0
C1
C0
After reset (0000)H
READ : READ COMMAND MEMORY
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
CH0/4 : These five bits define one of 32 channels.
C1/C0 : COMMAND
P0/1
CRC
C1
C0
Commands Bits
0
0
ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the
reception, generates an interrupt and waits new command such as START orn CONTINUE.
If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits
a new command such as START or CONTINUE.
0
1
START ; Rx DMA Controller is now going to transfer first frame into buffer related to the initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
1
0
CONTINUE ; Rx DMA Controller is now going to transfer next frame into buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already received.
1
1
HALT ; after receiving frame, HDLC Controller stops the reception, generates an interrupt and
waits a new command such as START or CONTINUE.
: PROTOCOL BITS
P1
P0
Transmission Mode
0
0
HDLC
0
1
Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.
1
0
Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.
1
1
Reserved
: CRC stored in external memory
CRC = 1, the CRC is stored at the end of the frame in external memory.
CRC = 0, the CRC is not stored into external memory.
AR10 : Address Recognition10
AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR.
If the first byte received and AF0/7 bits are not identical the frame is ignored.
AR10 = 0, First byte after openingflag of receivedframe is not compared to AF0/7 bits of AFRDR
Register.
AR11 : Address Recognition 11
AR11 = 1, First byte after opening flag of received frame is compared to all ”1”s.If the first byte
received is not all ”1”s the frame is ignored.
AR11 = 0, First byte after opening flag of received frame is not compared to all ”1”s.
AR20 : Address Recognition 20
AR20 = 1, Secondbyte after opening flag of receivedframe is comparedto AF8/15bits of AFRDR
Register. If the second byte received and AF8/15 bits are not identical the frame is ignored.
AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of
AFRDR Register.
64/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
AR21 : Address Recognition 21
AR21 = 1, Second byte after opening flag of received frame is compared to all ”1”s. If the
Second byte received is not all ”1”s the frame is ignored.
AR21 = 0, Second byte after opening flag of received frame is not compared to all ”1”s.
Second Byte
First Byte
AR21 AR20 AR11 AR10
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Conditions to Receive a Frame
Each frame is received without condition.
Only value of the first received byte must be equal to that of AF0/7 bits.
Only value of the first received byte must be equal to all ”1”s.
The value of the first received byte must be equal either to that of AF0/7 or
to all ”1”s.
Only value of the second received byte must be equal to that of AF8/15 bits.
The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal to that of AF8/15 bits.
The value of first received byte is must be equal to all ”1”s and the value of
second received byte must be equal to that of AF8/15 bits.
The value of the first received byte must be equal either to that of AF0/7 or
to all ”1”s and the value of the second received byte must be equal to that
of AF8/15 bits.
Only the value of the second received byte must be equal to all ”1”s.
The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal to all ”1”s.
The value of the first received byte must be equal to all ”1”s and the value of
the second received byte must be equal to ”1” also.
The value of the first received byte must be equal either to that of AF0/7 or
to ”1” and the value of the second received byte must be equal to all ”1”s.
The value of the second received byte must be equal either to that of AF8/15
or to all ”1”s.
The value of the first received byte must be equal to that of AF0/7 bits and
the value of the second received byte must be equal either to that of AF8/15
or to all ”1”s.
The value of the first received byte must be equal to ”1” and the value of the
second received byte must be equal either to that of AF8/15 or to all ”1”s.
The value of the first received byte must be equal either to that of AF0/7 or
to ”1” and the value of the second received byte must be equal either to that
of AF8/15 or to all ”1”s.
VIII.15 - Address Field Recognition Address Register - AFRAR (1C)H
bit15
CH4
CH3
CH2
CH1
CHO
READ
Nu
bit8
bit7
Nu
r
bit 0
e
s
e
r
v
e
d
After reset (0000)H
The write operation is lauched when AFRAR is written by the microprocessor.
READ : READ ADDRESS FIELD RECOGNITION MEMORY
READ=1, READ AFR MEMORY.
READ=0, WRITE AFR MEMORY.
CH0/4 : These five bits define one of 32 channels in reception
65/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H
bit15
AF15
AF14 AF13 AF12 AF11 AF10
AF9
bit8
bit7
AF8
AF7
bit 0
AF6
AF5
AF4
AF3
AF2
AF1
AF0
After reset (0001)H
AF0/15 : ADDRESS FIELD BITS
AF0/7 ; First byte received; AF8/15: Second byte received.
These two bytes are stored into Address Field Recognition Memory when AFRAR is written by
the microprocessor.
VIII.17 - Fill Character Register - FCR (20)H
bit15
r
e
s
e
r
v
e
bit8
bit7
d
FC7
bit 0
FC6
FC5
FC4
FC3
FC2
FC1
FC0
After reset (0000)H
FC0/7 : FILL CHARACTER (eight bits)
In TransparentMode M1, twomessages are separatedby FILLCHARACTERS andthe detection
of one FILL CHARACTER marks the end of a message.
VIII.18 - GCI Channels Definition Register 0 - GCIR0 (22)H
The definitions of x and y indices are the same for GCIR0, GCIR1, GCIR2, GCIR3 :
- 0 ≤ x ≤ 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5
- y = 0, TDM4 is selected
- y = 1, TDM5 is selected.
bit15
bit8
bit7
bit 0
ANA11 VCI11 V*11 VM11 ANA10 VCI10 V*10 VM10 ANA01 VCI01 V*01 VM01 ANA00 VCI00 V*00 VM00
TDM5
TDM4
TDM5
GCI CHANNEL 1
TDM4
GCI CHANNEL 0
After reset (0000)H
VMxy : VALIDATION of MONITOR CHANNELx, MULTIPLEX y :
When this bit is at 1, monitor channel xy is validated.
When this bit is at 0, monitor channel xy is not validated.
On line to reset (if necessary)one MON channel which had been selectedpreviously VMxy must
be put at 0 during 125ms before reselecting this channel. Deselecting one MON channel during
125ms resets this MON channel.
V*xy : VALIDATION of V Starx, MULTIPLEX y
When this bit is at 1, V Star protocol is validated if VMxy=1.
When this bit is at 0, GCI Monitor protocol is validated if VMxy=1.
VCxy : VALIDATION of Command/Indicate CHANNEL x, MULTIPLEXy
When this bit is at 1, Command/Indicate channelxy is validated.
When this bit is at 0, Command/Indicate channelxy is not validated.
It is necessary to let VCxy at ”0” during 125ms to initiate the Command/Indicate channel.
ANAxy : ANALOG APPLICATION
When this bit is at 1, Primitive has 6 bits if C/Ixy is validated.
When this bit is at 0, Primitive has 4 bits if C/Ixy is validated.
66/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.19 - GCI Channels Definition Register 1 - GCIR1 (24)H
bit15
bit8
bit7
bit 0
ANA31 VCI31 V*31 VM31 ANA30 VCI30 V*30 VM30 ANA21 VCI21 V*21 VM21 ANA20 VCI20 V*20 VM20
TDM5
TDM4
TDM5
GCI CHANNEL 3
TDM4
GCI CHANNEL 2
After reset (0000)H
For definition see GCI Channels Definition Register above.
VIII.20 - GCI Channels Definition Register 2 - GCIR2 (26)H
bit15
bit8
bit7
bit 0
ANA51 VCI51 V*51 VM51 ANA50 VCI50 V*50 VM30 ANA41 VCI41 V*41 VM41 ANA40 VCI40 V*40 VM40
TDM5
TDM4
TDM5
GCI CHANNEL 5
TDM4
GCI CHANNEL 4
After reset (0000)H
For definition see GCI Channels Definition Register above.
VIII.21 - GCI Channels Definition Register 3 - GCIR3 (28)H
bit15
bit8
bit7
bit 0
ANA71 VCI71 V*71 VM71 ANA70 VCI70 V*70 VM70 ANA61 VCI61 V*61 VM61 ANA60 VCI60 V*60 VM60
TDM5
TDM4
TDM5
GCI CHANNEL 7
TDM4
GCI CHANNEL 6
After reset (0000)H
For definition see GCI Channels Definition Register above.
67/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H
bit15
0
G0
CA2
CA1
CA0
READ
0
bit8
bit7
0
Nu
bit 0
Nu
C6
C5
C4
C3
C2
C1
After reset (00FF)H
When this register is written by the microprocessor, these different bits mean :
READ : READ C/I MEMORY
READ = 1, READ C/I MEMORY.
READ = 0, WRITE C/I MEMORY.
CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS
CA 0/2 : These bits define one of eight Command/Indicate Channels.
G0
: This bit defines one of two GCI multiplexes.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
C6/1 : New Primitive to be transmitted
C6 is transmitted first if ANA = 1.
C4 is transmitted first if ANA = 0.
The New Primitive is taken into account by the transmitter after writing bits 8 to 15 (if 8 bit microprocessor).
Transmit Command/Indicate Register (after reading)
bit15
0
G0
CA2
CA1
CA0
READ
Nu
bit8
bit7
Nu
PT1
bit 0
PT0
C6
C5
When this register is read by the microprocessor, these different bits mean :
READ : READ C/I MEMORY
READ = 1, READ C/I MEMORY.
READ = 0, WRITE C/I MEMORY.
CA 0/2 : TRANSMIT C/I ADDRESS
CA 0/2 : These bits define one of eight Command/Indicate Channels.
G0
: This bit defines one of two GCI multiplexes.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
C6/1 : Last Primitive transmitted.
PT0/1 : Status bits
68/83
P1
P0
Primitive Status
0
0
Primitive has not been transmitted yet.
0
1
Primitive has been transmitted once.
1
0
Primitive has been transmitted twice.
1
1
Primitive has been transmitted three times or more.
C4
C3
C2
C1
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.23 - Transmit Monitor Address Register - TMAR (2C)H
bit15
0
G0
MA2
MA1
MA0
READ
Nu
bit8
bit7
Nu
Nu
bit 0
Nu
TIV
FABT
L
NOB
0
Nu
After reset (000F)H
When this register is written by the microprocessor, these different bits mean :
READ : READ MON MEMORY
READ=1, READ MON MEMORY.
READ=0, WRITE MON MEMORY.
MA 0/2 : TRANSMIT MONITOR ADDRESS
MA 0/2 :These bits define one of eight Monitor Channel if validated.
G0
: This bit defines one of two GCI multiplexes.
G0 = 0, TDM4 is selected.
G0 = 1, TDM5 is selected.
NOB : NUMBER OF BYTE to be transmitted
NOB = 1, One byte to transmit.
NOB = 0, Two bytes to transmit.
L
: Last byte
L = 1, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is the last.
L = 0, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is not the
last.
FABT : FABT = 1, the current message is aborted by the transmitter.
TIV
: Timer interrupt is Validated
TIV = 1, Time Out alarm generates an interrupt when the timer has expired.
TIV = 0, Time Out alarm is masked.
If 8 bit microprocessor the Data (TMDR Register) is taken into account by the transmitter after writing bits
8 to 15 of this register.
Transmit Monitor Address Register (after reading)
bit15
0
G0
MA2
MA1
MA0
READ
Nu
bit8
bit7
Nu
Nu
bit 0
Nu
TO
ABT
L
NOBT EXE
IDLE
When this register is read by the microprocessor, these different bits mean :
READ, MA0/2, G0 have same definition as already described for the write register cycle.
IDLE
EXE
: When this bit is at ”1”, IDLE (all 1’s) is transmitted during the channel validation.
: EXECUTED
When this status bit is at ”1”, the command written previously by the microprocessor has been
executed and a new word can be stored in the Transmit Monitor Data Register (TMDR) by the
microprocessor.
When this bit is at ”0”, the command written previously by the microprocessor has not yet been
executed.
NOBT : NUMBER OF BYTE which has been transmitted.
NOBT = 1, the first byte is transmitting.
NOB T = 0, the second byte is transmitting, the first byte has been transmitted.
L
: Last byte ; this L bit is the L bit which has been written by the microprocessor.
ABT
: ABORT
ABT=1, the remote receiver has aborted the current message.
TO
: Time Out one millisecond
TO = 1, the remote receiver has not acknowledged the byte which has been transmitted one
millisecond ago.
69/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.24 - Transmit Monitor Data Register - TMDR (2E)H
bit15
M18
M17
M16
M15
M14
M13
M12
bit8
bit7
M11
M08
bit 0
M07
M06
M05
M04
M03
M02
M01
After reset (FFFF) H
M08/01 : First Monitor Byte to transmit. M08 bit is transmitted first.
M18/11 : Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first.
VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H
bit15
MI71
TDM5
MI61
MI51
MI41
MI31
MI21
MI11
bit8
bit7
MI01
MI70
TDM4
MI60
MI50
MI40
MI30
bit 0
MI20
MI10
MI00
After reset (0000)H
When the microprocessor read this register, this register is reset (0000)H.
MIxy
: Transmit Monitor Channel x Interrupt, Multiplex y with :
0 ≤ x ≤ 7, 1 of 8 GCI CHANNELS belonging to the same multiplex TDM4 or TDM5
y = 0, GCI CHANNEL belongs to the multiplex TDM4 and y = 1 to TDM5.
MIxy = 1 when :
- a word has been transmitted and pre-acknowledged by the Transmit Monitor Channel xy (In
this case the Transmit Monitor Data Register (TMDR) is available to transmit a new word) or
- the message has been aborted by the remote receive Monitor Channel or
- the Timer has reached one millisecond (in accordancewith TIV bit of TMAR) by IM3 bit of IMR.
When MIxy goes to ”1”, the Interrupt MTX bit of IR is generated. Interrupt MTX can be masked.
VIII.26 - Memory Interface Configuration Register - MICR (32)H
bit15
P41
P40
P31
P30
P21
P20
P11
bit8
bit7
P10
Z
bit 0
W
V
U
T
S
R
REF
After reset (E400)H
REF
: MEMORY REFRESH
REF = 1, DRAM REFRESH is validated,
REF = 0, DRAM REFRESH is not validated.
R,S,T : These three bits define the external RAM circuit organization (1word=2bytes)
The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 pin).
T
0
0
0
0
1
1
S
0
0
1
1
0
0
R
0
1
0
1
0
1
If refresh
128K x 8 SRAM circuit (up to 512K words)
512K x 8 SRAM circuit (up to 512K words)
256K x 16 DRAM circuit (up to 1M word)
1M x 4 (or 16) bits DRAM circuit (up to 4M words)
4M x 4 (or 16) bits DRAM circuit (up to 8M words)
101 to 111 not used (this writting is forbidden)
512 cycles / 8ms
1024 cycles / 16ms
2048 cycles / 32ms
The cycle duration is always 15.625ms (512 periods of the clock applied on XTAL1 Pin).
70/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
U,V,W,Z : These four bits define the different signals delivered by the MHDLC.
First Case : the external RAM circuit is DRAM (T = 1 or S = 1)
- U defines the time Tu comprised between beginning of cycle and falling edge of NRAS :
U = 1, Tu = 60ns - U = 0, Tu = 30ns
- V defines the time Tv comprised between falling edge of NRAS and falling edge of NCAS :
V = 1, Tv = 60ns - V = 0, Tv = 30ns
- W defines the time Tw comprised between falling edge of NCAS and rising edge of NCAS :
W = 1, Tw = 60ns - W = 0, Tw = 30ns
- Z defines the time Tz comprised between rising edge of NCAS and end of cycle :
Z = 1, Tz = 60ns - Z = 0, Tz = 30ns
The total cycle is Tu + Tv + Tw + Tz.
The different output signals are high impedance during 15ns before the end of each cycle.
Second Case : the external RAM circuit is SRAM (T = 0 or S = 0)
- U and V define a part of write cycle for SRAM : the time Tuv comprised between falling edge
and rising edge of NCE. The total of write cycle is : 15ns+Tuv + 15ns.
V
0
0
1
1
U
0
1
0
1
Tuv
30ns
60ns
90ns
120ns
- W and Z define a part of read cycle for SRAM : the time Twz comprised between falling edge
of NOE and rising edge of NOE. The total of read cycle is : Twz +30ns
Z
0
0
1
1
W
0
1
0
1
Twz
30ns
60ns
90ns
120ns
N.B. The different output signals are high impedance during 15ns before the end of each cycle. On the outside of each (DRAM
or SRAM) cycle all the outputs are high impedance or not in accordance with MBL bit (see ”MBL : Memory Bus Low
impedance”).
Memory
bit15
bit8
P4E1 P4E0 P3E1 P3E0 P2E1 P2E0 P1E1 P1E0
bit7
Z
bit 0
W
V
U
T
S
R
REF
After reset (E400)H
P1 E0/1 : PRIORITY 1 for entity defined by E0/1
P2 E0/1 : PRIORITY 2 for entity defined by E0/1
P3 E0/1 : PRIORITY 3 for entity defined by E0/1
P4 E0/1 : PRIORITY 4 for entity defined by E0/1
Entity definition :
E1
0
0
1
1
E0
0
1
0
1
Entity
Rx DMA Controller
Microprocessor
Tx DMA Controller
Interrupt Controller
71/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
PRIORITY 5 is the last priority for DRAM Refresh if validated. DRAM Refresh obtains PRIORITY 0 (the
first priority) automatically when the first half cycle is spend without access to memory.
After reset (E400)H , the Rx DMA Controller has the PRIORITY 1
the Microprocessor has the PRIORITY 2
the Tx DMA Controller has the PRIORITY 3
the Interrupt Controller has the PRIORITY 4
the DRAM Refresh has the PRIORITY 5
VIII.27 - Initiate Block Address Register - IBAR (34)H
bit15
A23
A22
A21
A20
A19
A18
A17
bit8
bit7
A16
A15
bit 0
A14
A13
A12
A11
A10
A9
A8
After reset (0000)H
A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the
external memory).The offset is zero (A0 to A7 =”0”).
The Initiate Block Address (IBA) is :
23
8
7
0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 0 0
The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.)
The least significant bit defines one of two bytes when the microprocessor selects one byte.
VIII.28 - Interrupt Queue Size Register - IQSR (36)H
bit15
r
e
s
e
r
v
bit8
bit7
d
HS2
e
bit 0
HS1
HS0
MS2
MS1
MS0
CS1
CS0
After reset (0000)H
CS0/1 : Command/Indicate Interrupt Queue Size
These two bits define the size of Command/Indicate Interrupt Queue in external memory.
The location is IBA + 256 + HDLC Queue size + Monitor Channel Queue Size (see The Initiate
Block Address (IBA)).
MS0/2 : Monitor Channel Interrupt Queue Size
These three bits define the size of Monitor Channel Interrupt Queue in external memory.
The location is IBA + 256 + HDLC Queue size.
HS0/2 : HDLC Interrupt Queue Size
These three bits define the size of HDLC status Interrupt Queue in external memory for each
channel.
The location is IBA+256 (see The Initiate Block Address (IBA))
72/83
HS2
HS1
HS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HDLC
Queue Size
128 words
256 words
384 words
512 words
640 words
768 words
896 words
1024 words
MS2
MS1
MS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MON
Queue Size
128 words
256 words
384 words
512 words
640 words
768 words
896 words
1024 words
CS1
CS0
0
0
1
1
0
1
0
1
C/I
Queue Size
64 words
128 words
192 words
256 words
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.29 - Interrupt Register - IR (38)H
bit15
Nu
bit8
Nu
SFCO PRSR
TIM
bit7
INT
INT
Tx
Tx
FOV FWAR FOV FWAR
bit 0
Rx
FOV
Rx
ICOV
FWAR
MTX MRX C/IRX HDLC
After reset (0000)H
This register is read only.
When this register is read by the microprocessor, this register is reset (0000)H.
If not masked, each bit at ”1” generates ”1” on INT0 pin.
HDLC
: HDLC INTERRUPT
HDLC = 1, Tx HDLC or Rx HDLC has generated an interrupt The status is in the HDLC
queue.
C/IRX
: Command/Indicate Rx Interrupt
C/IRX = 1, Rx Commande/Indicate has generated an interrupt. The status is in the HDLC
queue.
MRX
: Rx MONITOR CHANNEL INTERRUPT
MRX = 1, one Rx MONITOR CHANNEL has generated an interrupt.The status is in the Rx
Monitor Channel queue.
MTX
: Tx MONITOR CHANNEL INTERRUPT
MTX = 1, one or several Tx MONITOR CHANNELS have generated an interrupt. Transmit
Monitor Interrupt Register (TMIR) indicates the Tx Monitor Channels which have generated
this interrupt.
ICOV
: INTERRUPT CIRCULAR OVERLOAD
ICOV = 1, One of three circular interrupt memories is completed.
RxFWAR : Rx DMA CONTROLLER FIFO WARNING
RxFWAR = 1, Rx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed.
RxFOV
: Rx DMA CONTROLLER FIFO OVERLOAD
RxFOV = 1, Rx DMA CONTROLLER has generatedan interrupt,it cannottransfer data from
Rx HDLC to external memory, its fifo is completed.
TxFWAR : Tx DMA CONTROLLER FIFO WARNING
TxFWAR = 1, Tx DMA CONTROLLER has generated an interrupt, its fifo is 3/4 completed.
TxFOV
: Tx DMA CONTROLLER FIFO OVERLOAD
TxFOV = 1, Tx DMACONTROLLER has generated an interrupt, it cannot transfer data from
Tx HDLC to external memory, its fifo is completed.
INTFWAR : INTERRUPT CONTROLLER FIFO WARNING
INTFWAR = 1, INTERRUPT CONTROLLER has generated an interrupt, its fifo is 3/4
completed.
INTFOV
: INTERRUPT CONTROLLER FIFO OVERLOAD
INTFOV = 1, INTERRUPT CONTROLLER has generated an interrupt, it cannot transfer
status from DMA and GCI controllers to external memory, its internal fifo is completed.
TIM
: TIMER
TIM = 1, the programmable timer has generated an interrupt.
PRSR
: Pseudo Random Sequence Recovered
PRSR = 1,the Pseudo Random Sequencetransmitted by the generatorhas been recovered
by the analyzer.
SFCO
: Sequence Fault Counter Overload
SFCO = 1, the Fault Counter has reached the value FFFF(H).
73/83
STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.30 - Interrupt Mask Register - IMR (3A)H
bit15
Nu
Nu
IM13
IM12
IM11
IM10
IM9
bit8
bit7
IM8
IM7
bit 0
IM6
IM5
IM4
IM3
IM2
IM1
IM0
MS3
MS2
MS1
MS0
MM1
MM0
After reset (FFFF) H
IM13/0 : INTERRUPT MASK 0/7
When IM0 = 1, HDLC bit is masked.
When IM1 =1, C/IRX bit is masked.
When IM2 = 1, MRX bit is masked.
When IM3 = 1, MTX bit is masked.
When IM4 = 1, ICOV bit is masked
When IM5 = 1, RxFWAR bit is masked.
When IM6 = 1, RxFOV bit is masked.
When IM7 = 1, TxFWAR bit is masked.
When IM8 = 1, TxFOV bit is masked.
When IM9 = 1, INTFWAR bit is masked.
When IM10 = 1, INTFOV bit is masked.
When IM11 = 1, TIM bit is masked.
When IM12 = 1, PRSR bit is masked.
When IM13 = 1, SFCO bit is masked.
VIII.31 - Time Register - TIMR (3C)H
bit15
S3
S2
S1
S0
MS9
MS8
MS7
bit8
bit7
MS6
MS5
0 to 5s
bit 0
MS4
0 to 999ms
0 to
3x0.25ms
After reset (0800)H id 512ms
This programmable register indicates the time at the end of which the Watch Dog delivers logic ”1” on the
pin WDO (which is an output) but only if the microprocessor does not reset the counter assigned (with the
help of WDR bit of IDCR Identification and Dynamic Command Register) during the time defined by the
Timer Register.
The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM)
is generated at each period defined by the Timer Register if the microprocessor does not reset the counter
with the help of WDR (bit of IDCR).
When TSV=1{Time Stamping Validated (GCR)} this programmable register is not used.
VIII.32 - Test Register - TR (3E)H
bit15
bit8
bit7
T15/0 : Test bits 0/15
These bits are reserved for the test of the circuit in production
74/83
bit 0
STLC5464
IX - EXTERNAL REGISTERS
These registers are located in shared memory. Initiate Block Address Register (IBAR) gives the Initiate
Block Address (IBA) in shared memory (see Register IBAR(34)H on Page 73).
‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not
recommended.
IX.1 - Initialization Block in External Memory
Descriptor Address
Channel
Address
T
CH 0
R
T
CH1
R
CH 2
to
CH30
IBA+00
IBA+02
IBA+04
IBA+06
IBA+08
IBA+10
IBA+12
IBA+14
bit15
bit8
Not used
bit7
bit0
TDA High
Transmit Descriptor Address (TDA Low)
Not used
RDA High
Receive Descriptor Address (RDA Low)
Not used
TDA High
Transmit Descriptor Address (TDA Low)
Not used
RDA High
Receive Descriptor Address (RDA Low)
IBA+16
to
IBA+246
T
CH 31
R
IBA+248
IBA+250
IBA+252
IBA+254
Not used
TDA High
Transmit Descriptor Address (TDA Low)
Not used
RDA High
Receive Descriptor Address (RDA Low)
When Direct Memory Access Controller receives Start from one of 64 channels, it reads initialization block
immediately to know the first address of the first descriptor for this channel.
Bit 0 of Transmit Descriptor Address (TDA Low) and bit 0 of Receive Descriptor Address (RDA Low), are
at ZERO mandatory. This Least Significant Bit is not used by DMA Controller, The shared memory is
always a 16 bit memory for the DMA Controller.
N.B. If several descriptors are used to transmit one frame then before transmitting frame, DMA Controller
stores the address of the first Transmit Descriptor Address into this Initialization Block.
75/83
STLC5464
IX - EXTERNAL REGISTERS (continued)
IX.2 - Receive Descriptor
This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory
size only.
15
14
RDA+00
13
12
IBC
EOQ
RDA+02
11
10
9
8
7
6
5
Not used
RDA+04
4
3
2
1
Size Of the Buffer (SOB)
0
0
RBA High (8 bits)
Receive Buffer Address Low (16 bits)
RDA+06
Not used
RDA+08
NRDA High (8 bits)
Next Receive Descriptor Address Low (16 bits)
RDA+10
FR
ABT
OVF
FCRC
Number of Bytes Received (NBR)
The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor
and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC
only during the frame reception and read by the microprocessor.
SOB : Size Of the Buffer associated to descriptor up to 2048 words (1 word = 2 bytes).
If SOB = 0, DMAC goes to next descriptor.
RBA : Receive Buffer Address. LSB of RBA Low is at Zero mandatory.
RDA : Receive Descriptor Address.
NRDA : Next Receive Descriptor Address. LSB of NRDA Low is at Zero mandatory.
NBR : Number of Bytes Received (up to 4096).
IX.2.1 - Bits written by the Microprocessor only
IBC
EOQ
: Interrupt if the buffer has been completed.
IBC=1, the DMAC generates an interrupt if the buffer has been completed.
: End Of Queue.
EOQ=1, the DMAC stops immediately its reception generates an interrupt (HDLC = 1 in IR) and
waits a command from the HRCR (HDLC Receive Command Register).
EOQ=0, the DMAC continues.
IX.2.2 - Bits written by the Rx DMAC only
FR
ABT
OVF
FCRC
Definition
1
0
0
0
The frame has been received without error. The end of frame is in this buffer.
1
0
0
1
The frame has been received with false CRC.
0
0
0
0
If NBR is different to 0, the buffer related to this descriptor is completed.The end
of frame is not in this buffer.
0
0
0
0
If NBR is equal to 0, the Rx DMAC is receiving a frame.
0
1
0
0
ABORT. The received frame has been aborted by the remote transmitter or the
local microprocessor.
0
1
1
0
OVERFLOW of FIFO. The received frame has been aborted.
0
1
0
1
The received frame had not an integer of bytes.
IX.2.3 - Receive Buffer
Each receive buffer is defined by its receive descriptor.
The maximum size of the buffer is 2048 words (1 word=2 bytes)
15
0
RBA
First Buffer Location
RBA + SOB-2
Last Location Available = Recive Buffer Address (RBA) + Size Of the Buffer (SOB-2)
76/83
STLC5464
IX - EXTERNAL REGISTERS (continued)
IX.3 - Transmit Descriptor
This transmit descriptor is located in shared memory. The quantity of descriptors is limited by the memory
size only.
TDA+00
15
14
13
12
BINT
BOF
EOF
EOQ
TDA+02
11
9
8
7
6
5
4
3
2
1
0
Number of Bytes to be Transmitted (NBT)
Not used
CRC PRI
C
TDA+04
TBA High (8 bits)
Transmit Buffer Address Low (16 bits)
TDA+06
Not used
TDA+08
TDA+10
10
NTDA High (8 bits)
Next Transmit Descriptor Address Low (16 bits)
CFT
ABT
UND
The 5 first words located in shared memory to TDA+00 from TDA+08 are written by the microprocessor
and read by the DMAC only. The 6th word located in shared memory in TDA+10 is written by the DMAC
only during the frame reception and read by the microprocessor.
NBT : Number of Bytes to be transmitted (up to 4096).
TBA
: Transmit Buffer Address. LSB of TBA Low is at Zero mandatory.
TDA : Transmit Descriptor Address.
NTDA : Next Transmit Descriptor Address. LSB of NTDA Low is at Zero mandatory.
IX.3.1 - Bits written by the Microprocessor only
BINT
: Interrupt at the end of the frame or when the buffer is become empty.
BINT = 1,
if EOF = 1 the DMAC generates an interrupt when the frame has been transmitted ;
if EOF = 0 the DMAC generates an interrupt when the buffer is become empty.
BINT = 0, the DMAC does not generate an interrupt during the transmission of the frame.
BOF : Beginning Of Frame
BOF = 1,the transmit bufferassociated to this transmit descriptor containsthe beginningof frame.
BOF = 0,the transmit buffer associated to this transmitdescriptor does not contain the beginning
of frame.
EOF : End Of Frame
EOF = 1,the transmit buffer associated to this transmit descriptor contains the end of frame.
EOF = 0,the transmit buffer associated to this transmit descriptor does not contain the end of
frame.
EOQ : End Of Queue
EOQ = 1, the DMAC stops immediately its transmission, generates an interrupt (HDLC = 1 in
IR) and waits a command from the HTCR (HDLC Transmit Command Register).
EOQ = 0, the DMAC continues.
CRCC : CRC Corrupted
CRCC = 1,at the end of this frame the CRC will be corrupted by the Tx HDLC Controller.
PRI
: Priority Class 8 or 10
PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8.
PRI = 0, if CSMA/CR is validated for this channel the priority class is 10.
(see Register CSMA)
77/83
STLC5464
IX - EXTERNAL REGISTERS (continued)
IX.3.2 - Bits written by the Rx DMAC only
CFT
ABT
UND
: Frame correctly transmitted
CFT = 1, the Frame has been correctly transmitted.
CFT = 0, the Frame has not been correctly transmitted.
: Frame Transmitting Aborted
ABT = 1, the frame has been aborted by the microprocessor during the transmission.
ABT = 0, the microprocessor has not aborted the frame during the transmission.
: Underrun
UND = 1, the transmit FIFO has not been fed correctly during the transmission.
UND = 0, the transmit FIFO has been fed correctly during the transmission.
IX.3.3 - Transmit Buffer
Each transmit buffer is defined by its transmit descriptor.
The maximum size of the buffer is 2048 words (1 word=2 bytes)
15
0
TBA
First Word to Transmit
TBA + x ;
NBT is odd : x = NBT - 1
NBT is even : x = NBT - 2
Last Word to Transmit
IX.4 - Receive & Transmit HDLC Frame Interrupt
bit15
NS
0
Tx
A4
A3
A2
A1
bit8
bit7
A0
0
bit 0
0
0
CFT/CFR
BE/BF
HALT
EOQ
RRLF/ERF
This word is located in the HDLC interrupt queue ; IQSR Register indicates the size of this HDLC interrupt
queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the status word of the frame
which has been transmitted or received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
Transmitter
Tx
: Tx = 1, Transmitter
A4/0 : Tx HDLC Channel 0 to 31
RRLF : Ready to Repeat Last Frame
In consequenceof event suchas Abort Command HDLC, Controller is waiting Start or Continue.
EOQ : End of Queue
The Transmit DMA Controller (or the Receive DMA Controller) has encountered the current
Descriptor with EOQ at ”1”. DMA Controller is waiting ”Continue” from microprocessor.
HALT : The TransmitDMAController hasreceivedHALT from the microprocessor; it is waiting”Continue”
from microprocessor.
BE
: Buffer Empty
If BINT bit of Transmit Descriptor is at ‘1’, the Transmit DMA Controller puts BE at ”1” when the
buffer has been emptied.
CFT
: Correctly Frame Transmitted
A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is
at ‘1’. CFT is located in the last descriptor if several descriptors are used to define a frame.
78/83
STLC5464
IX - EXTERNAL REGISTERS (continued)
Receiver
Tx
: Tx = 0, Receiver
A4/0 : Rx HDLC Channel 0 to 31
ERF : Error detected on Received Frame
An error such as CRC not correct, Abort, Overflow has been detected.
EOQ : End of Queue
The receive DMA Controller has encountered the current receive Descriptor with EOQ at ”1”.
DMA Controller is waiting ”Continue” from microprocessor.
HALT : The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the
microprocessor; it is waiting ”Continue” from the microprocessor.
BE
: Buffer Filled
If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMA Controller puts BF at”1” when it has
filled the current buffer with data from the received frame.
CFR : Correctly Frame Received
A receive frame is ended with a correct CRC. The end ofthe frame islocated in the last descriptor
if several Descriptors.
IX.5 - Receive Command / Indicate Interrupt
IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0
Time Stamping not validated (bit of GCR Register)
bit15
NS
Nu
Nu
Nu
G0
A2
A1
bit8
bit7
A0
Nu
bit 0
Nu
C6
C5
C4
C3
C2
C1
This word is located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
G0
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
A2/0 : COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1
C6/1 : New Primitive received twice consecutively
79/83
STLC5464
IX - EXTERNAL REGISTERS (continued)
IX.5.2 - Receive Command / Indicate Interrupt when TSV = 1
Time Stamping validated (bit of GCR Register)
bit15
bit8
bit7
NS
Nu
Nu
Nu
G0
A2
A1
A0
Nu
Nu
C6
C5
C4
C3
C2
bit 0
C1
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
These two words are located in the Command/Indicate interrupt queue ; IQSR Register indicates the size
of this interrupt queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
G0
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
A2/0 : COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1
C6/1 : New Primitive received twice consecutively
T15/0 : Binary counter value when a new primitive is occurred.
IX.6 - Receive Monitor Interrupt
IX.6.1 - Receive Monitor Interrupt when TSV = 0
TSV : Time Stamping not Validated (bit of GCR Register)
bit15
bit8
NS
M18
M17
M16
M15
G0
A2
A1
A0
M14
M13
M12
M11
bit7
M8
bit 0
M7
M6
M5
ODD
A
F
L
M4
M3
M2
M1
These two words are transferred into the Monitor interrupt queue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at ‘1’
when it writes the status of these two bytes which has been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
G0
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
L
: Last byte
L = 1, the following word containsthe Last byte of messageif ODD =1, the previous word contains
the Last byte of message if ODD = 0.
L = 0, the following word and the previous word does not contains the Last byte of message.
F
: First byte
F=1, the following word contains the First byte of message.
F=0, the following word does not contain the First byte of message.
A
: Abort
A=1, Received message has been aborted.
80/83
STLC5464
IX - EXTERNAL REGISTERS (continued)
ODD
: Odd byte number
ODD = 1, one byte has been written in the following word.
ODD = 0, two bytes have been written in the following word.
In case of V* protocol ODD,A,F,L bits are respectively 1,0,1,1.
M1/8 : New Byte received twice consecutively if GCI Protocol has been validated.
Byte received once if V* Protocol has been validated.
M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated.
This byte is at ”1” in case of V* protocol.
IX.6.2 - Receive Monitor Interrupt when TSV = 1
TSV : Time Stamping Validated (bit of GCR Register)
bit15
bit8
NS
G0
A2
A1
A0
bit7
bit 0
ODD
A
F
L
M18
M17
M16
M15
M14
M13
M12
M11
M8
M7
M6
M5
M4
M3
M2
M1
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
These four words are located in the Monitor interrupt queue ; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
: New Status.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at ‘1’
when it writes the status of these two bytes which has been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
G0
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
L
: Last byte
L = 1, the following word contains the Last byte of message.
L = 0, the Last byte of message is not the following word.
F
: First byte
F=1, the following word contains the First byte of message.
F=0, the First byte of message is not the following word.
A
: Abort
A=1, Received message has been aborted.
ODD : Odd byte number
ODD = 1, one byte has been written in the following word.
ODD = 0, two bytes have been written in the following word.
M1/8 : New Byte received twice consecutively if GCI Protocol has been validated.
Byte received once if V* Protocol has been validated.
M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated.
This byte is at ”1” in case of V* protocol.
T15/0 : Binary counter value when a new primitive is occurred.
81/83
STLC5464
PMPQF160.EPS
X - PACKAGE MECHANICAL DATA
160 PINS - PLASTIC QUAD FLAT PACK
A
A1
A2
B
C
D
D1
D3
e
E
E1
E3
L
L1
K
82/83
Min.
0.25
3.17
0.22
0.13
30.95
27.90
30.95
27.90
0.65
Millimeters
Typ.
3.42
31.20
28.00
25.35
0.65
31.20
28.00
25.35
0.80
1.60
Max.
4.07
Min.
3.67
0.38
0.23
31.45
28.10
0.010
0.125
0.009
0.005
1.219
1.098
31.45
28.10
1.219
1.098
0.95
0.026
0o (Min.), 7o (Max.)
Inches
Typ.
0.135
1.228
1.102
0.998
0.026
1.228
1.102
0.998
0.0315
0.063
Max.
0.160
0.144
0.015
0.009
1.238
1.106
1.238
1.106
0.0374
PQFP160.TBL
Dimensions
STLC5464
Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1997 SGS-THOMSON Microelectronics - All Rights Reserved
2
Purchase of I C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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83/83