STMICROELECTRONICS TEA6415CD

TEA6415C
BUS-CONTROLLED VIDEO MATRIX SWITCH
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20MHz BANDWIDTH
CASCADABLE WITH ANOTHER TEA6415C
(INTERNAL ADDRESS CAN BE CHANGED BY
PIN 7 VOLTAGE)
8 INPUTS (CVBS, RGB, MAC, CHROMA, ...)
6 OUTPUTS
POSSIBILITY OF MAC OR CHROMA SIGNAL
FOR EACH INPUT BY SWITCHING-OFF THE
CLAMP WITH AN EXTERNAL RESISTOR
BRIDGE
BUS CONTROLLED
6.5dB GAIN BETWEEN ANY INPUT AND OUTPUT
-55dB CROSSTALK AT 5MHz
FULLY ESD PROTECTED
DIP20
(Plastic Package)
ORDER CODE : TEA6415C
DESCRIPTION
The main function of the TEA6415C is to switch 8
video input sources on the 6 outputs.
Each output can be switched to only one of the
inputs whereas but any same input may be connected to several outputs.
All the switching possibilities are controlled through
the I2C bus.
SO20
(Plastic Micropackage)
ORDER CODE : TEA6415CD
INPUT
1
20
INPUT
DATA
2
19
GROUND
INPUT
3
18
OUTPUT
CLOCK
4
17
OUTPUT
INPUT
5
16
OUTPUT
INPUT
6
15
OUTPUT
PROG
7
14
OUTPUT
INPUT
8
13
OUTPUT
VCC
9
12
GROUND
10
11
INPUT
INPUT
January 1996
6415C-01.EPS
PIN CONNECTIONS
1/10
TEA6415C
BLOCK DIAGRAM
P ERI
TV1
P ERI
TV2
TTX
18
17
16
LUMA PIP
CHROMA
POWER
MAC
DEC.
GND
1
CVBS
(P ERI P LUG1)
3
CVBS
(AM TUNER)
5
MAC S IGNAL
(AMTUNER)
6
CVBS
(P ERI P LUG2)
8
CVBS
(FM TUNER)
10
MAC S IGNAL
(FM TUNER)
11
SYNCHRO
(TTX/BTX)
20
14
13
12
T
E
A
6
4
1
5
C
BUS
DECODER
2
7
4
9
19
DATA
P ROG
CLOCK
VCC
GND
GENERAL DESCRIPTION
The main functionof the IC is to switch 8 video input
sources on 6 outputs.
Each output can be switched on only one of each
input. On each input an alignment of the lowest
level of the signal is made (bottom of synch. top for
CVBS or black level for RGB signals).
Each nominal gain between any input and output
is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external
resistor bridge, 5 VDC on the input. Each input can
be used as a normal input or as a MAC or Chroma
2/10
input (with external resistor bridge). All the switching possibilities are changed through the BUS.
Driving 75Ω load needs an external transistor.
It is possible to have the same input connected to
several outputs.
The starting configuration upon power on (power
supply : 0 to 10V) is undetermined.
In this case, 6 words of 16 bits are necessary to
determine one configuration. In other case, 1 word
of 16 bits is necessary to determine one configuration.
6415C-02.EPS
CVBS
(MAC/DEC)
15
TEA6415C
ABSOLUTE MAXIMUM RATINGS
VCC
Parameter
Value
Supply Voltage (Pin 9)
Unit
12
TA
Operating Ambient Temperature
Tstg
Storage Temperature
V
0, +70
o
C
- 20, +150
o
C
6415C-01.TBL
Symbol
Symbol
Rth(j-a)
Parameter
Junction-Ambient Thermal Resistance
Value
Unit
80
100
o
C/W
o
DIP20
SO20
C/W
6415C-02.TBL
THERMAL DATA
ELECTRICAL CHARACTERISTICS
TA = 25oC , VCC = 10V , RLOAD = 10kΩ , CLOAD = 3pF (unless otherwise specified)
Symbol
Min.
Typ.
Max.
VCC
Supply Voltage (Pin 9)
Parameter
8
10
11
Unit
V
ICC
Power Supply Current (without load on outputs ; VCC =10V)
20
30
40
mA
2
VPP
3
µA
INPUTS
Signal Amplitude (CVBS signal)
Input Current (per output connected, input voltage = 5VDC)
(this current is X6 when all outputs are connected on the input)
DC Level
1
3.3
DC Level Shift (temperature from 0 to 70oC)
3.6
3.9
V
5
100
mV
OUTPUTS (VIN = 1VPP for all dynamic tests) Pins 13 - 14 - 15 - 16 - 17 - 18
4.5
Output Impedance
5.5
50
Ω
7
dB
Gain
6
6.5
Bandwidth
-1dB attenuation
-3dB attenuation
7
15
20
Crosstalk
f = 5MHz
f = 3.58MHz
DC level
2.4
VPP
25
MHz
MHz
- 55
- 60
- 45
- 50
dB
dB
2.75
3.1
V
3/10
6415C-03.TBL
Dynamic
TEA6415C
I2C BUS CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
- 0.3
3.0
- 10
+ 1.5
VCC + 0.5
+ 10
V
V
µA
0
100
1000
300
kHz
ns
ns
10
pF
SCL
VIL
VIH
ILI
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
VI = 0 to VCC
fSCL
tR
tF
Clock Frequency
Input Rise Time
Input Fall Time
1.5V to 3V
1.5V to 3V
CI
Input Capacitance
SDA
VIL
Low Level Input Voltage
- 0.3
+ 1.5
V
VIH
ILI
CI
High Level Input Voltage
Input Leakage Current
Input Capacitance
VI = 0 to VCC
3.0
- 10
VCC + 0.5
+ 10
10
V
µA
pF
tR
tF
VOL
Input Rise Time
Input Fall Time
Low Level Output Voltage
1.5V to 3V
1.5V to 3V
IOL = 3mA
1000
300
0.4
ns
ns
V
tF
CL
Output Fall Time
Load Capacitance
3V to 1.5V
250
400
ns
pF
TIMING
µs
µs
ns
tSU, DAT
Clock Low Period
Clock High Period
Data Set-up Time
4.7
4.0
250
tHD, DAT
tSU, STO
tBUF
Data Hold Time
Set-up Time from Clock High to Stop
Start Set-up Time following a Stop
0
4.0
4.7
tHD, STA
Start Hold Time
4.0
µs
tSU, STA
Start Set-up Time following Clock Low-to High Transition
4.7
µs
340
ns
µs
µs
6415C-06.TBL
tLOW
tHIGH
Figure 1 : I2C Bus Timing
SDA
t BUF
t LOW
tf
SCL
t HD,STA
tr
t HD,DAT
t HIGH
t SU,DAT
t SU,STA
4/10
t SU,STO
6415C-10.EPS
SDA
TEA6415C
BUS SELECTIONS (I2C-BUS)
2nd byte of transmission
ADDRESS
MSB
DATA
LSB
00000
00100
00010
00110
00001
00101
00011
00111
XXX
XXX
XXX
- -XXX
XXX
XXX
- --
Selected Output
Pin 18
Pin 14
Pin 16
Not used
Pin 17
Pin 13
Pin 15
Not used
Output is selected by
address bits
Selected Input
000
100
010
110
001
101
011
111
Pin 5
Pin 8
Pin 3
Pin 20
Pin 6
Pin 10
Pin 1
Pin 11
Input is selected by
data bits
6415C-04.TBL
00XXX
00XXX
00XXX
00XXX
00XXX
00XXX
00XXX
00XXX
86
1000
0110
When pin PROG is connected to ground
06
0000
0110
When pin PROG is connected to VCC
6415C-05.TBL
Example :00100 101 connects Pin 10 (input) to Pin 14 (output) (equals 25 in hexadecimal)
Adress byte (1st byte of transmission)
IN / OUT PIN CONFIGURATION
Figure 2 : Input Configuration
Figure 3 : Output Configuration
VCC
VCC
14kΩ
x3
Allvide o
outputs
Pins 13-14-15
16-17-18
0.36 VCC
7kΩ
11kΩ
Pins 1-3-5-6
8-10-11-20
6415C-04.EPS
6 time s
6415C-03.EPS
8 NPN tra ns istors
Output
5/10
TEA6415C
IN / OUT PIN CONFIGURATION (continued)
Figure 4 : Bus I/O Configuration
Figure 5 : VCC Pin Configuration
VCC
VCC
P ins
2-4-7
VREF
ACK
20kΩ
* For Pin 2
(DATA) only
USE WITH AN OTHER TEA6415C
The programmation input (PROG) permits to operate with two TEA6415C in parallel and to select
them independantly through the I2C-BUS without
150 Ω
6415C-06.EPS
*
6415C-05.EPS
150 Ω
20k Ω
to I2L
pa rt
250 µA
9
modifying the adress byte. Consequentl y, the
switch capabilities are doubled or IC1 and IC2 can
be cascaded.
Figure 6
µP
logical ”0”
PROG
IC1
Video
Inputs
logical ”1”
Video
Outputs
PROG
6/10
Video
Outputs
6415C-07.EPS
IC2
Video
Inputs
TEA6415C
TYPICAL APPLICATION
100kΩ
22µF
11
10
12
9
CBVS
100k Ω
MAC
75 Ω
75Ω
220nF
100 µF
10Ω
VCC 10V
220nF
CVBS OUTPUT
13
8
CBVS
220nF
10kΩ
75Ω
14
15
CVBS OUTPUT
10kΩ
CVBS OUTPUT
16
10kΩ
CVBS OUTPUT
T
E
A
6
4
1
5
C
PROG (BUS)
100k Ω
10kΩ
7
22µF
MAC
6
100k Ω
CVBS OUTPUT
75Ω
220nF
5
CVBS
75Ω
17
4
18
3
CK (BUS)
10kΩ
220nF
CVBS
10kΩ
75Ω
19
2
20
1
220nF
CVBS
DA (BUS)
220nF
75Ω
CROSSTALK IMPROVEMENT
1 - When any input is not used, it must be bypassed
to ground through a 220nF capacitor.
CVBS
6415C-08.EPS
CVBS OUTPUT
75Ω
2 - An important improvement can be achieved
considering the input crosstalk by means of the
application (see technical note).
7/10
TEA6415C
OTHER APPLICATION DIAGRAM EXAMPLE
BUS
DECODER
CVBS1
CVBS2
CVBS3
Ye xt
VCC /2
VCC
Ce xt
Yint
VCC /2
VCC
T
E
A
6
4
1
5
C
Yout1 Cout1
Y, C
ADDER
Y, C
SEPARATOR
8/10
CVBSout1
Y+ C
Yout2 Cout2
CVBSout2
6415C-09.EPS
Cint
TEA6415C
PM-DIP20.EPS
PACKAGE MECHANICAL DATA
20 PINS – PLASTIC DIP
a1
B
b
b1
D
E
e
e3
F
I
L
Z
Min.
0.254
1.39
Millimeters
Typ.
Max.
1.65
0.45
0.25
Min.
0.010
0.055
Inches
Typ.
Max.
0.065
0.018
0.010
25.4
8.5
2.54
22.86
1.000
0.335
0.100
0.900
7.1
3.93
3.3
0.280
0.155
DIP20.TBL
Dimensions
0.130
1.34
0.053
9/10
TEA6415C
PM-SO20.EPS
PACKAGE MECHANICAL DATA
20 PINS – PLASTIC MICROPACKAGE (SO)
Dimensions
Millimeters
Typ.
0.1
0.35
0.23
Max.
2.65
0.3
2.45
0.49
0.32
Min.
Inches
Typ.
0.004
0.014
0.009
0.5
Max.
0.104
0.012
0.096
0.019
0.013
0.020
45o (typ.)
12.6
10
13.0
10.65
0.496
0.394
1.27
11.43
7.4
0.5
0.512
0.419
0.050
0.450
7.6
1.27
0.75
0.291
0.020
0.299
0.050
0.030
o
8 (Max.)
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1996 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco
The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
10/10
SO20.TBL
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
L
M
S
Min.