TEA6430 AUDIO CELLULAR MATRIX .. . .. .. 5 STEREO INPUTS - 4 STEREO OUTPUTS 3-STATE OPERATION FOR EACH OUTPUT GAIN OUTPUT CONTROL 0dB/2/4/6dB/MUTE FOR EACH VERY LOW NOISE AND DISTORTION I2C BUS CONTROL 4 SUB-ADDRESS FACILITY 90dB CROSSTALK BETWEEN ANY INPUT AND OUTPUT SHRINK 24 (Plastic Package) DESCRIPTION The TEA6430 switches 5 stereo inputs on 4 stereo outputs, providing the customer with high quality sound (low noise, low distortion). The 4 stereo outputs can be set separately in high impedance state, to enable parallel connection of several devices (up to 4). All functions are controlled through the I2C bus. ORDER CODE : TEA6430 May 1996 GND 1 24 SDA REF 2 23 SCL VCC 3 22 SUB L1 IN 4 21 R1 IN L2 IN 5 20 R2 IN L3 IN 6 19 R3 IN L4 IN 7 18 R4 IN L5 IN 8 17 R5 IN L1 OUT 9 16 R4 OUT R1 OUT 10 15 L4 OUT L2 OUT 11 14 R3 OUT R2 OUT 12 13 L3 OUT 6430-01.EPS PIN CONNECTIONS 1/10 TEA6430 BLOCK DIAGRAM RIGHT INP UTS 20 19 18 17 3 STATES OUT 10 G 3 STATES OUT 12 G 3 STATES OUT 14 G 3 STATES OUT 16 GAIN 24 S DA VS 3 2 SUPPLY 23 S CL BUS DECODER 22 ADR GND 1 5 6 7 3 STATES OUT 15 G 3 STATES OUT 13 G 3 STATES OUT 11 G 3 STATES OUT 9 8 6430-02.EPS 4 G LEFT OUTPUTS C RIGHT OUTPUTS 21 T E A 6 4 3 0 LEF T INP UTS The output loads have to be larger than 2kΩ (typical 10kΩ) and 1500pF ABSOLUTE MAXIMUM RATINGS Parameter Unit V Voltage at Pin i to GND 0, VCC V Toper Operating Ambient Temperature 0, + 70 o C Tstg Storage Temperature -20, + 150 o C VI Supply Voltage Value 12 VCC 6430-01.TBL Symbol Symbol R th (j-a) 2/10 Parameter Junction-ambient Thermal Resistance Value 75 Unit o C/W 6430-02.TBL THERMAL DATA TEA6430 ELECTRICAL CHARACTERISTICS (VCC = 8V, Tamb = 25oC, RL = 10kΩ, RG = 600Ω, f = 1kHz, G = 0dB, VIN = 0.5VRMS ; 3-state is controlled by I2C bus, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit 7.2 8 10.2 V 4 7 10 mA SUPPLY VCC Supply Voltage ICC Supply Current RR Ripple Rejection VIN = 0.5VRMS, f = 1kHz 70 dB AUDIO INPUTS VIN Max. Signal Amplitude VDC Input DC Level RI 2 VRMS VCC/2 Input Resistance 30 V 50 100 60 100 kΩ AUDIO OUTPUTS Output Resistance Output ”off” Impedance f = 20kHz, output disabled VOFF DC Offset Change Switching between inputs, see note 1 VOUT Output DC Level ZHI 50 0.4 VCC VN Output Noise Voltage B = 20-20kHz, flat, see note 2 G Gain B = 20-20kHz, R L = 2kΩ -0.5 Isolation ”off” State f = 1kHz, output disabled 85 THD Distortion VIN = 1VRMS , f = 1kHz VCL Clipping Level d = 0.3% 2 CS L, R Channel Separation f = 1kHz -85 Crosstalk Audio Channels f = 1kHz, see note 3 -85 CL Notes : Load Capacitance Ω kΩ 0.1 5 VCC/2 0.6 VCC mV V µV 2.5 0 +0.5 0.01 0.05 dB dB 2.3 % VRMS dB -100 1500 dB pF 1. DC offset change is less than maximum limit, in all configurations (one or several devices in parallel), provided that the reference Pins (P2) are all connected together. 2. Flat filter according to CCIR-468-4, B = 20Hz-20kHz 3. Measured from any selected output which contains no signal to a set of other outputs. 3/10 6430-03.TBL R OUT TEA6430 I2C BUS CHARACTERISTICS Symbol Test Conditions Parameter Standard Mode Min. Max. Fast Mode Min. Max. - 0.3 3.0 + 1.5 VCC + 0.5 - 0.3 3.0 + 1.5 VCC + 0.5 V V - 10 0 + 10 100 1000 - 10 0 + 10 400 300 µA kHz ns 300 10 ns pF + 1.5 VCC + 0.5 + 10 V V µA 10 300 300 pF ns ns Unit SCL VIL VIH Low Level Input Voltage High Level Input Voltage ILI fSCL tR Input Leakage Current Clock Frequency Input Rise Time VI = 0 to V DD Input Fall Time Input Capacitance 1.5V to 3V tF CI 1.5V to 3V 300 10 SDA VIL VIH ILI Low Level Input Voltage High Level Input Voltage Input Leakage Current CI tR tF Input Capacitance Input Rise Time Input Fall Time 1.5V to 3V 1.5V to 3V 10 1000 300 VOL tF Low Level Output Voltage Output Fall Time IOL = 3mA 3V to 1.5V 0.4 250 0.4 250 V ns CL Load Capacitance 400 400 pF VI = 0 to V DD - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 - 0.3 3.0 - 10 TIMING tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA tSU, STA Clock Low Period Clock High Period 4.7 4.0 1.3 0.6 Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop 250 0 4.0 Start Set-up Time following a Stop 4.7 1.3 µs Start Hold Time Start Set-up Time following Clock Low-to High Transition 4.0 4.7 0.6 0.6 µs µs 340 100 0 0.6 ms ms 340 ns ns µs 6430-04.TBL tLOW tHIGH Figure 1 : I2C Bus Timing SDA t BUF t LOW tf SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT t SU,STA 4/10 t SU,STO 6430-03.EPS SDA TEA6430 I2C BUS SELECTION I2C Bus Slave Address Address Value A6 1 A5 0 A4 0 A3 1 A2 1 A1 A1 A0 A0 R/W 0 Sub-address I2C Symbol Vsub Parameter Slave address HEXA 1 2 3 4 98 9E 9C 9A Note : Conditions Sub-address (see note) A1 A0 0 0 1 1 1 0 0 1 Pin 22 Voltage (typ.) Unit GND VCC 1/3 2/3 V V VCC VCC The first 3 levels are defined by connecting the sub-address pin to the appropriate level. Sub-address 4 will be selected when this pin is left open. Data Byte Input Select Output Select Gain Tri-state b7 T * * * * * * * * * * * * * * 0 1 b6 01 * * * * * * 0 0 1 1 * * * * * * b5 00 * * * * * * 0 1 0 1 * * * * * * b4 G1 * * * * * * * * * * 0 0 1 1 * * b3 G0 * * * * * * * * * * 0 1 0 1 * * b2 I2 0 0 0 0 1 1 * * * * * * * * * * b1 I1 0 0 1 1 0 0 * * * * * * * * * * b0 I0 0 1 0 1 0 1 * * * * * * * * * * Action IN1 IN2 IN3 IN4 IN5 Mute OUT1 OUT2 OUT3 OUT4 6dB 4dB 2dB 0dB Low impedance Tri-state Example : 00111100 enables L(R)2 out and connect it with a gain of 0dB to L(R)5 in. Power On Reset When active : outputs in 3-state. All outputs are disabled and L(R)5 is selected to drive all outputs. Gain = 0dB. Symbol Reset Parameter Start of Reset End of Reset Conditions Incr. VCC Decr. VCC Incr. VCC Min. 4.5 Typ. Max. Unit 2.5 4.2 V V V 5/10 TEA6430 TYPICAL PERFORMANCES Figure 2 : T A = 25°C All outputs enabled 9 8 7 5 7 8 10 9 11 12 SUPPLY VOLTAGE (V) Ripple Rejection as a Function of Supply Voltage RIPPLEREJECTION(dB) Gain = 0dB V IN = 600mV RMS T A = 25°C 85 83 7 8 9 10 11 12 SUPPLY VOLTAGE (V) Ripple Rejection as a Function of Gain 90 20 40 60 80 Ripple Rejection as a Function of Temperature 88 87 86 V C C = 8V Gain = 0dB f = 1kHz A ll outputs enabled 85 84 0 20 40 60 80 TEMPERATURE (°C) Figure 6 : Clipping Level as a Function of Supply Voltage 3.7 85 80 75 70 0 2 4 GAIN (dB) 6 T A = 25°C Distortion = 0.3% Gain = 0dB 3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 1.9 7 8 9 10 SUPPLY VOLTAGE (V) 11 12 6430-09.EPS VC C = 8V T A = 25°C VIN = 600m VRMS 65 6/10 0 83 -20 CLIPPING LEVEL ( V RMS ) RIPPLE REJECTION (dB) Figure 5 : 6 Figure 4 : 89 87 7 TEMPERATURE (°C) 6430-06.EPS RIPPLE REJECTION (dB) Figure 3 : V C C = 8V All outputs enabled 5 -20 6430-04.EPS 6 8 6430-05.EPS SUPPLYCURRENT (mA) 10 Supply Current as a Function of Temperature 6430-07.EPS Supply Current as a Function of Supply Voltage 6430-08.EPS SUPPLY CURRENT (mA) Figure 1 : TEA6430 TYPICAL PERFORMANCES (continued) Figure 7 : Distortion as a Function of Input Level Figure 8 : 0.05 0.6 0.4 0 0.8 0.4 Figure 9 : 1.2 1.6 VIN - VRMS (V) 2 2.4 6430-10.EPS 0.2 87 83 79 4 8 12 0.01 2 0 CROSSTALKLEVEL(dB) VCC = 8V Gain = 0dB VOUT = 2 VRMS TA = 25°C 0 0.02 6 4 Figure 10 : Crosstalk Level as a Function of Frequency (Gain = 6dB) 99 91 0.03 GAIN (dB) Crosstalk Level as a Function of Frequency (Gain = 0dB) 95 T A = 25°C VC C = 8V f = 1kHz VOUT = 1 VRMS 0.04 16 FREQUENCY (kHz) 22 91 VCC = 8V Gain = 6dB TA = 25°C 89 87 85 83 81 79 77 0 4 8 12 16 22 FREQUENCY (kHz) 7/10 6430-13.EPS 0.8 6430-11.EPS DISTORTION RATE (%) T A = 25°C VCC = 8V f = 1kHz Gain = 0dB 6430-12.EPS DISTORTION RATE (%) 1 CROSSTALKLEVEL(dB) Distortion as a Function of Gain TEA6430 PIN CONFIGURATIONS Figure 11 : Audio IN Figure 12 : Audio OUT V CC TRI-STATE V CC 50kΩ Matrix Point V CC /2 Pins 9 - 10 11 - 12- 13 14 - 15 - 16 L (R) x out x = 1, 2, 3, 4 TRI-STATE Figure 13 : PROG 6430-15.EPS 6430-14.EPS Pins 4 - 5 - 6 - 7 - 8 17 - 18 - 19 - 20 - 21 L (R) x in x = 1, 2, 3, 4 10kΩ TRI-STATE Figure 14 : Bus Inputs V CC VC C 20kΩ ESD PROT. VREFi 22 Pins 23 - 24 40kΩ to CMOS V REF to CMOS X4 6430-16.EPS 8/10 For SDA only 6430-17.EPS ACKN 3 TIMES IN // TEA6430 TYPICAL APPLICATION V CC (+8V) 100nF 1 24 SDA 2 23 SCL 3 C1 4 C2 LEFT INPUTS [1, 5] 5 C3 6 C4 7 C5 8 9 10 T E A 6 4 3 0 I2 C 22 C28 21 C27 20 C26 19 C25 18 RIGHT INPUTS [1, 5] C24 17 16 15 11 14 12 13 22µF 24 SDA 2 23 SCL 3 C6 4 C7 RIGHT INPUTS [6, 10] 5 C8 6 C9 7 C10 8 9 10 C11 C13 C12 R * C1 to C28 = 4.7µF OUT 1 22 VCC C23 21 C22 20 C21 19 C20 18 R 16 15 11 14 12 13 C17 C16 L OUT 2 RIGHT INPUTS [6, 10] C19 17 C15 C14 L T E A 6 4 3 0 I2 C R C18 L OUT 3 R L 6430-18.EPS 100nF 1 OUT 4 9/10 TEA6430 PACKAGE MECHANICAL DATA 24 PINS - PLASTIC SHRINK DIP E A2 A L A1 E1 Stand-off B B1 e e1 e2 c D 13 .015 F 0,38 1 PMSDIP24.EPS Gage Plane 12 e3 SDIP24 Dimensions A A1 A2 B B1 C D E E1 e e1 e2 e3 L Min. 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10 2.54 Millimeters Typ. 3.30 0.46 1.02 0.25 22.86 6.40 1.778 7.62 3.30 Max. 5.08 4.57 0.56 1.14 0.38 23.11 8.64 6.86 10.92 1.52 3.81 e2 Min. 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240 0.10 Inches Typ. 0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30 0.130 Max. 0.20 0.180 0.0220 0.045 0.0150 0.910 0.340 0270 0.430 0.060 0.150 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 10/10 SDIP24.TBL 24 E