FAIRCHILD 74VCX162838MTD

Revised July 2000
74VCX162838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in the Outputs
General Description
Features
The VCX162838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CP) signals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through the use of the
OE pin. These devices are ideally suited for buffered or
registered 168 pin and 200 pin SDRAM DIMM memory
modules.
■ Compatible with PC100 and PC133 DIMM module
specifications
The 74VCX162838 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCX162838 is also designed with 26Ω series resistors
in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
■ 1.65V–3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ 26Ω series resistors in the outputs
■ tPD (CP to On)
3.9 ns max for 3.0V to 3.6V VCC
5.4 ns max for 2.3V to 2.7V VCC
9.8 ns max for 1.65V to 1.95V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Static Drive (IOH/IOL)
±12 mA @ 3.0V VCC
The 74VCX162838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor. The minimum
value of the resistor is determined by the current -sourcing capability of the
driver.
Ordering Code:
Ordering Code
Package Number
Package Descriptions
74VCX162838MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
© 2000 Fairchild Semiconductor Corporation
DS500045
Description
OE
Output Enable Input (Active LOW)
I0–I15
Inputs
O0–O15
Outputs
CP
Clock Pulse Input
REGE
Register Enable Input
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74VCX162838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26Ω
Series Resistors in the Outputs
August 1997
74VCX162838
Connection Diagram
Truth Table
Inputs
Outputs
CP
REGE
In
OE
On
↑
H
H
L
H
↑
H
L
L
L
X
L
H
L
H
X
L
L
L
L
X
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Functional Description
The 74VCX162838 consists of sixteen selectable noninverting buffers or registers with word wide controls. Mode
functionality is selected through operation of the CP and
REGE pin as shown by the truth table. When REGE is held
at a logic “1” the device operates as a 16-bit register. Data
is transferred from In to On on the rising edge of the CP pin.
When the REGE pin is held at a logic “0” the device operates in a flow through mode and data propagates directly
from the I to the O outputs. All outputs can be 3-stated by
holding the OE pin at a logic “1”.
Logic Diagram
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2
Supply Voltage (VCC)
−0.5V to +4.6V
DC Input Voltage (VI)
−0.5V to +4.6V
Recommended Operating
Conditions (Note 4)
Power Supply
Output Voltage (VO)
Operating
−0.5V to +4.6V
Outputs 3-STATE
Outputs Active (Note 3)
DC Input Diode Current (IIK) VI < 0V
1.65V to 3.6V
Data Retention Only
−0.5V to VCC +0.5V
−50 mA
Output Voltage (VO)
DC Output Diode Current (IOK)
Output in Active States
VO < 0V
−50 mA
Output in “OFF” State
VO > VCC
+50 mA
Output Current in IOH/IOL
DC Output Source/Sink Current
±50 mA
(IOH/IOL)
Storage Temperature Range (TSTG)
0V to VCC
0.0V to 3.6V
VCC = 3.0V to 3.6V
±12 mA
VCC = 2.3V to 2.7V
±8 mA
VCC = 1.65V to 2.3V
DC VCC or GND Current per
Supply Pin (ICC or GND)
1.2V to 3.6V
−0.3V to +3.6V
Input Voltage
±100 mA
±3 mA
Free Air Operating Temperature (TA)
−65°C to +150°C
−40°C to +85°C
Minimum Input Edge Rate (∆t/∆V)
VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < VCC ≤ 3.6V)
Symbol
Parameter
Conditions
VCC
(V)
Min
2.0
VIH
HIGH Level Input Voltage
2.7–3.6
VIL
LOW Level Input Voltage
2.7–3.6
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
IOH = −100 µA
Max
Units
V
0.8
V
2.7–3.6
VCC − 0.2
V
IOH = −6 mA
2.7
2.2
V
IOH = −8 mA
3.0
2.4
V
IOH = −12 mA
3.0
2.2
V
IOL = 100 µA
2.7–3.6
0.2
V
2.7
0.4
V
IOL = 8 mA
3.0
0.55
V
IOL = 12 mA
3.0
0.8
V
2.7–3.6
±5.0
µA
2.7–3.6
±10
µA
µA
IOL = 6 mA
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 3.6V
VI = V IH or VIL
IOFF
Power-OFF Leakage Current
0 ≤ (VI, VO) ≤ 3.6V
0
10
ICC
Quiescent Supply Current
VI = V CC or GND
2.7–3.6
20
µA
VCC ≤ (VI, VO) ≤ 3.6V (Note 5)
2.7–3.6
±20
µA
VIH = VCC −0.6V
2.7–3.6
750
µA
∆ICC
Increase in ICC per Input
Note 5: Outputs disabled or 3-STATE only.
3
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74VCX162838
Absolute Maximum Ratings(Note 2)
74VCX162838
DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V)
Symbol
Parameter
Conditions
VCC
(V)
Min
1.6
VIH
HIGH Level Input Voltage
2.3–2.7
VIL
LOW Level Input Voltage
2.3–2.7
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
II
Input Leakage Current
IOZ
3-STATE Output Leakage
IOH = −100 µA
Max
Units
V
0.7
V
2.3–2.7
VCC − 0.2
V
IOH = −4 mA
2.3
2.0
V
IOH = −6 mA
2.3
1.8
V
IOH = −8 mA
2.3
1.7
IOL = 100 µA
2.3–2.7
0.2
V
IOL = 6 mA
2.3
0.4
V
IOL = 8 mA
2.3
0.6
V
2.3–2.7
±5.0
µA
2.3–2.7
±10
µA
µA
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
V
IOFF
Power-OFF Leakage Current
0 ≤ (VI, VO) ≤ 3.6V
0
10
ICC
Quiescent Supply Current
VI = VCC or GND
2.3–2.7
20
µA
VCC ≤ (VI, VO) ≤ 3.6V (Note 6)
2.3–2.7
±20
µA
Max
Units
Note 6: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V ≤ VCC < 2.3V)
Symbol
Parameter
Conditions
VCC
(V)
Min
0.65 × VCC
VIH
HIGH Level Input Voltage
1.65 - 2.3
VIL
LOW Level Input Voltage
1.65 - 2.3
VOH
HIGH Level Output Voltage
IOH = −100 µA
1.65 - 2.3
VCC − 0.2
IOH = −3 mA
1.65
1.25
1.65 - 2.3
VOL
LOW Level Output Voltage
IOL = 100 µA
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
IOZ
3-STATE Output Leakage
IOL = 3 mA
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
V
0.35 × VCC
V
V
V
0.2
V
1.65
0.3
V
1.65 - 2.3
±5.0
µA
1.65 - 2.3
±10
µA
IOFF
Power-OFF Leakage Current
0 ≤ (VI, VO) ≤ 3.6V
0
10
µA
ICC
Quiescent Supply Current
VI = VCC or GND
1.65 - 2.3
20
µA
VCC ≤ (VI, VO) ≤ 3.6V (Note 7)
1.65 - 2.3
±20
µA
Note 7: Outputs disabled or 3-STATE only.
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4
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
VCC = 3.3V ± 0.3V
Parameter
Min
Max
VCC = 2.5V ± 0.2V
Min
Max
200
VCC = 1.8V
Min
Units
Max
fMAX
Maximum Clock Frequency
250
tPHL, tPLH
Prop Delay In to On (REGE = 0)
0.8
3.5
1.0
4.9
100
1.5
9.8
ns
tPHL, tPLH
Prop Delay CP to On (REGE = 1)
0.8
3.9
1.0
5.4
1.5
9.8
ns
tPHL, tPLH
Prop Delay REGE to On
0.8
3.9
1.0
5.4
1.5
9.8
ns
tPZL, tPZH
Output Enable Time
0.8
4.0
1.0
5.7
1.5
9.8
ns
tPLZ, tPHZ
Output Disable Time
0.8
4.1
1.0
4.6
1.5
8.3
ns
tS
Setup Time
1.0
1.0
2.5
tH
Hold Time
0.7
0.7
1.0
ns
tW
Pulse Width
1.5
1.5
4.0
ns
tOSHL
Output to Output Skew (Note 9)
0.5
tOSLH
MHz
ns
0.5
0.75
ns
Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Extended AC Electrical Characteristics (Note 10)
TA = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.3V
Symbol
CL = 50 pF
Parameter
Min
Units
Max
tPHL, tPLH
Prop Delay In to On (REGE = 0)
1.0
3.8
ns
tPHL, tPLH
Prop Delay CP to On (REGE = 1)
1.4
4.2
ns
tPHL, tPLH
Prop Delay REGE to On
1.0
4.2
ns
tPZL, tPZH
Output Enable Time
1.0
4.3
ns
tPLZ, tPHZ
Output Disable Time
1.0
4.4
ns
tS
Setup Time
1.0
ns
tH
Hold Time
0.7
ns
Note 10: This parameter is guaranteed by characterization but not tested.
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VOHV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC
(V)
TA = +25°C
Typical
1.8
0.15
2.5
0.25
3.3
0.35
1.8
−0.15
2.5
−0.25
3.3
−0.35
1.8
1.55
2.5
2.05
3.3
2.65
Units
V
V
V
Capacitance
Symbol
Parameter
Conditions
TA = +25°C
Typical
Units
CIN
Input Capacitance
VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC
6
pF
COUT
Output Capacitance
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
7
pF
CPD
Power Dissipation Capacitance
VI =0V or VCC, f = 10 MHz, V CC = 1.8V, 2.5V or 3.3V
20
pF
5
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74VCX162838
AC Electrical Characteristics (Note 8)
74VCX162838
AC Loading and Waveforms
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
trec Waveforms
Symbol
VCC
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VX
VOL +0.3V
VOL +0.15V
VOL +0.15V
VY
VOH −0.3V
VOH −0.15V
VOH −0.15V
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48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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74VCX162838 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs and 26Ω
Series Resistors in the Outputs
Physical Dimensions inches (millimeters) unless otherwise noted