SAMSUNG KFG5616Q1A-DEB5

OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
OneNANDTM Specification
Density
256Mb
Part No.
VCC(core & IO)
Temperature
PKG
KFG5616Q1A-DEB5
1.8V(1.7V~1.95V)
Extended
67FBGA(LF)
KFG5616Q1A-PEB5
1.8V(1.7V~1.95V)
Extended
48TSOP1
KFG5616D1A-DEB5
2.65V(2.4V~2.9V)
Extended
67FBGA(LF)
KFG5616D1A-PEB5
2.65V(2.4V~2.9V)
Extended
48TSOP1
KFG5616U1A-DIB5
3.3V(2.7V~3.6V)
Industrial
67FBGA(LF)
KFG5616U1A-PIB5
3.3V(2.7V~3.6V)
Industrial
48TSOP1
Version: Ver. 1.1
Date: Aug 12, 2005
1
OneNAND256(KFG5616x1A-xxB5)
1.0
FLASH MEMORY
INTRODUCTION
This specification contains information about the Samsung Electronics Company OneNAND™‚ Flash memory product family. Section
1.0 includes a general overview, revision history, and product ordering information.
Section 2.0 describes the OneNAND device. Section 3.0 provides information about device operation. Electrical specifications and
timing waveforms are in Sections 4.0 though 6.0. Section 7.0 provides additional application and technical notes pertaining to use of
the OneNAND. Package dimensions are found in Section 8.0
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
OneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their
rightful owners.
Copyright © 2005, Samsung Electronics Company, Ltd
2
OneNAND256(KFG5616x1A-xxB5)
1.1
FLASH MEMORY
Revision History
Document Title
OneNAND
Revision History
Revision No. History
Draft Date
Remark
0.0
1. Initial Issue
April 17, 2005
Preliminary
1.0
1. Corrected the errata
2. Added Data Protection flow chart.
3. Removed Cache Read Operation.
4. Added additional information on command register.
5. Revised Interrupt status register information.
6. Added INT pin schematic.
7. Changed tPGM1 to 205 from 320us, tPGM2 to 220 from 350us.
8. Revised AC/DC parameters
9. Revised ECC Bypass Description
10. Revised Reset Parameters and Timing Diagrams.
May 17, 2005
Final
1.1
1. Corrected the errata
2. Revised Invalid Block Table Creation Flow Chart.
3. Revised Multi Block Erase Description.
4. Revised Reset Mode Operation.
Aug 12, 2005
Final
3
OneNAND256(KFG5616x1A-xxB5)
1.2
FLASH MEMORY
Flash Product Type Selector
Samsung offers a variety of Flash solutions including NAND Flash, OneNAND™ and NOR Flash. Samsung offers Flash products
both component and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia.
To determine which Samsung Flash product solution is best for your application, refer the product selector chart.
Application Requires
Samsung Flash Products
NAND
OneNAND™
Fast Sequential Read
•
•
Fast Write/Program
•
NOR
•
Fast Random Read
•
Multi Block Erase
Erase Suspend/Resume
• (Max 64 Blocks)
•
•
•
• (EDC)
• (ECC)
•
•
ECC
External (Hardware/Software)
Internal
X
Scalability
•
•
Copyback
Lock/Unlock/Lock-Tight
1.3
Ordering Information
K F G 56 1 6 X 1 A - X X B 5
Samsung
OneNAND Memory
Speed
5 : 54MHz
6 : 66MHz
Product Line desinator
B : Include Bad Block
D : Daisy Sample
Device Type
G : Single Chip
Operating Temperature Range
E = Extended Temp. (-30 °C to 85 °C)
I = Industrial Temp. (-40 °C to 85 °C)
Density
56 : 256Mb
Package
D : FBGA(Lead Free)
P : TSOP(Lead Free)
Organization
x16 Organization
Version
A : 2nd Generation
Operating Voltage Range
Q : 1.8V(1.7 V to 1.95V)
D : 2.65V(2.4V to 2.9V)
U : 3.3V(2.7 V to 3.6V)
Page Architecture
1 : 1KB Page
4
OneNAND256(KFG5616x1A-xxB5)
1.4
FLASH MEMORY
Architectural Benefits
OneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory array.
The chip integrates system features including:
• A BootRAM and bootloader
• Two independent bi-directional 1KB DataRAM buffers
• A High-Speed x16 Host Interface
• On-chip Error Correction
• On-chip NOR interface controller
This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications
that would otherwise have to use more NOR components.
OneNAND takes advantage of the higher performance NAND program time, low power, and high density and combines it with the
synchronous read performance of NOR. The NOR Flash host interface makes OneNAND an ideal solution for applications like G3
Smart Phones, Camera Phones, and mobile applications that have large, advanced multimedia applications and operating systems,
but lack a NAND controller.
When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance, small footprint solution.
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
5
OneNAND256(KFG5616x1A-xxB5)
1.5
Product Features
Device Architecture
• Design Technology:
• Supply Voltage:
• Host Interface:
• 3KB Internal BufferRAM:
• SLC NAND Array:
Device Performance
• Host Interface Type:
•
•
•
•
•
FLASH MEMORY
Programmable Burst Read Latency
Multiple Sector Read:
Multiple Reset Modes:
Multi Block Erase
Low Power Dissipation:
90nm
1.8V (1.7V ~ 1.95V), 2.65V (2.4 ~ 2.9V), 3.3V (2.7 ~3.6V)
16 bit
1KB BootRAM, 2KB DataRAM
(1K+32)B Page Size, (64K+2K)B Block Size
Synchronous Burst Read
- Up to 54MHz clock frequency
- Linear Burst 4-, 8-, 16, 32-words with wrap around
- Continuous 512 word Sequential Burst
Asynchronous Random Read
- 76ns access time
Asynchronous Random Write
Latency 3(up to 40MHz), 4, 5, 6, and 7
Up to 2 sectors using Sector Count Register
Cold/Warm/Hot/NAND Flash Core Resets
up to 64 Blocks
Typical Power,
- Standby current :
10µA @1.8V Device
25µA @2.65V/3.3V Device
- Synchronous Burst Read current(54MHz) : [email protected] Device
[email protected]/3.3v Device
- Load current :
[email protected] Device,
[email protected]/3.3V Device
- Program current :
[email protected] Device,
[email protected]/3.3V Device
- Erase current :
[email protected] Device,
[email protected]/3.3V Device
- Multi Block Erase current :
[email protected] Device,
[email protected]/3.3V Device
System Hardware
• Voltage detector generating internal reset signal from Vcc
- Write Protection for BootRAM
• Hardware reset input (RP)
- Write Protection for NAND Flash Array
• Data Protection Modes
- Write Protection during power-up
- Write Protection during power-down
• User-controlled One Time Programmable(OTP) area
• Internal 2bit EDC / 1bit ECC
• Internal Bootloader supports Booting Solution in system
• Handshaking Feature
• Detailed chip information
Packaging
• 256Mb products
- INT pin indicates Ready / Busy
- Polling the interrupt register status bit
- by ID register
67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA
48 TSOP 1, 12mm x 20mm, 0.5mm pitch
6
OneNAND256(KFG5616x1A-xxB5)
1.6
FLASH MEMORY
General Overview
OneNAND™‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes control
logic, a NAND Flash array, and 3KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 2KB
for data buffering (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed of
~76ns.
The device operates up to a maximum host-driven clock frequency of 54MHz for synchronous reads at Vcc(or Vccq. Refer to chapter
4.2) with minimum 4-clock latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait cycles are determined by programmable read latency.
OneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter
register. The device includes one block-sized OTP (One Time Programmable) area that can be used to increase system security or
to provide identification capabilities.
7
OneNAND256(KFG5616x1A-xxB5)
2.0
DEVICE DESCRIPTION
2.1
Detailed Product Description
FLASH MEMORY
The OneNAND is an advanced generation, high-performance NAND-based Flash memory.
It integrates on-chip a single-level-cell (SLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page
buffer for the Flash array, and a one-time-programmable block.
The combination of these memory areas enable high-speed pipelining of reads from host, BufferRAM, Page Buffer, and NAND Flash
Array memory.
Clock speeds up to 54MHz with a x16 wide I/O yields a 54MByte/second bandwidth.
The OneNAND also includes a Boot RAM and boot loader. This enables the device to efficiently load boot code at device startup from
the NAND Array without the need for off-chip boot device.
One block of the NAND Array is set aside as an OTP memory area. This area, available to the user, can be configured and locked
with secured user information.
On-chip controller interfaces enable the device to operate in systems without NAND Host controllers.
8
OneNAND256(KFG5616x1A-xxB5)
2.2
FLASH MEMORY
Definitions
B (capital letter)
Byte, 8bits
W (capital letter)
Word, 16bits
b (lower-case letter)
Bit
ECC
Error Correction Code
Calculated ECC
ECC that has been calculated during a load or program access
Written ECC
ECC that has been stored as data in the NAND Flash array or in the BufferRAM
BufferRAM
On-chip internal buffer consisting of BootRAM and DataRAM
BootRAM
A 1KB portion of the BufferRAM reserved for Boot Code buffering
DataRAM
A 2KB portion of the BufferRAM reserved for Data buffering
Sector
Part of a Page of which 512B is the main data area and 16B is the spare data area.
It is also the minimum Load/Program/Copy-Back Program unit
during a 1~2 sector operation is available.
Data unit
Possible data unit to be read from memory to BufferRAM or to be programmed to memory.
- 528B of which 512B is in main area and 16B in spare area
- 1056B of which 1024B is in main area and 32B in spare area
9
OneNAND256(KFG5616x1A-xxB5)
2.3
2.3.1
FLASH MEMORY
Pin Configuration
48TSOP1
N.C
A15
A14
A13
A12
A11
A10
A9
A8
WE
VSS
VCC
INT
AVD
RP
A7
A6
A5
A4
A3
A2
A1
A0
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
0.5mm pitch
(TOP VIEW, Facing Down)
TSOP1 OneNAND Chip
48pin, 12mm x 20mm, 0.5mm pitch TSOP1
10
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
OE
DQ15
DQ7
DQ14
DQ6
VCCQ
DQ13
DQ5
DQ12
DQ4
DQ11
DQ3
DQ10
DQ2
VSS
DQ9
DQ1
DQ8
DQ0
RDY
CLK
CE
VCC
OneNAND256(KFG5616x1A-xxB5)
2.3.2
FLASH MEMORY
67ball FBGA
NC
NC
NC
VSS
VSS
DQ13
NC
DQ1
OE
DQ9
VCC
Core
NC
DQ4
DQ11
DQ10
DQ3
VCC
IO
DQ15
A12
DQ0
A15
DQ5
DQ6
CLK
CE
DQ2
NC
NC
A9
A14
A13
AVD
A7
A11
A8
NC
INT
A0
A1
NC
A10
A6
NC
NC
RDY
A4
A5
A2
A3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
WE
RP
DQ14
NC
DQ12
DQ8
DQ7
(TOP VIEW, Balls Facing Down)
67ball FBGA OneNAND Chip
67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA
11
OneNAND256(KFG5616x1A-xxB5)
2.4
FLASH MEMORY
Pin Description
Pin Name
Type
Nameand Description
Host Interface
Address Inputs
- Inputs for addresses during read and write operation, which are for addressing
BufferRAM & Register.
A15~A0
I
DQ15~DQ0
I/O
Data Inputs/Outputs
- Inputs data during program and commands for all operations, outputs data during memory array/
register read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are disabled.
INT
O
Interrupt
Notifying Host when a command has completed. It is open drain output with internal resister (~50k
Ohm). After power up, it is at Hi-z state. And after IOBE is set to 1, it does not turn to hi-z condition when
the chip is deselected or when outputs are disabled.
RDY
O
Ready
Indicates data valid in synchronous read modes and is activated while CE is low
CLK
I
Clock
CLK synchronizes the device to the system bus frequency in synchronous read mode.
The first rising edge of CLK in conjunction with AVD low latches address input.
WE
I
Write Enable
WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge
AVD
I
Address Valid Detect
Indicates valid address presence on address inputs. During asynchronous read operation, all addresses
are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on
CLK’s rising edge while AVD is held low for one clock cycle.
> Low : for asynchronous mode, indicates valid address ;for burst mode,
causes starting address to be latched on rising edge on CLK
> High : device ignores address inputs
RP
I
Reset Pin
When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up
and bootloading.
CE
I
Chip Enable
CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,
and places DQ in Hi-Z
OE
I
Output Enable
OE-low enables the device’s output data buffers during a read cycle.
Power Supply
VCC-Core
/ Vcc
VCC-IO
/ Vccq
Power for OneNAND Core
This is the power supply for OneNAND Core.
Power for OneNAND I/O
This is the power supply for OneNAND I/O
Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc.
VSS
Ground for OneNAND
DNU
Do Not Use
Leave it disconnected. These pins are used for testing.
etc.
NC
No Connection
Lead is not internally connected.
NOTE:
Do not leave power supply(Vcc-Core/Vcc-IO, VSS) disconnected.
12
OneNAND256(KFG5616x1A-xxB5)
2.5
FLASH MEMORY
Block Diagram
BufferRAM
DQ15~DQ0
Bootloader
BootRAM
A15~A0
StateMachine
CLK
DataRAM0
CE
WE
Host Interface
OE
DataRAM1
NAND Flash
Array
Error
RP
Correction
AVD
INT
RDY
2.6
Internal Registers
Logic
(Address/Command/Configuration
/Status Registers)
OTP
(One Block)
Memory Array Organization
The OneNAND architecture integrates several memory areas on a single chip.
2.6.1
Internal (NAND Array) Memory Organization
The on-chip internal memory is a single-level-cell (SLC) NAND array used for data storage and code. The internal memory is divided
into a main area and a spare area.
Main Area
The main area is the primary memory array. This main area is divided into Blocks of 64 Pages. Within a Block, each Page is 1KB and
is comprised of 2 Sectors. Within a Page, each Sector is 512B and is comprised of 256 Words.
Spare Area
The spare area is used for invalid block information and ECC storage. Spare area internal memory is associated with corresponding
main area memory. Within a Block, each Page has two 16B Sectors of spare area. Each spare area Sector is 8 words.
13
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Internal Memory Array Information
Area
Block
Page
Sector
Main
64KB
1KB
512B
Spare
2KB
32B
16B
Internal Memory Array Organization
Sector
Main Area
Spare Area
512B
16B
Page
Main Area
512B Sector0
Spare Area
512B Sector1
1KB
16B Sector0
16B Sector1
32B
Block
Main Area
Spare Area
1KB Page0
32B Page0
Page 0
1KB Page63
32B Page63
Page 63
64KB
2KB
14
OneNAND256(KFG5616x1A-xxB5)
2.6.2
FLASH MEMORY
External (BufferRAM) Memory Organization
The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering.
The BootRAM is a 1KB buffer that receives Boot Code from the internal memory and makes it available to the host at start up.
There are two independent 1KB bi-directional data buffers, DataRAM0 and DataRAM1. These dual buffers enable the host to execute
simultaneous Read-While load, and Write-While-program operations after Boot Up. During Boot Up, the BootRam is used by the host
to initialize the main memory, and deliver boot code from NAND Flash core to host.
Internal (Nand Array)
Memory
External (BufferRAM)
Memory
Boot code (1KB)
BootRAM (1KB)
Host
Nand Array
DataRAM0 (1KB)
DataRAM1 (1KB)
OTP Block
The external memory is divided into a main area and a spare area. Each buffer is the equivalent size of a Sector.
The main area data is 512B. The spare area data is 16B.
External Memory Array Information
Area
BootRAM
DataRAM0
DataRAM1
Total Size
1KB+32B
1KB+32B
1KB+32B
Number of Sectors
2
2
2
Main
512B
512B
512B
Spare
16B
16B
16B
Sector
15
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
External Memory Array Organization
Main area data
(512B)
Spare area data
(16B)
{
{
BootRAM
DataRAM0
DataRAM1
BootRAM 0
BootRAM 1
DataRAM 0_0
DataRAM 0_1
DataRAM 1_0
DataRAM 1_1
16
Sector: (512 + 16) Byte
OneNAND256(KFG5616x1A-xxB5)
2.7
FLASH MEMORY
Memory Map
The following tables are the memory maps for the OneNAND.
2.7.1
Internal (NAND Array) Memory Organization
The following tables show the Internal Memory address map in word order.
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block0
0000h
0000h~00FDh
64KB
Block32
0020h
0000h~00FDh
64KB
Block1
0001h
0000h~00FDh
64KB
Block33
0021h
0000h~00FDh
64KB
Block2
0002h
0000h~00FDh
64KB
Block34
0022h
0000h~00FDh
64KB
Block3
0003h
0000h~00FDh
64KB
Block35
0023h
0000h~00FDh
64KB
Block4
0004h
0000h~00FDh
64KB
Block36
0024h
0000h~00FDh
64KB
Block5
0005h
0000h~00FDh
64KB
Block37
0025h
0000h~00FDh
64KB
Block6
0006h
0000h~00FDh
64KB
Block38
0026h
0000h~00FDh
64KB
Block7
0007h
0000h~00FDh
64KB
Block39
0027h
0000h~00FDh
64KB
Block8
0008h
0000h~00FDh
64KB
Block40
0028h
0000h~00FDh
64KB
Block9
0009h
0000h~00FDh
64KB
Block41
0029h
0000h~00FDh
64KB
Block10
000Ah
0000h~00FDh
64KB
Block42
002Ah
0000h~00FDh
64KB
Block11
000Bh
0000h~00FDh
64KB
Block43
002Bh
0000h~00FDh
64KB
Block12
000Ch
0000h~00FDh
64KB
Block44
002Ch
0000h~00FDh
64KB
Block13
000Dh
0000h~00FDh
64KB
Block45
002Dh
0000h~00FDh
64KB
Block14
000Eh
0000h~00FDh
64KB
Block46
002Eh
0000h~00FDh
64KB
Block15
000Fh
0000h~00FDh
64KB
Block47
002Fh
0000h~00FDh
64KB
Block16
0010h
0000h~00FDh
64KB
Block48
0030h
0000h~00FDh
64KB
Block17
0011h
0000h~00FDh
64KB
Block49
0031h
0000h~00FDh
64KB
Block18
0012h
0000h~00FDh
64KB
Block50
0032h
0000h~00FDh
64KB
Block19
0013h
0000h~00FDh
64KB
Block51
0033h
0000h~00FDh
64KB
Block20
0014h
0000h~00FDh
64KB
Block52
0034h
0000h~00FDh
64KB
Block21
0015h
0000h~00FDh
64KB
Block53
0035h
0000h~00FDh
64KB
Block22
0016h
0000h~00FDh
64KB
Block54
0036h
0000h~00FDh
64KB
Block23
0017h
0000h~00FDh
64KB
Block55
0037h
0000h~00FDh
64KB
Block24
0018h
0000h~00FDh
64KB
Block56
0038h
0000h~00FDh
64KB
Block25
0019h
0000h~00FDh
64KB
Block57
0039h
0000h~00FDh
64KB
Block26
001Ah
0000h~00FDh
64KB
Block58
003Ah
0000h~00FDh
64KB
Block27
001Bh
0000h~00FDh
64KB
Block59
003Bh
0000h~00FDh
64KB
Block28
001Ch
0000h~00FDh
64KB
Block60
003Ch
0000h~00FDh
64KB
Block29
001Dh
0000h~00FDh
64KB
Block61
003Dh
0000h~00FDh
64KB
Block30
001Eh
0000h~00FDh
64KB
Block62
003Eh
0000h~00FDh
64KB
Block31
001Fh
0000h~00FDh
64KB
Block63
003Fh
0000h~00FDh
64KB
NOTE 1) The 2nd bit of Page and Sector address register is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
17
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block64
0040h
0000h~00FDh
64KB
Block96
0060h
0000h~00FDh
64KB
Block65
0041h
0000h~00FDh
64KB
Block97
0061h
0000h~00FDh
64KB
Block66
0042h
0000h~00FDh
64KB
Block98
0062h
0000h~00FDh
64KB
Block67
0043h
0000h~00FDh
64KB
Block99
0063h
0000h~00FDh
64KB
Block68
0044h
0000h~00FDh
64KB
Block100
0064h
0000h~00FDh
64KB
Block69
0045h
0000h~00FDh
64KB
Block101
0065h
0000h~00FDh
64KB
Block70
0046h
0000h~00FDh
64KB
Block102
0066h
0000h~00FDh
64KB
Block71
0047h
0000h~00FDh
64KB
Block103
0067h
0000h~00FDh
64KB
Block72
0048h
0000h~00FDh
64KB
Block104
0068h
0000h~00FDh
64KB
Block73
0049h
0000h~00FDh
64KB
Block105
0069h
0000h~00FDh
64KB
Block74
004Ah
0000h~00FDh
64KB
Block106
006Ah
0000h~00FDh
64KB
Block75
004Bh
0000h~00FDh
64KB
Block107
006Bh
0000h~00FDh
64KB
Block76
004Ch
0000h~00FDh
64KB
Block108
006Ch
0000h~00FDh
64KB
Block77
004Dh
0000h~00FDh
64KB
Block109
006Dh
0000h~00FDh
64KB
Block78
004Eh
0000h~00FDh
64KB
Block110
006Eh
0000h~00FDh
64KB
Block79
004Fh
0000h~00FDh
64KB
Block111
006Fh
0000h~00FDh
64KB
Block80
0050h
0000h~00FDh
64KB
Block112
0070h
0000h~00FDh
64KB
Block81
0051h
0000h~00FDh
64KB
Block113
0071h
0000h~00FDh
64KB
Block82
0052h
0000h~00FDh
64KB
Block114
0072h
0000h~00FDh
64KB
Block83
0053h
0000h~00FDh
64KB
Block115
0073h
0000h~00FDh
64KB
Block84
0054h
0000h~00FDh
64KB
Block116
0074h
0000h~00FDh
64KB
Block85
0055h
0000h~00FDh
64KB
Block117
0075h
0000h~00FDh
64KB
Block86
0056h
0000h~00FDh
64KB
Block118
0076h
0000h~00FDh
64KB
Block87
0057h
0000h~00FDh
64KB
Block119
0077h
0000h~00FDh
64KB
Block88
0058h
0000h~00FDh
64KB
Block120
0078h
0000h~00FDh
64KB
Block89
0059h
0000h~00FDh
64KB
Block121
0079h
0000h~00FDh
64KB
Block90
005Ah
0000h~00FDh
64KB
Block122
007Ah
0000h~00FDh
64KB
Block91
005Bh
0000h~00FDh
64KB
Block123
007Bh
0000h~00FDh
64KB
Block92
005Ch
0000h~00FDh
64KB
Block124
007Ch
0000h~00FDh
64KB
Block93
005Dh
0000h~00FDh
64KB
Block125
007Dh
0000h~00FDh
64KB
Block94
005Eh
0000h~00FDh
64KB
Block126
007Eh
0000h~00FDh
64KB
Block95
005Fh
0000h~00FDh
64KB
Block127
007Fh
0000h~00FDh
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
18
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block128
0080h
0000h~00FDh
64KB
Block160
00A0h
0000h~00FDh
64KB
Block129
0081h
0000h~00FDh
64KB
Block161
00A1h
0000h~00FDh
64KB
Block130
0082h
0000h~00FDh
64KB
Block162
00A2h
0000h~00FDh
64KB
Block131
0083h
0000h~00FDh
64KB
Block163
00A3h
0000h~00FDh
64KB
Block132
0084h
0000h~00FDh
64KB
Block164
00A4h
0000h~00FDh
64KB
Block133
0085h
0000h~00FDh
64KB
Block165
00A5h
0000h~00FDh
64KB
Block134
0086h
0000h~00FDh
64KB
Block166
00A6h
0000h~00FDh
64KB
Block135
0087h
0000h~00FDh
64KB
Block167
00A7h
0000h~00FDh
64KB
Block136
0088h
0000h~00FDh
64KB
Block168
00A8h
0000h~00FDh
64KB
Block137
0089h
0000h~00FDh
64KB
Block169
00A9h
0000h~00FDh
64KB
Block138
008Ah
0000h~00FDh
64KB
Block170
00AAh
0000h~00FDh
64KB
Block139
008Bh
0000h~00FDh
64KB
Block171
00ABh
0000h~00FDh
64KB
Block140
008Ch
0000h~00FDh
64KB
Block172
00ACh
0000h~00FDh
64KB
Block141
008Dh
0000h~00FDh
64KB
Block173
00ADh
0000h~00FDh
64KB
Block142
008Eh
0000h~00FDh
64KB
Block174
00AEh
0000h~00FDh
64KB
Block143
008Fh
0000h~00FDh
64KB
Block175
00AFh
0000h~00FDh
64KB
Block144
0090h
0000h~00FDh
64KB
Block176
00B0h
0000h~00FDh
64KB
Block145
0091h
0000h~00FDh
64KB
Block177
00B1h
0000h~00FDh
64KB
Block146
0092h
0000h~00FDh
64KB
Block178
00B2h
0000h~00FDh
64KB
Block147
0093h
0000h~00FDh
64KB
Block179
00B3h
0000h~00FDh
64KB
Block148
0094h
0000h~00FDh
64KB
Block180
00B4h
0000h~00FDh
64KB
Block149
0095h
0000h~00FDh
64KB
Block181
00B5h
0000h~00FDh
64KB
Block150
0096h
0000h~00FDh
64KB
Block182
00B6h
0000h~00FDh
64KB
Block151
0097h
0000h~00FDh
64KB
Block183
00B7h
0000h~00FDh
64KB
Block152
0098h
0000h~00FDh
64KB
Block184
00B8h
0000h~00FDh
64KB
Block153
0099h
0000h~00FDh
64KB
Block185
00B9h
0000h~00FDh
64KB
Block154
009Ah
0000h~00FDh
64KB
Block186
00BAh
0000h~00FDh
64KB
Block155
009Bh
0000h~00FDh
64KB
Block187
00BBh
0000h~00FDh
64KB
Block156
009Ch
0000h~00FDh
64KB
Block188
00BCh
0000h~00FDh
64KB
Block157
009Dh
0000h~00FDh
64KB
Block189
00BDh
0000h~00FDh
64KB
Block158
009Eh
0000h~00FDh
64KB
Block190
00BEh
0000h~00FDh
64KB
Block159
009Fh
0000h~00FDh
64KB
Block191
00BFh
0000h~00FDh
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
19
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block192
00C0h
0000h~00FDh
64KB
Block224
00E0h
0000h~00FDh
64KB
Block193
00C1h
0000h~00FDh
64KB
Block225
00E1h
0000h~00FDh
64KB
Block194
00C2h
0000h~00FDh
64KB
Block226
00E2h
0000h~00FDh
64KB
Block195
00C3h
0000h~00FDh
64KB
Block227
00E3h
0000h~00FDh
64KB
Block196
00C4h
0000h~00FDh
64KB
Block228
00E4h
0000h~00FDh
64KB
Block197
00C5h
0000h~00FDh
64KB
Block229
00E5h
0000h~00FDh
64KB
Block198
00C6h
0000h~00FDh
64KB
Block230
00E6h
0000h~00FDh
64KB
Block199
00C7h
0000h~00FDh
64KB
Block231
00E7h
0000h~00FDh
64KB
Block200
00C8h
0000h~00FDh
64KB
Block232
00E8h
0000h~00FDh
64KB
Block201
00C9h
0000h~00FDh
64KB
Block233
00E9h
0000h~00FDh
64KB
Block202
00CAh
0000h~00FDh
64KB
Block234
00EAh
0000h~00FDh
64KB
Block203
00CBh
0000h~00FDh
64KB
Block235
00EBh
0000h~00FDh
64KB
Block204
00CCh
0000h~00FDh
64KB
Block236
00ECh
0000h~00FDh
64KB
Block205
00CDh
0000h~00FDh
64KB
Block237
00EDh
0000h~00FDh
64KB
Block206
00CEh
0000h~00FDh
64KB
Block238
00EEh
0000h~00FDh
64KB
Block207
00CFh
0000h~00FDh
64KB
Block239
00EFh
0000h~00FDh
64KB
Block208
00D0h
0000h~00FDh
64KB
Block240
00F0h
0000h~00FDh
64KB
Block209
00D1h
0000h~00FDh
64KB
Block241
00F1h
0000h~00FDh
64KB
Block210
00D2h
0000h~00FDh
64KB
Block242
00F2h
0000h~00FDh
64KB
Block211
00D3h
0000h~00FDh
64KB
Block243
00F3h
0000h~00FDh
64KB
Block212
00D4h
0000h~00FDh
64KB
Block244
00F4h
0000h~00FDh
64KB
Block213
00D5h
0000h~00FDh
64KB
Block245
00F5h
0000h~00FDh
64KB
Block214
00D6h
0000h~00FDh
64KB
Block246
00F6h
0000h~00FDh
64KB
Block215
00D7h
0000h~00FDh
64KB
Block247
00F7h
0000h~00FDh
64KB
Block216
00D8h
0000h~00FDh
64KB
Block248
00F8h
0000h~00FDh
64KB
Block217
00D9h
0000h~00FDh
64KB
Block249
00F9h
0000h~00FDh
64KB
Block218
00DAh
0000h~00FDh
64KB
Block250
00FAh
0000h~00FDh
64KB
Block219
00DBh
0000h~00FDh
64KB
Block251
00FBh
0000h~00FDh
64KB
Block220
00DCh
0000h~00FDh
64KB
Block252
00FCh
0000h~00FDh
64KB
Block221
00DDh
0000h~00FDh
64KB
Block253
00FDh
0000h~00FDh
64KB
Block222
00DEh
0000h~00FDh
64KB
Block254
00FEh
0000h~00FDh
64KB
Block223
00DFh
0000h~00FDh
64KB
Block255
00FFh
0000h~00FDh
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
20
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block256
0100h
0000h~00FDh
64KB
Block288
0120h
0000h~00FDh
64KB
Block257
0101h
0000h~00FDh
64KB
Block289
0121h
0000h~00FDh
64KB
Block258
0102h
0000h~00FDh
64KB
Block290
0122h
0000h~00FDh
64KB
Block259
0103h
0000h~00FDh
64KB
Block291
0123h
0000h~00FDh
64KB
Block260
0104h
0000h~00FDh
64KB
Block292
0124h
0000h~00FDh
64KB
Block261
0105h
0000h~00FDh
64KB
Block293
0125h
0000h~00FDh
64KB
Block262
0106h
0000h~00FDh
64KB
Block294
0126h
0000h~00FDh
64KB
Block263
0107h
0000h~00FDh
64KB
Block295
0127h
0000h~00FDh
64KB
Block264
0108h
0000h~00FDh
64KB
Block296
0128h
0000h~00FDh
64KB
Block265
0109h
0000h~00FDh
64KB
Block297
0129h
0000h~00FDh
64KB
Block266
010Ah
0000h~00FDh
64KB
Block298
012Ah
0000h~00FDh
64KB
Block267
010Bh
0000h~00FDh
64KB
Block299
012Bh
0000h~00FDh
64KB
Block268
010Ch
0000h~00FDh
64KB
Block300
012Ch
0000h~00FDh
64KB
Block269
010Dh
0000h~00FDh
64KB
Block301
012Dh
0000h~00FDh
64KB
Block270
010Eh
0000h~00FDh
64KB
Block302
012Eh
0000h~00FDh
64KB
Block271
010Fh
0000h~00FDh
64KB
Block303
012Fh
0000h~00FDh
64KB
Block272
0110h
0000h~00FDh
64KB
Block304
0130h
0000h~00FDh
64KB
Block273
0111h
0000h~00FDh
64KB
Block305
0131h
0000h~00FDh
64KB
Block274
0112h
0000h~00FDh
64KB
Block306
0132h
0000h~00FDh
64KB
Block275
0113h
0000h~00FDh
64KB
Block307
0133h
0000h~00FDh
64KB
Block276
0114h
0000h~00FDh
64KB
Block308
0134h
0000h~00FDh
64KB
Block277
0115h
0000h~00FDh
64KB
Block309
0135h
0000h~00FDh
64KB
Block278
0116h
0000h~00FDh
64KB
Block310
0136h
0000h~00FDh
64KB
Block279
0117h
0000h~00FDh
64KB
Block311
0137h
0000h~00FDh
64KB
Block280
0118h
0000h~00FDh
64KB
Block312
0138h
0000h~00FDh
64KB
Block281
0119h
0000h~00FDh
64KB
Block313
0139h
0000h~00FDh
64KB
Block282
011Ah
0000h~00FDh
64KB
Block314
013Ah
0000h~00FDh
64KB
Block283
011Bh
0000h~00FDh
64KB
Block315
013Bh
0000h~00FDh
64KB
Block284
011Ch
0000h~00FDh
64KB
Block316
013Ch
0000h~00FDh
64KB
Block285
011Dh
0000h~00FDh
64KB
Block317
013Dh
0000h~00FDh
64KB
Block286
011Eh
0000h~00FDh
64KB
Block318
013Eh
0000h~00FDh
64KB
Block287
011Fh
0000h~00FDh
64KB
Block319
013Fh
0000h~00FDh
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
21
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block320
0140h
0000h~00FDh
64KB
Block352
0160h
0000h~00FDh
64KB
Block321
0141h
0000h~00FDh
64KB
Block353
0161h
0000h~00FDh
64KB
Block322
0142h
0000h~00FDh
64KB
Block354
0162h
0000h~00FDh
64KB
Block323
0143h
0000h~00FDh
64KB
Block355
0163h
0000h~00FDh
64KB
Block324
0144h
0000h~00FDh
64KB
Block356
0164h
0000h~00FDh
64KB
Block325
0145h
0000h~00FDh
64KB
Block357
0165h
0000h~00FDh
64KB
Block326
0146h
0000h~00FDh
64KB
Block358
0166h
0000h~00FDh
64KB
Block327
0147h
0000h~00FDh
64KB
Block359
0167h
0000h~00FDh
64KB
Block328
0148h
0000h~00FDh
64KB
Block360
0168h
0000h~00FDh
64KB
Block329
0149h
0000h~00FDh
64KB
Block361
0169h
0000h~00FDh
64KB
Block330
014Ah
0000h~00FDh
64KB
Block362
016Ah
0000h~00FDh
64KB
Block331
014Bh
0000h~00FDh
64KB
Block363
016Bh
0000h~00FDh
64KB
Block332
014Ch
0000h~00FDh
64KB
Block364
016Ch
0000h~00FDh
64KB
Block333
014Dh
0000h~00FDh
64KB
Block365
016Dh
0000h~00FDh
64KB
Block334
014Eh
0000h~00FDh
64KB
Block366
016Eh
0000h~00FDh
64KB
Block335
014Fh
0000h~00FDh
64KB
Block367
016Fh
0000h~00FDh
64KB
Block336
0150h
0000h~00FDh
64KB
Block368
0170h
0000h~00FDh
64KB
Block337
0151h
0000h~00FDh
64KB
Block369
0171h
0000h~00FDh
64KB
Block338
0152h
0000h~00FDh
64KB
Block370
0172h
0000h~00FDh
64KB
Block339
0153h
0000h~00FDh
64KB
Block371
0173h
0000h~00FDh
64KB
Block340
0154h
0000h~00FDh
64KB
Block372
0174h
0000h~00FDh
64KB
Block341
0155h
0000h~00FDh
64KB
Block373
0175h
0000h~00FDh
64KB
Block342
0156h
0000h~00FDh
64KB
Block374
0176h
0000h~00FDh
64KB
Block343
0157h
0000h~00FDh
64KB
Block375
0177h
0000h~00FDh
64KB
Block344
0158h
0000h~00FDh
64KB
Block376
0178h
0000h~00FDh
64KB
Block345
0159h
0000h~00FDh
64KB
Block377
0179h
0000h~00FDh
64KB
Block346
015Ah
0000h~00FDh
64KB
Block378
017Ah
0000h~00FDh
64KB
Block347
015Bh
0000h~00FDh
64KB
Block379
017Bh
0000h~00FDh
64KB
Block348
015Ch
0000h~00FDh
64KB
Block380
017Ch
0000h~00FDh
64KB
Block349
015Dh
0000h~00FDh
64KB
Block381
017Dh
0000h~00FDh
64KB
Block350
015Eh
0000h~00FDh
64KB
Block382
017Eh
0000h~00FDh
64KB
Block351
015Fh
0000h~00FDh
64KB
Block383
017Fh
0000h~00FDh
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
22
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block384
0180h
0000h~00FDh
64KB
Block416
01A0h
0000h~00FDh
64KB
Block385
0181h
0000h~00FDh
64KB
Block417
01A1h
0000h~00FDh
64KB
Block386
0182h
0000h~00FDh
64KB
Block418
01A2h
0000h~00FDh
64KB
Block387
0183h
0000h~00FDh
64KB
Block419
01A3h
0000h~00FDh
64KB
Block388
0184h
0000h~00FDh
64KB
Block420
01A4h
0000h~00FDh
64KB
Block389
0185h
0000h~00FDh
64KB
Block421
01A5h
0000h~00FDh
64KB
Block390
0186h
0000h~00FDh
64KB
Block422
01A6h
0000h~00FDh
64KB
Block391
0187h
0000h~00FDh
64KB
Block423
01A7h
0000h~00FDh
64KB
Block392
0188h
0000h~00FDh
64KB
Block424
01A8h
0000h~00FDh
64KB
Block393
0189h
0000h~00FDh
64KB
Block425
01A9h
0000h~00FDh
64KB
Block394
018Ah
0000h~00FDh
64KB
Block426
01AAh
0000h~00FDh
64KB
Block395
018Bh
0000h~00FDh
64KB
Block427
01ABh
0000h~00FDh
64KB
Block396
018Ch
0000h~00FDh
64KB
Block428
01ACh
0000h~00FDh
64KB
Block397
018Dh
0000h~00FDh
64KB
Block429
01ADh
0000h~00FDh
64KB
Block398
018Eh
0000h~00FDh
64KB
Block430
01AEh
0000h~00FDh
64KB
Block399
018Fh
0000h~00FDh
64KB
Block431
01AFh
0000h~00FDh
64KB
Block400
0190h
0000h~00FDh
64KB
Block432
01B0h
0000h~00FDh
64KB
Block401
0191h
0000h~00FDh
64KB
Block433
01B1h
0000h~00FDh
64KB
Block402
0192h
0000h~00FDh
64KB
Block434
01B2h
0000h~00FDh
64KB
Block403
0193h
0000h~00FDh
64KB
Block435
01B3h
0000h~00FDh
64KB
Block404
0194h
0000h~00FDh
64KB
Block436
01B4h
0000h~00FDh
64KB
Block405
0195h
0000h~00FDh
64KB
Block437
01B5h
0000h~00FDh
64KB
Block406
0196h
0000h~00FDh
64KB
Block438
01B6h
0000h~00FDh
64KB
Block407
0197h
0000h~00FDh
64KB
Block439
01B7h
0000h~00FDh
64KB
Block408
0198h
0000h~00FDh
64KB
Block440
01B8h
0000h~00FDh
64KB
Block409
0199h
0000h~00FDh
64KB
Block441
01B9h
0000h~00FDh
64KB
Block410
019Ah
0000h~00FDh
64KB
Block442
01BAh
0000h~00FDh
64KB
Block411
019Bh
0000h~00FDh
64KB
Block443
01BBh
0000h~00FDh
64KB
Block412
019Ch
0000h~00FDh
64KB
Block444
01BCh
0000h~00FDh
64KB
Block413
019Dh
0000h~00FDh
64KB
Block445
01BDh
0000h~00FDh
64KB
Block414
019Eh
0000h~00FDh
64KB
Block446
01BEh
0000h~00FDh
64KB
Block415
019Fh
0000h~00FDh
64KB
Block447
01BFh
0000h~00FDh
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
23
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block
Block Address
Page and Sector
Address(1)
Size
Block
Block Address
Page and Sector
Address(1)
Size
Block448
01C0h
0000h~00FDh
64KB
Block480
01E0h
0000h~00FDh
64KB
Block449
01C1h
0000h~00FDh
64KB
Block481
01E1h
0000h~00FDh
64KB
Block450
01C2h
0000h~00FDh
64KB
Block482
01E2h
0000h~00FDh
64KB
Block451
01C3h
0000h~00FDh
64KB
Block483
01E3h
0000h~00FDh
64KB
Block452
01C4h
0000h~00FDh
64KB
Block484
01E4h
0000h~00FDh
64KB
Block453
01C5h
0000h~00FDh
64KB
Block485
01E5h
0000h~00FDh
64KB
Block454
01C6h
0000h~00FDh
64KB
Block486
01E6h
0000h~00FDh
64KB
Block455
01C7h
0000h~00FDh
64KB
Block487
01E7h
0000h~00FDh
64KB
Block456
01C8h
0000h~00FDh
64KB
Block488
01E8h
0000h~00FDh
64KB
Block457
01C9h
0000h~00FDh
64KB
Block489
01E9h
0000h~00FDh
64KB
Block458
01CAh
0000h~00FDh
64KB
Block490
01EAh
0000h~00FDh
64KB
Block459
01CBh
0000h~00FDh
64KB
Block491
01EBh
0000h~00FDh
64KB
Block460
01CCh
0000h~00FDh
64KB
Block492
01ECh
0000h~00FDh
64KB
Block461
01CDh
0000h~00FDh
64KB
Block493
01EDh
0000h~00FDh
64KB
Block462
01CEh
0000h~00FDh
64KB
Block494
01EEh
0000h~00FDh
64KB
Block463
01CFh
0000h~00FDh
64KB
Block495
01EFh
0000h~00FDh
64KB
Block464
01D0h
0000h~00FDh
64KB
Block496
01F0h
0000h~00FDh
64KB
Block465
01D1h
0000h~00FDh
64KB
Block497
01F1h
0000h~00FDh
64KB
Block466
01D2h
0000h~00FDh
64KB
Block498
01F2h
0000h~00FDh
64KB
Block467
01D3h
0000h~00FDh
64KB
Block499
01F3h
0000h~00FDh
64KB
Block468
01D4h
0000h~00FDh
64KB
Block500
01F4h
0000h~00FDh
64KB
Block469
01D5h
0000h~00FDh
64KB
Block501
01F5h
0000h~00FDh
64KB
Block470
01D6h
0000h~00FDh
64KB
Block502
01F6h
0000h~00FDh
64KB
Block471
01D7h
0000h~00FDh
64KB
Block503
01F7h
0000h~00FDh
64KB
Block472
01D8h
0000h~00FDh
64KB
Block504
01F8h
0000h~00FDh
64KB
Block473
01D9h
0000h~00FDh
64KB
Block505
01F9h
0000h~00FDh
64KB
Block474
01DAh
0000h~00FDh
64KB
Block506
01FAh
0000h~00FDh
64KB
Block475
01DBh
0000h~00FDh
64KB
Block507
01FBh
0000h~00FDh
64KB
Block476
01DCh
0000h~00FDh
64KB
Block508
01FCh
0000h~00FDh
64KB
Block477
01DDh
0000h~00FDh
64KB
Block509
01FDh
0000h~00FDh
64KB
Block478
01DEh
0000h~00FDh
64KB
Block510
01FEh
0000h~00FDh
64KB
Block479
01DFh
0000h~00FDh
64KB
Block511
01FFh
0000h~00FDh
64KB
NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range.
Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register.
24
OneNAND256(KFG5616x1A-xxB5)
2.7.2
FLASH MEMORY
Internal Memory Spare Area Assignment
The figure below shows the assignment of the spare area in the Internal Memory NAND Array.
Main area
256W
Spare
area
8W
Main area
256W
Spare
area
8W
ECCm ECCm
Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3 ECCm
1st
2nd
3rd
MSB
MSB LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
ECCs
2nd
MSB
LSB
(Note3) Note4 Note4
MSB
LSB
MSB
{
{
{
{
{
{
{
{
LSB
LSB
ECCs
1st
1st W
2nd W
3rd W
4th W
5th W
6th W
7th W
8th W
Spare Area Assignment in the Internal Memory NAND Array Information
Word
1
2
3
4
Byte
LSB
MSB
Note
Description
1
Invalid Block information in 1st and 2nd page of an invalid block
2
Managed by internal ECC logic for Logical Sector Number data
3
Reserved for future use
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Dedicated to internal ECC logic. Read Only.
ECCm 1st for main area data
MSB
Dedicated to internal ECC logic. Read Only.
ECCm 2nd for main area data
LSB
Dedicated to internal ECC logic. Read Only.
ECCm 3rd for main area data
MSB
Dedicated to internal ECC logic. Read Only.
ECCs 1st for 2nd word of spare area data
LSB
Dedicated to internal ECC logic. Read Only.
ECCs 2nd for 3rd word of spare area data
5
6
7
MSB
8
LSB
MSB
3
Reserved for future use
4
Available to the user
25
OneNAND256(KFG5616x1A-xxB5)
2.7.3
FLASH MEMORY
External Memory (BufferRAM) Address Map
The following table shows the External Memory address map in Word and Byte Order.
Note that the data output is unknown while host reads a register bit of reserved area.
Division
Main area
(64KB)
Spare area
(8KB)
Address
(word order)
Address
(byte order)
0000h~00FFh
00000h~001FEh
Size
(total 128KB)
512B
0100h~01FFh
00200h~003FEh
512B
0200h~02FFh
00400h~005FEh
512B
0300h~03FFh
00600h~007FEh
512B
0400h~04FFh
00800h~009FEh
512B
0500h~05FFh
00A00h~00BFEh
512B
0600h~7FFFh
00C00h~0FFFEh
61KB
8000h~8007h
10000h~1000Eh
16B
8008h~800Fh
10010h~1001Eh
16B
1KB
2KB
61KB
32B
Usage
Description
BootM 0
BootRAM Main sector0
BootM 1
BootRAM Main sector1
DataM 0_0
DataRAM Main page0/sector0
DataM 0_1
DataRAM Main page0/sector1
DataM 1_0
DataRAM Main page1/sector0
DataM 1_1
DataRAM Main page1/sector1
Reserved
Reserved
BootS 0
BootRAM Spare sector0
BootS 1
BootRAM Spare sector1
8010h~8017h
10020h~1002Eh
16B
DataS 0_0
DataRAM Spare page0/sector0
8018h~801Fh
10030h~1003Eh
16B
DataS 0_1
DataRAM Spare page0/sector1
8020h~8027h
10040h~1004Eh
16B
DataS 1_0
DataRAM Spare page1/sector0
8028h~802Fh
10050h~1005Eh
16B
DataS 1_1
DataRAM Spare page1/sector1
64B
8030h~8FFFh
1006Eh~11FFEh
8096B
8096B
Reserved
Reserved
Reserved
(24KB)
9000h~BFFFh
12000h~17FFEh
24KB
24KB
Reserved
Reserved
Reserved
(8KB)
C000h~CFFFh
18000h~19FFEh
8KB
8KB
Reserved
Reserved
Reserved
(16KB)
D000h~EFFFh
1A000h~1DFFEh
16KB
16KB
Reserved
Reserved
Registers
(8KB)
F000h~FFFFh
1E000h~1FFFEh
8KB
8KB
Registers
Registers
26
OneNAND256(KFG5616x1A-xxB5)
2.7.4
FLASH MEMORY
External Memory Map Detail Information
The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas.
• BootRAM(Main area)
-0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB
0100h~01FFh(512B)
BootM 1
(sector 1 of page 0)
0000h~00FFh(512B)
BootM 0
(sector 0 of page 0)
• DataRAM(Main area)
-0200h~05FFh: 4(sector) x 512byte(NAND main area) = 2KB
0200h~02FFh(512B)
DataM 0_0
(sector 0 of page 0)
0400h~04FFh(512B)
DataM 1_0
(sector 0 of page 1)
0300h~03FFh(512B)
DataM 0_1
(sector 1 of page 0)
0500h~05FFh(512B)
DataM 1_1
(sector 1 of page 1)
• BootRAM(Spare area)
-8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B
8008h~800Fh(16B)
BootS 1
(sector 1 of page 0)
8000h~8007h(16B)
BootS 0
(sector 0 of page 0)
• DataRAM(Spare area)
-8010h~802Fh: 4(sector) x 16byte(NAND spare area) = 64B
8010h~8017h(16B)
DataS 0_0
(sector 0 of page 0)
8020h~8027h(16B)
DataS 1_0
(sector 0 of page 1)
8018h~801Fh(16B)
DataS 0_1
(sector 1 of page 0)
*NAND Flash array consists of 1KB page size and 64KB block size.
27
8028h~802Fh(16B)
DataS 1_1
(sector 1 of page 1)
OneNAND256(KFG5616x1A-xxB5)
2.7.5
FLASH MEMORY
External Memory Spare Area Assignment
Equivalent to 1word of NAND Flash
Buf.
Word
Address
Byte
Address
BootS 0
8000h
10000h
BI
8001h
10002h
Managed by Internal ECC logic
BootS 1
DataS
0_0
DataS
0_1
F
E
D
C
B
A
9
8
7
5
4
3
2
1
8002h
10004h
8003h
10006h
8004h
10008h
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
8005h
1000Ah
ECC Code for Spare area data (1st)
ECC Code for Main area data (3rd)
8006h
1000Ch
FFh(Reserved for the future use)
ECC Code for Spare area data (2nd)
8007h
1000Eh
Free Usage
8008h
10010h
BI
8009h
10012h
800Ah
10014h
Reserved for the future use
6
Managed by Internal ECC logic
Reserved for the current and future use
Managed by Internal ECC logic
Reserved for the future use
Managed by Internal ECC logic
800Bh
10016h
800Ch
10018h
ECC Code for Main area data (2nd)
Reserved for the current and future use
ECC Code for Main area data (1st)
800Dh
1001Ah
ECC Code for Spare area data (1st)
ECC Code for Main area data (3rd)
800Eh
1001Ch
FFh(Reserved for the future use)
ECC Code for Spare area data (2nd)
800Fh
1001Eh
Free Usage
8010h
10020h
BI
8011h
10022h
8012h
10024h
8013h
10026h
8014h
10028h
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
8015h
1002Ah
ECC Code for Spare area data (1 )
ECC Code for Main area data (3rd)
8016h
1002Ch
FFh(Reserved for the future use)
ECC Code for Spare area data (2nd)
8017h
1002Eh
Free Usage
8018h
10030h
BI
8019h
10032h
801Ah
10034h
Managed by Internal ECC logic
Reserved for the future use
Managed by Internal ECC logic
Reserved for the current and future use
st
Managed by Internal ECC logic
Reserved for the future use
Managed by Internal ECC logic
801Bh
10036h
801Ch
10038h
ECC Code for Main area data (2nd)
Reserved for the current and future use
ECC Code for Main area data (1st)
801Dh
1003Ah
ECC Code for Spare area data (1 )
ECC Code for Main area data (3rd)
801Eh
1003Ch
FFh(Reserved for the future use)
ECC Code for Spare area data (2nd)
801Fh
1003Eh
st
Free Usage
28
0
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Equivalent to 1word of NAND Flash
Buf.
DataS 1_0
DataS 1_1
Word
Byte
Address Address
F
E
D
C
B
A
9
8
7
6
5
8020h
10040h
BI
8021h
10042h
Managed by Internal ECC logic
3
2
1
8022h
10044h
8023h
10046h
8024h
10048h
ECC Code for Main area data (2nd)
ECC Code for Main area data (1st)
8025h
1004Ah
ECC Code for Spare area data (1st)
ECC Code for Main area data (3rd)
8026h
1004Ch
FFh(Reserved for the future use)
ECC Code for Spare area data (2nd)
8027h
1004Eh
Free Usage
8028h
10050h
BI
8029h
10052h
802Ah
10054h
Reserved for the future use
4
0
Managed by Internal ECC logic
Reserved for the current and future use
Managed by Internal ECC logic
Reserved for the future use
Managed by Internal ECC logic
802Bh
10056h
802Ch
10058h
ECC Code for Main area data (2nd)
Reserved for the current and future use
ECC Code for Main area data (1st)
802Dh
1005Ah
ECC Code for Spare area data (1st)
ECC Code for Main area data (3rd)
802Eh
1005Ch
FFh(Reserved for the future use)
ECC Code for Spare area data (2nd)
802Fh
1005Eh
Free Usage
NOTE:
- BI: Invalid block Information
>Host can use complete spare area except BI and ECC code area. For example,
Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation.
>In case of ’with ECC’ mode, OneNAND automatically generates ECC code for both main and spare data of memory during program operation,
but does not update ECC code to spare bufferRAM during load operation.
>When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register
as it is.
29
OneNAND256(KFG5616x1A-xxB5)
2.8
FLASH MEMORY
Registers
Section 2.8 of this specification provides information about the OneNAND registers.
2.8.1
Register Address Map
This map describes the register addresses, register name, register description, and host accessibility.
Address
(word order)
Address
(byte order)
Name
Host
Access
F000h
1E000h
Manufacturer ID
R
F001h
1E002h
Device ID
R
Device identification
F002h
1E004h
Version ID
R
N/A
F003h
1E006h
Data Buffer size
R
Data buffer size
F004h
1E008h
Boot Buffer size
R
Boot buffer size
F005h
1E00Ah
Amount of
buffers
R
Amount of data/boot buffers
Description
Manufacturer identification
F006h
1E00Ch
Technology
R
Info about technology
F007h~F0FFh
1E00Eh~1E1FEh
Reserved
-
Reserved for user
F100h
1E200h
Start address 1
R/W
NAND Flash Block address
F101h
1E202h
Start address 2
R/W
N/A
F102h
1E204h
Start address 3
R/W
Destination Block address for Copy back program
Destination Page & Sector address for Copy
back program
F103h
1E206h
Start address 4
R/W
F104h
1E208h
Start address 5
-
N/A
F105h
1E20Ah
Start address 6
-
N/A
F106h
1E20Ch
Start address 7
-
N/A
F107h
1E20Eh
Start address 8
R/W
F108h~F1FFh
1E210h~1E3FEh
Reserved
-
F200h
1E400h
Start Buffer
R/W
NAND Flash Page & Sector address
Reserved for user
Buffer Number for the page data transfer to/from the
memory and the start Buffer Address
The meaning is with which buffer to start and how many
buffers to use for the data transfer
F201h~F207h
1E402h~1E40Eh
Reserved
-
Reserved for user
F208h~F21Fh
1E410h~1E43Eh
Reserved
-
Reserved for vendor specific purposes
F220h
1E440h
Command
R/W
F221h
1E442h
System
Configuration 1
R, R/W
F222h
1E444h
System
Configuration 2
-
N/A
F223h~F22Fh
1E446h~1E45Eh
Reserved
-
Reserved for user
F230h~F23Fh
1E460h~1E47Eh
Reserved
-
Reserved for vendor specific purposes
F240h
1E480h
Controller Status
R
Controller Status and result of memory operation
F241h
1E482h
Interrupt
R/W
F242h~F24Bh
1E484h~1E496h
Reserved
-
F24Ch
1E498h
Start
Block Address
R/W
30
Host control and memory operation commands
Memory and Host Interface Configuration
Memory Command Completion Interrupt Status
Reserved for user
Start memory block address in Write Protection mode
OneNAND256(KFG5616x1A-xxB5)
Address
(word order)
Address
(byte order)
F24Dh
FLASH MEMORY
Name
Host
Access
1E49Ah
Reserved
R/W
F24Eh
1E49Ch
Write Protection
Status
R
Current memory Write Protection status
(unlocked/locked/tight-locked)
F24Fh~FEFFh
1E49Eh~1FDFEh
Reserved
-
Reserved for user
FF00h
1FE00h
ECC Status
Register
R
ECC status of sector
FF01h
1FE02h
ECC Result of
main area data
R
ECC error position of Main area data error for first
selected Sector
FF02h
1FE04h
ECC Result of
spare area data
R
ECC error position of Spare area data error for first
selected Sector
FF03h
1FE06h
ECC Result of
main area data
R
ECC error position of Main area data error for second
selected Sector
FF04h
1FE08h
ECC Result of
spare area data
R
ECC error position of Spare area data error for second
selected Sector
FF05h~FFFFh
1FE0Ah~1FFFEh
Reserved
-
Reserved for vendor specific purposes
2.8.2
Description
Reserved for user
Manufacturer ID Register F000h (R)
This Read register describes the manufacturer's identification.
Samsung Electronics Company manufacturer's ID is 00ECh.
F000h, default = 00ECh
15
14
13
12
11
10
9
8
7
ManufID
31
6
5
4
3
2
1
0
OneNAND256(KFG5616x1A-xxB5)
2.8.3
FLASH MEMORY
Device ID Register F001h (R)
This Read register describes the device.
F001h, see table for default.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DeviceID
Device Identification
Device Identification
Description
DeviceID [1:0] Vcc
00 = 1.8V, 01 = 2.65V/3.3V, 10/11 = reserved
DeviceID [2] Muxed/Demuxed
0 = Muxed, 1 = Demuxed
DeviceID [3] Single/DPP
0 = Single, 1 = DDP
DeviceID [7:4] Density
0000 = 128Mb, 0001 = 256Mb, 0010 = 512Mb, 0011 = 1Gb, 0100 = 2Gb, 0101=4Gb
DeviceID [8] Top/Bottom Boot
0 = Bottom Boot, 1 = Top Boot
Device ID Default
Device
DeviceID[15:0]
KFG5616Q1A
0014h
KFG5616D1A
0015h
KFG5616U1A
0015h
32
OneNAND256(KFG5616x1A-xxB5)
2.8.4
FLASH MEMORY
Version ID Register F002h
This register is reserved for manufacturer
2.8.5
Data Buffer Size Register F003h (R)
This Read register describes the size of the Data Buffer.
F003h, default = 0400h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
DataBufSize
Data Buffer Size Information
Version Identification
Description
Total data buffer size in Words equal to 2 buffers of 512 Words each
DataBufSize
2.8.6
(2 x 512 = 210) in the memory interface
Boot Buffer Size Register F004h (R)
This Read register describes the size of the Boot Buffer.
F004h, default = 0200h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
BootBufSize
Register Information
BootBufSize
Description
Total boot buffer size in Words equal to 1 buffer of 512 Words
(1 x 512 = 29) in the memory interface
33
OneNAND256(KFG5616x1A-xxB5)
2.8.7
FLASH MEMORY
Number of Buffers Register F005h (R)
This Read register describes the number of each Buffer.
F005h, default = 0201h
15
14
13
12
11
10
9
8
7
6
5
DataBufAmount
4
3
2
1
0
2
1
0
BootBufAmount
Number of Buffers Information
Register Information
Description
DataBufAmount
The number of data buffers = 2 (2N, N=1)
BootBufAmount
The number of boot buffers = 1 (2N, N=0)
2.8.8
Technology Register F006h (R)
This Read register describes the internal NAND array technology.
F006h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
Tech
Technology Information
Technology
Register Setting
NAND SLC
0000h
NAND MLC
0001h
Reserved
0002h ~ FFFFh
34
4
3
OneNAND256(KFG5616x1A-xxB5)
2.8.9
FLASH MEMORY
Start Address1 Register F100h (R/W)
This Read/Write register describes the NAND Flash block address which will be loaded, programmed, or erased.
F100h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
Reserved(0000000)
4
3
2
FBA
Device
Number of Block
FBA
256Mb
512
FBA[8:0]
Start Address1 Information
Register Information
Description
FBA
NAND Flash Block Address
2.8.10 Start Address2 Register F101h (R/W)
This register is reserved for future use.
35
1
0
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.11 Start Address3 Register F102h (R/W)
This Read/Write register describes the NAND Flash destination block address which will be copy back programmed.
F102h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
Reserved(0000000)
4
3
2
1
0
FCBA
Device
Number of Block
FBA
256Mb
512
FCBA[8:0]
Start Address3 Information
Register Information
Description
FCBA
NAND Flash Copy Back Block Address
2.8.12 Start Address4 Register F103h (R/W)
This Read/Write register describes the NAND Flash destination page address in a block and the NAND Flash destination sector
address in a page for copy back programming.
F103h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
Reserved(00000000)
4
FCPA
3
2
1
Start Address4 Information
Item
Description
Default Value
Range
FCPA
NAND Flash Copy Back Page
Address
000000
000000 ~ 111111,
6 bits for 64 pages
FCSA
NAND Flash Copy Back Sector
Address
0
0 ~ 1,
1 bit for 2 sectors
36
0
Reserved FCSA
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.13 Start Address5 Register F104h
This register is reserved for future use.
2.8.14 Start Address6 Register F105h
This register is reserved for future use.
2.8.15 Start Address7 Register F106h
This register is reserved for future use.
2.8.16 Start Address8 Register F107h (R/W)
This Read/Write register describes the NAND Flash start page address in a block for a page load, copy back program, or program
operation and the NAND Flash start sector address in a page for a load, copy back program, or program operation.
F107h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
Reserved (00000000)
4
FPA
3
2
1
0
Reserved
FSA
Start Address8 Information
Item
Description
Default Value
Range
FPA
NAND Flash Page Address
000000
000000 ~ 111111,
6 bits for 64 pages
FSA
NAND Flash Sector Address
0
0 ~ 1,
1 bit for 2 sectors
37
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.17 Start Buffer Register F200h (R/W)
This Read/Write register describes the BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA).
The BufferRAM Sector Count (BSC) field specifies the number of sectors to be loaded, programmed, or copy back programmed. At 0
value (the default value), the number of sector is "2". For example, if BSA = 1000, BSC = 0, then the selected BufferRAM will count
up from '1000 → 1001'.
The BufferRAM Sector Address (BSA) is the sector 0~1 address in the internal BootRAM and DataRAM where data is placed.
F200h, default = 0000h
15
14
13
12
11
10
Reserved(0000)
9
8
7
6
BSA
5
4
3
2
1
Reserved(0000000)
0
BSC
Start Buffer Register Information
Item
Description
BSA[3]
Selection bit between BootRAM and DataRAM
BSA[2]
Selection bit between DataRAM0 and DataRAM1
BSA[0]
Selection bit between Sector0 and Sector1 in the internal BootRAM
Selection bit between Sector0 and Sector1 in the internal DataRAM
Main area data
(512B)
Spare area data
(16B)
{
{
BSA
BootRAM
DataRAM0
DataRAM1
BootRAM 0
0000
BootRAM 1
0001
DataRAM 0_0
1000
DataRAM 0_1
1001
DataRAM 1_0
1100
DataRAM 1_1
1101
38
Sector: (512 + 16) Byte
BSC
Number of Sectors
1
1 sector
0
2 sectors
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.18 Command Register F220h (R/W)
This Read/Write register describes the operation of the OneNAND interface.
Note that all command should be issued when INT is turned to busy from ready state, by writing 0 to INT register. After any command
is issued, INT goes back to ready state as the corresponding operation is completed. (00F0h and 00F3h may be issued during busy
at certain cases. Refer to command register table below)
F220h, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command
CMD
Operation
Acceptable
command
during busy
0000h
Load single/multiple sector data unit into buffer
00F0h, 00F3h
0013h
Load single/multiple spare sector into buffer
00F0h, 00F3h
0080h
Program single/multiple sector data unit from buffer1)
00F0h, 00F3h
001Ah
Program single/multiple spare data unit from buffer
00F0h, 00F3h
001Bh
Copy back Program operation
00F0h, 00F3h
0023h
Unlock NAND array a block
-
002Ah
Lock NAND array a block
-
002Ch
Lock-tight NAND array a block
0071h
Erase Verify Read
00F0h, 00F3h
0094h
Block Erase
00F0h, 00F3h
0095h
Multi-Block Erase
00F0h, 00F3h
00B0h
Erase Suspend
-
0030h
Erase Resume
00F0h, 00F3h
00F0h
Reset NAND Flash Core
00F3h
Reset OneNAND
0065h
OTP Access
-
2)
00F0h, 00F3h
NOTE:
1) 0080h programs both main and spare area, while 001Ah programs only spare area. Refer to chapter 5.8 for NOP limits in issuing these commands.
When using 0080h and 001Ah command, Read-only part in spare area must be masked by FF. (Refer to chapter 2.7.2)
2)’Reset OneNAND’(=Hot reset) command makes the registers and NAND Flash core into default state as the warm reset(=reset by RP pin).
39
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.19 System Configuration 1 Register F221h (R, R/W)
This Read/Write register describes the system configuration.
F221h, default = 40C0h
8
7
6
5
4
R/W
15
14
R/W
13
12
11
R/W
10
9
R/W
R/W
R/W
R/W
R/W
3
R
2
1
R
0
RM
BRL
BL
ECC
RDY
pol
INT
pol
IOBE
RDY
Conf
Reserved(000)
BWPS
Read Mode (RM)
RM
Read Mode
0
Asynchronous read(default)
1
Synchronous read
Read Mode Information[15]
Item
Definition
Description
RM
Read Mode
Selects between asynchronous read mode and
synchronous read mode
Burst Read Latency (BRL)
BRL
Latency Cycles
000
8(N/A)
001
9(N/A)
010
10(N/A)
011
3(up to 40MHz)
100
4(default, min.)
101
5
110
6
111
7
Burst Read Latency (BRL) Information[14:12]
Item
Definition
Description
BRL
Burst Read Latency
Specifies the access latency in the burst read
transfer for the initial access
40
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Burst Length (BL)
BL
Burst Length(Main)
Burst Length(Spare)
000
Continuous(default)
001
4 words
010
8 words
011
16 words
100
32 words
N/A
101~111
Reserved
Burst Length (BL) Information[11:9]
Item
BL
Definition
Description
Burst Length
Specifies the size of the burst length during a synchronous
read, wrap around and linear burst read
Error Correction Code (ECC) Information[8]
Item
Definition
Description
Error Correction Code Operation
0 = with correction (default)
1 = without correction (bypassed)
Item
Definition
Description
RDYpol
RDY signal polarity
1 = high for ready (default)
0 = low for ready
INT bit of Interrupt Status Register
INT Pin output
0 (busy)
High
1 (ready)
Low
ECC
RDY Polarity (RDYpol) Information[7]
INT Polarity (INTpol) Information[6]
INTpol
0
1 (default)
0 (busy)
Low
1 (ready)
High
41
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
I/O Buffer Enable (IOBE)
IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid
after IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register.
I/O Buffer Enable Information[5]
Item
Definition
Description
IOBE
I/O Buffer Enable for INT and
RDY signals
0 = disable (default)
1 = enable
RDY Configuration (RDY conf)
RDY Configuration Information[4]
Item
RDY conf
Definition
Description
RDY configuration
0=active one clock before valid data(default)
1=active with valid data active
Boot Buffer Write Protect Status (BWPS)
Boot Buffer Write Protect Status Information[0]
Item
Definition
Description
BWPS
Boot Buffer Write Protect Status
0 = locked (fixed)
42
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.20 System Configuration 2 Register F222h
This register is reserved for future use.
2.8.21 Controller Status Register F240h (R)
This Read register shows the overall internal status of the OneNAND and the controller.
F240h, default = 0000h
15
14
13
12
11
10
9
OnGo
Lock
Load
Prog
Erase
Error
Sus
8
7
6
Reserv
RSTB
ed(0)
5
OTPL
4
3
2
Reserved(000000)
1
0
TO
(0)
OnGo
This bit shows the overall internal status of the OneNAND device.
OnGo Information[15]
Item
Definition
Description
OnGo
Internal Device Status
0 = ready
1 = busy
Lock
This bit shows whether the host is loading data from the NAND Flash array into the locked BootRAM or whether the host is performing a program/erase of a locked block of the NAND Flash array.
Lock Information[14]
Lock
Locked/Unlocked Check Result
0
Unlocked
1
Locked
Load
This bit shows the Load Operation status.
Load Information[13]
Item
Load
Definition
Description
Load Operation status
0 = ready (default)
1 = busy or error (see controller status output modes)
43
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Program
This bit shows the Program Operation status.
Program Information[12]
Item
Definition
Description
Prog
Program Operation status
0 = ready (default)
1 = busy or error (see controller status output modes)
Erase
This bit shows the Erase Operation status.
Erase Information[11]
Item
Definition
Description
Erase
Erase Operation status
0 = ready (default)
1 = busy or error (see controller status output modes)
Error
This bit shows the overall Error status, including Load Reset, Program Reset, and Erase Reset status.
Error Information[10]
Error
Current Sector/Page Load/Program/CopyBack. Program/
Erase Result and Invalid Command Input
0
Pass
1
Fail
Erase Suspend (Sus)
This bit shows the Erase Suspend status.
Sus Information[9]
Sus
Erase Suspend Status
0
Erase Resume(Default)
1
Erase Suspend, Program Ongoing(Susp.), Load Ongoing(Susp.),
Program Fail(Susp.), Load Fail(Susp.), Invalid Command(Susp.)
44
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Reset / Busy (RSTB)
This bit shows the Reset Operation status.
RSTB Information[7]
Item
Definition
Description
RSTB
Reset Operation Status
0 = ready (default)
1 = busy (see controller status output modes)
OTP Lock Status (OTPL)
This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against
accidental re-programming of data stored in the OTP block.
The OTPL status bit is automatically updated at power-on.
OTP Lock Information[6]
OTPL
OTP Locked/Unlocked Status
0
OTP Block Unlock Status(Default)
1
OTP Block Lock Status(Disable OTP Program/Erase)
Time Out (TO)
This bit determines if there is a time out for load, program, copy back program, and erase operations. It is fixed at 'no time out'.
TO Information[0]
Item
Definition
Description
TO
Time Out
0 = no time out
45
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Controller Status Register Output Modes
Controller Status Register [15:0]
Mode
[15]
[14]
[13]
[12]
OnGo
Lock
Load
Prog
[11]
[10]
Erase Error
[9]
Sus
[8]
[7]
[6]
[5:1]
Reserved(0) RSTB OTPL Reserved(0)
[0]
TO
Load Ongoing
1
0
1
0
0
0
0
0
0
0/1
00000
0
Program Ongoing
1
0
0
1
0
0
0
0
0
0/1
00000
0
Erase Ongoing
1
0
0
0
1
0
0
0
0
0/1
00000
0
Reset Ongoing
1
0
0
0
0
0
0
0
1
0/1
00000
0
Multi-Block Erase
Ongoing
1
0
0
0
1
0
0
0
0
0/1
00000
0
Erase Verify Read
Ongoing
1
0
0
0
0
0
0
0
0
0/1
00000
0
Load OK
0
0
0
0
0
0
0
0
0
0/1
00000
0
Program OK
0
0
0
0
0
0
0
0
0
0/1
00000
0
Erase OK
0
0
0
0
0
0
0
0
0
0/1
00000
0
0
0
0
0
0
0
0
0
0
0/1
00000
0
Load Fail1)
0
0
1
0
0
1
0
0
0
0/1
00000
0
Program Fail
0
0
0
1
0
1
0
0
0
0/1
00000
0
Erase Fail
0
0
0
0
1
1
0
0
0
0/1
00000
0
0
0
0
0
1
1
0
0
0
0/1
00000
0
Load Reset2)
0
0
1
0
0
1
0
0
1
0/1
00000
0
Program Reset
0
0
0
1
0
1
0
0
1
0/1
00000
0
Erase Verify Read
OK3)
Erase Verify Read
Fail3)
Erase Reset
0
0
0
0
1
1
0
0
1
0/1
00000
0
Erase Suspend
0
0
0
0
1
0
1
0
0
0/1
00000
0
Program Lock
0
1
0
1
0
1
0
0
0
0/1
00000
0
Erase Lock
0
1
0
0
1
1
0
0
0
0/1
00000
0
Load Lock(Buffer
Lock)
0
1
1
0
0
1
0
0
0
0/1
00000
0
OTP Program
Fail(Lock)
0
1
0
1
0
1
0
0
0
1
00000
0
OTP Program Fail
0
0
0
1
0
1
0
0
0
0
00000
0
OTP Erase Fail
0
1
0
0
1
1
0
0
0
0/1
00000
0
Program Ongoing(Susp.)
1
0
0
1
1
0
1
0
0
0/1
00000
0
Load Ongoing(Susp.)
1
0
1
0
1
0
1
0
0
0/1
00000
0
Program Fail(Susp.)
0
0
0
1
1
1
1
0
0
0/1
00000
0
Load Fail(Susp.)
0
0
1
0
1
1
1
0
0
0/1
00000
0
Invalid Command
0
0
0
0
0
1
0
0
0
0/1
00000
0
Invalid Command(Susp.)
0
0
0
0
1
1
1
0
0
0/1
00000
0
NOTE:
1. ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable)
2. ERm and ERs bits in ECC status register at Load Reset case are 00. (No error)
3. Multi Block Erase status should be checked by Erase Verify Read operation.
46
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.22 Interrupt Status Register F241h (R/W)
This Read/Write register shows status of the OneNAND interrupts.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
15
14
13
INT
12
11
10
9
8
Reserved(0000000)
7
6
5
4
RI
WI
EI
RSTI
3
2
1
0
Reserved(0000)
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes
low if INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
Status
Default State
Conditions
Cold
Warm/hot
Valid
State
interrupt
Function
1
1
0
off
sets itself to ’1’
One or more of RI, WI, RSTI and EI is set to ’1’,
or 0065h, 0023h, 0071h, 002A and 002C commands are completed
0→ 1
Pending
clears to ’0’
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
1→ 0
off
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
Status
Default State
Conditions
Cold
Warm/hot
Valid
State
Interrupt
Function
1
0
0
off
sets itself to ’1’
At the completion of an Load Operation
(0000h, 0013h, Load Data into Buffer,
or boot is done)
0→ 1
Pending
clears to ’0’
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
1→ 0
off
Write Interrupt (WI)
This is the Write interrupt bit.
WI Interrupt [6]
Default State
Status
Conditions
sets itself to ’1’
At the completion of an Program Operation
(0080h, 001Ah, 001Bh)
clears to ’0’
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
47
Cold
Warm/hot
Valid
State
interrupt
Function
0
0
0
off
0→ 1
Pending
1→ 0
off
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Erase Interrupt (EI)
This is the Erase interrupt bit.
EI Interrupt [5]
Default State
Status
Conditions
sets itself to ’1’
At the completion of an Erase Operation
(0094h, 0095h, 0030h)
clears to ’0’
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
Cold
Warm/hot
Valid
State
Interrupt
Function
0
0
0
off
0→ 1
Pending
1→ 0
off
Reset Interrupt (RSTI)
This is the Reset interrupt bit.
RSTI Interrupt [4]
Default State
Status
Conditions
sets itself to ’1’
At the completion of an Reset Operation
(00B0h, 00F0h, 00F3h or
warm reset is released)
clears to ’0’
’0’ is written to this bit
Cold
Warm/hot
Valid
State
interrupt
Function
0
1
0
off
0→ 1
Pending
1→ 0
off
2.8.23 Start Block Address Register F24Ch (R/W)
This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock
Block' command, 'Unlock Block' command, or ’Lock-Tight' Command.
F24Ch, default = 0000h
15
14
13
12
11
10
9
8
7
Reserved(00000000)
6
5
4
3
2
1
0
SBA
Device
Number of Block
SBA
256Mb
512
[8:0]
SBA Information[9:0]
Item
Definition
Description
SBA
Start Block Address
Precedes Lock Block, Unlock Block, or Lock-Tight commands
48
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.24 End Block Address Register F24Dh
This register is reserved for future use.
2.8.25 NAND Flash Write Protection Status Register F24Eh (R)
This Read register shows the Write Protection Status of the NAND Flash memory array.
To read the write protection status, FBA has to be set before reading the register.
F24Eh, default = 0002h
15
14
13
12
11
10
9
8
7
6
5
4
3
Reserved(0000000000000)
2
1
0
US
LS
LTS
Write Protection Status Information[2:0]
Item
Bit
Definition
Description
US
2
Unlocked Status
1 = current NAND Flash block is unlocked
LS
1
Locked Status
1 = current NAND Flash block is locked
LTS
0
Locked-Tight Status
1 = current NAND Flash block is locked-tight
2.8.26 ECC Status Register FF00h (R)
This Read register shows the Error Correction Status. The OneNAND can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or
more error detection and correction is not supported.
ECC can be performed on the NAND Flash main and spare memory areas. The ECC status register can also show the number of
errors in a sector as a result of an ECC check in during a load operation. ECC status bits are also updated during a boot loading operation.
FF00h, default = 0000h
15
14
13
12
11
10
9
8
7
Reserved(00000000)
6
ERm1
5
4
3
ERs1
2
ERm0
Error Status
ERm, ERs
ECC Status
00
No Error
01
1-bit error(correctable)
10
2 bits error (uncorrectable)
11
Reserved
49
1
0
ERs0
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
ECC Information[7:0]
Item
Definition
Description
ERm0
1st selected sector of
the main BufferRAM
Status of errors in the 1st selected sector of the main BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
ERm1
2nd selected sector of
the main BufferRAM
Status of errors in the 2nd selected sector of the main BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
ERs0
1st selected sector of
the spare BufferRAM
Status of errors in the 1st selected sector of the spare BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
ERs1
2nd selected sector of
the spare BufferRAM
Status of errors in the 2nd selected sector of the spare BufferRAM
as a result of an ECC check during a load operation.
Also updated during a Bootload operation.
2.8.27 ECC Result of 1st Selected Sector, Main Area Data
Register FF01h (R)
This Read register shows the Error Correction result for the 1st selected sector of the main area data. ECCposWord0 is the error
position address in the Main Area data of 256 words. ECCposIO0 is the error position address which selects 1 of 16 DQs.
ECCposWord0 and ECCposIO0 are also updated at boot loading.
FF01h, default = 0000h
15
14
13
12
11
10
9
8
Reserved(0000)
7
6
5
4
3
ECCposWord0
2
1
0
ECCposIO0
2.8.28 ECC Result of 1st Selected Sector, Spare Area Data
Register FF02h (R)
This Read register shows the Error Correction result for the 1st selected sector of the spare area data. ECClogSector0 is the error
position address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO0 is the error position address which selects 1 of 16
DQs. ECClogSector0 and ECCposIO0 are also updated at boot loading.
FF02h, default = 0000h
15
14
13
12
11
10
9
8
7
6
Reserved(0000000000)
5
4
ECClogSector0
50
3
2
1
ECCposIO0
0
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.29 ECC Result of 2nd Selected Sector, Main Area Data
Register FF03h (R)
This Read register shows the Error Correction result for the 2nd selected sector of the main area data. ECCposWord1 is the error
position address in the Main Area data of 256 words. ECCposIO1 is the error position address which selects 1 of 16 DQs.
ECCposWord1 and ECCposIO1 are also updated at boot loading.
FF03h, default = 0000h
15
14
13
12
11
10
9
8
Reserved(0000)
7
6
5
4
3
ECCposWord1
2
1
0
ECCposIO1
2.8.30 ECC Result of 2nd Selected Sector, Spare Area Data
Register FF04h (R)
This Read register shows the Error Correction result for the 2nd selected sector of the spare area data. ECClogSector1 is the error
position address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO1 is the error position address which selects 1 of 16
DQs. ECClogSector1 and ECCposIO1 are also updated at boot loading.
FF04h, default = 0000h
15
14
13
12
11
10
9
8
7
6
Reserved(0000000000)
5
4
ECClogSector1
3
2
ECC Log Sector
ECClogSector0~ECClogSector1 indicates the error position in the 2nd word and LSB of 3rd word in the spare area.
Refer to note 2 in chapter 2.7.2
ECClogSector Information [5:4]
ECClogSector
Error Position
00
2nd word
01
3rd word
10, 11
Reserved
51
1
ECCposIO1
0
OneNAND256(KFG5616x1A-xxB5)
3.0
FLASH MEMORY
DEVICE OPERATION
This section of the datasheet discusses the operation of the OneNAND device. It is followed by AC/DC
Characteristics and Timing Diagrams which may be consulted for further information.
The OneNAND supports a limited command-based interface in addition to a register-based interface for performing operations on the
device.
3.1
Command Based Operation
The command-based interface is active in the boot partition. Commands can only be written with a boot area address. Boot area data
is only returned if no command has been issued prior to the read.
The entire address range, except for the boot area, can be used for the data buffer. All commands are written to the boot partition.
Writes outside the boot partition are treated as normal writes to the buffers or registers.
The command consists of one or more cycles depending on the command. After completion of the command the device starts its execution. Writing incorrect information including address and data to the boot partition or writing an improper command will terminate
the previous command sequence and make the device enter the ready status.
The defined valid command sequences are stated in Command Sequences Table.
Command Sequences
Command Definition
Read Data from Buffer
Write Data to Buffer
Reset OneNAND
Load Data into Buffer3)
Read Identification Data 6)
Cycles
Add
1
Data
Add
1
Data
Add
1
Data
Add
2
Data
Add
2
Data
1st cycle
Data
DP
Data
BP2)
00F0h
BP
BP
00E0h
0000h4)
BP
XXXXh5)
0090h
Data
NOTE:
1) DP(Data Partition) : DataRAM Area
2) BP(Boot Partition) : BootRAM Area [0000h ~ 01FFh, 8000h ~ 800Fh].
3) Load Data into Buffer operation is available within a block(64KB)
4) Load 1KB unit into DataRAM0. Current Start address(FPA) is automatically incremented by 1KB unit after the load.
5) 0000h -> Data is Manufacturer ID
0001h -> Data is Device ID
0002h -> Current Block Write Protection Status
6) WE toggling can terminate ’Read Identification Data’ operation.
52
2nd cycle
DP1)
OneNAND256(KFG5616x1A-xxB5)
3.1.1
FLASH MEMORY
Reading Data From Buffer
The buffer memory can be read by addressing a Read to the desired buffer area.
3.1.2
Writing Data to Buffer
The buffer memory can be written to by addressing a Write to a desired buffer area.
3.1.3
Reset OneNAND Command
The Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device.
3.1.4
Load Data Into Buffer Command
Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially
writing 00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0. This operation refers
to FBA and FPA. FSA, BSA, and BSC are not considered.
At the end of this operation, FPA will be automatically increased by 1. So continuous issue of this command will sequentially load data
in next page to DataRAM0. This page address increment is restricted within a block.
The default value of FBA and FPA is 0. Therefore, initial issue of this command after power on will load the first page of memory,
which is usually boot code.
3.1.5
Read Identification Data Command
The Read Identification Data command consists of two cycles. It gives out the devices identification data according to the given
address. The first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in Identification
Data Description Table.
Identification Data Description
Address
Data Out
0000h
Manufacturer ID : 00ECh
0001h
Device ID : refer to chapter 2.8.3
0002h
Current Block Write Protection Status 1)
Note 1) To read the write protection status, FBA has to be set before issuing this command.
53
OneNAND256(KFG5616x1A-xxB5)
3.2
FLASH MEMORY
Device Bus Operation
The device bus operations are shown in the table below.
Operation
CE
OE
WE
ADQ0~15
RP
CLK
AVD
Standby
H
X
X
High-Z
H
X
X
Warm Reset
X
X
X
High-Z
L
X
X
Asynchronous Write
L
H
L
Add. In /
Data In
H
L
Asynchronous Read
L
L
H
Add. In /
Data Out
H
L
Load Initial Burst Read
L
H
H
Add. In
H
Burst Read
L
L
H
Burst Data
Out
H
Terminate Burst Read
Cycle
H
X
H
High-Z
H
X
X
Terminate Burst Read
Cycle via RP
X
X
X
High-Z
L
X
X
H
H
Add In
H
Terminate Current Burst
Read Cycle and Start
New Burst Read Cycle
Note : L=VIL (Low), H=VIH (High), X=Don’t Care.
54
H
OneNAND256(KFG5616x1A-xxB5)
3.3
FLASH MEMORY
Reset Mode Operation
The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Core Reset. Section 3.3 discusses the operation of
these reset modes.
The Register Reset Table shows the which registers are affected by the various types or Reset operations.
Internal Register Reset Table
Internal Registers
Default Cold Reset
Warm Reset
(RP)
Hot
Hot
NAND Flash
Reset
Reset
Core Reset
(00F3h) (BP-F0)
(00F0h)
F000h
Manufacturer ID Register (R)
00ECh
N/A
N/A
N/A
N/A
F001h
Device ID Register (R): OneNAND
(Note 3)
N/A
N/A
N/A
N/A
F002h
Version ID Register (R): N/A
N/A
N/A
N/A
N/A
N/A
F003h
Data Buffer size Register (R)
0400h
N/A
N/A
N/A
N/A
F004h
Boot Buffer size Register (R)
0200h
N/A
N/A
N/A
N/A
F005h
Amount of Buffers Register (R)
0201h
N/A
N/A
N/A
N/A
F006h
Technology Register (R)
0000h
N/A
N/A
N/A
N/A
F100h
Start Address1 Register (R/W): FBA
0000h
0000h
0000h
0000h
N/A
F101h
Start Address2 Register (R/W): Reserved
0000h
0000h
0000h
0000h
N/A
F102h
Start Address3 Register (R/W): FCBA
0000h
0000h
0000h
0000h
N/A
F103h
Start Address4 Register (R/W): FCPA, FCSA
0000h
0000h
0000h
0000h
N/A
F107h
Start Address8 Register (R/W): FPA, FSA
0000h
0000h
0000h
0000h
N/A
F200h
Start Buffer Register (R/W): BSA, BSC
0000h
0000h
0000h
0000h
N/A
F220h
Command Register (R/W)
0000h
0000h
0000h
0000h
N/A
F221h
System Configuration 1 Register (R/W)
40C0h
40C0h
(Note1)
(Note1)
N/A
F240h
Controller Status Register (R)
0000h
0000h
0000h
0000h
N/A
F241h
Interrupt Status Register (R/W)
-
8080h
8010h
8010h
N/A
F24Ch
Start Block Address (R/W)
0000h
0000h
0000h
N/A
N/A
F24Dh
End Block Address: N/A
N/A
N/A
N/A
N/A
N/A
F24Eh
NAND Flash Write Protection Status (R)
0002h
0002h
0002h
N/A
N/A
FF00h
ECC Status Register (R) (Note2)
0000h
0000h
0000h
0000h
0000h
FF01h
ECC Result of Sector 0 Main area data Register(R)
0000h
0000h
0000h
0000h
0000h
FF02h
ECC Result of Sector 0 Spare area data Register (R)
0000h
0000h
0000h
0000h
0000h
FF03h
ECC Result of Sector 1 Main area data Register(R)
0000h
0000h
0000h
0000h
0000h
FF04h
ECC Result of Sector 1 Spare area data Register (R)
0000h
0000h
0000h
0000h
0000h
NOTE: 1) RDYpol, INTpol, IOBE are reset by Cold reset. The other bits except OTPL are reset by cold/warm/hot reset.
OTPL is updated by cold reset, referring to the specified OTP area.
2) ECC Status Register & ECC Result Registers are reset when any command is issued.
3) Refer to Device ID Register F001h.
55
OneNAND256(KFG5616x1A-xxB5)
3.3.1
FLASH MEMORY
Cold Reset Mode Operation
See Timing Diagram 6.9
At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal.
This triggers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from
the beginning of memory into the BootRAM. This sequence is the Cold Reset of OneNAND.
The POR(Power On Reset) triggering level is typically 1.5V. Boot code copy operation activates 400us after POR.
Therefore, the system power should reach 1.7V within 400us from the POR triggering level for bootcode data to be valid.
For 2.65V and 3.3V device, POR level is typically 1.8V and system power should reach 2.2V within 400us.
It takes approximately 70us to copy 1KB of bootcode. Upon completion of loading into the BootRAM, it is available to be read by the
host. The INT pin is not available until after IOBE = 1 and IOBE bit can be changed by host.
3.3.2
Warm Reset Mode Operation
See Timing Diagrams 6.10
A Warm Reset means that the host resets the device by using the RP pin. When the a RP low is issued, the device logic stops all current operations and executes internal reset operation and resets current NAND Flash core operation synchronized with the
falling edge of RP.
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status.
The BufferRAM data is kept unchanged after Warm/Hot reset operations.
The device guarantees the logic reset operation in case RP pulse is longer than tRP min. (200ns).
The device may reset if tRP < tRP min(200ns), but this is not guaranteed.
Warm reset will abort the current NAND Flash core operation. During a warm reset, the content of memory cells being altered is no
longer valid as the data will be partially programmed or erased.
Warm reset has no effect on contents of BootRAM and DataRAM.
3.3.3
Hot Reset Mode Operation
See Timing Diagram 6.11
A Hot Reset means that the host resets the device by Reset command. The reset command can be either Command based or
Register Based. Upon receiving the Reset command, the device logic stops all current operation and executes an internal reset
operation and resets the current NAND Flash core operation.
During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status. The
BufferRAM data is kept unchanged after Warm/Hot reset operations.
Hot reset will abort the current NAND Flash core operation. During a Hot reset, the content of memory cells being altered is no longer
valid as the data will be partially programmed or erased.
Hot reset has no effect on contents of BootRAM and DataRAM.
3.3.4
NAND Flash Core Reset Mode Operation
See Timing Diagram 6.12
The Host can reset the NAND Flash Core operation by issuing a NAND Flash Core reset command. NAND Flash core reset will
abort the current NAND Flash core operation. During a NAND Flash core reset, the content of memory cells being altered is no longer
valid as the data will be partially programmed or erased.
Hot reset has no effect on contents of BootRAM and DataRAM, as well as register values.
56
OneNAND256(KFG5616x1A-xxB5)
3.4
FLASH MEMORY
Write Protection Operation
The OneNAND can be write-protected to prevent re-programming or erasure of data.
The areas of write-protection are the BootRAM, and the NAND Flash Array.
3.4.1
BootRAM Write Protection Operation
At system power-up, voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal
which triggers bootcode loading. And the designated size data(1KB) is copied from the first page of the first block in the NAND flash
array to the BootRAM.
After the bootcode loading is completed, the BootRAM is always locked to protect the boot code from the accidental write.
3.4.2
NAND Flash Array Write Protection Operation
The device has both hardware and software write protection of the NAND Flash array.
Hardware Write Protection Operation
The hardware write protection operation is implemented by executing a Cold or Warm Reset. On power up, the NAND Flash Array is
in its default, locked state. The entire NAND Flash array goes to a locked state after a Cold or Warm Reset.
Software Write Protection Operation
The software write protection operation is implemented by writing a Lock command (002Ah) or a Lock-tight command (002Ch) to
command register (F220h).
Lock (002Ah) and Lock-tight (002Ch) commands write protects the block defined in the Start Block Address Register F24Ch.
3.4.3
NAND Array Write Protection States
There are three lock states in the NAND Array: unlocked, locked, and locked-tight.
OneNAND supports lock/unlock/lock-tight by one block, so each block should be locked/unlocked/locked-tight individually.
Write Protection Status
The current block Write Protection status can be read in NAND Flash Write Protection Status Register(F24Eh). There are three bits US, LS, LTS -, which are not cleared by hot reset. These Write Protection status registers are updated when FBA is set, and when
Write Protection command is entered.
The followings summarize locking status.
example)
In default, [2:0] values are 010.
-> If host executes unlock block operation, then [2:0] values turn to 100.
-> If host executes lock-tight block operation, then [2:0] values turn to 001.
57
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
3.4.3.1 Unlocked NAND Array Write Protection State
An Unlocked block can be programmed or erased. The status of an unlocked block can be changed to locked or locked-tight using
the appropriate software command. (locked-tight state can be achieved via lock-tight command which follows lock command)
Only one block can be released from lock state to unlock state with Unlock command and addresses. The unlocked block can be
changed with new lock command. Therefore, each block has its own lock/unlock/lock-tight state.
Unlocked
Unlock Command Sequence:
Start block address+Unlock block command (0023h)
3.4.3.2 Locked NAND Array Write Protection State
A Locked block cannot be programmed or erased. All blocks default to a locked state following a Cold or Warm Reset. Unlocked
blocks can be changed to locked using the Lock block command. The status of a locked block can be changed to unlocked or
locked-tight using the appropriate software command.
Locked
Lock Command Sequence:
Start block address+Lock block command (002Ah)
58
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
3.4.3.3 Locked-tight NAND Array Write Protection State
A block that is in a locked-tight state can only be changed to lock state after a Cold or Warm Reset. Unlock and Lock command
sequences will not affect its state. This is an added level of write protection security.
A block must first be set to a locked state before it can be changed to locked-tight using the Lock-tight command. locked-tight blocks
will revert to a locked state following a Cold or Warm Reset.
Locked-tight
Lock-Tight Command Sequence:
Start block address+Lock-tight block command (002Ch)
3.4.4
NAND Flash Array Write Protection State Diagram
Lock
RP pin: High
&
Start block address
Lock block Command
or
Cold reset or
Warm reset
unlock
RP pin: High
&
Start block address
+Unlock block Command
Lock
Power On
Lock
RP pin: High
&
Start block address
+Lock-tight block Command
Cold reset or
Warm reset
Lock
Lock-tight
Lock
59
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Data Protection Operation Flow Diagram
Start
Write ’SBA’ of Flash
Add: F24Ch DQ=SBA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’lock/unlock/lock-tight’
Command
Add: F220h
DQ=002Ah/0023h/002Ch
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Lock/Unlock/Lock-Tight
completed
Note) Samsung strongly recommend to follow the above flow chart
60
OneNAND256(KFG5616x1A-xxB5)
3.5
FLASH MEMORY
Data Protection During Power Down Operation
See Timing Diagram 6.13
The device is designed to offer protection from any involuntary program/erase during power-transitions.
An internal voltage detector disables all functions whenever Vcc is below POR level, about 1.3V. It is recommended that the RP pin,
which provides hardware protection, should be kept at VIL before power-down.
3.6
Load Operation
The Load operation is initiated by setting up the start address from which the data is to be loaded. The Load command is issued in
order to initiate the load.
During a Load operation, the device:
-Transfers the data from NAND Flash array into the BufferRAM
-ECC is checked and any detected and corrected error is reported in the status response as well as
any unrecoverable error.
Once the BufferRAM has been filled, an interrupt is issued to the host so that the contents of the BufferRAM can be read. The read
from the BufferRAM can be an asynchronous read mode or synchronous read mode. The status information related to load operation
can be checked by the host if required.
The device has a dual data buffer memory architecture (DataRAM0, DataRAM1), each 1KB in size. Each DataRAM buffer has 2
Sectors. The device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to
the other data buffer. Refer to the information for more details in section 3.12.1, "Read-While-Load Operation".
Load Operation Flow Chart Diagram
Start
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Wait for INT register
low to high transition
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F241h DQ[15]=INT
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Read Controller
Status Register
Add: F240h DQ[10]=Error
Write 0 to interrupt register
Add: F241h DQ=0000h
DQ[10]=0?
YES
Host reads data from
DataRAM
Read completed
61
NO
Map Out
OneNAND256(KFG5616x1A-xxB5)
3.7
FLASH MEMORY
Read Operation
See Timing Diagrams 6.1, 6.2, 6.3 and 6.4
The device has two read modes; Asynchronous Read and Synchronous Burst Read.
The initial state machine automatically sets the device into the Asynchronous Read Mode (RM=0) to prevent the
spurious altering of memory content upon device power up or after a Hardware reset. No commands are required
to retrieve data in Asynchronous Read Mode.
The Synchronous Read Mode is enabled by setting RM bit of System Configuration1 Register (F221h) to
Synchronous Read Mode (RM=1). See Section 2.8.19 for more information about System Configuration1 Register.
3.7.1
Asynchronous Read Mode Operation (RM=0)
See Timing Diagrams 6.3 and 6.4
In an Asynchronous Read Mode, data is output with respect to a logic input, AVD.
Output data will appear on DQ15-DQ0 in when a valid address is asserted on A15-A0 while driving AVD and CE to VIL. / WE is held
at VIH. The function of the AVD signal is to latch the valid address.
Address access time from AVD low (tAA) is equal to the delay from valid addresses to valid output data.
The Chip Enable access time (tCE) is equal to the delay from the falling edge of CE to valid data at the outputs.
The Output Enable access time (tOE) is the delay from the falling edge of OE to valid data at the output.
3.7.2
Synchronous Read Mode Operation (RM=1)
See Timing Diagrams 6.1 and 6.2
In a Synchronous Read Mode, data is output with respect to a clock input.
The device is capable of a continuous linear burst operation and a fixed-length linear burst operation of a preset length. Burst
address sequences for continuous and fixed-length burst operations are shown in the table below.
Burst Address Sequences
Wrap
around
Burst Address Sequence(Decimal)
Start
Addr.
Continuous Burst
4-word Burst
8-word Burst
16-word Burst
32-word Burst
0
0-1-2-3-4-5-6...
0-1-2-3-0...
0-1-2-3-4-5-6-7-0...
0-1-2-3-4-....-13-14-15-0...
0-1-2-3-4-....-29-30-31-0...
1
1-2-3-4-5-6-7...
1-2-3-0-1...
1-2-3-4-5-6-7-0-1...
1-2-3-4-5-....-14-15-0-1...
1-2-3-4-5-....-30-31-0-1...
2
2-3-4-5-6-7-8...
2-3-0-1-2...
2-3-4-5-6-7-0-1-2...
2-3-4-5-6-....-15-0-1-2...
2-3-4-5-6-....-31-0-1-2...
.
.
.
.
.
.
.
.
.
.
.
.
In the burst mode, the initial word will be output asynchronously, regardless of BRL. While the following words will be determined by
BRL value.
The latency is determined by the host based on the BRL bit setting in the System Configuration 1 Register. The default BRL is 4
latency cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3. BRL can be set up to 7 latency cycles.
62
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
3.7.2.1 Continuous Linear Burst Read Operation
See Timing Diagram 6.2
First Clock Cycle
The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the
system by pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be
read out.
Subsequent Clock Cycles
Subsequent words are output (Burst Access Time from Valid Clock to Output) tBA after the rising edge of each successive clock
cycle, which automatically increments the internal address counter.
Terminating Burst Read
The device will continue to output sequential burst data until the system asserts CE high, or RP low, wrapping around until it reaches
the designated address (see Section 2.7.3 for address map information). Alternately, a Cold/Warm/Hot Reset, asserting CE high, or a
WE low pulse will terminate the burst read operation.
Synchronous Read Boundary
Division
Add.map(word order)
BootRAM Main(0.5Kw)
0000h~01FFh
BufferRAM0 Main(0.5Kw)
0200h~03FFh
BufferRAM1 Main(0.5Kw)
0400h~05FFh
Reserved Main
0600h~7FFFh
BootRAM Spare(16w)
8000h~800Fh
BufferRAM0 Spare(16w)
8010h~801Fh
BufferRAM1 Spare(16w)
8020h~802Fh
Reserved Spare
8030h~8FFFh
Reserved Register
9000h~EFFFh
Register(4Kw)
F000h~FFFFh
Not Support
Not Support
Not Support
Not Support
Not Support
* Reserved area is not available on Synchronous read
3.7.2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation
See Timing Diagram 6.1
An alternate Burst Read Mode enables a fixed number of words to be read from consecutive address.
The device supports a burst read from consecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. When the last
word in the burst has been reached, assert CE and OE high to terminate the operation.
In this mode, the start address for the burst read can be any address of the address map with one exception. The device does not
support a 32-word linear burst read on the spare area of the BufferRAM.
63
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
3.7.2.3 Programmable Burst Read Latency Operation
See Timing Diagrams 6.1 and 6.2
Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks.
The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with
the (n+1)th rising edge.
The number of total initial access cycles is programmable from three to seven cycles. After the number of programmed burst clock
cycles is reached, the rising edge of the next clock cycle triggers the next burst data.
Four Clock Burst Read Latency (default condition)
Rising edge of the clock cycle following last read latency
triggers next burst data
≈
CE
CLK
0
1
2
3
≈
-1
4
≈
AVD
tBA
Valid
Address
A0:
A15
D6
D7
D0
D1
D2
D3
≈
DQ0:
DQ15
D7
D0
tIAA
Hi-Z
3.7.3
≈
RDY
≈
tRDYS
OE
tRDYA
Hi-Z
Handshaking Operation
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine
when the initial word of burst data is ready to be read.
To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see
Section 2.8.19, "System Configuration1 Register").
The rising edge of RDY which is derived at the same cycle of data fetch clock indicates the initial word of valid burst data.
64
OneNAND256(KFG5616x1A-xxB5)
3.7.4
FLASH MEMORY
Output Disable Mode Operation
When the CE or OE input is at VIH, output from the device is disabled.
The outputs are placed in the high impedance state.
3.8
Program Operation
The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array.
The device has two 1KB data buffers, each 1 Page (1KB + 32B) in size. Each page has 2 sectors of 512B each main area and 16B
spare area. The device can be programmed in units of 1~2 sectors.
The architecture of the DataRAMs permits a simultaneous data-write operation from the Host to one of data buffers and a program
operation from the other data buffer to the NAND Flash Array memory. Refer to Section 3.12.2, "Write While Program Operation", for
more information.
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited.
Page 63
(64)
Page 63
:
Page 31
:
(32)
Page 31
:
Page 2
Page 1
Page 0
(1)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
Data register
(3)
(32)
(2)
Data register
From the LSB page to MSB page
DATA IN: Data (1)
(64)
Ex.) Random page program (Prohibition)
Data (64)
DATA IN: Data (1)
65
Data (64)
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Program Operation Flow Diagram
Write 0 to interrupt register
Add: F241h DQ=0000h
Start
Write Data into DataRAM2)
ADD: DP DQ=Data-in
Write ’Program’ Command
Add: F220h
DQ=0080h or 001Ah
Data Input
Completed?
YES
NO
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Read Controller
Status Register
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F240h DQ[10]=Error
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
DQ[10]=0?
YES
Program completed
*
NO
Program Error
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
Note 1) This must happen before data input
2) Data input could be done anywhere between "Start" and "Write Program Command".
During the execution of the Internal Program Routine, the host is not required to provide any further controls or
timings. Furthermore, all commands, except a Reset command, will be ignored. A reset during a program operation will cause data
corruption at the corresponding location.
If a program error is detected at the completion of the Internal Program Routine, map out the block, including the page in error, and
copy the target data to another block. An error is signaled if DQ10 = "1" of Controller Status Register(F240h) .
Data input from the Host to the DataRAM can be done at any time during the Internal Program Routine after "Start" but before the
"Write Program Command" is written.
66
OneNAND256(KFG5616x1A-xxB5)
3.9
FLASH MEMORY
Copy-Back Program Operation
The Copy-Back program is configured to quickly rewrite data stored in one page without utilizing memory other than OneNAND.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of block is updated and the rest of the block also need to be copied to the newly assigned
free block.
Data from the source page is saved in one of the on-chip DataRAM buffers and then programmed directly into the destination page.
The DataRAM overwrites the previous data using the Buffer Sector Address (BSA) and Buffer Sector Count (BSC).
The Copy-Back Program Operation does this by performing sequential page-reads without a serial access and executing a
copy-program using the address of the destination page.
Copy-Back Program Operation Flow Chart
Start
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write ’Copy-back Program’
command
Add: F220h DQ=001Bh
Wait for INT register
low to high transition
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Add: F241h DQ[15]=INT
Write ’FCBA’ of Flash
Add: F102h DQ=FCBA
Read Controller
Status Register
Add: F240h DQ[10]=Error
Write ’FCPA, FCSA’ of Flash
Add: F103h DQ=FCPA, FCSA
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC 1)
DQ[10]=0?
YES
Copy back completed
NO
Copy back Error
Write 0 to interrupt register
Add: F241h DQ=0000h
*
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
Note 1) Selected DataRAM by BSA & BSC is used for Copy back operation, so previous data is overwritten.
2) FBA, FPA and FSA should be input prior to FCBA, FCPA and FCSA.
67
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
The Copy-Back steps shown in the flow chart are:
• Data is read from the NAND Array using Flash Block Address (FBA), Flash Page Address (FPA) and
Flash Sector Address (FSA). FBA, FPA, and FSA identify the source address to read data from NAND Flash array.
• The BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA) identifies how many sectors
and the location of the sectors in DataRAM that are used.
• The destination address in the NAND Array is written using the Flash Copy-Back Block Address (FCBA),
Flash Copy-Back Page Address (FCPA), and Flash Copy-Back Sector Address (FCSA).
• The Copy-Back Program command is issued to start programming.
• Upon completion of copy-back programming to the destination page address, the Host checks the status
to see if the operation was successfully completed. If there was an error, map out the block including the
page in error and copy the target data to another block.
68
OneNAND256(KFG5616x1A-xxB5)
3.9.1
FLASH MEMORY
Copy-Back Program Operation with Random Data Input
See Timing Diagram 6.7
The Copy-Back Program Operation with Random Data Input in OneNAND consists of 2 phase, Load data into DataRAM, Modify data
and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the
host, then programmed into the destination page.
As shown in the flow chart, data modification is possible upon completion of load operation. ECC is also available at the end of load
operation. Therefore, using hardware ECC of OneNAND, accumulation of 1 bit error can be avoided.
Copy-Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit, byte, word, or sector of
source page to destination page while it is being copied.
Copy-Back Program Operation with Random Data Input Flow Chart
Start
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
DQ[10]=0?
NO
Map Out
YES
Random Data Input
Add: Random Address in
Selected DataRAM
DQ=Data
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Program’ Command
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Add: F220h
DQ=0080h or 001Ah
Read Controller
Status Register
Wait for INT register
low to high transition
Add: F240h DQ[10]=Error
Add: F241h DQ[15]=INT
Read Controller
Status Register
Add: F240h DQ[10]=Error
DQ[10]=0?
YES
Copy back completed
69
NO
Copy back Error
OneNAND256(KFG5616x1A-xxB5)
3.10
FLASH MEMORY
Erase Operation
There are multiple methods for erasing data in the device including Block Erase and Multi-Block Erase.
3.10.1 Block Erase Operation
See Timing Diagram 6.8
The device can be erased one block at a time. To erase a block is to write all 1's into the desired memory block by executing the Internal Erase Routine. All previous data is lost.
Block Erase Operation Flow Chart
Start
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Erase’ Command
Add: F220h DQ=0094h
Wait for INT register
low to high transition
Add: F241h DQ=[15]=INT
Read Controller
Status Register
Add: F240h DQ[10]=Error
DQ[10]=0?
YES
NO
Erase completed
Erase Error
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
70
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
In order to perform the Internal Erase Routine, the following command sequence is necessary.
• The Host sets the block address of the memory location.
• The Erase Command initiates the Internal Erase Routine. During the execution of the Routine, the host is
not required to provide further controls or timings. During the Internal erase routine, all commands, except
the Reset command and Erase Suspend Command, written to the device will be ignored.
A reset during an erase operation will cause data corruption at the corresponding location.
3.10.2 Multi-Block Erase Operation
See Timing Diagram 6.8
Using Multi-Block Erase, the device can erase up to 64 multiple blocks simultaneously.
Multiple blocks can be erased by issuing a Multi-Block Erase command and writing the block address of the memory location to be
erased. The final Flash Block Address (FBA) and Block Erase command initiate the internal multi block erase routine. During a
Multi-Block Erase, the OnGo bit of the Controller Status Register is set to '1'(busy) from the time first block address to be latched is
written until the actual erase has finished.
During block address latch sequence, issuing of other commands except Block Erase and Multi Block Erase at INT=High will abort
the current operation. So to speak, It will cancel the previously latched addresses of Multi Block Erase Operation.
On the other hand, Other command issue at INT=low will be ignored.
A reset during an erase operation will cause data corruption at the address location being operated on during the reset.
Despite a failed block during Multi-Block Erase operation, the device will continue the erase operation until all other specified blocks
are erased.
Erase Suspend Command issue during Multi Block Erase Address latch sequence is prohibited.
Locked Blocks
If there are locked blocks in the specified range, the Multi-Block Erase operation works as the follows.
Case 1: All specified blocks except BA(2) will be erased.
[BA(1)+0095h] + [BA((2), locked)+0095h] + ... + [BA(N-1)+0095h] + [BA(N)+0094h]
Case 2: Multi-Block Erase Operation is suspended and fails to start if the last Block Erase command is put together with the locked
block address until right command and address input are issued.
[BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA((N), locked)+0094h]
Case 3: All specified blocks except BA(N) are erased.
[BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA((N), locked)+0094h] + [BA(N+1)+0094h]
71
OneNAND256(KFG5616x1A-xxB5)
3.10.3
FLASH MEMORY
Multi-Block Erase Verify Read Operation
After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase Verify Command combined
with address of each block.
If a failed address is identified, it must be managed in firmware.
Multi Block Erase/ Multi Block Erase Verify Read Flow Chart
Read Controller
Status Register
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Start
Add: F240h DQ[10]=Error
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
DQ[10]=0?
Write 0 to interrupt register
Add: F241h DQ=0000h
NO
Write ’Block Erase
Command’
YES
Add: F220h DQ=0094h
Erase completed
Write ’Multi Block Erase’
Command
Wait for INT register
low to high transition
Add: F220h DQ=0095h
Erase Error
Add: F241h DQ=[15]=INT
NO
Wait for INT register
low to high transition
Write ’FBA’ of Flash
Add: F100h DQ=FBA
Add: F241h DQ=[15]=INT
Final Multi Block
Erase?
NO
Final Multi Block
Erase Address?
YES
Multi Block Erase completed
Write 0 to interrupt register
Add: F241h DQ=0000h
Multi Block Erase Verify Read
YES
Write ’Multi Block Erase
Verify Read Command’
Add: F220h DQ=0071h
Wait for INT register
low to high transition
Add: F241h DQ=[15]=INT
72
OneNAND256(KFG5616x1A-xxB5)
3.10.4
FLASH MEMORY
Erase Suspend / Erase Resume Operation
The Erase Suspend/Erase Resume Commands interrupt and restart a Block Erase or Multi-Block Erase operation so that user may
perform another urgent operation on the block that is not being designated by Erase/Multi-Block Erase Operation.
Erase Suspend During a Block Erase Operation
When Erase Suspend command is written during a Block Erase or Multi-Block Erase operation, the device requires a maximum of
500us to suspend erase operation. Erase Suspend Command issue during Block Address latch sequence is prohibited.
After the erase operation has been suspended, the device is ready for the next operation including a load, program, copy-back
program, Lock, Unlock, Lock-tight, Hot Reset, NAND Flash Core Reset, Command Based Reset, Multi-Block Erase Read Verify, or
OTP Access.
The subsequent operation can be to any block that was NOT being erased.
A special case arises pertaining Erase Suspend to the OTP. A Reset command is used to exit from the OTP Access mode. If the
Reset-triggered exit from the OTP Access Mode happens during an Erase Suspend Operation, the erase routine could fail. Therefore
to exit from the OTP Access Mode without suspending the erase operation stop, a 'NAND Flash Core Reset' command should be
issued.
For the duration of the Erase Suspend period the following commands are not accepted:
• Block Erase/Multi-Block Erase/Erase Suspend
Erase Suspend and Erase Resume Operation Flow Chart
Start
Write 0 to interrupt register
Add: F241h DQ=0000h
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Erase Resume
Command’
Add: F220h DQ=0030h
Write ’Erase Suspend
Command’1)
Add: F220h DQ=00B0h
Wait for INT register
low to high transition for 500us
Add: F241h DQ=[15]=INT
Another Operation *
Note
Wait for INT register
low to high transition
Add: F241h DQ=[15]=INT
Check Controller Status Register
in case of Block Erase
Do Multi Block Erase Verify Read
in case of Multi Block Erase
* Another Operation ; Load, Program
Copy-back Program, OTP Access2),
Hot Reset, Flash Reset, CMD Reset,
Multi Block Erase Verify, Lock,
Lock-tight, Unlock
1) Erase Suspend command input is prohibited during Multi Block Erase address latch period.
2) If OTP access mode exit happens with Reset operation during Erase Suspend mode,
Reset operation could hurt the erase operation. So if a user wants to exit from OTP access mode
without the erase operation stop, Reset NAND Flash Core command should be used.
73
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Erase Resume
When the Erase Resume command is executed, the Block Erase will restart. The Erase Resume operation does not actually resume
the erase, but starts it again from the beginning.
When an Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state.
For Multi Block Erase, Erase suspend/Resume can be operated after final Erase command (0094h) is issued. Therefore, Erase
Resume operation does not actually resume from the erased block. But resumes the multi block erase from the begging.
3.11
OTP Operation
On Block of the NAND Flash Array memory is reserved as a One-Time Programmable Block memory area.
The OTP block can be read, programmed and locked using the same operations as any other NAND Flash Array memory block.
OTP block cannot be erased.
OTP block is fully-guaranteed to be a valid block.
Entering the OTP Block
The OTP block is separately accessible from the rest of the NAND Flash Array by using the OTP Access command instead of the
Flash Block Address (FBA).
Exiting the OTP Block
To exit the OTP Access Mode, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed.
Exiting the OTP Block during an Erase Operation
If the Reset-triggered exit from the OTP Access Mode happens during an Erase Suspend Operation, the erase
routine could fail. Therefore to exit from the OTP Access Mode without suspending the erase operation stop, a
'NAND Flash Core Reset' command should be issued.
The OTP Block Page Assignments
OTP area is one block size ((64K+2K)B, 64 Pages) and is divided into two areas. The 20-page User Area is available as an OTP storage area. The 44-page Manufacturer Area is programmed by the manufacturer prior to shipping the device to the user.
OTP Block Page Allocation Information
Area
Page
Use
User
0 ~ 19 (20 pages)
Designated as user area
Manufacturer
20 ~ 63 (44 pages)
Used by the device manufacturer
74
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
OTP Area Structure
Page:1KB+32B
Sector(main area):512B
One Block:
64pages
64KB+2KB
Sector(spare area):16B
Manufacturer Area :
44pages
page 20~ page 63
User Area :
20pages
page 0~ page 19
75
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
3.11.1 OTP Load Operation
An OTP Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer,
thus making the OTP contents available to the Host.
The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of
a Flash Block Address (FBA) command.
After being accessed with the OTP Access Command, the contents of OTP memory area are loaded using the same operations
as a normal load operation to the NAND Flash Array memory (see section 3.6 for more information).
To exit the OTP access mode following an OTP Load Operation, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed.
OTP Read Operation Flow Chart
Start
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Write ’FPA, FSA’ of Flash1)
Add: F107h DQ=FPA, FSA
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Host reads data from
DataRAM
OTP Reading completed
Do Cold/Warm/Hot
/NAND Flash Core Reset
OTP Exit
Note 1) FBA(NAND Flash Block Address) could be omitted or could be any address.
76
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
3.11.2 OTP Program Operation
An OTP Program Operation accesses the OTP area and programs content from the DataRAM on-chip buffer to the designated
page(s) of the OTP.
A memory location in the OTP area can be programmed only one time (no erase operation permitted).
The OTP area is programmed using the same sequence as normal program operation after being accessed by the command (see
section 3.8 for more information).
Programming the OTP Area
• Issue the OTP Access Command
• Write data into the DataRAM (data can be input at anytime between the "Start" and "Write Program" commands)
• Issue a Flash Block Address (FBA) which is unlocked area address of NAND Flash Array address map.
• Issue a Write Program command to program the data from the DataRAM into the OTP
• When the OTP programming is complete, do a Cold-, Warm-, Hot-, NAND Flash Core Reset to exit the OTP Access mode.
77
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
OTP Program Operation Flow Chart
Write ’FBA’ of Flash
Add: F100h DQ=FBA3)
Start
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write 0 to interrupt register
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F241h DQ[15]=INT
Add: F220h
DQ=0080h or 001Ah
Automatically
checked
Write Data into DataRAM2)
Add: DP DQ=Data-in
OTPL=0?
NO
Automatically
updated
YES
Data Input
Completed?
NO
Add: F241h DQ[15]=INT
Update Controller
Status Register
Add: F240h
DQ[14]=1(Lock), DQ[10]=1(Error)
Read Controller
Status Register
Wait for INT register
low to high transition
Add: F240h DQ[10]=0(Pass)
Add: F241h DQ[15]=INT
OTP Programming completed
Read Controller
Status Register
Wait for INT register
low to high transition
Add: F240h DQ[10]=1(Error)
Do Cold/Warm/Hot
/NAND Flash Core reset
Do Cold/Warm/Hot
/NAND Flash Core reset
OTP Exit
OTP Exit
Note 1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NAND Flash Array address map.
78
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
3.11.3 OTP Lock Operation
Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to
prevent any changes from being made.
Unlike the main area of the NAND Flash Array memory, once the OTP block is locked, it cannot be unlocked.
Locking the OTP
Programming to the OTP area can be prevented by locking the OTP area. Locking the OTP area is accomplished by
programming XXXCh to 8th word of sector0 of page0 of the spare0 memory area.
At device power-up, this word location is checked and if XXXCh is found, the OTPL bit of the Controller Status Register is set to "1",
indicating the OTP is locked. When the Program Operation finds that the status of the OTP is locked, the device updates the Error Bit
of the Controller Status Register as "1" (fail).
OTP Lock Operation Steps
•
•
•
•
•
•
•
Issue the OTP Access Command
Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and "Write Program" commands)
Write 'XXXCH' data into the 8th word of sector0 of page0 of the spare0 memory area of the DataRAM.
Issue a Flash Block Address (FBA) to unlocked address in the NAND Flash Array address map.
Issue a Program command to program the data from the DataRAM into the OTP
When the OTP lock is complete, do a Cold Reset to exit the OTP Access mode and update OTP lock bit[6].
OTP lock bit[6] of the Controller Status Register will be set to "1" and the OTP will be locked.
79
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
OTP Lock Operation Flow Chart
Start
Write ’FBA’ of Flash1)
Add: F100h DQ=FBA
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’OTP Access’ Command
Add: F220h DQ=0065h
Write ’FBA’ of Flash
Add: F100h DQ=FBA3)
Write ’FPA, FSA’ of Flash
Add: F107h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=0001h
Write 0 to interrupt register
Add: F241h DQ=0000h
Wait for INT register
low to high transition
Write Program command
Add: F241h DQ[15]=INT
Add: F220h
DQ=0080h or 001Ah
Write Data into DataRAM2)
Add: 8th Word
in spare0/sector0/page0
DQ=XXXCh
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Do Cold reset
Automatically
updated
Update Controller
Status Register
Add: F240h
DQ[6]=1(OTPL)
OTP lock completed
Note 1) FBA(NAND Flash Block Address) could be omitted or any address.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) FBA should point the unlocked area address among NAND Flash Array address map.
80
OneNAND256(KFG5616x1A-xxB5)
3.12
FLASH MEMORY
Dual Operations
The device has independent dual data buffers on-chip (except during the Boot Load period) that enables higher
performance read and program operation.
3.12.1 Read-While-Load Operation
This operation accelerates the read performance of the device by enabling data to be read out by the host from one DataRAM buffer
while the other DataRAM buffer is being loaded with data from the NAND Flash Array memory.
1) Data Load
Page A
3) Data Load
Page B
2) Data Load
Data
Buffer0
Data
Buffer1
2) Data Read
3) Data Read
The dual data buffer architecture provides the capability of executing a data-read operation from one of DataRAM buffers during a
simultaneous data-load operation from Flash to the other buffer. Simultaneous load and read operation to same data buffer is
prohibited. See sections 3.6 and 3.7 for more information on Load and Read Operations.
If host sets FBA, FSA, or FPA while loading into designated page, it will fail the internal load operation. Address registers should not
be updated until internal operation is completed.
3.12.2 Write-While-Program Operation
This operation accelerates the programming performance of the device by enabling data to be written by the host into one DataRAM
buffer while the NAND Flash Array memory is being programmed with data from the other DataRAM buffer.
Page A
Page B
2) Program
3) Program
1) Data Write
Data
Buffer0
Data
Buffer1
3) Data Write
2) Data Write
The dual data buffer architecture provides the capability of executing a data-write operation to one of DataRAM buffers during simultaneous data-program operation to Flash from the other buffer. Simultaneous program and write operation to same data buffer is
prohibited. See sections 3.8 for more information on Program Operation.
If host sets FBA, FSA, or FPA while programming into designated page, it will fail the internal program operation. Address registers
should not be updated until internal operation is completed.
81
INT
OE
WE
0~15
DQ
0~15
ADD
Flash
_add
Page A
Add_
reg
0000h
Int_
reg
LD_
CMD
CMD_
reg
1)
Data Load
_DB0
1)
Data Load
_DB0
Read
Status
CS_
reg
DB1
_add
Add_
reg
0000h
Int_
reg
LD_
CMD
CMD_
reg
DB0_radd*
Data Load
2)
_DB1
Data Read
_DB0 *
Data Load
2)
_DB1
* DBS should be set before accessing DataRAM for DDP
Flash
_add
Page B
Add_
reg
Int_reg : Interrupt Register Address
Add_reg : Address Register Address
Flash_add : Flash Address to be loaded
DBn_add : DataRAM Address to be loaded
CMD_reg : Command Register Address
LD_CMD : Load Command
Data Load_DBn : Load Data from NAND Flash Array to DataRAMn
CS_reg : Controller Status Register Address
Data Read_DBn : Read Data from DBn
DBn_radd : DataRAM Address to be read
DB0
_add
Add_
reg
Read While Load Diagram
OneNAND256(KFG5616x1A-xxB5)
82
FLASH MEMORY
INT
OE
WE
0~15
DQ
0~15
ADD
Data Write
_DB0 *
DB0_wadd*
Page A
Flash
_add
1)
Add_
reg
0000h
Int_
reg
PD_
CMD
CMD_
reg
Data PGM
_PageA
Data Write
_DB1 *
DB1_wadd*
Data PGM
_PageA
Add_reg : Address Register Address
DBn_add : DataRAM Address to be programmed
DBn_wadd : DataRAM Address to be written
Data Write_DBn : Write Data to DataRAMn
Flash_add : Flash Address to be programmed
Int_reg : Interrupt Register Address
CMD_reg : Command Register Address
PD_CMD : Program Command
Data PGM_PageA : Program Data from DataRAM to PageA
CS_reg : Controller Status Register Address
DB0
_add
Add_
reg
Write While Program Diagram
2)
Flash
_add
Add_
reg
DB1
_add
Add_
reg
0000h
Int_
reg
PD_
CMD
CMD_
reg
Data PGM
_PageB
Data PGM
_PageB
Data Write
_DB0 *
DB0_wadd*
* DBS should be set before accessing DataRAM for DDP
Read
Status
CS_
reg
Page B
OneNAND256(KFG5616x1A-xxB5)
83
FLASH MEMORY
OneNAND256(KFG5616x1A-xxB5)
3.13
FLASH MEMORY
ECC Operation
The OneNAND device has on-chip ECC with the capability of detecting 2 bit errors and correcting 1-bit errors in the NAND Flash
Array memory main and spare areas.
As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation, the device initiates a background operation which generates an Error Correction Code (ECC) of 24bits for each sector main area data and 10bits
for 2nd and 3rd word data of each sector spare area.
During a Load operation from the NAND Flash Array memory Page, the on-chip ECC engine generates a new ECC. The 'Load ECC
result' is compared to the originally 'Program ECC' thus detecting the number and position of errors. Single-bit error is corrected.
ECC is updated by the device automatically. After a Load Operation, the Host can determine whether there was error by reading the
'ECC Status Register' (refer to section 2.8.26).
Error types are divided into 'no error', '1bit correctable error', and '2bit error uncorrectable error'.
OneNAND supports 2bit EDC even though 2bit error seldom or never occurs. Hence, it is not recommeded for Host to read 'ECC Status Register' for checking ECC error because the built-in Error Correction Logic of OneNAND automatically corrects ECC error.
When the device reads the NAND Flash Array memory main and spare area data with an ECC operation, the device doesn't place
the newly generated ECC for main and spare area into the buffer. Instead it places the ECC which was generated and written during
the program operation into the buffer.
An ECC operation is also done during the Boot Loading operation.
3.13.1 ECC Bypass Operation
In an ECC bypass operation, the device does not generate ECC as a background operation. The result does not indicate error position (refer to the ECC Result Table).
In a Program Operation the ECC code to NAND Flash Array memory spare area is not updated.
During a Load operation, the on-chip ECC engine does not generate a new ECC internally. Also the ECC Status & Result to Registers are invalid. The error is not corrected and detected by itself, so that ECC bypass operation is not recommended for host.
ECC bypass operation is set by the 9bit of System Configuration 1 Register (see section 2.8.19)
ECC Code and ECC Result by ECC Operation
Program operation
Operation
Load operation
ECC Code Update to NAND ECC Code at BufferRAM Spare
Flash Array Spare Area
Area
ECC Status & Result Update
to Registers
1bit Error
ECC operation
Update
Pre-written ECC code(1) loaded
Update
Correct
ECC bypass
Not update
Pre-written code(1) loaded
Invalid
Not correct
NOTE:
1. Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation.
84
OneNAND256(KFG5616x1A-xxB5)
3.14
FLASH MEMORY
Invalid Block Operation
Invalid blocks are defined as blocks in the device's NAND Flash Array memory that contain one or more invalid bits whose reliability
is not guaranteed by Samsung.
The information regarding the invalid block(s) is called the Invalid Block Information. Devices with invalid block(s) have the same
quality level as devices with all valid blocks and have the same AC and DC characteristics.
An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source
line by a select transistor.
The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block
address, is always fully guaranteed to be a valid block.
Due to invalid marking, during load operation for identifying invalid block, a load error may occur.
3.14.1 Invalid Block Identification Table Operation
A system must be able to recognize invalid block(s) based on the original invalid block information and create an invalid block table.
Invalid blocks are identified by erasing all address locations in the NAND Flash Array memory except locations where the invalid
block(s) information is written prior to shipping.
An invalid block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has non-FFFFh data at the 1st word of sector0.
Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased.
Any intentional erase of the original invalid block information is prohibited.
The following suggested flow chart can be used to create an Invalid Block Table.
85
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Invalid Block Table Creation Flow Chart
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
*
Check "FFFFh" at the 1st word of sector 0 of
spare area in 1st and 2nd page
Check
"FFFFh" ?
Yes
No
Last Block ?
Yes
End
3.14.2 Invalid Block Replacement Operation
Within its life time, additional invalid blocks may develop with NAND Flash Array memory. Refer to the device's qualification report for
the actual data.
The following possible failure modes should be considered to implement a highly reliable system.
In the case of a status read failure after erase or program, a block replacement should be done. Because program status failure
during a page program does not affect the data of the other pages in the same block, a block replacement can be executed with a
page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced
block.
Block Failure Modes and Countermeasures
Failure Mode
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Single Bit Failure in Load Operation
Error Correction by ECC mode of the device
86
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Referring to the diagram for further illustration, when an error happens in the nth page of block 'A' during program operation, copy
the data in the 1st ~ (n-1)th page to the same location of block 'B' via data buffer0.
Then copy the nth page data of block 'A' in the data buffer1 to the nth page of block 'B' or any free block. Do not further erase or
program block 'A' but instead complete the operation by creating an 'Invalid Block Table' or other appropriate scheme.
Block Replacement Operation Sequence
1st
∼
(n-1)th
nth
{
Block A
1
an error occurs.
Data Buffer0 of the device
(page)
1
1st
∼
(n-1)th
nth
{
Data Buffer1 of the device
(assuming the nth page data is maintained)
Block B
2
(page)
87
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
4.0
DC CHARACTERISTICS
4.1
Absolute Maximum Ratings
Parameter
Vcc
Voltage on any pin relative to VSS
All Pins
Symbol
Rating
Vcc (for 1.8V)
-0.5 to + 2.45
Vcc (for 2.65V/3.3V)
-0.5 to + 4.6
VIN (for 1.8V)
-0.5 to + 2.45
VIN (for 2.65V/3.3V)
-0.5 to + 4.6
Extended
Temperature Under Bias
Storage Temperature
Recommended Operating Temperature
°C
-40 to +125
Tstg
-65 to +150
°C
mA
IOS
5
TA (Extended Temp.)
-30 to +85
TA (Industrial Temp.)
-40 to +85
Short Circuit Output Current
V
-30 to +125
Tbias
Industrial
Unit
°C
NOTES:
1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. [email protected] device, [email protected]/
3.3V device). Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
4.2
Operating Conditions
Voltage reference to GND
Parameter
Symbol
VCC-core / Vcc
Supply Voltage
VCC- IO / Vccq
VSS
1.8V Device
2.65V Device
3.3V Device
Unit
Min
Typ.
Max
Min
Typ.
Max
Min
Typ.
Max
1.7
1.8
1.95
2.4
2.65
2.9
2.7
3.3
3.6
V
0
0
0
0
0
0
0
0
0
V
NOTES:
1. The system power should reach 1.7V after POR triggering level(typ. 1.5V) within 400us.
For 2.65V and 3.3V device, the system power should reach 2.2V after POR triggering level(typ. 1.8V) within 400us.
2. Vcc-Core (or Vcc) should reach the operating voltage level prior to or at the same time as Vcc-IO (or Vccq).
88
OneNAND256(KFG5616x1A-xxB5)
4.3
FLASH MEMORY
DC Characteristics
1.8V device
Parameter
Symbol
Test Conditions
Input Leakage Current
ILI
VIN=VSS to VCC, VCC=VCCmax
Output Leakage Current
2.65V device
Max
Min
Typ
Max
3.3V device
Typ
- 1.0
-
+ 1.0 - 1.0
-
+ 1.0 - 1.0
-
+ 1.0 µA
ILO
VOUT=VSS to VCC, VCC=VCCmax,
- 1.0
CE or OE=VIH(Note 1)
-
+ 1.0 - 1.0
-
+ 1.0 - 1.0
-
+ 1.0 µA
Active Asynchronous
Read Current (Note 2)
ICC1
CE=VIL, OE=VIH
-
8
15
Active Burst Read
Current (Note 2)
ICC2
CE=VIL, OE=VIH
54Mhz
-
12
1MHz
-
3
Active Write Current
(Note 2)
ICC3
CE=VIL, OE=VIH
-
Active Load Current
(Note 3)
ICC4
CE=VIL, OE=VIH, WE=VIH
Active Program Current
(Note 3)
ICC5
Active Erase Current
(Note 3)
Multi Block Erase Current (Note 3)
-
14
20
20
-
20
4
-
5
8
15
-
-
30
40
CE=VIL, OE=VIH, WE=VIH
-
25
ICC6
CE=VIL, OE=VIH, WE=VIH
-
ICC7
CE=VIL, OE=VIH, WE=VIH,
64blocks
Min
Typ
Max
Unit
Min
-
14
20
mA
25
-
20
25
mA
7
-
5
7
mA
17
22
-
17
22
mA
-
30
40
-
30
40
mA
30
-
28
35
-
28
35
mA
20
25
-
23
30
-
23
30
mA
-
20
25
-
23
30
-
23
30
mA
Standby Current
ISB
CE= RP=VCC ± 0.2V
-
10
50
-
25
80
-
25
80
µA
Input Low Voltage
VIL
-
-0.5
-
0.4
-0.5
-
0.4
0
-
0.8
V
Input High Voltage
(Note 4)
VIH
-
VCCq0.4
-
-
VCCq
V
Output Low Voltage
VOL
IOL = 100 µA , VCC=VCCmin ,
VCCq=VCCqmin
-
-
0.2
-
-
0.2
-
-
0.22*
Vccq
V
Output High Voltage
VOH
IOH = -100 µA , VCC=VCCmin ,
VCCq=VCCqmin
VCCq0.1
-
-
VCCq0.4
-
-
0.8*V
-
-
V
Note 1. CE should be VIH for RDY. IOBE should be ’0’ for INT.
Note 2. Icc active for Host access
Note 3. ICC active for Internal operation. (without host access)
Note 4. Vccq is equivalent to Vcc-IO
89
VCCq VCCq+0.4 0.4
-
VCCq 0.7*V
+0.4 CCq
CCq
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
5.0
AC CHARACTERISTICS
5.1
AC Test Conditions
Parameter
Value
Input Pulse Levels
0V to VCC
Input Rise and Fall Times
CLK
3ns
other inputs
5ns
Input and Output Timing Levels
VCC/2
Output Load
CL = 30pF
Device
Under
Test
VCC
Input & Output
Test Point
VCC/2
VCC/2
* CL = 30pF including scope
and Jig capacitance
0V
Input Pulse and Test Point
5.2
Output Load
Device Capacitance
CAPACITANCE(TA = 25 °C, VCC = 1.8V, f = 1.0MHz)
Item
Symbol
Test Condition
CIN1
VIN=0V
Input Capacitance
Single
Unit
Min
Max
-
10
Control Pin Capacitance
CIN2
VIN=0V
-
10
Output Capacitance
COUT
VOUT=0V
-
10
INT Capacitance
CINT
VOUT=0V
-
15
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
5.3
Valid Block Characteristics
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
502
-
512
Blocks
NOTES:
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block.
90
OneNAND256(KFG5616x1A-xxB5)
5.4
FLASH MEMORY
AC Characteristics for Synchronous Burst Read
See Timing Diagrams 6.1, 6.2
Parameter
Symbol
KFG5616x1A
Min
Max
Unit
Clock
CLK
1
54
MHz
Clock Cycle
tCLK
18.5
-
ns
Initial Access Time
tIAA
-
76
ns
Burst Access Time Valid Clock to Output Delay
tBA
-
14.5
ns
AVD Setup Time to CLK
tAVDS
7
-
ns
AVD Hold Time from CLK
tAVDH
7
-
ns
Address Setup Time to CLK
tACS
7
-
ns
Address Hold Time from CLK
tACH
7
-
ns
Data Hold Time from Next Clock Cycle
tBDH
4
-
ns
Output Enable to Data
tOE
-
20
ns
CE Disable to Output High Z
tCEZ1)
-
20
ns
OE Disable to Output High Z
tOEZ1)
-
17
ns
CE Setup Time to CLK
tCES
7
-
ns
CLK High or Low Time
tCLKH/L
tCLK/3
-
ns
CLK 2) to RDY valid
tRDYO
-
14.5
ns
CLK to RDY Setup Time
tRDYA
-
14.5
ns
RDY Setup Time to CLK
tRDYS
4
-
ns
CE low to RDY valid
tCER
-
15
ns
Note
1. If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ.
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ.
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.
2. It is the following clock of address fetch clock.
91
OneNAND256(KFG5616x1A-xxB5)
5.5
FLASH MEMORY
AC Characteristics for Asynchronous Read
See Timing Diagrams 6.3, 6.4, 6.5 and 6.6
Parameter
Symbol
KFG5616x1A
Unit
Min
Max
Unit
Access Time from CE Low
tCE
-
76
ns
Asynchronous Access Time from AVD Low
tAA
-
76
ns
Asynchronous Access Time from address valid
tACC
-
76
ns
Read Cycle Time
tRC
76
-
ns
AVD Low Time
tAVDP
12
-
ns
Address Setup to rising edge of AVD
tAAVDS
7
-
ns
Address Hold from rising edge of AVD
tAAVDH
7
-
ns
Output Enable to Output Valid
tOE
-
20
ns
WE disable to OE enable
tOEH
0
-
ns
CE Setup to AVD falling edge
tCA
0
-
ns
CE Disable to Output & RDY High Z1)
tCEZ
-
20
ns
OE Disable to Output High Z1)
tOEZ
-
17
ns
WE Disable to AVD Enable
tWEA
15
-
ns
NOTE:
1. If OE is disabled at the same time or before CE is disabled, the output will go to high-z by tOEZ.
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by tCEZ.
If CE and OE are disabled at the same time, the output will go to high-z by tOEZ.
These parameters are not 100% tested.
5.6
AC Characteristics for Warm Reset (RP), Hot Reset
and NAND Flash Core Reset
See Timing Diagrams 6.12, 6.13 and 6.14
Parameter
Symbol
Min
Max
Unit
tReady1
(BufferRAM)
-
5
µs
RP & Reset Command Latch(During Load Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
10
µs
RP & Reset Command Latch(During Program Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
20
µs
RP & Reset Command Latch(During Erase Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
500
µs
RP & Reset Command Latch(NOT During Internal Routines) to INT High (Note1)
tReady2
(NAND Flash Array)
-
10
µs
tRP
200
-
ns
RP & Reset Command Latch to BootRAM Access
RP Pulse Width (Note2)
Note
1. These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value.
2. The device may reset if tRP < tRP min(200ns), but this is not guaranteed.
92
OneNAND256(KFG5616x1A-xxB5)
5.7
FLASH MEMORY
AC Characteristics for Asynchronous Write/Load/
Program/Erase Operation
See Timing Diagrams 6.7, 6.8 and 6.9
Parameter
Symbol
Min
Typ
Max
Unit
tWC
70
-
-
ns
AVD low pulse width
tAVDP
12
-
-
ns
Address Setup Time
tAWES
0
-
-
ns
Address Hold Time
tAH
30
-
-
ns
Data Setup Time
tDS
25
-
-
ns
Data Hold Time
tDH
0
-
-
ns
WE Cycle Time
CE Setup Time
tCS
0
-
-
ns
CE Hold Time
tCH
10
-
-
ns
WE Pulse Width
tWPL
40
-
-
ns
WE Pulse Width High
tWPH
30
-
-
ns
AVD Disable to WE Disable
tVLWH
15
-
-
ns
WE Disable to AVD Enable
tWEA
15
-
-
ns
5.8
AC Characteristics for Load/Program/Erase
Performance
See Timing Diagrams 6.8, 6.9, and 6.10
Parameter
Symbol
Min
Typ
Max
Unit
Sector Load time(Note 1)
tRD1
-
23
35
µs
Page Load time(Note 1)
tRD2
-
25
40
µs
Sector Program time(Note 1)
tPGM1
-
205
720
µs
Page Program time(Note 1)
tPGM2
-
220
750
µs
OTP Access Time(Note 1)
tOTP
-
500
700
ns
Lock/Unlock/Lock-tight Time(Note 1)
tLOCK
-
500
700
ns
tESP
-
400
500
µs
1 Block
tERS1
-
2
3
ms
2~64 Blocks
tERS2
4
6
ms
Erase Suspend Time(Note 1)
Erase Resume Time(Note 1)
Number of Partial Program Cycles in the sector (Including main and
spare area)
Block Erase time (Note 1)
Multi BlocK Erase Verify Read time(Note 1)
NOP
-
-
2
cycles
1 Block
tBERS1
-
2
3
ms
2~64 Blocks
tBERS2
-
4
6
ms
tRD3
-
70
100
µs
Note 1) These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor
value.
93
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
6.0
TIMING DIAGRAMS
6.1
8-Word Linear Burst Mode with Wrap Around
See AC Characteristics Table 5.4
5 cycles for initial access shown.
BRL=4
tCLK
tCES
tCLKH tCLKL
≈
CE
tCER
tCEZ
CLK
≈
tAVDS
≈
tRDYO
AVD
tAVDH
≈ ≈
tBDH
tACS
A0-A15
tBA
tACH
D6
D7
D0
D1
D2
D3
≈
DQ0-DQ15
D7
tOEZ
tIAA
tOE
≈
OE
tRDYS
tRDYA
Hi-Z
6.2
Hi-Z
≈
RDY
D0
Continuous Linear Burst Mode with Wrap Around
See AC Characteristics Table 5.4
5 cycles for initial access shown.
BRL=4
tCLK
tCES
≈
CE
tCER
tCEZ
CLK
≈
tAVDS
≈
tRDYO
AVD
tAVDH
≈ ≈
tBDH
tACS
A0-A15
tBA
tACH
Da
Da+1
Da+2
Da+3
Da+4
Da+5
Da+n
≈
DQ0-DQ15
tOEZ
tIAA
tOE
≈
OE
Hi-Z
tRDYA
tRDYS
≈
RDY
Da+n+1
94
Hi-Z
OneNAND256(KFG5616x1A-xxB5)
6.3
FLASH MEMORY
Asynchronous Read (VA and AVD Transition Before CE Low)
See AC Characteristics Table 5.5
VIL
CLK
CE
tCEZ
tAVDP
AVD
tOE
OE
WE
tCE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
A0-A15
RDY
VA
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, RD=Read Data.
6.4
Asynchronous Read (VA and AVD Transition After CE Low)
See AC Characteristics Table 5.5
CLK
VIL
CE
tCEZ
tAA
tAVDP
AVD
tOE
OE
tWEA
WE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
A0-A15
RDY
VA
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, RD=Read Data.
95
OneNAND256(KFG5616x1A-xxB5)
6.5
FLASH MEMORY
Asynchronous Read (VA and AVD Transition After CE Low)
See AC Characteristics Table 5.5
VIL
CLK
CE
tCEZ
tAVDP
AVD
tAAVDS
OE
tOE
tWEA
WE
tOEZ
DQ0-DQ15
Valid RD
tAAVDH
tACC
A0-A15
RDY
VA
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, RD=Read Data.
6.6
Asynchronous Read (AVD is tied to CE)
See AC Characteristics Table 5.5
CLK
VIL
tRC
CE
tCEZ
tOE
OE
WE
tCE
tOEZ
Valid RD
DQ0-DQ15
tACC
A0-A15
VA
RDY Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, RD=Read Data.
96
OneNAND256(KFG5616x1A-xxB5)
6.7
FLASH MEMORY
Asynchronous Write
See AC Characteristics Table 5.7
CLK
VIL
tCH
tCS
tCS
CE
tWPL
tWPH
WE
tWC
OE
RP
tAH
A0-A15
VA
tAWES
DQ0-DQ15
RDY
VA
tDS
tDH
Valid WD
Valid WD
Hi-Z
Hi-Z
NOTE: VA=Valid Read Address, WD=Write Data.
97
OneNAND256(KFG5616x1A-xxB5)
6.8
FLASH MEMORY
Load Operation Timing
See AC Characteristics Tables 5.7 and 5.8
Load Command Sequence
tAWES
A0:A15
Read Data
tAH
CA
AA
LMA
≈ ≈
DQ0-DQ15
BA
LCD
tCS
tDH
CE
≈
tCH
OE
Da
≈
tCH
tDS
BA
tWPL
≈
WE
tWPH
tRD
tCS
VIL
tWC
≈
CLK
INT
NOTES:
1. AA = Address of address register
CA = Address of command register
LCD = Load Command
LMA = Address of memory to be loaded
BA = Address of BufferRAM to load the data
BD = Program Data
SA = Address of status register
2. “In progress” and “complete” refer to status register
3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
98
Da+1
OneNAND256(KFG5616x1A-xxB5)
6.9
FLASH MEMORY
Program Operation Timing
See AC Characteristics Tables 5.7 and 5.8
Program Command Sequence (last two cycles)
tAH
tAWES
A0:A15
Read Status Data
BA
AA
PMA
tCH
PCD
BD
tCS
tCH
SA
≈ ≈
DQ0-DQ15
CA
tCS
≈
tCH
OE
In
Progress
≈
tDH
tDS
CE
SA
tWPL
≈
WE
tWPH
tCS
VIL
≈
CLK
tPGM
tWC
INT
NOTES:
1. AA = Address of address register
CA = Address of command register
PCD = Program Command
PMA = Address of memory to be programmed
BA = Address of BufferRAM to load the data
BD = Program Data
SA = Address of status register
2. “In progress” and “complete” refer to status register
3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
99
Complete
OneNAND256(KFG5616x1A-xxB5)
6.10
FLASH MEMORY
Block Erase Operation Timing
See AC Characteristics Tables 5.7 and 5.8
Erase Command Sequence (last two cycles)
tAWES
A0:A15
Read Status Data
tAH
CA
AA
EMA
≈ ≈
DQ0-DQ15
SA
ECD
tCS
tDH
CE
≈
tCH
OE
In
Progress
≈
tCH
tDS
SA
tWPL
≈
WE
tWPH
tBERS
tCS
VIL
tWC
≈
CLK
INT
NOTES:
1. AA = Address of address register
CA = Address of command register
ECD = Erase Command
EMA = Address of memory to be erased
SA = Address of status register
2. “In progress” and “complete” refer to status register
3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
100
Complete
OneNAND256(KFG5616x1A-xxB5)
6.11
FLASH MEMORY
Cold Reset Timing
POR triggering level
System Power
1)
OneNAND
Operation
Sleep
Bootcode - copy done
Bootcode copy
Idle
2)
RP
INT
High-Z
INT bit
0 (default)
IOBE bit
0 (default)
INTpol bit
1 (default)
3)
1
1
Note: 1) Bootcode copy operation starts 400us later than POR activation.
The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data.
For 2.65V and 3.3V device, The system power should reach Vcc after POR triggering level(typ. 1.8V) within 400us for valid boot code data.
2) 1K bytes Bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of NAND Flash array to BootRAM.
Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.
3) INT register goes ‘Low’ to ‘High’ on the condition of ‘Bootcode-copy done’ and RP rising edge.
If RP goes ‘Low’ to ‘High’ before ‘Bootcode-copy done’, INT register goes to ‘Low’ to ‘High’ as soon as ‘Bootcode-copy done’
101
OneNAND256(KFG5616x1A-xxB5)
6.12
FLASH MEMORY
Warm Reset Timing
See AC Characteristics Tables 5.6
CE, OE
RP
tRP
tReady1
High-Z
RDY
High-Z
tReady2
INT
Operation
Status
Idle1)
Reset Ongoing2)
BootRAM Access3)
INT Bit Polling4)
Idle1)
NOTES:
1. The status which can accept any register based operation(Load, Program, Erase command, etc).
2. The status where reset is ongoing.
3. The status allows only BootRAM(BL1) read operation for Boot Sequence.(refer to 7.2.2 Boot Sequence)
4. To read BL2 of Boot Sequence, Host should wait INT until becomes ready. and then, Host can issue load command.
(refer to 7.2.2 Boot Sequence, 7.1 Methods of Determing Interrupt status)
102
OneNAND256(KFG5616x1A-xxB5)
6.13
FLASH MEMORY
Hot Reset Timing
AVD
BP(Note 3)
or F220h
A0~A15
00F0h
or 00F3h4)
DQ0~DQ15
CE
OE
WE
tReady2
INT
bit
RDY
OneNAND
Operation
High-Z
Operation or Idle
OneNAND reset
Idle
NOTE:
1. Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept
unchanged after Warm/Hot reset operations.
2. Reset command : Command based reset or Register based reset
3. BP(Boot Partition): BootRAM area [0000h~01FFh, 8000h~800Fh]
4. 00F0h for BP, and 00F3h for F220h
103
OneNAND256(KFG5616x1A-xxB5)
6.14
FLASH MEMORY
NAND Flash Core Reset Timing
AVD
F220h
A0~A15
DQ0~DQ15
00F0h
CE
OE
WE
tReady2
INT
bit
RDY
OneNAND
Operation
6.15
High-Z
Operation or Idle
NAND Flash Core reset
Idle
Data Protection Timing During Power Down
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.3V. RP pin provides hardware protection and is recommended to be kept at VIL
before power-down.
VCC
typ. 1.3V
0V
RP
INT
OneNAND
Operation
Idle
One NAND Reset
104
NAND Write
Protected
OneNAND256(KFG5616x1A-xxB5)
7.0
FLASH MEMORY
TECHNICAL AND APPLICATION NOTES
From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a
system are included in this section. Contact your Samsung Representative to determine if additional notes are available.
7.1
Methods of Determining Interrupt Status
There are two methods of determining Interrupt Status on the OneNAND. Using the INT pin or monitoring the Interrupt Status Register Bit.
The OneNAND INT pin is an output pin function used to notify the Host when a command has been completed. This provides a hardware method of signaling the completion of a program, erase, or load operation.
In its normal state, the INT pin is high if the INT polarity bit is default. Before a command is written to the command register, the INT
bit must be written to '0' so the INT pin transitions to a low state indicating start of the operation. Upon completion of the command
operation by the OneNAND’s internal controller, INT returns to a high state.
INT is an open drain output allowing multiple INT outputs to be Or-tied together. INT does not float to a hi-Z condition when the chip is
deselected or when outputs are disabled. Refer to section 2.8 for additional information about INT.
INT can be implemented by tying INT to a host GPIO or by continuous polling of the Interrupt status register.
7.1.1
The INT Pin to a Host General Purpose I/O
INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation.
COMMAND
INT
This can be configured to operate either synchronously or asynchronously as shown in the diagrams below.
105
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Synchronous Mode Using the INT Pin
When operating synchronously, INT is tied directly to a Host GPIO.
Host
OneNAND
CE
CE
AVD
AVD
CLK
CLK
RDY
RDY
OE
OE
GPIO
INT
Asynchronous Mode Using the INT Pin
When configured to operate in an asynchronous mode, CE and AVD of the OneNAND are tied to CE of the Host. CLK is tied to the
Host Vss (Ground). RDY is tied to a no-connect. OE of the OneNAND and Host are tied together and INT is tied to a GPIO.
Host
OneNAND
CE
CE
AVD
7.1.2
Vss
CLK
N.C
RDY
OE
OE
GPIO
INT
Polling the Interrupt Register Status Bit
An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of
using the INT pin.
Command
INT
This can be configured in either a synchronous mode or an asynchronous mode.
106
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Synchronous Mode Using Interrupt Status Register Bit Polling
When operating synchronously, CE, AVD, CLK, RDY, OE, and DQ pins on the host and OneNAND are tied together.
Host
OneNAND
CE
CE
AVD
AVD
CLK
CLK
RDY
RDY
OE
OE
DQ
DQ
Asynchronous Mode Using Interrupt Status Register Bit Polling
When configured to operate in an asynchronous mode, CE and AVD of the OneNAND are tied to CE of the Host. CLK is tied to the
Host Vss (Ground). RDY is tied to a no-connect. OE and DQ of the OneNAND and Host are tied together.
Host
OneNAND
CE
CE
AVD
Vss
CLK
N.C
RDY
OE
OE
DQ
DQ
107
OneNAND256(KFG5616x1A-xxB5)
7.1.3
FLASH MEMORY
Determining Rp Value
Because the pull-up resistor value is related to tr(INT) an appropriate value can obtained with the following reference charts.
INT pol = ’High’
Vcc and Vccq
Rp
~50k ohm
INT
Ready Vcc
VOH
VOL
Vss
Busy State
tf
tr
KFG5616x1A @ Vcc = 1.8V, TA = 25°C , CL = 30pF
2.142
0.18
0.09
tf[ns]
3.77
1K
≈
0.089
tr[us]
0.06
1.345
0.045
≈
0.7727
1.788
0.036
3.77
3.77
3.77
3.77
3.77
10K
20K
30K
Rp(ohm)
40K
50K
108
≈≈
≈
tr,tf
Ibusy
Ibusy [mA]
2.431
1.75
≈
5.420
0.000
Open(100K)
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
INT pol = ’Low’
Vcc and Vccq
INT
Rp
~50k ohm
tf
tr
Ready
Vcc
VOH
Busy State
Vss
VOL
KFG5616x1A @ Vcc = 1.8V, TA = 25°C , CL = 30pF
1.623
0.18
0.09
tr[ns]
6.49
1K
≈
0.067
tf[us]
0.06
1.02
0.045
≈
0.586
1.356
0.036
6.49
6.49
6.49
6.49
6.49
10K
20K
30K
Rp(ohm)
40K
50K
109
≈≈
≈
tr,tf
Ibusy
Ibusy [mA]
1.84
1.75
≈
4.05
0.000
Open(100K)
OneNAND256(KFG5616x1A-xxB5)
7.2
FLASH MEMORY
Boot Sequence
One of the best features OneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader
despite the fact that its core architecture is based on NAND Flash. Thus, OneNAND does not make any additional booting device
necessary for a system, which imposes extra cost or area overhead on the overall system.
As the system power is turned on, the boot code originally stored in NAND Flash Arrary is moved to BootRAM automatically and then
fetched by CPU through the same interface as SRAM’s or NOR Flash’s if the size of the boot code is less than 1KB. If its size is larger
than 1KB and less than or equal to 2KB, only 1KB of it can be moved to BootRAM automatically and fetched by CPU, and the rest of
it can be loaded into one of the DataRAMs whose size is 1KB by Load Command and CPU can take it from the DataRAM after finishing the code-fetching job for BootRAM. If its size is larger than 2KB, the 1KB portion of it can be moved to BootRAM automatically
and fetched by CPU, and its remaining part can be moved to DRAM through two DataRAMs using dual buffering and taken by CPU
to reduce CPU fetch time.
A typical boot scheme usually used to boot the system with OneNAND is explained at Patition of NAND Flash Array and OneNAND
Boot Sequence. In this boot scheme, boot code is comprised of BL1, where BL stands for Boot Loader, BL2, and BL3. Moreover, the
size of the boot code is larger than 3KB (the 3rd case above). BL1 is called primary boot loader in other words. Here is the table of
detailed explanations about the function of each boot loader in this specific boot scheme.
7.2.1
Boot Loaders in OneNAND
Boot Loaders in OneNAND
Boot Loader
Description
BL1
Moves BL2 from NAND Flash Array to DRAM through two DataRAMs using dual buffering
BL2
Moves OS image (or BL3 optionally) from NAND Flash Array to DRAM through two DataRams using dual buffering
BL3 (Optional)
Moves or writes the image through USB interface
NAND Flash Array of OneNAND is divided into the partitions as described at Partition of NAND Flash Array to show where each
component of code is located and how much portion of the overall NAND Flash Array each one occupies. In addition, the boot
sequence is listed below and depicted at Boot Sequence.
7.2.2
Boot Sequence
Boot Sequence :
1. Power is on
BL1 is loaded into BootRAM
2. BL1 is executed in BootRAM
BL2 is loaded into DRAM through two DataRams using dual buffering by BL1
3. BL2 is executed in DRAM
OS image is loaded into DRAM through two DataRams using dual buffering by BL2
4. OS is running
110
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Block 512
Reservoir
Partition 6
File System
Partition 5
Sector 0 Sector 1
Page 63
Page 62
Block 162
Partition 4
NBL3
BL3
Partition 3
:
:
BL2
Os Image
Block 2
Block 1
Block 0
NBL1
BL1
Page 2
Page 1
NBL2
BL2
BL1
Page 0
Partition of NAND Flash array
Reservoir
File System
step 3
Data Ram 1
Os Image
Data Ram 0
Os Image
Boot Ram(BL 1)
BL1
BL2
BL 2
step 2
step 1
NAND Flash Array
Internal BufferRAM
OneNAND
DRAM
NOTE:
Step 2 and Step 3 can be copied into DRAM through two DataRAMs using dual buffering
OneNAND Boot Sequence
111
OneNAND256(KFG5616x1A-xxB5)
8.0
FLASH MEMORY
PACKAGE DIMENSIONS
67-FBGA-7.00x9.00
Units:millimeters
7.00±0.10
A
#A1 INDEX
0.80x7=5.60
0.10 MAX
7.00±0.10
(Datum A)
2.800
0.80
6
5
4
3
2
B
1
#A1
D
E
3.60
F
G
H
0.32±0.05
0.90±0.10
BOTTOM VIEW
TOP VIEW
67-∅ 0.45±0.05
∅ 0.20 M A B
256Mb product (KFG5616x1A)
112
9.00±0.10
B
0.80x9=7.20
0.80
A
C
0.45±0.05
9.00±0.10
9.00±0.10
(Datum B)
OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
0.50
0.0197
12.40
0.488 MAX
( 0.25 )
0.010
#1
12.00
0.472
+0.003
0.008-0.001
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
+0.075
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
18.40±0.10
0.724±0.004
0.125 0.035
0.25
0.010 TYP
1.00±0.05
0.039±0.002
( 0.50 )
0.020
256Mb product (KFG5616x1A)
113
1.20
0.047MAX
0.05
0.002 MIN