VICOR VTM48EH020040A00

VTM48EH020 x 040A00
(Formerly VIV0103THJ)
VTM™
Current Multiplier
S
®
US
C
FEATURES
• 48 Vdc to 2 Vdc 40 A current multiplier
- Operating from standard 48 V or 24 V PRMTM regulators
• High efficiency (>91%) reduces system power
consumption
• High density (267 A/in3)
• “Half Chip” VI Chip® package enables surface mount,
low impedance interconnect to system board
• Contains built-in protection features against:
-
Overvoltage
Overcurrent
Short Circuit
Overtemperature
• Provides enable / disable control, internal temperature
monitoring, current monitoring
• ZVS / ZCS resonant Sine Amplitude Converter topology
• Less than 50 ºC temperature rise at full load
in typical applications
TYPICAL APPLICATIONS
• High End Computing Systems
• Automated Test Equipment
• High Density Power Supplies
• Communications Systems
•0
C
NRTL
US
DESCRIPTION
The VI Chip® current multiplier is a high efficiency (>91%)
Sine Amplitude Converter™ (SAC™) operating from a
26 to 55 Vdc primary bus to deliver an isolated output.
The Sine Amplitude Converter offers a low AC impedance
beyond the bandwidth of most downstream regulators, which
means that capacitance normally at the load can be located
at the input to the Sine Amplitude Converter. Since the K factor
of the VTM48EH020T040A00 is 1/24, that capacitance value
can be reduced by a factor of 576, resulting in savings of board
area, materials and total system cost.
The VTM48EH020T040A00 is provided in a VI Chip® package
compatible with standard pick-and-place and surface mount
assembly processes. The co-molded VI Chip® package provides
enhanced thermal management due to large thermal interface
area and superior thermal conductivity. With high conversion
efficiency the VTM48EH020T040A00 increases overall system
efficiency and lowers operating costs compared to conventional
approaches.
The VTM48EH020T040A00 enables the utilization of Factorized
Power ArchitectureTM providing efficiency and size benefits by
lowering conversion and distribution losses and promoting high
density point of load conversion.
VIN = 26 to 55 V
IOUT = 40 A (NOM)
VOUT = 1.1 to 2.3 V (NO LOAD)
K= 1/24
PART NUMBERING
PART NUMBER
PRODUCT GRADE
T = -40° to 125 °C
VTM48EH020 x 040A00
M = -55° to 125 °C
For Storage and Operating Temperatures see Section 6.0 General Characteristics
Regulator
PR
PC
TM
IL
Current Multiplier
VC
SG
OS
CD
PC
IM
VC
TM
VTM™
PRM™
+In
+Out
-In
-Out
+In
+Out
-In
-Out
VIN
L
O
A
D
(See Application Note AN:024)
Factorized Power Architecture™
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 1 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent
damage to the device.
MIN
MAX
UNIT
MIN
MAX
UNIT
+ IN to - IN . . . . . . . . . . . . . . . . . . . . . . .
-1.0
60
VDC
IM to - IN.................................................
PC to - IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
20
VDC
+ IN / - IN to + OUT / - OUT (hipot)........
TM to -IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
7
VDC
+ IN / - IN to + OUT / - OUT (working)...
VC to - IN . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
20
VDC
+ OUT to - OUT.......................................
0
-1.0
3.15
VDC
2250
VDC
60
VDC
4
VDC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40 °C < TJ < 125 °C (T-Grade); All other specifications are at TJ = 25 ºC unless otherwise noted.
ATTRIBUTE
SYMBOL
Input Voltage Range
VIN
VIN Slew Rate
dVIN /dt
VIN UV Turn Off
VIN_UV
CONDITIONS / NOTES
No external VC applied
VC applied
No Load power dissipation
PNL
Inrush current peak
IINRP
Module latched shutdown,
No external VC applied, IOUT = 40A
VIN = 45 V
VIN = 26 V to 55 V
VIN = 45 V, TC = 25 ºC
VIN = 26 V to 55 V, TC = 25 ºC
VC enable, VIN = 45 V COUT = 1500 µF,
RLOAD = 47 mΩ
IIN_DC
K
VOUT
K = VOUT / VIN, IOUT = 0 A
VOUT = VIN • K - IOUT • ROUT, Section 11
DC input current
Transfer ratio
Output voltage
Output current (average)
Output current (peak)
Output power (average)
IOUT_AVG
IOUT_PK
POUT_AVG
ηAMB
Efficiency (ambient)
ηHOT
η20%
Efficiency (hot)
Efficiency (Over load range)
Output resistance (Cold)
Output resistance (Ambient)
Output resistance (Hot)
Switching frequency
Output ripple frequency
ROUT_COLD
ROUT_AMB
ROUT_HOT
FSW
FSW_RP
Output voltage ripple
VOUT_PP
Output inductance (parasitic)
LOUT_PAR
Output capacitance (internal)
COUT_INT
Output capacitance (external)
COUT_EXT
PROTECTION
OVLO
Overvoltage lockout
response time
Output overcurrent trip
Short circuit protection trip current
Output overcurrent response
time constant
Short circuit protection response time
Thermal shutdown setpoint
TPEAK < 10 ms, IOUT_AVG ≤ 40 A
IOUT_AVG ≤ 40 A
VIN = 45 V, IOUT = 40 A
VIN = 26 V to 55 V, IOUT = 40 A
VIN = 45 V, IOUT = 20 A
VIN = 45 V, TC = 100 °C, IOUT = 40 A
8 A < IOUT < 40 A
TC = -40 °C, IOUT = 40 A
TC = 25 °C, IOUT = 40 A
TC = 100 °C, IOUT = 40 A
Module latched shutdown
TOVLO
Effective internal RC filter
IOCP
ISCP
13.3
1.4
2.4
2.5
Effective internal RC filter (Integrative).
TSCP
From detection to cessation
of switching (Instantaneous)
MAX
V/µs
26.0
V
3.9
4.8
3.0
3.7
W
10
A
1.8
A
V/V
V
A
A
W
40
60
88.5
88.5
83.0
88.0
88.0
77.0
1.6
1.8
2.6
1.60
3.20
55.5
VDC
90.2
%
90.3
89.6
2.1
2.7
3.2
1.80
3.60
2.6
3.4
5.0
1.90
3.80
%
%
mΩ
mΩ
mΩ
MHz
MHz
165
350
mV
600
pH
120
µF
57.7
1500
µF
59.8
V
2.4
125
UNIT
55
55
1
1/24
44
80
TOCP
TYP
26
0
COUT = 0 F, IOUT = 40 A, VIN = 45 V,
20 MHz BW, Section 12
Frequency up to 30 MHz,
Simulated J-lead model
VOUT = 2 V
VTM Standalone Operation
VIN pre-applied, VC enable
VIN_OVLO+
TJ_OTP
MIN
70
µs
100
A
A
5.5
ms
1
µs
130
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
135
ºC
Rev. 2.1
6/2012
Page 2 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40 °C < TJ < 125 °C (T-Grade); All other specifications are at TJ = 25 °C unless otherwise noted.
• Used to wake up powertrain circuit.
• A minimum of 12 V must be applied indefinitely for VIN < 26 V
to ensure normal operation.
• VC slew rate must be within range for a successful start.
SIGNAL TYPE
STATE
Steady
ATTRIBUTE
VTM CONTROL : VC
• PRM VC can be used as valid wake-up signal source.
• VC voltage may be continuously applied;
there will be minimal VC current drawn when VIN > 26 V and VC < 13.
• Internal resistance used in adaptive loop compensation
SYMBOL
External VC voltage
VVC_EXT
VC current draw threshold
VVC_TH
VC current draw
IVC
VC internal resistor
RVC-INT
VC slew rate
dVC/dt
VC inrush current
IINR_VC
CONDITIONS / NOTES
Required for startup, and operation
below 26 V. See Section 7.
Low VC current draw for VIN >26 V
VC = 13 V, VIN = 0 V
VC = 13 V, VIN > 26 V
VC = 16.5 V, VIN > 26 V
TYP
12
MAX UNIT
16.5
13
90
6
90
9.31
V
150
mA
kΩ
V/µs
VC = 16.5 V, dVC/dt = 0.25 V/µs
750
VIN pre-applied, PC floating, VC enable
VC output turn-on delay
TON
500
CPC = 0 µF, COUT = 1500 µF
Transitional
VC = 12 V to PC high, VIN = 0 V,
10
VC to PC delay
TVC_PC
25
dVC/dt = 0.25 V/µs
Internal VC capacitance
CVC_INT
VC = 0 V
2.2
PRIMARY CONTROL : PC
• The PC pin enables and disables the VTM.
• Module will shutdown when pulled low with an impedance
When held below 2 V, the VTM will be disabled.
less than 400 Ω.
• PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V
• In an array of VTMs, connect PC pin to synchronize startup.
during fault mode given VIN > 26 V and VC > 12 V.
• PC pin cannot sink current and will not disable other module
• After successful start-up and under no fault condition, PC can be used as
during fault mode.
a 5 V regulated voltage source with a 2 mA maximum current.
mA
Start Up
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
0.02
V
0.25
ANALOG
INPUT
Required for proper startup;
MIN
MIN
TYP
PC voltage
VPC
4.7
5.0
5.3
PC source current
IPC_OP
2
ANALOG
PC resistance (internal)
RPC_INT
Internal pull down resistor
50
150
400
OUTPUT
PC source current
IPC_EN
50
100
300
Start Up
PC capacitance (internal)
CPC_INT
Section 7
50
PC resistance (external)
RPC_EXT
60
PC voltage (enable)
VPC_EN
2
2.5
3
Enable
PC voltage (disable)
VPC_DIS
2
Disable
DIGITAL
PC pull down current
IPC_PD
5.1
INPUT / OUPUT
PC disable time
TPC_DIS_T
4
Transitional
PC fault response time
TFR_PC
From fault to PC = 2 V
100
TEMPERATURE MONITOR : TM
• The TM pin monitors the internal temperature of the VTM controller IC
• The TM pin has a room temperature setpoint of 3 V (@27 °C)
within an accuracy of ±5 °C.
and approximate gain of 10 mV/ °C.
• Can be used as a "Power Good" flag to verify that the VTM is operating.
STATE
ANALOG
OUTPUT
Steady
Disable
DIGITAL OUTPUT
(FAULT FLAG)
Transitional
ATTRIBUTE
TM voltage
TM source current
TM gain
SYMBOL
VTM_AMB
ITM
ATM
TM voltage ripple
VTM_PP
TM voltage
TM resistance (internal)
TM capacitance (external)
TM fault response time
VTM_DIS
RTM_INT
CTM_EXT
TFR_TM
CONDITIONS / NOTES
TJ controller = 27 °C
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
V
mA
kΩ
µA
pF
kΩ
V
V
mA
µs
µs
TYP
MAX UNIT
2.95
3.00
3.05
100
V
µA
mV/°C
200
mV
50
50
V
kΩ
pF
µs
10
From fault to TM = 1.5 V
µF
MIN
CTM = 0 F, VIN = 45 V,
IOUT = 40 A
Internal pull down resistor
µs
MAX UNIT
Steady
SIGNAL TYPE
µs
120
25
0
40
10
Rev. 2.1
6/2012
Page 3 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
3.0 SIGNAL CHARACTERISTICS (CONT.)
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40 °C < TJ < 125 °C (T-Grade); All other specifications are at TJ = 25 °C unless otherwise noted.
CURRENT MONITOR : IM
• The nominal IM pin voltage varies between 0.3 V and 1.64 V
representing the output current within ±25% under all operating line
temperature conditions between 50% and 100%.
SIGNAL TYPE
STATE
ANALOG
OUTPUT
ATTRIBUTE
IM voltage (no load)
IM voltage (50%)
IM voltage (full load)
IM gain
IM resistance (external)
Steady
• The IM pin provides a DC analog voltage proportional to
the output current of the VTM.
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
VIM_NL
VIM_50%
VIM_FL
A IM
RIM_EXT
TC = 25ºC, VIN = 45 V, IOUT = 0 A
TC = 25ºC, VIN = 45 V, IOUT = 20 A
TC = 25ºC, VIN = 45 V, IOUT = 40 A
TC = 25ºC, VIN = 45 V, IOUT > 20 A
0.15
0.3
0.82
1.64
41
0.45
V
V
V
mV/A
MΩ
2.5
4.0 TIMING DIAGRAM
IOUT
6
7
ISSP
IOCP
1
2 3
VC
4
8
d
5
b
VVC-EXT
a
VOVLO
VIN
NL
≥ 26 V
c
e
f
VOUT
TM
VTM-AMB
PC
g
5V
3V
a: VC slew rate (dVC/dt)
b: Minimum VC pulse rate
c: TOVLO
d: TOCP
e: Output turn on delay (TON)
f: PC disable time (TPC_DIS_T)
g: VC to PC delay (TVC_PC)
1. Initiated VC pulse
2. Controller start
3. VIN ramp up
4. VIN = VOVLO
5. VIN ramp down no VC pulse
6. Overcurrent
7. Start up on short circuit
8. PC driven low
Notes:
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
– Timing and voltage is not to scale
– Error pulse width is load dependent
Rev. 2.1
6/2012
Page 4 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
5.0 APPLICATION CHARACTERISTICS
The following values, typical of an application environment, are collected at TC = 25 ºC unless otherwise noted. See associated
figures for general trend data.
ATTRIBUTE
SYMBOL
No load power dissipation
Efficiency (ambient)
Efficiency (hot)
Output resistance (ambient)
Output resistance (hot)
Output resistance (cold)
PNL
ηAMB
ηHOT
ROUT_AMB
ROUT_HOT
ROUT_COLD
Output voltage ripple
VOUT_PP
VOUT Transient (positive)
VOUT_TRAN+
VOUT Transient (negative)
VOUT_TRAN-
CONDITIONS / NOTES
TYP
UNIT
VIN = 45 V
VIN = 45 V, IOUT = 40 A
VIN = 45 V, IOUT = 40 A, TC = 100 ºC
VIN = 45 V, IOUT = 40 A
VIN = 45 V, IOUT = 40 A, TC = 100 ºC
VIN = 45 V, IOUT = 40 A, TC = -40 ºC
COUT = 0 F, IOUT = 40 A, VIN = 45 V,
20 MHz BW, Section 12
IOUT_STEP = 0 A TO 40A, VIN = 45 V,
ISLEW > 10 A /us
IOUT_STEP = 40 A to 0 A, VIN = 45 V
ISLEW > 10 A /us
2.6
90.3
89.8
2.7
3.1
2.2
W
%
%
mΩ
mΩ
mΩ
193
mV
20
mV
20
mV
Full Load Efficiency vs. Case Temperature
No Load Power Dissipation vs. Line
92
Full Load Efficiency (%)
4.5
4
3.5
3
2.5
2
1.5
90
88
86
84
82
1
26
29
32
36
39
42
45
49
52
-40
55
-20
-40 °C
TCASE:
25 °C
VIN :
100 °C
20
40
60
80
100
26 V
45 V
55 V
Figure 2 — Full load efficiency vs. temperature
Figure 1 — No load power dissipation vs. VIN
Efficiency & Power Dissipation 25 °C Case
Efficiency & Power Dissipation -40 °C Case
18
92
18
88
16
88
16
12
10
76
72
8
PD
68
6
η
84
Efficiency (%)
η
80
14
Power Dissipation (W)
92
84
Efficiency (%)
0
Case Temperature (°C)
Input Voltage (V)
80
14
12
76
10
72
8
PD
68
6
64
4
64
4
60
2
60
2
56
0
56
0
4
8
12
16
20
24
28
32
36
0
0
40
4
26 V
45 V
55 V
8
12
16
20
24
28
32
36
40
Output Current (A)
Load Current (A)
VIN:
Power Dissipation (W)
No Load Power Dissipation (W)
5
26 V
45 V
Figure 3 — Efficiency and power dissipation at –40 °C
55 V
VIN:
26 V
45 V
55 V
26 V
45 V
55 V
Figure 4 — Efficiency and power dissipation at 25 °C
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 5 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
ROUT vs. Case Temperature at VIN = 45 V
Efficiency & Power Dissipation 100 °C Case
88
16
η
Efficiency (%)
84
80
14
12
10
76
72
8
PD
68
6
64
4
60
2
3.5
3.0
Rout (mΩ)
18
Power Dissipation (W)
92
0
4
8
12
16
20
24
28
32
36
2.0
1.5
0
56
2.5
1.0
40
-40
-20
Output Current (A)
26 V
VIN:
45 V
55 V
26 V
45 V
55 V
I OUT :
Ripple vs. Load
40
60
80
100
4A
40 A
IM Voltage vs. Load at VIN = 45 V
200
2.00
175
1.75
1.50
IM (V)
150
125
1.25
1.00
0.75
100
0.50
75
0.25
50
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
Load Current (A)
16
20
24
28
32
36
40
Load Current (A)
TCASE:
Vpk-pk (mV)
Figure 7 — VRIPPLE vs. IOUT ; No external COUT.
Board mounted module, scope setting : 20 MHz analog BW
-40 ºC
25 ºC
100 ºC
Figure 8 — IM voltage vs. load
IM Voltage vs. TCASE & Line
IM Voltage vs. Load 25 °C Case
2.00
2.0
1.75
1.9
1.50
1.8
IM (V)
1.25
IM (V)
20
Figure 6 — ROUT vs. temperature
Figure 5 — Efficiency and power dissipation at 100 °C
Ripple (mV pk-pk)
0
Case Temperature (°C)
1.00
0.75
1.7
1.6
1.5
0.50
1.4
0.25
1.3
0
0
4
8
12
16
20
24
28
32
36
40
-40
-20
0
VIN :
26 V
Figure 9 — IM voltage vs. load
45 V
20
40
60
80
100
TCASE (°C)
Load Current (A)
55 V
VIN
26 V
45 V
55 V
Figure 10 — Full load IM voltage vs. TCASE
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 6 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
Safe Operating Area
80
Output Current (A)
70
60
10 ms Max
50
40
Continuous
30
20
10
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Output Voltage (V)
Figure 11 — Safe operating area
Figure 12 — Full load ripple, 100 µF CIN; No external COUT.
Board mounted module, scope setting : 20 MHz analog BW
Figure 13 — Start up from application of VIN ; VC pre-applied
COUT = 0 µF
Figure 14 — Start up from application of VC; VIN pre-applied
COUT = 0 µF
Figure 15 — 0 A – 40 A transient response:
CIN = 100 µF, no external COUT
Figure 16 — 40 A – 0 A transient response:
CIN = 100 µF, no external COUT
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 7 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
6.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40 ºC < TJ < 125 ºC (T-Grade); All Other specifications are at TJ = 25 °C unless otherwise noted.
ATTRIBUTE
SYMBOL
MECHANICAL
Length
Width
Height
Volume
Weight
L
W
H
Vol
W
CONDITIONS / NOTES
TYP
MAX
UNIT
21.7 / [0.85]
16.4 / [0.64]
6.48 / [0.255]
22.0 / [0.87]
16.5 / [0.65]
6.73 / [0.265]
2.44 / [0.150]
8.0 / 0.28
22.3 / [0.88]
16.6 / [0.66]
6.98 / [0.275]
mm/[in]
mm/[in]
mm/[in]
cm3/[in3]
g/[oz]
No heat sink
Nickel
Palladium
Gold
Lead finish
MIN
0.51
0.02
0.003
2.03
0.15
0.051
-40
-55
125
125
°C
°C
Ws/°C
3
lbs
125
125
°C
°C
µm
THERMAL
Operating temperature
TJ
VTM48EH020T040A00 (T-Grade)
VTM48EH020M040A00 (M-Grade)
Thermal capacity
5
ASSEMBLY
Peak compressive force
Applied to case (Z-axis)
Supported by J-lead only
Storage temperature
TST
ESDHBM
ESD withstand
ESDMM
VTM48EH020T040A00 (T-Grade)
VTM48EH020M040A00 (M-Grade)
Human Body Model,
"JEDEC JESD 22-A114C.01"
Machine Model,
"JEDEC JESD 22-A115-A"
2.5
-40
-65
1500
VDC
400
SOLDERING
MSL 5
MSL 6, TOB = 4hrs
Peak temperature during reflow
Peak time above 183 °C
Peak heating rate during reflow
Peak cooling rate post reflow
SAFETY
Working voltage (IN – OUT)
Isolation voltage (hipot)
Isolation capacitance
Isolation resistance
MTBF
Agency approvals / standards
1.5
1.5
VIN_OUT
VHIPOT
CIN_OUT
RIN_OUT
Unpowered Unit
2250
1350
10
1750
MIL HDBK 217, 25 ºC,
4.5
Ground Benign
cTUVus
cURus
CE Marked for low voltage directive and RoHS recast directive, as applicable
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
225
245
150
3
6
°C
°C
s
°C/s
°C/s
60
VDC
VDC
pF
MΩ
2150
MHrs
Rev. 2.1
6/2012
Page 8 of 16
v i c o r p o w e r. c o m
VTM48EH020 x 040A00
7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM
The VTM Control (VC) pin is an input pin which powers the
internal VCC circuitry when within the specified voltage range
of 12 V to 16.5 V. This voltage is required in order for the VTM
module to start, and must be applied as long as the input is
below 26 V. In order to ensure a proper start, the slew rate of
the applied voltage must be within the specified range.
Some additional notes on the using the VC pin:
• In most applications, the VTM™ module will be powered
by an upstream PRM which provides a 10 ms VC pulse
during startup. In these applications the VC pins of the PRM
and VTM should be tied together.
• The VC voltage can be applied indefinitely allowing for
continuous operation down to 0 VIN.
• The fault response of the VTM module is latching.
A positive edge on VC is required in order to restart the unit.
If VC is continuously applied the PC pin may be toggled
to restart the module.
Primary Control (PC) pin can be used to accomplish the
following functions:
• Delayed start: Upon the application of VC, the PC pin will
source a constant 100 µA current to the internal RC
network. Adding an external capacitor will allow further
delay in reaching the 2.5 V threshold for module start.
• Auxiliary voltage source: Once enabled in regular
operational conditions (no fault), each VTM PC provides a
regulated 5 V, 2 mA voltage source.
• Output disable: PC pin can be actively pulled down in order
to disable the module. Pull down impedance shall be lower
than 400 Ω.
• Fault detection flag: The PC 5 V voltage source is internally
turned off as soon as a fault is detected. It is important to
notice that PC doesn’t have current sink capability. Therefore,
in an array, PC line will not be capable of disabling
neighboring modules if a fault is detected.
• Fault reset: PC may be toggled to restart the unit if VC
is continuously applied.
Temperature Monitor (TM) pin provides a voltage
proportional to the absolute temperature of the converter
control IC.
It can be used to accomplish the following functions:
• Monitor the control IC temperature: The temperature in
Kelvin is equal to the voltage on the TM pin scaled
by 100. (i.e. 3.0 V = 300 K = 27 ºC). If a heat sink is applied,
TM can be used to thermally protect the system.
• Fault detection flag: The TM voltage source is internally
turned off as soon as a fault is detected. For system
monitoring purposes (microcontroller interface) faults are
detected on falling edges of TM signal.
Current Monitor (IM) pin provides a voltage proportional to
the output current of the VTM module. The nominal voltage
will vary between 0.3 V and 1.64 V over the output current
range of the module (See Figures 8–10). The accuracy of the
IM pin will be within 25% under all line and temperature
conditions between 50% and 100% load.
8.0 STARTUP BEHAVIOR
Depending on the sequencing of the VC with respect to the
input voltage, the behavior during startup will vary as follows:
• Normal Operation (VC applied prior to VIN): In this case the
controller is active prior to ramping the input. When the
input voltage is applied, the VTM output voltage will track
the input (See Figure 13). The inrush current is determined by
the input voltage rate of rise and output capacitance. If the
VC voltage is removed prior to the input reaching 26 V, the
VTM module may shut down.
• Stand Alone Operation (VC applied after VIN ): In this case the
module output will begin to rise upon the application of the
VC voltage (See Figure 14). The Adaptive Soft Start circuit
(See Section 10) may vary the ouput rate of rise in order to
limit the inrush current to it’s maximum level. When starting
into high capacitance, or a short, the output current will be
limited for a maximum of 900 µsec. After this period, the
adaptive soft start circuit will time out and the module
may shut down. No restart will be attempted until VC is
re-applied, or PC is toggled. The maximum output
capacitance is limited to 1500 µF in this mode of operation
to ensure a sucessful start.
9.0 THERMAL CONSIDERATIONS
VI Chip® products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with
the input / output conditions, thermal management and
environmental conditions. Maintaining the top of the
VTM48EH020T040A00 case to less than 100 ºC will keep all
junctions within the VI Chip® below 125 ºC for most
applications.
The percent of total heat dissipated through the top surface
versus through the J-lead is entirely dependent on the
particular mechanical and thermal environment. The heat
dissipated through the top surface is typically 60%. The heat
dissipated through the J-lead onto the PCB board surface is
typically 40%. Use 100% top surface dissipation when
designing for a conservative cooling solution.
It is not recommended to use a VI Chip® module for an
extended period of time at full load without proper heat
sinking.
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 9 of 16
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v i c o r p o w e r. c o m
PC
-VIN
VC
+VIN
560 pF
2.5 V
Rvc
Enable
100 uA
150 K
1.5 k
2.5 V
PC Pull-Up
& Source
10.5 V
Buck
Regulator
Supply
18 V
CIN
5V
Enable
2 mA
OVLO
UVLO
VIN
Adaptive
Soft Start
Gate
Drive
Supply
Enable
Fault Logic
Enable
Modulator
Q2
Primary Current
Sensing
Primary
Gate
Drive
Q1
Lr
Over
Temperature
Protection
Cr
Primary Stage &
Resonant Tank
Slow
current
limit
Fast
current
limit
Overcurrent
Protection
Secondary
Gate Drive
Power
Transformer
VREF
(130ºC ± 5°C)
Vref
C2
C1
40 K
Synchronous
Rectification
Q4
3 V max.
240 µA max.
Temperature
dependent
voltage source
Q3
COUT
TM
IM
-VOUT
+VOUT
VTM48EH020 x 040A00
10.0 VTM™ MODULE BLOCK DIAGRAM
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 10 of 16
VTM48EH020 x 040A00
11.0 SINE AMPLITUDE CONVERTER™ POINT OF LOAD CONVERSION
The Sine Amplitude Converter™ (SAC™) uses a high frequency
resonant tank to move energy from input to output. (The
resonant tank is formed by Cr and leakage inductance Lr in the
power transformer windings as shown in the VTM™ Module
Block Diagram. See Section 10). The resonant LC tank,
operated at high frequency, is amplitude modulated as
function of input voltage and output current. A small amount
of capacitance embedded in the input and output stages of
the module is sufficient for full functionality and is key to
achieving power density.
The VTM48EH020T040A00 SAC can be simplified into the
following model:
76 pH
IOUT
IOUT
LLININ==
3.7
5 nH
nH
OUT
RROUT
2.7 mΩ
+
R
RCIN
CIN
6.3 mΩ
CCININ
900 nF
RRCOUT
COUT
87 mΩ
V•I
1/24 • IOUT
VIN
V
IN
LOUT = 600 pH
+
+
–
–
+
22 µΩ
1/24 • VIN
COUT
COUT
IIQQ
120 µF
VVOUT
OUT
0.053 A
K
–
–
Figure 17 — VI Chip® module AC model
At no load:
VOUT = VIN • K
(1)
ROUT = 0 Ω and IQ = 0 A, Eq. (3) now becomes Eq. (1) and is
essentially load independent. A resistor R is now placed in
series with VIN as shown in Figure 18.
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
R
R
V
K = OUT
VIN
(2)
VVin
IN
+
–
SAC™
SAC
= 1/32
1/32
KK =
Vout
V
OUT
In the presence of load, VOUT is represented by:
VOUT = VIN • K – IOUT • ROUT
(3)
The relationship between VIN and VOUT becomes:
and IOUT is represented by:
IOUT =
IIN – IQ
K
Figure 18 — K = 1/32 Sine Amplitude Converter™
with series input resistor
(4)
ROUT represents the impedance of the SAC, and is a function of
the RDSON of the input and output MOSFETs and the winding
resistance of the power transformer. IQ represents the
quiescent current of the SAC control and gate drive circuitry.
The use of DC voltage transformation provides additional
interesting attributes. Assuming for the moment that
VOUT = (VIN – IIN • R) • K
(5)
Substituting the simplified version of Eq. (4)
(IQ is assumed = 0 A) into Eq. (5) yields:
VOUT = VIN • K – IOUT • R • K2
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
(6)
Rev. 2.1
6/2012
Page 11 of 16
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This is similar in form to Eq. (3), where ROUT is used to
represent the characteristic impedance of the SAC™. However,
in this case a real R on the input side of the SAC is effectively
scaled by K2 with respect to the output.
Assuming that R = 1 Ω, the effective R as seen from the secondary
side is 0.98 mΩ, with K = 1/32 as shown in Figure 18.
A similar exercise should be performed with the additon of a
capacitor, or shunt impedance, at the input to the SAC. A
switch in series with VIN is added to the circuit. This is depicted
in Figure 19.
S
VVin
IN
+
–
C
SAC™
SAC
K = 1/32
K = 1/32
VVout
OUT
Figure 19 — Sine Amplitude Converter™ with input capacitor
A change in VIN with the switch closed would result in a
change in capacitor current according to the following
equation:
IC(t) = C
dVIN
dt
Low impedance is a key requirement for powering a highcurrent, low-voltage load efficiently. A switching regulation
stage should have minimal impedance, while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit, scaling down series impedance
leading back to the source and scaling up shunt capacitance
(or energy storage) as a function of its K factor squared.
However, these benefits are not useful if the series impedance
of the SAC is too high. The impedance of the SAC must be low
well beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables magnetic
components to be small since magnetizing currents remain
low. Small magnetics mean small path lengths for turns. Use of
low loss core material at high frequencies reduces core losses
as well.
The two main terms of power loss in the VTM™ module are:
- No load power dissipation (PNL ): defined as the power
used to power up the module with an enabled power
train at no load.
- Resistive loss (ROUT): refers to the power loss across the
VTM current multiplier modeled as pure resistive impedance.
PDISSIPATED = PNL + PROUT
(7)
(10)
Therefore,
POUT = PIN – PDISSIPATED = PIN – PNL – PROUT
Assume that with the capacitor charged to VIN, the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
IC = IOUT • K
(11)
The above relations can be combined to calculate the overall
module efficiency:
(8)
η =
(9)
=
POUT = PIN – PNL – PROUT
PIN
PIN
(12)
Substituting Eq. (1) and (8) into Eq. (7) reveals:
IOUT =
C
K2
•
dVOUT
dt
Writing the equation in terms of the output has yielded a K2
scaling factor for C, this time in the denominator of the
equation. For a K factor less than unity, this results in an
effectively larger capacitance on the output when expressed in
terms of the input. With a K=1/32 as shown in Figure 19,
C=1 µF would effectively appear as C=1024 µF when viewed
from the output.
VIN • IIN – PNL – (IOUT)2 • ROUT
VIN • IIN
= 1–
(
)
PNL + (IOUT)2 • ROUT
VIN • IIN
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 12 of 16
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12.0 INPUT AND OUTPUT FILTER DESIGN
A major advantage of a SAC™ system versus a conventional
PWM converter is that the former does not require large
functional filters. The resonant LC tank, operated at extreme
high frequency, is amplitude modulated as a function of input
voltage and output current and efficiently transfers charge
through the isolation transformer. A small amount of
capacitance embedded in the input and output stages of the
module is sufficient for full functionality and is key to achieving
high power density.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
1.Guarantee low source impedance.
To take full advantage of the VTM™ module dynamic
response, the impedance presented to its input terminals
must be low from DC to approximately 5 MHz. Input
capacitance may be added to improve transient
performance or compensate for high source impedance.
2.Further reduce input and /or output voltage ripple without
sacrificing dynamic response.
Given the wide bandwidth of the VTM module, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the output of the module multiplied by its
K factor.
3.Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
cause failures.
The VI Chip® module input/output voltage ranges must
not be exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating input
range. Even during this condition, the powertrain is
exposed to the applied voltage and power MOSFETs must
withstand it.
13.0 CAPACITIVE FILTERING CONSIDERATIONS
FOR A SINE AMPLITUDE CONVERTER
It is important to consider the impact of adding input and
output capacitance to a Sine Amplitude Converter™ on the
system as a whole. Both the capacitance value, and the
effective impedance of the capacitor must be considered.
A Sine Amplitude Converter has a DC ROUT value which has
already been discussed in section 11. The AC ROUT of the SAC
contains several terms:
• Resonant tank impedance
• Input lead inductance and internal capacitance
• Output lead inductance and internal capacitance
The values of these terms are shown in the behavioral model in
section 11. It is important to note on which side of the
transformer these impedances appear and how they reflect
across the transformer given the K factor.
The overall AC impedance varies from model to model but for
most models it is dominated by DC ROUT value from DC to
beyond 500 KHz. The behavioral model in section 11 should be
used to approximate the AC impedance of the specific model.
Any capacitors placed at the output of the VTM module reflect
back to the input of the module by the square of the K factor
(Eq. 9) with the impedance of the module appearing in series.
It is very important to keep this in mind when using a PRM™
regulator to power the VTM™. Most PRM regulators have a
limit on the maximum amount of capacitance that can be
applied to the output. This capacitance includes both the
regulator output capacitance and the current multiplier output
capacitance reflected back to the input. In PRM regulator remote
sense applications, it is important to consider the reflected value
of VTM current multiplier output capacitance when designing
and compensating the PRM regulator control loop.
Capacitance placed at the input of the VTM module appear to
the load reflected by the K factor, with the impedance of the
VTM module in series. In step-down VTM ratios, the effective
capacitance is increased by the K factor. The effective ESR of
the capacitor is decreased by the square of the K factor, but
the impedance of the VTM module appears in series. Still, in
most step-down VTM modules an electrolytic capacitor placed
at the input of the module will have a lower effective
impedance compared to an electrolytic capacitor placed at the
output. This is important to consider when placing capacitors
at the output of the current multiplier. Even though the
capacitor may be placed at the output, the majority of the AC
current will be sourced from the lower impedance, which in
most cases will be the VTM current multiplier. This should be
studied carefully in any system design using a VTM current
multiplier. In most cases, it should be clear that electrolytic
output capacitors are not necessary to design a stable, wellbypassed system.
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 13 of 16
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VTM48EH020 x 040A00
14.0 CURRENT SHARING
The SAC™ topology bases its performance on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with some resistive drop
and positive temperature coefficient.
This type of characteristic is close to the impedance
characteristic of a DC power distribution system, both in
behavior (AC dynamic) and absolute value (DC dynamic).
When connected in an array with the same K factor, the
VTM™ module will inherently share the load current with
parallel units, according to the equivalent impedance divider
that the system implements from the power source to the
point of load.
Some general recommendations to achieve matched array
impedances:
• Dedicate common copper planes within the PCB
to deliver and return the current to the modules.
• Provide the PCB layout as symmetric as possible.
• Apply same input / output filters (if present) to each unit.
16.0 REVERSE OPERATION
The VTM48EH020T040A00 is capable of reverse operation.
If a voltage is present at the output which satisfies the
condition VOUT > VIN • K at the time the VC voltage is applied,
or after the unit has started, then energy will be transferred
from secondary to primary. The input to output ratio will be
maintained. The VTM48EH020T040A00 will continue to
operate in reverse as long as the input and output are within
the specified limits. The VTM48EH020T040A00 has not been
qualified for continuous operation (>10 ms) in the reverse
direction.
For further details see AN:016 Using BCM™ Bus Converters
in High Power Arrays.
VIN
ZIN_EQ1
VTM™1
ZOUT_EQ1
VOUT
RO_1
ZIN_EQ2
VTM™2
ZOUT_EQ2
RO_2
+
–
DC
Load
ZIN_EQn
VTM™n
ZOUT_EQn
RO_n
Figure 20 — VTM™ module array
15.0 FUSE SELECTION
In order to provide flexibility in configuring power systems
VI Chip® products are not internally fused. Input line fusing of
VI Chip® products is recommended at system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
• Current rating (usually greater than maximum
VTM module current)
• Maximum voltage rating (usually greater than the maximum
possible input voltage)
• Ambient temperature
• Nominal melting I2t
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 14 of 16
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VTM48EH020 x 040A00
17.1 MECHANICAL DRAWING
mm
(inch)
NOTES:
mm
2. DIMENSIONS ARE inch .
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
4. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
17.2 RECOMMENDED LAND PATTERN
4
3
2
1
A
+Out
+In
B
C
D
E
F
G
H
J
K
-Out
L
M
IM
TM
VC
PC
-In
Bottom View
NOTES:
3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
mm
2. DIMENSIONS ARE inch .
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
4. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
Signal
Name
Designation
+In
–In
IM
TM
VC
PC
+Out
–Out
A1-B1, A2-B2
L1-M1, L2-M2
E1
F2
G1
H2
A3-D3, A4-D4
J3-M3, J4-M4
17.3 RECOMMENDED HEAT SINK PUSH PIN LOCATION
Notes:
1. Maintain 3.50 (0.138) Dia. keep-out zone
free of copper, all PCB layers.
2. (A) minimum recommended pitch is 24.00 (0.945)
this provides 7.50 (0.295) component
edge–to–edge spacing, and 0.50 (0.020)
clearance between Vicor heat sinks.
(B) Minimum recommended pitch is 25.50 (1.004).
This provides 9.00 (0.354) component
edge–to–edge spacing, and 2.00 (0.079)
clearance between Vicor heat sinks.
3. V•I Chip™ module land pattern shown
for reference only, actual land pattern may differ.
Dimensions from edges of land pattern
to push–pin holes will be the same for
all half size V•I Chip Products.
4. RoHS compliant per CST–0001 latest revision.
5. Unless otherwise specified:
Dimensions are mm (inches)
tolerances are:
x.x (x.xx) = ±0.13 (0.01)
x.xx (x.xxx) = ±0.13 (0.005)
6. Plated through holes for grounding clips (33855)
shown for reference. Heat sink orientation and
device pitch will dictate final grounding solution.
(NO GROUNDING CLIPS)
(WITH GROUNDING CLIPS)
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 15 of 16
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VTM48EH020 x 040A00
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power
systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes
to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to
be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the extent
Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of each
product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the “Express
Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment and is not
transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS ALL
REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT TO
THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR PARTICULAR
PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable for
collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no
liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating
safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to
obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the
buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective
within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR
WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support devices or
systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly
used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical
component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products and components in life
support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products
described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this
document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263;
7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: [email protected]
Technical Support: [email protected]
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 2.1
6/2012
Page 16 of 16
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