FREESCALE MC68HC16Y1

MOTOROLA
Freescale Semiconductor, Inc.
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by MC68HC16Y1TS/D Rev. 1
SEMICONDUCTOR
TECHNICAL DATA
MC68HC16Y1
Technical Summary
16-Bit Modular Microcontroller
1 Introduction
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The MC68HC16Y1 is a high-speed 16-bit control unit that is upwardly code compatible with M68HC11
controllers. It is a member of the M68300/68HC16 Family of modular microcontrollers.
M68HC16 controllers are built up from standard modules that interface via a common internal bus.
Standardization facilitates rapid development of devices tailored for specific applications.
The MC68HC16Y1 incorporates a true 16-bit CPU (CPU16), a single-chip integration module (SCIM),
an 8/10-bit analog-to-digital converter (ADC), a multichannel communication interface (MCCI), a general-purpose timer (GPT), a time processing unit (TPU), a 2 Kbyte standby RAM module with TPU ROM
emulation capability (TPURAM), and a 48 Kbyte masked ROM module (MRM). These modules are interconnected by the Motorola intermodule bus (IMB).
The MC68HC16Y1 can either synthesize an internal clock signal from an external reference, or use an
external clock input directly. Operation with a 32.768 kHz reference frequency is standard, but operation
with a 4.0 MHz reference is available as an option — contact your Motorola representative for more information. System hardware and software allow changes in clock rate during operation. Because the
MC68HC16Y1 is a fully static design, register and memory contents are not affected by clock rate
changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MC68HC16Y1 low. Power consumption can be minimized by stopping the system
clock. The M68HC16 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability.
Table 1 Ordering Information
Package Type
Frequency (MHz)
Temperature
Order Number
Plastic Surface Mount
FC Suffix
16.78
–40° to +85°C
M68HC16Y1CFC
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1992, 1996 For More Information On This Product,
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TABLESemiconductor,
OF CONTENTS Inc.
Section
1
1.1
1.2
1.3
1.4
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
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3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
4
4.1
4.2
5
5.1
5.2
5.3
6
6.1
6.2
6.3
6.4
6.5
7
7.1
7.2
7.3
8
8.1
8.2
8.3
9
9.1
10
Page
Introduction
1
Features ......................................................................................................................................3
Pin Description ............................................................................................................................6
Address Map ...............................................................................................................................8
Intermodule Bus ..........................................................................................................................8
CPU16
9
Overview .....................................................................................................................................9
M68HC11 Compatibility ...............................................................................................................9
Programmer's Model .................................................................................................................10
Condition Code Register ...........................................................................................................11
Data Types ................................................................................................................................12
Addressing Modes .....................................................................................................................12
Instruction Set ...........................................................................................................................13
Single-Chip Integration Module
32
System Configuration ................................................................................................................34
Operating Modes .......................................................................................................................36
Emulation Support .....................................................................................................................40
System Clock ............................................................................................................................43
External Bus Interface ...............................................................................................................47
Reset .........................................................................................................................................51
Interrupts ...................................................................................................................................53
General-Purpose Input/Output ..................................................................................................55
Chip Selects ..............................................................................................................................60
Emulation Mode Chip Select Signals ........................................................................................62
Factory Test ..............................................................................................................................68
Time Processor Unit
69
TPU ROM Functions .................................................................................................................70
TPU Registers ...........................................................................................................................71
General-Purpose Timer Module
80
Compare/Capture Unit .............................................................................................................81
Pulse-Width Modulator ..............................................................................................................83
GPT Registers ...........................................................................................................................85
Analog-to-Digital Converter Module
92
ADC Operation ..........................................................................................................................93
Analog Subsystem ....................................................................................................................93
Digital Control Subsystem .........................................................................................................94
Bus Interface Subsystem ..........................................................................................................94
ADC Registers ...........................................................................................................................94
Multichannel Communication Interface
100
MCCI Registers .......................................................................................................................101
Serial Peripheral Interface .......................................................................................................104
Serial Communication Interface ..............................................................................................107
Standby RAM with TPU Emulation
113
TPURAM Register Block .........................................................................................................113
TPURAM Registers .................................................................................................................113
TPURAM Operation ................................................................................................................114
Masked ROM Module
116
Masked ROM Control Registers ..............................................................................................117
Summary of Changes
120
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MC68HC16Y1
MC68HC16Y1TS/D
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1.1 Features
• CPU16
— 16-Bit Architecture
— Full Set of 16-Bit Instructions
— Three 16-Bit Index Registers
— Two 16-Bit Accumulators
— Control-Oriented Digital Signal Processing Capability
— 1 Megabyte of Program Memory and 1 Megabyte of Data Memory
— High-Level Language Support
— Fast Interrupt Response Time
— Background Debugging Mode
• Single-Chip Integration Module
— Single-Chip or Expanded Modes of Operation
— External Bus Support in Expanded Mode
— Nine Programmable Chip Select Outputs
— System Protection Logic
— Watchdog Timer, Clock Monitor, and Bus Monitor
— Parallel Ports Option On Address and Data Bus in Single-Chip Mode
— PLL Clock System
• Time Processor Unit
— Dedicated Microengine Operating Independently of CPU16
— 16 Independently Programmable Channels and Pins
— Two Timer Count Registers with Programmable Prescalers
— Selectable Channel Priority Levels
• General-Purpose Timer
— Two 16-Bit Free-Running Counters with Prescaler
— Three Input Capture Channels
— Four Output Compare Channels
— One Input Capture/Output Compare Channel
— One Pulse Accumulator/Event Counter Input
— Two Pulse Width Modulation Outputs
— Optional External Clock Input
• 8/10-Bit Analog-to-Digital Converter
— Eight Channels, Eight Result Registers
— Eight Automated Modes
— Three Result Alignment Modes
• Multichannel Communication Interface
— Dual Serial Communication Interface
— Serial Peripheral Interface
• TPU Emulation RAM
— 2 Kbyte Static RAM
— External Standby Voltage Supply Input
• Masked ROM
— 48 Kbyte 16-Bit Array
— User-Selectable Default Base Address
— User-Selectable Bootstrap ROM Function
— User-Selectable ROM Verification Code
MC68HC16Y1
MC68HC16Y1TS/D
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TP[15:0]
T2CLK
48
KBYTES
ROM
ADDR[23:19]
IC4/OC5/OC1
OC4/OC1
OC3/OC1
OC2/OC1
OC1
IC3
IC2
IC1
TPU
ADDR[23:0]
ADDR[2:0]
SIZ1
SIZ0
AS
DS
PE3
AVEC
DSACK1
DSACK0
PWMA
PWMB
PCLK
IMB
DATA[15:0]
PORT AD
CONTROL
PADA7/AN7
PADA6/AN6
PADA5/AN5
PADA4/AN4
PADA3/AN3
PADA2/AN2
PADA1/AN1
PADA0/AN0
ADC
CPU16
IRQ[7:1]
CONTROL
PORT F
VRH
VRL
2
KBYTES
SRAM
CONTROL
PORT E
EBI
CONTROL
PORT G/H
PORT GP
CONTROL
PWMA
PWMB
PCLK
VSTBY
VSTBY
BKPT
IPIPE1
IPIPE0
DSI
DSO
DSCLK
VDDA
VSSA
MODCLK
BKPT/DSCLK
IPIPE1/DSI
IPIPE0/DSO
TSC
TEST
QUOT
FREEZE
CONTROL
CLOCK
CONTROL
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PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
MCCI
PAI
CONTROL
PORT A/B
FC2
FC1
FC0
GPT
PAI
CONTROL
PORT C
CHIP
SELECTS BR
BG
BGACK
CS
TXDA
RXDA
TXDB
RXDB
SS
SCK
MOSI
MISO
PORT MC
CONTROL
PMC7/TXDA
PMC6/RXDA
PMC5/TXDB
PMC4/RXDB
PMC3/SS
PMC2/SCK
PMC1/MOSI
PMC0/MISO
CSBOOT
BR/CS0
BG/CSM
BGACK/CSE
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1
PC0/FC0/CS3
PA[7:0]/ADDR[18:11]
PB[7:0]/ADDR[10:3]
ADDR[2:0]
PE7/SIZ1
PE6/SIZ0
PE5/AS
PE4/DS
PE3
PE2/AVEC
PE1/DSACK1
PE0/DSACK0
PG[7:0]/DATA[15:8]
PH[7:0]/DATA[7:0]
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
XFC
VDDSYN
TSC
FREEZE/QUOT
Y1 BLOCK
Figure 1 MC68HC16Y1 Block Diagram
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MC68HC16Y1
MC68HC16Y1TS/D
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
MC68HC16Y1
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
1
VRH
AN5
AN4
AN3
AN2
AN1
AN0
VSSA
VDDA
VDDE
VSSE
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
VSSI
ADDR10
ADDR11
ADDR12
ADDR13
VDDE
VSSE
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
SS
MOSI
MISO
SCK
TXDA
RXDA
TXDB
VDDE
40
120
VDDE
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
VDDE
VSSE
DATA11
DATA12
DATA13
DATA14
DATA15
VSSI
ADDR0
DSACK0
DSACK1
AVEC
PE3
VDDE
VSSE
DS
AS
SIZ0
SIZ1
R/W
MODCLK
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
81
41
VSSE
RXDB
CHAN0
CHAN1
CHAN2
CHAN3
VDDE
VSSE
CHAN4
CHAN5
CHAN6
CHAN7
CHAN8
CHAN9
CHAN10
CHAN11
VDDE
VSSE
CHAN12
CHAN13
CHAN14
CHAN15
T2CLK
NC
VSTBY
XTAL
VDDSYN
EXTAL
VSSI
VDDI
XFC
VDDE
VSSE
CLKOUT
VSSE
RESET
HALT
BERR
FREEZE/QUOT
TSC
80
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160
VRL
AN6
AN7
VDDE
VSSE
IC1
IC2
IC3
OC1
OC2
OC3
OC4
IC4/OC5
PAI
PWMA
PWMB
PCLK
VDDE
VSSE
IPIPE0/DSO
IPIPE1/DSI
BKPT/DSCLK
NC
VSSI
VDDI
ADDR23/CS10
ADDR22/CS9
ADDR21/CS8
ADDR20/CS7
ADDR19/CS6
VDDE
VSSE
FC2/CS5
FC1
FC0/CS3
BGACK/CSE
BG/CSM
BR/CS0
CSBOOT
VSSE
121
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Y1 160-PIN QFP
Figure 2 MC68HC16Y1 160-Pin QFP Pinout
MC68HC16Y1
MC68HC16Y1TS/D
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1.2 Pin Description
The table below describes MC68HC16Y1 pin characteristics. All inputs detect CMOS logic levels. All
outputs can be put in a high-impedance state, but the method of doing so differs depending upon pin
function. Refer to Table 3 for a description of output drivers. An entry in the Discrete I/O column of Table
2 indicates that a pin has an alternate I/O function — port designation is given when it applies. Refer to
Figure 1 for port organization.
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Table 2 MC68HC16Y1 Pin Characteristics
Pin
Mnemonic
ADDR23/CS10/ECLK
ADDR[22:19]/CS[9:6]
ADDR[18:11]
ADDR[10:3]
ADDR[2:0]
AN[7:0]1
AS
AVEC
BERR
BG/CSM
BGACK/CSE
BKPT/DSCLK
BR/CS0
CLKOUT
CSBOOT
DATA[15:8]1
DATA[7:0]1
DS
DSACK1
DSACK0
DSI/IPIPE1
DSO/IPIPE0
EXTAL2
FC2/CS5
FC1
FC0/CS3
FREEZE/QUOT
HALT
IC4/OC5
IC[3:1]
IRQ[7:1]
MISO
MODCLK1
MOSI
OC[4:1]
PAI3
PCLK3
SS
PE3
MOTOROLA
6
Output
Driver
A
A
A
A
A
—
Input
Synchronized
Y
Y
Y
Y
Y
Y
Input
Hysteresis
N
N
Y
Y
N
Y
Discrete
I/O
—
O
I/O
I/O
—
I
Port
Designation
—
C[6:3]
A[7:0]
B[7:0]
—
ADA[7:0]
B
B
B
B
B
—
B
A
B
AW
Y
Y
Y
—
Y
Y
Y
—
—
Y
Y
N
N
—
N
Y
N
—
—
Y
I/O
I/O
—
—
—
—
—
—
—
I/O
E5
E2
—
—
—
—
—
—
—
G[7:0]
AW
Y
Y
I/O
H[7:0]
B
B
B
A
A
—
Y
Y
Y
Y
—
—
Y
N
N
Y
—
—
I/O
I/O
I/O
—
—
—
E4
E1
E0
—
—
—
A
A
A
A
Bo
A
A
B
Bo
B
Y
Y
Y
—
Y
Y
Y
Y
Y
Y
N
N
N
—
N
Y
Y
Y
Y
Y
O
O
O
—
—
I/O
I/O
I/O
I/O
I/O
C0
C1
C2
—
—
GP7
GP[2:0]
F[7:1]
MC0
F0
Bo
A
—
Y
Y
Y
Y
Y
Y
I/O
I/O
I
MC1
GP[6:3]
—
—
Y
Y
I
—
Bo
B
Y
Y
Y
Y
I/O
I/O
MC3
E3
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Table 2 MC68HC16Y1 Pin Characteristics (Continued)
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Pin
Mnemonic
Output
Driver
A
Input
Synchronized
Y
Input
Hysteresis
Y
Discrete
I/O
O
Port
Designation
—
VRH5
A
Bo
Bo
Bo
Bo
B
—
A
—
Bo
Bo
—
Y
Y
Y
Y
Y*
Y
Y
Y
Y
Y
Y
—
N
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
—
—
—
I/O
I/O
I/O
I/O
—
—
—
I/O
I/O
—
—
—
MC6
MC4
MC2
E[7:6]
—
—
—
MC7
MC5
—
VRL5
—
—
—
—
—
XFC2
—
—
—
—
—
XTAL2
—
—
—
—
—
PWMA, PWMB4
R/W
RESET
RXDA
RXDB
SCK
SIZ[1:0]
TSC
TPUCH[15:0]
T2CLK
TXDA
TXDB
NOTES
1. DATA[15:0] are synchronized during reset only. MODCLK, MCCI and ADC pins are
synchronized only when used as input port pins.
2. EXTAL, XFC, and XTAL are clock reference connections.
3. PAI and PCLK can be used for discrete input, but are not part of an I/O port.
4. PWMA and PWMB can be used for discrete output, but are not part of an I/O port.
5. VRH and VRLare ADC reference voltage inputs.
Table 3 MC68HC16Y1 Driver Types
Type
A
Aw
B1
I/O
O
O
O
Bo
O
Description
Output-only signals that are always driven. No external pull-up required.
Type A output with weak P-channel pull-up during reset.
Three-state output that includes circuitry to pull up output before high impedance is established, to insure rapid rise time. An external holding resistor is required to
maintain logic level while in the high-impedance state.
Type B output that can be operated in an open-drain mode.
1. Pins with this type of driver may only go into high-impedance state under certain conditions. The TSC signal
can put all pins with this type of driver in high-impedance state.
Table 4 MC68HC16Y1 Power Connections
VDDA/VSSA
VDDSYN
MC68HC16Y1
MC68HC16Y1TS/D
A/D Converter Power
Clock Synthesizer Power
VSSE/VDDE
External Peripheral Power (Source and Drain)
VSTBY
Standby RAM Power/Clock Synthesizer Power
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1.3 Address Map
The internal address map of the MC68HC16Y1 is shown below. Although there are 24 intermodule bus
(IMB) address lines, the CPU16 uses only ADDR[19:0]. ADDR[23:20] follow the logic state of ADDR19
— addresses $080000 to $F7FFFF are not accessible. The RAM array is positioned by the base address register in the RAM CTRL block. Reset disables the RAM array. Unimplemented blocks are
mapped externally.
$YFF700
$YFF73F
ADC
64 BYTES
$YFF820
$YFF83F
ROM CTRL
32 BYTES
$YFF900
GPT
64 BYTES
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$YFF93F
2K SRAM ARRAY
(MAPPED TO 2K BOUNDARY)
$YFFA00
SCIM
128 BYTES
$YFFA7F
$YFFB00
$YFFB3F
$YFFC00
$YFFC3F
SRAM CTRL
64 BYTES
MCCI
64 BYTES
$YFFE00
TPU
512 BYTES
48K ROM ARRAY
(MAPPED TO ANY 64K BOUNDARY)
$YFFFFF
"Y1 MEMORY MAP"
Figure 3 MC68HC16Y1 Address Map
In the address map, Y = M111, where M is the modmap signal state on the IMB. M reflects the state of
the modmap bit in the module configuration register of the single-chip integration module. In the
MC68HC16Y1, Y must equal $F — if M is cleared, IMB modules will be inaccessible until a reset occurs.
M can be written only once after reset.
1.4 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate design of modular microcontrollers. It contains circuitry to support exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MC68HC16Y1 communicate with
one another and with external components via the IMB. Although the full IMB supports 24 address and
16 data lines, the MC68HC16Y1 uses only 16 data lines and 20 address lines. Because the CPU16
uses only 20 address lines, ADDR[23:20] are tied to ADDR19 when processor driven. ADDR[23:20] are
brought out to pins for test purposes.
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MC68HC16Y1TS/D
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2 CPU16
The CPU16 is a true 16-bit, high-speed device. It was designed to give M68HC11 users a path to higher
performance while maintaining maximum compatibility with existing systems.
2.1 Overview
Ease of programming is an important consideration in using a microcontroller. The CPU16 instruction
set is optimized for high performance. There are two 16-bit general-purpose accumulators and three
16-bit index registers. The CPU16 supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load and
store operations, as well as 16- and 32-bit signed fractional operations. Program diagnosis is enhanced
by a background debugging mode.
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CPU16 memory space includes a 1 Mbyte data space and a 1 Mbyte program space. Twenty-bit addressing and transparent bank switching are used to implement extended memory. In addition, most
instructions automatically handle bank boundaries.
The CPU16 includes instructions and hardware to implement control-oriented digital signal processing
functions with a minimum of interfacing. A multiply and accumulate unit provides the capability to multiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accumulator. Modulo addressing supports finite impulse response filters.
Use of high-level languages is increasing as controller applications become more complex and control
programs become larger. High-level languages aid rapid development of software, with less error, and
are readily portable. The CPU16 instruction set supports high-level languages.
2.2 M68HC11 Compatibility
CPU16 architecture is a superset of M68HC11 architecture. All M68HC11 resources are available in
the HC16. M68HC11 instructions are either directly implemented in the M68HC16, or have been replaced by instructions with an equivalent form — the instruction sets are source code compatible. Some
instructions are executed differently in the M68HC16. These instructions are mainly related to interrupt
and exception processing — M68HC11 code that processes interrupts, handles stack frames, or manipulates the condition code register must be rewritten.
Execution times and number of cycles for all instructions are different, so that cycle-related delays and
timed control routines may be affected.
The CPU16 also has several new or enhanced addressing modes. M68HC11 direct mode addressing
has been replaced by a special form of indexed addressing that uses the new IZ register and a reset
vector to provide greater flexibility.
MC68HC16Y1
MC68HC16Y1TS/D
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2.3 Programmer's Model
20
16 15
8 7
0
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A
D
B
ACCUMULATORS A AND B
ACCUMULATOR D (A : B)
E
ACCUMULATOR E
XK
IX
INDEX REGISTER X
YK
IY
INDEX REGISTER Y
ZK
IZ
INDEX REGISTER Z
SK
SP
STACK POINTER
PK
PC
PROGRAM COUNTER
CCR
EK
XK
YK
PK
CONDITION CODE REGISTER
PC EXTENSION REGISTER
ZK
SK
ADDRESS EXTENSION REGISTER
STACK EXTENSION REGISTER
H
MAC MULTIPLIER REGISTER
I
MAC MULTIPLICAND REGISTER
35
16
AM (MSB)
AM (LSB)
XMSK
MAC ACCUMULATORMSB [35:16]
MAC ACCUMULATOR LSB [15:0]
YMSK
MAC XY MASK REGISTER
Accumulator A — 8-bit general-purpose register
Accumulator B — 8-bit general-purpose register
Accumulator D — 16-bit register formed by concatenating accumulators A and B
Accumulator E — 16-bit general-purpose register
Accumulator M — 36-bit MAC result register
Index Register X — 16-bit indexing register, addressing extended by XK field in K register
Index Register Y — 16-bit indexing register, addressing extended by YK field in K register
Index Register Z — 16-bit indexing register, addressing extended by ZK field in K register
Stack Pointer — 16-bit dedicated register, addressing extended by the SK register
Program Counter — 16-bit dedicated register, addressing extended by PK field in CCR
Condition Code Register — 16-bit register containing condition flags, interrupt priority mask, and the program
counter address extension field
K Register — 16-bit register made up of four 4-bit address extension fields
SK Register — 4-bit register containing the stack pointer address extension field
H Register — 16-bit multiply and accumulate input (multiplier) register
I Register — 16-bit multiply and accumulate input (multiplicand) register
XMSK, YMSK — Determine which bits change when an offset is added
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MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
2.4 Condition Code Register
15
14
13
12
11
10
9
8
S
MV
H
EV
N
Z
V
C
7
6
INT
5
4
3
SM
2
1
0
PK
The condition code register can be considered as two functional blocks. The MSB, which corresponds
to the CCR in the M68HC11, contains the low-power stop control bit and processor status flags. The
LSB contains the interrupt priority field, the DSP saturation mode control bit, and the program counter
address extension field.
S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed.
1 = Perform NOP when LPSTOP instruction is executed.
Freescale Semiconductor, Inc...
MV — Accumulator M overflow flag
Set when overflow into the accumulator M sign bit (AM35) has occurred.
H — Half Carry Flag
Set when a carry from bit 3 in accumulators A or B occurs during BCD addition.
EV — Extension Bit Overflow Flag
Set when an overflow into bit 31 of accumulator M has occurred.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when twos complement overflow occurs as the result of an operation.
C — Carry Flag
Set when a carry or borrow occurs during arithmetic operation. Also used during shift and rotate operations to facilitate multiple word operations.
INT[2:0] — Interrupt Priority Mask
The value of this field ($0 to $7) specifies the CPU16 interrupt priority level.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from accumulator M using TMRT or TMET will be
given maximum positive or negative value, depending on the state of the AM sign bit before overflow.
PK[3:0] — Program Counter Address Extension Field
This field is concatenated with the program counter to form a 20-bit pseudolinear address.
MC68HC16Y1
MC68HC16Y1TS/D
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2.5 Data Types
The CPU16 supports the following data types:
— Bit data
— 8-bit (byte) and 16-bit (word) integers
— 32-bit long integers
— 16-bit and 32-bit signed fractions (MAC operations only)
— 20-bit effective address consisting of 16-bit page address plus 4-bit extension
A byte is 8 bits wide and can be accessed at any byte location. A word is composed of two consecutive
bytes, and is addressed at the lower byte. Instruction fetches are always accessed on word boundaries.
Word operands are normally accessed on word boundaries as well, but may be accessed on odd byte
boundaries, with a substantial performance penalty.
Freescale Semiconductor, Inc...
To be compatible with the M68HC11, misaligned word transfers and misaligned stack accesses are allowed. Transferring a misaligned word requires two successive byte operations.
2.6 Addressing Modes
The CPU16 provides 10 types of addressing. Each type encompasses one or more addressing modes.
Six CPU16 addressing types are identical to M68HC11 addressing types.
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an extension field
to form a 20-bit effective address. Extension fields are part of a bank switching scheme that provides
the CPU16 with a 1 Mbyte address space. Bank switching is transparent to most instructions — ADDR[19:16] of the effective address change when an access crosses a bank boundary. However, it is
important to note that the value of the associated extension field is dependent on the type of instruction,
and generally does not change when this occurs.
In the immediate modes, the instruction argument is contained in bytes or words immediately following
the instruction. The effective address is the address of the byte following the instruction. The AIS, AIX/
Y/Z, ADDD and ADDE instructions have an extended 8-bit mode where the immediate value is an 8-bit
signed number that is sign-extended to 16 bits, then added to the appropriate register — this decreases
execution time.
Extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective address is formed by concatenating EK and the 16-bit extension.
In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used
to calculate the effective address. Signed 16-bit mode and signed 20-bit mode are extensions to the
M68HC11 indexed addressing mode.
For 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in the index register and its associated extension field.
For 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained
in the index register and its associated extension field.
For 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. This
mode is used for JMP and JSR instructions.
Inherent mode instructions use information available to the processor to determine the effective address. Operands (if any) are system resources and are thus not fetched from memory.
Accumulator offset mode adds the contents of 16-bit accumulator E to one of the index registers and its
associated extension field to form the effective address. This mode allows use of index registers and
an accumulator within loops without corrupting accumulator D.
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Freescale Semiconductor, Inc.
Relative modes are used for branch and long branch instructions. A byte or word signed twos complement offset is added to the program counter if the branch condition is satisfied. The new PC value, concatenated with the PK field, is the effective address.
Post-modified index mode is used with the MOVB and MOVW instructions. A signed 8-bit offset is added to index register X after the effective address formed by XK and IX is used.
In M68HC11 systems, direct mode can be used to perform rapid accesses to RAM or I/O mapped into
page 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of page 0 for exception vectors. To
compensate for the loss of direct mode, the ZK field and index register Z have been assigned reset initialization vectors — by resetting the ZK field to a chosen page, and using 8-bit unsigned index mode
with IZ, a programmer can access useful data structures anywhere in the address map.
Freescale Semiconductor, Inc...
2.7 Instruction Set
The CPU16 has an 8-bit instruction set. It uses a prebyte to support a multipage opcode map. This arrangement makes it possible to fetch an 8-bit operand simultaneously with a page 0 opcode. If a program makes maximum use of 8-bit offset indexed addressing mode, it will have a significantly smaller
instruction space.
The instruction set is based upon that of the M68HC11, but the opcode map has been rearranged to
maximize performance with a 16-bit data bus. All M68HC11 instructions are supported by the CPU16,
although they may be executed differently. Most M68HC11 code will run on the CPU16 following reassembly. The user must take into account changed instruction times, the interrupt mask, and the new
interrupt stack frame.
The CPU16 has a full range of 16-bit arithmetic and logic instructions, including signed and unsigned
multiplication and division. New instructions have been added to support extended addressing and digital signal processing.
The following table is a summary of the CPU16 instruction set. Because it is only affected by a few instructions, the LSB of the condition code register is not shown in the table — instructions which affect
the interrupt mask and PK field are noted.
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MC68HC16Y1TS/D
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Table 5 Instruction Set Summary
Mnemonic
Description
ADCA
Add B to A
(A ) + (B) ⇒ A
Add B to X
(XK : IX) + (000 : B) ⇒ XK : IX
Add B to Y
(YK : IY) + (000 : B) ⇒ YK : IY
Add B to Z
(ZK : IZ) + (000 : B) ⇒ ZK : IZ
Add E to AM[31:15]
(AM[31:15]) + (E) ⇒ AM
Add concatenated
(E : D) + (AM) ⇒ AM
E and D to AM
Add with Carry to A
(A) + (M) + C ⇒ A
ADCB
Add with Carry to B
(B) + (M) + C ⇒ B
ADCD
Add with Carry to D
(D) + (M : M + 1) + C ⇒ D
ADCE
Add with Carry to E
(E) + (M : M + 1) + C ⇒ E
ADDA
Add to A
(A) + (M) ⇒ A
ABA
ABX
ABY
ABZ
ACE
ACED
Freescale Semiconductor, Inc...
Operation
MOTOROLA
14
Address
Instruction
Condition Codes
Mode
INH
INH
INH
INH
INH
INH
Opcode
370B
374F
375F
376F
3722
3723
Operand
—
—
—
—
—
—
Cycles
2
2
2
2
2
4
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
43
53
63
73
1743
1753
1763
1773
2743
2753
2763
C3
D3
E3
F3
27C3
27D3
27E3
17C3
17D3
17E3
17F3
83
93
A3
2783
2793
27A3
37B3
37C3
37D3
37E3
37F3
3733
3743
3753
3763
3773
41
51
61
71
2741
2751
2761
1741
1751
1761
1771
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
—
—
—
gggg
gggg
gggg
hh ll
ff
ff
ff
—
—
—
jj kk
gggg
gggg
gggg
hh ll
jj kk
gggg
gggg
gggg
hh ll
ff
ff
ff
ii
—
—
—
gggg
gggg
gggg
hh ll
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
4
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
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S
—
—
—
—
—
—
MV
—
—
—
—
V
C
— ∆ ∆ ∆
— — — —
— — — —
— — — —
— ∆ — — —
— ∆ — — —
∆
—
—
—
—
—
— —
∆
—
∆
∆
∆
∆
— —
∆
—
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
— —
H EV N
Z
∆
—
—
—
∆
—
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
ADDB
Add to B
(B) + (M) ⇒ B
ADDD
Add to D
(D) + (M : M + 1) ⇒ D
ADDE
Add to E
(E) + (M : M + 1) ⇒ E
ADE
ADX
ADY
ADZ
AEX
AEY
AEZ
AIS
(E) + (D) ⇒ E
(XK : IX) + («D) ⇒ XK : IX
(YK : IY) + («D) ⇒ YK : IY
(ZK : IZ) + («D) ⇒ ZK : IZ
(XK : IX) + («E) ⇒ XK : IX
(YK : IY) + («E) ⇒ YK : IY
(ZK : IZ) + («E) ⇒ ZK : IZ
SK : SP + «IMM ⇒ SK : SP
ANDA
Add D to E
Add D to X
Add D to Y
Add D to Z
Add E to X
Add E to Y
Add E to Z
Add Immediate Data to
SP
Add Immediate Value
to X
Add Immediate Value
to Y
Add Immediate Value
to Z
AND A
ANDB
AND B
(B) • (M) ⇒ B
AIX
AIY
AIZ
MC68HC16Y1
MC68HC16Y1TS/D
XK : IX + «IMM ⇒ XK : IX
YK : IY + «IMM ⇒ YK : IY
ZK : IZ + «IMM ⇒ ZK : IZ
(A) • (M) ⇒ A
Address
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM8
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
INH
INH
IMM8
IMM16
IMM8
IMM16
IMM8
IMM16
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
Instruction
Opcode
C1
D1
E1
F1
27C1
27D1
27E1
17C1
17D1
17E1
17F1
81
91
A1
FC
2781
2791
27A1
37B1
37C1
37D1
37E1
37F1
7C
3731
3741
3751
3761
3771
2778
37CD
37DD
37ED
374D
375D
376D
3F
373F
3C
373C
3D
373D
3E
373E
46
56
66
76
1746
1756
1766
1776
2746
2756
2766
C6
D6
E6
F6
17C6
17D6
17E6
17F6
27C6
27D6
27E6
Operand
ff
ff
ff
ii
—
—
—
gggg
gggg
gggg
hh ll
ff
ff
ff
ii
—
—
—
jjkk
gggg
gggg
gggg
hh ll
ii
jj kk
gggg
gggg
gggg
hh ll
—
—
—
—
—
—
—
ii
jj kk
ii
jj kk
ii
jj kk
ii
jj kk
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
Condition Codes
Cycles
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
4
6
6
6
6
2
4
6
6
6
6
2
2
2
2
2
2
2
2
4
2
4
2
4
2
4
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
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S MV H EV N
— — ∆ — ∆
Z
∆
V
∆
C
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
— — — — —
∆
— —
— — — — —
∆
— —
— — — — —
∆
— —
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MOTOROLA
15
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
Opcode
86
96
A6
2786
2796
27A6
37B6
37C6
37D6
37E6
37F6
3736
3746
3756
3766
3776
373A
Operand
ff
ff
ff
—
—
—
jj kk
gggg
gggg
gggg
hh ll
jj kk
gggg
gggg
gggg
hh ll
jj kk
Cycles
6
6
6
6
6
6
4
6
6
6
6
4
6
6
6
6
4
04
14
24
1704
1714
1724
1734
3704
ff
ff
ff
gggg
gggg
gggg
hh ll
—
8
8
8
8
8
8
8
2
S MV H EV N
— — — — ∆
Z
∆
V
0
C
—
— — — —
∆
∆
0
—
∆
∆
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
ANDD
AND D
(D) • (M : M + 1) ⇒ D
ANDE
AND E
(E) • (M : M + 1) ⇒ E
ANDP1
ASL
AND CCR
(CCR) • IMM16⇒ CCR
Arithmetic Shift Left
ASLA
Arithmetic Shift Left A
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
ASLB
Arithmetic Shift Left B
INH
3714
—
2
— — — —
∆
∆
∆
∆
ASLD
Arithmetic Shift Left D
INH
27F4
—
2
— — — —
∆
∆
∆
∆
ASLE
Arithmetic Shift Left E
INH
2774
—
2
— — — —
∆
∆
∆
∆
ASLM
Arithmetic Shift Left
AM
INH
27B6
—
4
—
∆
∆
— —
∆
ASLW
Arithmetic Shift Left
Word
∆
∆
— — — —
∆
∆
∆
∆
Arithmetic Shift Right A
8
8
8
8
8
8
8
8
8
8
8
2
∆
ASRA
gggg
gggg
gggg
hh ll
ff
ff
ff
gggg
gggg
gggg
hh ll
—
∆
Arithmetic Shift Right
2704
2714
2724
2734
0D
1D
2D
170D
171D
172D
173D
370D
— — — —
ASR
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
— — — —
∆
∆
∆
∆
ASRB
Arithmetic Shift Right B
INH
371D
—
2
— — — —
∆
∆
∆
∆
ASRD
Arithmetic Shift Right D
INH
27FD
—
2
— — — —
∆
∆
∆
∆
ASRE
Arithmetic Shift Right E
INH
277D
—
2
— — — —
∆
∆
∆
∆
MOTOROLA
16
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∆
∆
∆
—
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
ASRM
Arithmetic Shift Right
AM
ASRW
Arithmetic Shift Right
Word
BCC4
BCLR
Branch if Carry Clear
If C = 0, branch
Clear Bit(s)
(M) • (Mask) ⇒ M
BCLRW
Clear Bit(s) Word
(M : M + 1) • (Mask) ⇒
M:M+1
Address
Instruction
Condition Codes
Mode
INH
Opcode
27BA
Operand
—
Cycles
4
S MV H EV N
— — — ∆ ∆
IND16, X
IND16, Y
IND16, Z
EXT
REL8
270D
271D
272D
273D
B4
gggg
gggg
gggg
hh ll
rr
8
8
8
8
6, 2
— — — —
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
08
18
28
38
1708
1718
1728
2708
8
8
8
8
8
8
8
10
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
IND16, Y
2718
IND16, Z
2728
EXT
2738
mm gggg
mm gggg
mm gggg
mm hh ll
mm ff
mm ff
mm ff
gggg
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
∆
Z V
— —
C
∆
∆
∆
∆
— — — — — — — —
10
10
10
BCS4
BEQ4
Branch if Carry Set
If C = 1, branch
REL8
B5
rr
6, 2
— — — — — — — —
Branch if Equal
If Z = 1, branch
REL8
B7
rr
6, 2
— — — — — — — —
BGE4
Branch if Greater Than
or Equal to Zero
Enter Background Debug Mode
If N ⊕ V = 0, branch
REL8
BC
rr
6, 2
— — — — — — — —
If BDM enabled
enter BDM;
else, illegal instruction
If Z + (N ⊕ V) = 0, branch
INH
37A6
—
—
— — — — — — — —
REL8
BE
rr
6, 2
— — — — — — — —
BGND
BGT 4
BHI 4
BITA
Branch if Greater Than
Zero
Branch if Higher
If C + Z = 0, branch
REL8
B2
rr
6, 2
— — — — — — — —
Bit Test A
(A) • (M)
0
—
— — — —
∆
∆
0
—
BLE 4
Branch if Less Than or
Equal to Zero
Branch if Lower or
Same
Branch if Less Than
Zero
Branch if Minus
If Z + (N ⊕ V) = 1, branch
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6, 2
∆
(B) • (M)
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
rr
∆
Bit Test B
49
59
69
79
1749
1759
1769
1779
2749
2759
2769
C9
D9
E9
F9
17C9
17D9
17E9
17F9
27C9
27D9
27E9
BF
— — — —
BITB
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
REL8
If C + Z = 1, branch
REL8
B3
rr
6, 2
— — — — — — — —
If N ⊕ V = 1, branch
REL8
BD
rr
6, 2
— — — — — — — —
If N = 1, branch
REL8
BB
rr
6, 2
— — — — — — — —
Branch if Not Equal
If Z = 0, branch
REL8
B6
rr
6, 2
— — — — — — — —
BLS4
BLT4
BMI 4
BNE 4
MC68HC16Y1
MC68HC16Y1TS/D
For More Information On This Product,
Go to: www.freescale.com
— — — — — — — —
MOTOROLA
17
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Mnemonic
BPL4
BRA
BRCLR4
BRN
Freescale Semiconductor, Inc...
BRSET4
Operation
Description
Address
Branch if Plus
If N = 0, branch
Mode
REL8
Opcode
BA
Operand
rr
Cycles
6, 2
S MV H EV N Z V C
— — — — — — — —
Branch Always
Branch if Bit(s) Clear
If 1 = 1, branch
If (M) • (Mask) = 0, branch
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B0
CB
DB
EB
0A
6
10, 12
10, 12
10, 12
10, 14
— — — — — — — —
— — — — — — — —
IND16, Y
1A
IND16, Z
2A
EXT
3A
rr
mm ff rr
mm ff rr
mm ff rr
mm
gggg rrrr
mm
gggg rrrr
mm
gggg rrrr
mm hh ll
rrrr
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B1
8B
9B
AB
0B
2
10, 12
10, 12
10, 12
10, 14
IND16, Y
1B
IND16, Z
2B
EXT
3B
rr
mm ff rr
mm ff rr
mm ff rr
mm
gggg rrrr
mm
gggg rrrr
mm
gggg rrrr
mm hh ll
rrrr
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
09
19
29
39
1709
1719
1729
2709
8
8
8
8
8
8
8
10
IND16, Y
2719
IND16, Z
2729
EXT
2739
mm gggg
mm gggg
mm gggg
mm hh ll
mm ff
mm ff
mm ff
gggg
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
(PK : PC) − 2 ⇒ PK : PC
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
(PK:PC) + Offset ⇒ PK:PC
If V = 0, branch
REL8
36
rr
10
— — — — — — — —
REL8
B8
rr
6, 2
— — — — — — — —
— — — — — — — —
Branch Never
Branch if Bit(s) Set
If 1 = 0, branch
If (M) • (Mask) = 0, branch
BSET
Set Bit(s)
(M) • (Mask) ⇒ M
BSETW
Set Bit(s) in Word
(M : M + 1) • (Mask)
⇒M:M+1
BSR
Branch to Subroutine
BVC4
Branch if Overflow
Clear
Branch if Overflow Set
BVS4
CBA
CLR
Instruction
Condition Codes
10, 14
10, 14
10, 14
10, 14
10, 14
10, 14
∆
∆
0
—
— — — —
∆
∆
0
—
10
10
If V = 1, branch
REL8
B9
rr
6, 2
(A) – (B)
$00 ⇒ M
Clear A
Clear B
Clear D
Clear E
Clear AM
$00 ⇒ A
$00 ⇒ B
$0000 ⇒ D
$0000 ⇒ E
$000000000 ⇒ AM[32:0]
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
371B
05
15
25
1705
1715
1725
1735
3705
3715
27F5
2775
27B7
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
—
2
4
4
4
6
6
6
6
2
2
2
2
2
MOTOROLA
18
— — — —
10
Compare A to B
Clear Memory
CLRA
CLRB
CLRD
CLRE
CLRM
— — — — — — — —
— — — — — — — —
For More Information On This Product,
Go to: www.freescale.com
— — — —
— — — —
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
∆
0
∆
1
∆
0
∆
0
— 0 1 0 0
— 0 1 0 0
— 0 1 0 0
— 0 1 0 0
0 — — — —
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
CLRW
Clear Memory Word
$0000 ⇒ M : M + 1
CMPA
Compare A to Memory
(A) – (M)
CMPB
Compare B to Memory
(B) – (M)
COM
One’s Complement
$FF – (M) ⇒ M
COMA
COMB
COMD
COME
COMW
One’s Complement A
One’s Complement B
One’s Complement D
One’s Complement E
One’s Complement
Word
$FF – (A) ⇒ A
$FF – (B) ⇒ B
$FFFF – (D) ⇒ D
$FFFF – (E) ⇒ E
$FFFF – M : M + 1 ⇒
M:M+1
CPD
Compare D to Memory
(D) – (M : M + 1)
CPE
Compare E to Memory
(E) – (M : M + 1)
CPS
Compare SP to
Memory
(SP) – (M : M + 1)
MC68HC16Y1
MC68HC16Y1TS/D
Address
Mode
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
Instruction
Opcode
2705
2715
2725
2735
48
58
68
78
1748
1758
1768
1778
2748
2758
2768
C8
D8
E8
F8
17C8
17D8
17E8
17F8
27C8
27D8
27E8
00
10
20
1700
1710
1720
1730
3700
3710
27F0
2770
2700
2710
2720
2730
88
98
A8
2788
2798
27A8
37B8
37C8
37D8
37E8
37F8
3738
3748
3758
3768
3778
4F
5F
6F
174F
175F
176F
177F
377F
Operand
gggg
gggg
gggg
hh ll
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
gggg
gggg
gggg
hh ll
ff
ff
ff
—
—
—
jj kk
gggg
gggg
gggg
hh ll
jjkk
gggg
gggg
gggg
hhll
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
Condition Codes
Cycles
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
8
8
8
8
8
8
8
2
2
2
2
8
8
8
8
6
6
6
6
6
6
4
6
6
6
6
4
6
6
6
6
6
6
6
6
6
6
6
4
For More Information On This Product,
Go to: www.freescale.com
S MV H EV N
— — — — 0
Z
1
V
0
C
0
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
0
1
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
0
0
0
0
0
1
1
1
1
1
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
—
—
—
—
—
—
—
—
—
—
MOTOROLA
19
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Operand
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
—
Cycles
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
2
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
INH
01
11
21
1701
1711
1721
1731
3701
3711
2701
2711
2721
2731
3728
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
gggg
gggg
gggg
hh ll
—
8
8
8
8
8
8
8
2
2
8
8
8
8
24
INH
3729
—
INH
3725
(E) ∗ (D) ⇒ E : D
INH
(A) ⊕ (M) ⇒ A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
(IX) – (M : M + 1)
CPY
Compare IY to Memory
(IY) – (M : M + 1)
CPZ
Compare IZ to Memory
(IZ) – (M : M + 1)
DAA
Decimal Adjust A
DEC
Decrement Memory
(A)10
(M) – $01 ⇒ M
DECA
DECB
DECW
Decrement A
Decrement B
Decrement Memory
Word
(A) – $01 ⇒ A
(B) – $01 ⇒ B
(M : M + 1) – $0001
⇒M:M+1
EDIV
Extended Unsigned
Divide
EDIVS
Extended Signed Divide
EMUL
Extended Unsigned
Multiply
Extended Signed Multiply
Exclusive OR A
(E : D) / (IX)
Quotient ⇒ IX
Remainder ⇒ D
(E : D) / (IX)
Quotient ⇒ IX
Remainder ⇒ ACCD
(E) ∗ (D) ⇒ E : D
MOTOROLA
20
Condition Codes
Opcode
4C
5C
6C
174C
175C
176C
177C
377C
4D
5D
6D
174D
175D
176D
177D
377D
4E
5E
6E
174E
175E
176E
177E
377E
3721
Compare IX to Memory
EORA
Instruction
Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
INH
CPX
EMULS
Address
S MV H EV N
— — — — ∆
Z
∆
V
∆
C
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
U
∆
— — — —
∆
∆
∆
—
— — — —
— — — —
— — — —
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
— — — —
∆
∆
∆
∆
38
— — — —
∆
∆
∆
∆
—
10
— — — —
∆
∆
—
∆
3726
—
8
— — — —
∆
∆
—
∆
44
54
64
74
1744
1754
1764
1774
2744
2754
2764
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
6
6
6
2
6
6
6
6
6
6
6
— — — —
∆
∆
0
—
For More Information On This Product,
Go to: www.freescale.com
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
—
—
—
jjkk
gggg
gggg
gggg
hhll
jj kk
gggg
gggg
gggg
hh ll
—
Cycles
6
6
6
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
4
6
6
6
6
22
S MV H EV N
— — — — ∆
Z
∆
V
0
C
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — — —
∆
∆
∆
INH
3727
—
8
— — — —
∆
∆
∆
∆
INH
372A
—
22
— — — — —
∆
0
∆
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
IND20, X
IND20, Y
IND20, Z
EXT20
IND20, X
IND20, Y
IND20, Z
EXT20
03
13
23
1703
1713
1723
1733
3703
3713
2703
2713
2723
2733
4B
5B
6B
7A
89
99
A9
FA
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
gggg
gggg
gggg
hh ll
zg gggg
zg gggg
zg gggg
zb hh ll
zg gggg
zg gggg
zg gggg
zb hh ll
8
8
8
8
8
8
8
2
2
8
8
8
8
8
8
8
6
12
12
12
10
— — — —
∆
∆
∆
—
— — — —
— — — —
— — — —
∆
∆
∆
∆
∆
∆
∆
∆
∆
—
—
—
REL16
3784
rrrr
6, 4
— — — — — — — —
If C = 1, branch
REL16
3785
rrrr
6, 4
— — — — — — — —
If Z = 1, branch
REL16
3787
rrrr
6, 4
— — — — — — — —
If EV = 1, branch
REL16
3791
rrrr
6, 4
— — — — — — — —
REL16
378C
rrrr
6, 4
— — — — — — — —
REL16
378E
rrrr
6, 4
— — — — — — — —
(B) ⊕ (M) ⇒ B
EORD
Exclusive OR D
(D) ⊕ (M : M + 1) ⇒ D
EORE
Exclusive OR E
(E) ⊕ (M : M + 1) ⇒ E
FDIV
IDIV
Fractional
Unsigned Divide
Fractional Signed
Multiply
Integer Divide
INC
Increment Memory
(D) / (IX) ⇒ IX
Remainder ⇒ D
(E) ∗ (D) ⇒ E : D[31:1]
0 ⇒ D[0]
(D) / (IX) ⇒ IX;
Remainder ⇒ D
(M) + $01 ⇒ M
INCA
INCB
INCW
Increment A
Increment B
Increment Memory
Word
(A) + $01 ⇒ A
(B) + $01 ⇒ B
(M : M + 1) + $0001
⇒M:M+1
JMP
Jump
〈ea〉 ⇒ PK : PC
JSR
Jump to Subroutine
LBCC4
Long Branch if Carry
Clear
Long Branch if Carry
Set
Long Branch if Equal
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
〈ea〉 ⇒ PK : PC
If C = 0, branch
LBEQ4
LBEV4
LBGE4
LBGT 4
Long Branch if EV Set
Long Branch if Greater
If N ⊕ V = 0, branch
Than or Equal to Zero
Long Branch if Greater If Z ✛ (N ⊕ V) = 0, branch
Than Zero
MC68HC16Y1
MC68HC16Y1TS/D
Condition Codes
Opcode
C4
D4
E4
F4
17C4
17D4
17E4
17F4
27C4
27D4
27E4
84
94
A4
2784
2794
27A4
37B4
37C4
37D4
37E4
37F4
3734
3744
3754
3764
3774
372B
Exclusive OR B
LBCS4
Instruction
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
EORB
FMULS
Address
For More Information On This Product,
Go to: www.freescale.com
— — — — — — — —
— — — — — — — —
MOTOROLA
21
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Mnemonic
Description
Address
If C ✛ Z = 0, branch
Mode
REL16
Opcode
3782
Instruction
Operand
rrrr
Cycles
6, 4
S MV H EV N Z V C
— — — — — — — —
Condition Codes
LBHI 4
Long Branch if Higher
LBLE 4
Long Branch if Less If Z ✛ (N ⊕ V) = 1, branch
Than or Equal to Zero
Long Branch if Lower
If C ✛ Z = 1, branch
or Same
Long Branch if Less
If N ⊕ V = 1, branch
Than Zero
Long Branch if Minus
If N = 1, branch
REL16
378F
rrrr
6, 4
— — — — — — — —
REL16
3783
rrrr
6, 4
— — — — — — — —
REL16
378D
rrrr
6, 4
— — — — — — — —
REL16
378B
rrrr
6, 4
— — — — — — — —
Long Branch if MV Set
If MV = 1, branch
REL16
3790
rrrr
6, 4
— — — — — — — —
Long Branch if Not
Equal
Long Branch if Plus
If Z = 0, branch
REL16
3786
rrrr
6, 4
— — — — — — — —
If N = 0, branch
REL16
378A
rrrr
6, 4
— — — — — — — —
If 1 = 1, branch
If 1 = 0, branch
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
(PK : PC) + Offset ⇒
PK : PC
If V = 0, branch
REL16
REL16
REL16
3780
3781
27F9
rrrr
rrrr
rrrr
6
6
10
— — — — — — — —
— — — — — — — —
— — — — — — — —
REL16
3788
rrrr
6, 4
— — — — — — — —
If V = 1, branch
REL16
3789
rrrr
6, 4
— — — — — — — —
(M) ⇒ A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
EXT
45
55
65
75
1745
1755
1765
1775
2745
2755
2765
C5
D5
E5
F5
17C5
17D5
17E5
17F5
27C5
27D5
27E5
85
95
A5
2785
2795
27A5
37B5
37C5
37D5
37E5
37F5
3735
3745
3755
3765
3775
2771
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
—
—
—
jj kk
gggg
gggg
gggg
hh ll
jj kk
gggg
gggg
gggg
hh ll
hh ll
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
4
6
6
6
6
8
LBLS4
LBLT 4
LBMI 4
LBMV4
LBNE 4
Freescale Semiconductor, Inc...
Operation
LBPL4
LBRA
LBRN
LBSR
Long Branch Always
Long Branch Never
Long Branch to
Subroutine
LBVC4
LDAA
Long Branch if
Overflow Clear
Long Branch if
Overflow Set
Load A
LDAB
Load B
(M) ⇒ B
LDD
Load D
(M : M + 1) ⇒ D
LDE
Load E
(M : M + 1) ⇒ E
LDED
Load Concatenated
E and D
(M : M + 1) ⇒ E
(M + 2 : M + 3) ⇒ D
LBVS4
MOTOROLA
22
For More Information On This Product,
Go to: www.freescale.com
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — — — — — —
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
(M : M + 1)X ⇒ H R
Mode
EXT
Opcode
27B0
Instruction
Operand
—
Cycles
8
Condition Codes
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
INH
CF
DF
EF
17CF
17DF
17EF
17FF
37BF
CC
DC
EC
17CC
17DC
17EC
17FC
37BC
CD
DD
ED
17CD
17DD
17ED
17FD
37BD
CE
DE
EE
17CE
17DE
17EE
17FE
37BE
27F1
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
ff
ff
ff
gggg
gggg
gggg
hh ll
jj kk
—
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
6
6
6
6
6
6
6
4
4, 20
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
0F
1F
2F
170F
171F
172F
173F
370F
ff
ff
ff
gggg
gggg
gggg
hh ll
—
8
8
8
8
8
8
8
2
— — — —
0
∆
∆
∆
— — — —
0
∆
∆
∆
S MV H EV N Z V C
— — — — — — — —
LDHI
Initialize H and I
LDS
Load SP
(M : M + 1) ⇒ SP
LDX
Load IX
(M : M + 1) ⇒ IX
LDY
Load IY
(M : M + 1) ⇒ IY
LDZ
Load IZ
(M : M + 1) ⇒ IZ
LPSTOP
Low Power Stop
If S
then STOP
else NOP
LSR
Logical Shift Right
LSRA
Logical Shift Right A
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
LSRB
Logical Shift Right B
INH
371F
—
2
— — — —
0
∆
∆
∆
LSRD
Logical Shift Right D
INH
27FF
—
2
— — — —
0
∆
∆
∆
LSRE
Logical Shift Right E
INH
277F
—
2
— — — —
0
∆
∆
∆
LSRW
Logical Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
270F
271F
272F
273F
gggg
gggg
gggg
hh ll
8
8
8
8
— — — —
0
∆
∆
∆
Freescale Semiconductor, Inc...
(M : M + 1)Y ⇒ I R
MC68HC16Y1
MC68HC16Y1TS/D
For More Information On This Product,
Go to: www.freescale.com
— — — — — — — —
MOTOROLA
23
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Mnemonic
Operation
MAC
Multiply and
Accumulate
Signed 16-Bit
Fractions
MOVB
Move Byte
Description
(HR) ∗ (IR) ⇒ E : D
(AM) + (E : D) ⇒ AM
Qualified (IX) ⇒ IX
Qualified (IY) ⇒ IY
(HR) ⇒ IZ
(M : M + 1)X ⇒ HR
Address
Mode
IMM8
Instruction
Condition Codes
Opcode
7B
Operand
xoyo
Cycles
12
30
32
37FE
31
33
37FF
3724
02
12
22
1702
1712
1722
1732
3702
3712
27F2
2772
2702
2712
2722
2732
274C
47
57
67
77
1747
1757
1767
1777
2747
2757
2767
C7
D7
E7
F7
17C7
17D7
17E7
17F7
27C7
27D7
27E7
87
97
A7
2787
2797
27A7
37B7
37C7
37D7
37E7
37F7
ff hh ll
ff hh ll
hh ll hh ll
ff hh ll
ff hh ll
hh ll hh ll
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
—
gggg
gggg
gggg
hh ll
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
—
—
—
jj kk
gggg
gggg
gggg
hh ll
8
8
10
8
8
10
10
8
8
8
8
8
8
8
2
2
2
2
8
8
8
8
2
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
S MV H EV N Z
— ∆ — ∆ — —
V
∆
C
—
(M : M + 1)Y ⇒ IR
MOVW
Freescale Semiconductor, Inc...
MUL
NEG
NEGA
NEGB
NEGD
NEGE
NEGW
NOP
ORAA
ORAB
ORD
(M1) ⇒ M2
IXP to EXT
EXT to IXP
EXT to EXT
Move Word
(M : M + 11) ⇒ M : M + 12 IXP to EXT
EXT to IXP
EXT to EXT
Multiply
(A) ∗ (B) ⇒ D
INH
Negate Memory
$00 – (M) ⇒ M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
Negate A
$00 – (A) ⇒ A
INH
Negate B
$00 – (B) ⇒ B
INH
Negate D
$0000 – (D) ⇒ D
INH
Negate E
$0000 – (E) ⇒ E
INH
Negate Memory Word
$0000 – (M : M + 1)
IND16, X
⇒M:M+1
IND16, Y
IND16, Z
EXT
Null Operation
—
INH
OR A
(A) ✛ (M) ⇒ A
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
OR B
(B) ✛ (M) ⇒ B
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
OR D
(D) ✛ (M : M + 1) ⇒ D
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
MOTOROLA
24
For More Information On This Product,
Go to: www.freescale.com
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — — — — —
— — — — ∆ ∆ ∆
∆
∆
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
— — — — — — — —
— — — — ∆ ∆ 0 —
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
ORE
OR E
(E) ✛ (M : M + 1) ⇒ E
ORP 1
(CCR) ✛ IMM16 ⇒ CCR
PSHA
OR Condition Code
Register
Push A
PSHB
Push B
PSHM
Push Multiple
Registers
PSHMAC
PULA
Mask bits:
0=D
1=E
2 = IX
3 = IY
4 = IZ
5=K
6 = CCR
7 = (reserved)
Push MAC State
Pull A
PULB
Pull B
PULM 1
Pull Multiple Registers
PULMAC
RMAC
Mask bits:
0 = CCR[15:4]
1=K
2 = IZ
3 = IY
4 = IX
5=E
6=D
7 = (reserved)
Pull MAC State
Repeating
Multiply and
Accumulate
Signed 16-Bit
Fractions
(SK : SP) + 1 ⇒ SK : SP
Push (A)
(SK : SP) – 2 ⇒ SK : SP
(SK : SP) + 1 ⇒ SK : SP
Push (B)
(SK : SP) – 2 ⇒ SK : SP
For mask bits 0 to 7:
Address
Instruction
Opcode
3737
3747
3757
3767
3777
373B
Operand
jj kk
gggg
gggg
gggg
hh ll
jj kk
Cycles
4
6
6
6
6
4
INH
3708
—
4
— — — — — — — —
INH
3718
—
4
— — — — — — — —
IMM8
34
ii
4 + 2N
— — — — — — — —
If mask bit set
Push register
(SK : SP) – 2 ⇒ SK : SP
MAC Registers ⇒ Stack
(SK : SP) + 2 ⇒ SK : SP
Pull (A)
(SK : SP) – 1 ⇒ SK : SP
(SK : SP) + 2 ⇒ SK : SP
Pull (B)
(SK : SP) – 1 ⇒ SK : SP
For mask bits 0 to 7:
S MV H EV N
— — — — ∆
Z
∆
V
0
C
—
∆
∆
∆
∆
∆
∆
∆
∆
N=
number of
iterations
INH
INH
27B8
3709
—
—
14
6
— — — — — — — —
— — — — — — — —
INH
3719
—
6
— — — — — — — —
IMM8
35
ii
4+2(N+1)
∆
∆
∆
∆
∆
∆
∆
∆
N=
number of
iterations
If mask bit set
(SK : SP) + 2 ⇒ SK : SP
Pull register
Stack ⇒ MAC Registers
Repeat until (E) < 0
(AM) + (H) ∗ (I) ⇒ AM
Qualified (IX) ⇒ IX;
Qualified (IY) ⇒ IY;
(M : M + 1)X ⇒ H;
Condition Codes
Mode
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
INH
IMM8
27B9
FB
—
xoyo
16
6 + 12
per
iteration
— — — — — — — —
— ∆ — ∆ — — — —
0C
1C
2C
170C
171C
172C
173C
370C
ff
ff
ff
gggg
gggg
gggg
hh ll
—
8
8
8
8
8
8
8
2
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
371C
—
2
— — — —
∆
∆
∆
∆
(M : M + 1)Y ⇒ I
(E) – 1 ⇒ E
ROL
Rotate Left
ROLA
Rotate Left A
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
ROLB
Rotate Left B
INH
MC68HC16Y1
MC68HC16Y1TS/D
For More Information On This Product,
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MOTOROLA
25
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
ROLD
Rotate Left D
Mode
INH
ROLE
Rotate Left E
INH
277C
—
2
— — — —
∆
∆
∆
∆
ROLW
Rotate Left Word
∆
∆
— — — —
∆
∆
∆
∆
Rotate Right A
8
8
8
8
8
8
8
8
8
8
8
2
∆
RORA
gggg
gggg
gggg
hh ll
ff
ff
ff
gggg
gggg
gggg
hh ll
—
∆
Rotate Right
270C
271C
272C
273C
0E
1E
2E
170E
171E
172E
173E
370E
— — — —
ROR
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
— — — —
∆
∆
∆
∆
RORB
Rotate Right B
INH
371E
—
2
— — — —
∆
∆
∆
∆
RORD
Rotate Right D
INH
27FE
—
2
— — — —
∆
∆
∆
∆
RORE
Rotate Right E
INH
277E
—
2
— — — —
∆
∆
∆
∆
RORW
Rotate Right Word
gggg
gggg
gggg
hh ll
—
8
8
8
8
12
∆
∆
∆
∆
Return from Interrupt
270E
271E
272E
273E
2777
— — — —
RTI2
IND16, X
IND16, Y
IND16, Z
EXT
INH
∆
∆
∆
∆
∆
RTS3
Return from Subroutine
INH
27F7
—
12
— — — — — — — —
SBA
SBCA
Subtract B from A
Subtract with Carry
from A
INH
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
370A
42
52
62
72
1742
1752
1762
1772
2742
2752
2762
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
2
6
6
6
2
6
6
6
6
6
6
6
— — — —
— — — —
MOTOROLA
26
(SK : SP) + 2 ⇒ SK : SP
Pull CCR
(SK : SP) + 2 ⇒ SK : SP
Pull PC
(PK : PC) – 6 ⇒ PK : PC
(SK : SP) + 2 ⇒ SK : SP
Pull PK
(SK : SP) + 2 ⇒ SK : SP
Pull PC
(PK : PC) – 2 ⇒ PK : PC
(A) – (B) ⇒ A
(A) – (M) – C ⇒ A
Opcode
27FC
Operand
—
Cycles
2
For More Information On This Product,
Go to: www.freescale.com
S MV H EV N
— — — — ∆
Z
∆
V
∆
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
SBCB
Subtract with Carry
from B
(B) – (M) – C ⇒ B
SBCD
Subtract with Carry
from D
(D) – (M : M + 1) – C ⇒ D
SBCE
Subtract with Carry
from E
(E) – (M : M + 1) – C ⇒ E
SDE
STAA
Subtract D from E
Store A
(E) – (D)⇒ E
(A) ⇒ M
STAB
Store B
(B) ⇒ M
STD
Store D
(D) ⇒ M : M + 1
STE
Store E
(E) ⇒ M : M + 1
STED
Store Concatenated
D and E
(E) ⇒ M : M + 1
(D) ⇒ M + 2 : M + 3
MC68HC16Y1
MC68HC16Y1TS/D
Address
Mode
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
INH
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND16, X
IND16, Y
IND16, Z
EXT
EXT
Instruction
Opcode
C2
D2
E2
F2
17C2
17D2
17E2
17F2
27C2
27D2
27E2
82
92
A2
2782
2792
27A2
37B2
37C2
37D2
37E2
37F2
3732
3742
3752
3762
3772
2779
4A
5A
6A
174A
175A
176A
177A
274A
275A
276A
CA
DA
EA
17CA
17DA
17EA
17FA
27CA
27DA
27EA
8A
9A
AA
278A
279A
27AA
37CA
37DA
37EA
37FA
374A
375A
376A
377A
2773
Operand
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
—
—
—
jj kk
gggg
gggg
gggg
hh ll
jj kk
gggg
gggg
gggg
hh ll
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
—
—
—
gggg
gggg
gggg
hh ll
gggg
gggg
gggg
hh ll
hh ll
Condition Codes
Cycles
6
6
6
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
4
6
6
6
6
2
4
4
4
6
6
6
6
4
4
4
4
4
4
6
6
6
6
4
4
4
6
6
6
6
6
6
4
4
4
6
6
6
6
6
8
For More Information On This Product,
Go to: www.freescale.com
S MV H EV N
— — — — ∆
Z
∆
V
∆
C
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
— — — —
∆
∆
∆
∆
∆
0
∆
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — — — — — —
MOTOROLA
27
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
STS
Store SP
(SP) ⇒ M : M + 1
STX
Store IX
(IX) ⇒ M : M + 1
STY
Store IY
(IY) ⇒ M : M + 1
STZ
Store Z
(IZ) ⇒ M : M + 1
SUBA
Subtract from A
(A) – (M) ⇒ A
SUBB
Subtract from B
(B) – (M) ⇒ B
SUBD
Subtract from D
(D) – (M : M + 1) ⇒ D
SUBE
Subtract from E
(E) – (M : M + 1) ⇒ E
MOTOROLA
28
Address
Mode
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
E, X
E, Y
E, Z
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
IMM16
IND16, X
IND16, Y
IND16, Z
EXT
Instruction
Opcode
8F
9F
AF
178F
179F
17AF
17BF
8C
9C
AC
178C
179C
17AC
17BC
8D
9D
AD
178D
179D
17AD
17BD
8E
9E
AE
178E
179E
17AE
17BE
40
50
60
70
1740
1750
1760
1770
2740
2750
2760
C0
D0
E0
F0
17C0
17D0
17E0
17F0
27C0
27D0
27E0
80
90
A0
2780
2790
27A0
37B0
37C0
37D0
37E0
37F0
3730
3740
3750
3760
3770
Operand
ff
ff
ff
gggg
gggg
gggg
hh ll
ff
ff
ff
gggg
gggg
gggg
hh ll
ff
ff
ff
gggg
gggg
gggg
hh ll
ff
ff
ff
gggg
gggg
gggg
hh ll
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
—
—
—
jj kk
gggg
gggg
gggg
hh ll
jj kk
gggg
gggg
gggg
hh ll
Condition Codes
Cycles
4
4
4
6
6
6
6
4
4
4
6
6
6
6
4
4
4
6
6
6
6
4
4
4
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
6
6
6
6
6
6
4
6
6
6
6
4
6
6
6
6
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S MV H EV N
— — — — ∆
Z
∆
V
0
C
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — —
∆
∆
0
—
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
— — — —
∆
∆
∆
∆
MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
SWI
Software Interrupt
SXT
Sign Extend B into A
TAB
TAP
TBA
TBEK
TBSK
TBXK
TBYK
TBZK
TDE
TDMSK
Transfer A to B
Transfer A to CCR
Transfer B to A
Transfer B to EK
Transfer B to SK
Transfer B to XK
Transfer B to YK
Transfer B to ZK
Transfer D to E
Transfer D to
XMSK : YMSK
Transfer D to CCR
TDP1
TED
TEDM
TEKB
TEM
TMER
Transfer E to D
Transfer E and D to
AM[31:0]
Sign Extend AM
Transfer EK to B
Transfer E to
AM[31:16]
Sign Extend AM
Clear AM LSB
Transfer AM to E
Rounded
TMET
Transfer AM to E Truncated
TMXED
Transfer AM to
IX : E : D
TPA
TPD
TSKB
Transfer CCR MSB to
A
Transfer CCR to D
Transfer SK to B
TST
Test for Zero or Minus
TSTA
Test A for
Zero or Minus
Test B for
Zero or Minus
Test D for
Zero or Minus
Test E for
Zero or Minus
TSTB
TSTD
TSTE
MC68HC16Y1
MC68HC16Y1TS/D
Description
(PK : PC) + 2 ⇒ PK : PC
Push (PC)
(SK : SP) – 2 ⇒ SK : SP
Push (CCR)
(SK : SP) – 2 ⇒ SK : SP
$0 ⇒ PK
SWI Vector ⇒ PC
If B7 = 1
then A = $FF
else A = $00
(A) ⇒ B
(A[7:0]) ⇒ CCR[15:8]
(B) ⇒ A
(B) ⇒ EK
(B) ⇒ SK
(B) ⇒ XK
(B) ⇒ YK
(B) ⇒ ZK
(D) ⇒ E
(D[15:8]) ⇒ X MASK
(D[7:0]) ⇒ Y MASK
(D) ⇒ CCR[15:4]
Address
Instruction
Condition Codes
Mode
INH
Opcode
3720
Operand
—
Cycles
16
S MV H EV N Z V C
— — — — — — — —
INH
27F8
—
2
— — — —
∆
∆
— —
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3717
37FD
3707
27FA
379F
379C
379D
379E
277B
372F
—
—
—
—
—
—
—
—
—
—
2
4
2
2
2
2
2
2
2
2
—
∆
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
—
—
—
∆
∆
∆
—
—
—
—
—
∆
—
∆
∆
∆
—
—
—
—
—
∆
—
0
∆
0
—
—
—
—
—
0
—
—
∆
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
INH
372D
—
4
∆
(E) ⇒ D
(D) ⇒ AM[15:0]
(E) ⇒ AM[31:16]
AM[35:32] = AM31
$0 ⇒ B[7:4]
(EK) ⇒ B[3:0]
(E) ⇒ AM[31:16]
$00 ⇒ AM[15:0]
AM[35:32] = AM31
INH
INH
27FB
27B1
—
—
2
4
— — — — ∆ ∆ 0 —
— 0 — 0 — — — —
INH
27BB
—
2
— — — — — — — —
INH
27B2
—
4
—
0
—
0
— — — —
Rounded (AM) ⇒ Temp
If (SM • (EV ✛ MV))
then Saturation ⇒ E
else Temp[31:16] ⇒ E
If (SM • (EV ✛ MV))
then Saturation ⇒ E
else AM[31:16] ⇒ E
AM[35:32] ⇒ IX[3:0]
AM35 ⇒ IX[15:4]
AM[31:16] ⇒ E
AM[15:0] ⇒ D
(CCR[15:8]) ⇒ A
INH
27B4
—
6
—
∆
—
∆
∆
∆
— —
INH
27B5
—
2
— — — —
∆
∆
— —
INH
27B3
—
6
— — — — — — — —
INH
37FC
—
2
— — — — — — — —
(CCR) ⇒ D
(SK) ⇒ B[3:0]
$0 ⇒ B[7:4]
(M) – $00
INH
INH
372C
37AF
—
—
2
2
— — — — — — — —
— — — — — — — —
06
16
26
1706
1716
1726
1736
3706
ff
ff
ff
gggg
gggg
gggg
hh ll
—
6
6
6
6
6
6
6
2
— — — —
∆
∆
0
0
(A) – $00
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
— — — —
∆
∆
0
0
(B) – $00
INH
3716
—
2
— — — —
∆
∆
0
0
(D) – $0000
INH
27F6
—
2
— — — —
∆
∆
0
0
(E) – $0000
INH
2776
—
2
— — — —
∆
∆
0
0
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MOTOROLA
29
Freescale Semiconductor, Inc.
Table 5 Instruction Set Summary (Continued)
Freescale Semiconductor, Inc...
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
S MV H EV N
— — — — ∆
Z
∆
V
0
C
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TZS
Transfer Z to SP
INH
376E
—
TZX
Transfer Z to X
INH
274E
—
TZY
Transfer Z to Y
INH
275E
—
WAI
Wait for Interrupt
INH
27F3
—
XGAB
Exchange A with B
INH
371A
—
XGDE
Exchange D with E
INH
277A
—
XGDX
Exchange D with X
INH
37CC
—
XGDY
Exchange D with Y
INH
37DC
—
XGDZ
Exchange D with Z
INH
37EC
—
XGEX
Exchange E with X
INH
374C
—
XGEY
Exchange E with Y
INH
375C
—
XGEZ
Exchange E with Z
INH
376C
—
NOTES:
1. CCR[15:4] change according to results of operation. The PK field is not affected.
2. CCR[15:0] change according to copy of CCR pulled from stack.
3. PK field changes according to state pulled from stack. The rest of the CCR is not affected.
4. Cycle times for conditional branches are shown in "taken, not taken" order.
2
2
2
8
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSTW
Test for
Zero or Minus Word
(M : M + 1) – $0000
TSX
TSY
TSZ
TXKB
Transfer SP to X
Transfer SP to Y
Transfer SP to Z
Transfer XK to B
TXS
TXY
TXZ
TYKB
Transfer X to SP
Transfer X to Y
Transfer X to Z
Transfer YK to B
TYS
TYX
TYZ
TZKB
Transfer Y to SP
Transfer Y to X
Transfer Y to Z
Transfer ZK to B
(SK : SP) + 2 ⇒ XK : IX
(SK : SP) + 2 ⇒ YK : IY
(SK : SP) + 2 ⇒ ZK : IZ
$0 ⇒ B[7:4]
(XK) ⇒ B[3:0]
(XK : IX) – 2 ⇒ SK : SP
(XK : IX) ⇒ YK : IY
(XK : IX) ⇒ ZK : IZ
$0 ⇒ B[7:4]
(YK) ⇒ B[3:0]
(YK : IY) – 2 ⇒ SK : SP
(YK : IY) ⇒ XK : IX
(YK : IY) ⇒ ZK : IZ
$0 ⇒ B[7:4]
(ZK) ⇒ B[3:0]
(ZK : IZ) – 2 ⇒ SK : SP
(ZK : IZ) ⇒ XK : IX
(ZK : IZ) ⇒ ZK : IY
WAIT
(A) ⇔ (B)
(D) ⇔ (E)
(D) ⇔ (IX)
(D) ⇔ (IY)
(D) ⇔ (IZ)
(E) ⇔ (IX)
(E) ⇔ (IY)
(E) ⇔ (IZ)
MOTOROLA
30
Mode
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
Opcode
2706
2716
2726
2736
274F
275F
276F
37AC
Operand
gggg
gggg
gggg
hh ll
—
—
—
—
Cycles
6
6
6
6
2
2
2
2
INH
INH
INH
INH
374E
275C
276C
37AD
—
—
—
—
INH
INH
INH
INH
375E
274D
276D
37AE
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MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 6 Instruction Set Abbreviations and Symbols
A
AM
B
CCR
D
E
EK
IR
HR
IX
IY
IZ
K
PC
PK
SK
SL
SP
XK
YK
ZK
XMSK
YMSK
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
∆
0
1
M
R
S
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Accumulator A
Accumulator M
Accumulator B
Condition code register
Accumulator D
Accumulator E
Extended addressing extension field
MAC multiplicand register
MAC multiplier register
Index register X
Index register Y
Index register Z
Address extension register
Program counter
Program counter extension field
Stack pointer extension field
Multiply and accumulate sign latch
Stack pointer
Index register X extension field
Index register Y extension field
Index register Z extension field
Modulo addressing index register X mask
Modulo addressing index register Y mask
Stop disable control bit
AM overflow indicator
Half carry indicator
AM extended overflow indicator
Negative indicator
Zero indicator
Two's complement overflow indicator
Carry/borrow indicator
Interrupt priority field
Saturation mode control bit
Program counter extension field
Bit not affected
Bit changes as specified
Bit cleared
Bit set
Memory location used in operation
Result of operation
Source data
X
M
M +1
M:M+1
(...)X
(...)Y
(...)Z
E, X
E, Y
E, Z
EXT
EXT20
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
IND20, X
IND20, Y
IND20, Z
INH
IXP
REL8
REL16
b
ff
gggg
hh
ii
jj
kk
ll
mm
mmmm
rr
rrrr
xo
yo
z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Register used in operation
Address of one memory byte
Address of byte at M + $0001
Address of one memory word
Contents of address pointed to by IX
Contents of address pointed to by IY
Contents of address pointed to by IZ
IX with E offset
IY with E offset
IZ with E offset
Extended
20-bit extended
8-bit immediate
16-bit immediate
IX with unsigned 8-bit offset
IY with unsigned 8-bit offset
IZ with unsigned 8-bit offset
IX with signed 16-bit offset
IY with signed 16-bit offset
IZ with signed 16-bit offset
IX with signed 20-bit offset
IY with signed 20-bit offset
IZ with signed 20-bit offset
Inherent
Post-modified indexed
8-bit relative
16-bit relative
4-bit address extension
8-bit unsigned offset
16-bit signed offset
High byte of 16-bit extended address
8-bit immediate data
High byte of 16-bit immediate data
Low byte of 16-bit immediate data
Low byte of 16-bit extended address
8-bit mask
16-bit mask
8-bit unsigned relative offset
16-bit signed relative offset
MAC index register X offset
MAC index register Y offset
4-bit zero extension
+
•
/
>
<
=
≥
≤
≠
—
—
—
—
—
—
—
—
—
—
Addition
Subtraction or negation (2's complement)
Multiplication
Division
Greater
Less
Equal
Equal or greater
Equal or less
Not equal
•
+
⊕
NOT
:
⇒
⇔
±
«
%
$
—
—
—
—
—
—
—
—
—
—
—
AND
Inclusive OR (OR)
Exclusive OR (EOR)
Complementation
Concatenation
Transferred
Exchanged
Sign bit; also used to show tolerance
Sign extension
Binary value
Hexadecimal value
MC68HC16Y1
MC68HC16Y1TS/D
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MOTOROLA
31
Freescale Semiconductor, Inc.
3 Single-Chip Integration Module
The single-chip integration module (SCIM) consists of six submodules that control system start-up, initialization, configuration, and external bus with a minimum of external devices. A block diagram of the
SCIM is shown below.
SYSTEM CONFIGURATION
AND PROTECTION
Freescale Semiconductor, Inc...
CLOCK SYNTHESIZER
CHIP SELECTS
CLKOUT
EXTAL
MODCLK
UPPER ADDRESS
CHIP SELECTS
EXTERNAL BUS
EXTERNAL BUS INTERFACE
RESET
FACTORY TEST
TSC
FREEZE/QUOT
SIM BLOCK
Figure 4 Single-Chip Integration Module Block Diagram
MOTOROLA
32
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MC68HC16Y1
MC68HC16Y1TS/D
Freescale Semiconductor, Inc.
Table 7 SCIM Address Map
Address
YFFA00
8 7
0
SCIM MODULE CONFIGURATION (SCIMCR)
YFFA02
FACTORY TEST (SCIMTR)
YFFA04
CLOCK SYNTHESIZER CONTROL (SYNCR)
YFFA06
YFFA08
UNUSED
RESET STATUS REGISTER (RSR)
MODULE TEST E (SCIMTRE)
YFFA0A
PORT A DATA REGISTER (PORTA) PORT B DATA REGISTER (PORTB)
YFFA0C
PORT G DATA REGISTER (PORTG) PORT H DATA REGISTER (PORTH)
YFFA0E
PORT G DATA DIRECTION (DDRG) PORT H DATA DIRECTION (DDRH)
YFFA10
Freescale Semiconductor, Inc...
15
UNUSED
PORTE DATA (PORTE0)
YFFA12
UNUSED
PORTE DATA (PORTE1)
YFFA14
PORT A/B DATA DIRECTION
(DDRAB)
PORT E DATA DIRECTION (DDRE)
YFFA16
UNUSED
PORT E PIN ASSIGNMENT (PEPAR)
YFFA18
UNUSED
PORTF DATA (PORTF0)
YFFA1A
UNUSED
PORTF DATA (PORTF1)
YFFA1C
UNUSED
PORT F DATA DIRECTION (DDRF)
YFFA1E
UNUSED
PORT F PIN ASSIGNMENT (PFPAR)
YFFA20
UNUSED
SYSTEM PROTECTION CONTROL
(SYPCR)
YFFA22
YFFA24
PERIODIC INTERRUPT CONTROL (PICR)
PERIODIC INTERRUPT TIMING (PITR)
YFFA26
UNUSED
SOFTWARE SERVICE (SWSR)
YFFA28
UNUSED
PORTFE
YFFA2A
UNUSED
PORT F EDGE DETECT
INTERRUPT (PFIVR)
YFFA2C
UNUSED
PORT F EDGE-DETECT
INTERRUPT LEVEL (PFLVR)
YFFA2E
UNUSED
UNUSED
YFFA30
TEST MODULE MASTER SHIFT A (TSTMSRA)
YFFA32
TEST MODULE MASTER SHIFT B (TSTMSRB)
YFFA34
TEST MODULE SHIFT COUNT (TSTSC)
YFFA36
TEST MODULE REPETITION COUNTER (TSTRC)
YFFA38
TEST MODULE CONTROL (CREG)
YFFA3A
TEST MODULE DISTRIBUTED REGISTER (DREG)
YFFA3C
UNUSED
UNUSED
YFFA3E
UNUSED
UNUSED
YFFA40
UNUSED
PORT C DATA (PORTC)
YFFA42
UNUSED
UNUSED
YFFA44
CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
YFFA46
CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
YFFA48
CHIP-SELECT BASE BOOT (CSBARBT)
YFFA4A
CHIP-SELECT OPTION BOOT (CSORBT)
YFFA4C
CHIP-SELECT BASE 0 (CSBAR0)
YFFA4E
CHIP-SELECT OPTION 0 (CSOR0)
MC68HC16Y1
MC68HC16Y1TS/D
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Table 7 SCIM Address Map
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Address
15
8 7
YFFA50
UNUSED
YFFA52
UNUSED
YFFA54
UNUSED
YFFA56
UNUSED
0
YFFA58
CHIP-SELECT BASE 3 (CSBAR3)
YFFA5A
CHIP-SELECT OPTION 3 (CSOR3)
YFFA5C
UNUSED
YFFA5E
UNUSED
YFFA60
CHIP-SELECT BASE 5 (CSBAR5)
YFFA62
CHIP-SELECT OPTION 5 (CSOR5)
YFFA64
CHIP-SELECT BASE 6 (CSBAR6)
YFFA66
CHIP-SELECT OPTION 6 (CSOR6)
YFFA68
CHIP-SELECT BASE 7 (CSBAR7)
YFFA6A
CHIP-SELECT OPTION 7 (CSOR7)
YFFA6C
CHIP-SELECT BASE 8 (CSBAR8)
YFFA6E
CHIP-SELECT OPTION 8 (CSOR8)
YFFA70
CHIP-SELECT BASE 9 (CSBAR9)
YFFA72
CHIP-SELECT OPTION 9 (CSOR9)
YFFA74
CHIP-SELECT BASE 10 (CSBAR10)
YFFA76
CHIP-SELECT OPTION 10 (CSOR10)
YFFA78
UNUSED
UNUSED
YFFA7A
UNUSED
UNUSED
YFFA7C
UNUSED
UNUSED
YFFA7E
UNUSED
UNUSED
Y = M111 where M is the modmap bit in the SCIMCR.
3.1 System Configuration
The MC68HC16Y1 can operate as a stand-alone device (single-chip modes), with 24-bit external address bus and an 8-bit external data bus (partially expanded mode), or with a 24-bit external address
bus and a 16-bit external data bus. However, since ADDR[23:20] follow the state of ADDR19, the external bus is effectively only 20 bits wide. In addition, SCIM pins can be configured for use as I/O ports
or programmable chip select signals. System configuration is determined by setting bits in the SCIM
module configuration register (SCIMCR), and by asserting certain MCU pins during reset.
SCIMCR — Single-Chip Integration Module Configuration Register
15
EXOFF
14
13
12
11
10
FRZSW
FRZBM
CPUD
SLVE
0
1
*
*
0
9
8
SHEN
$YFFA00
7
6
5
4
SUPV
MM
ABD
RWD
1
1
*
*
3
2
1
0
1
1
IARB
RESET:
0
1
0
0
1
1
* Reset state is mode dependent — see bit description below
The module configuration register controls system configuration. It can be read or written at any time,
except for the module mapping (MM) bit, which must remain set to one.
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EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog continues to run.
1 = When FREEZE is asserted, the software watchdog is disabled.
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FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the periodic interrupt timer counters continue to run.
1 = When FREEZE is asserted, the periodic interrupt timer counters are disabled, preventing interrupts during software debug.
CPUD — CPU Development Support Disable
0 = Instruction pipeline signals available on pins IPIPE0 and IPIPE1
1 = Pins IPIPE0 and IPIPE1 placed in high-impedance state unless a breakpoint occurs
CPUD iscleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode.
SLVE — Slave Mode Enable
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
This bit is a read-only status bit that reflects the state of DATA11 during reset. Slave mode is used for
factory testing. Reset state is the complement of DATA11 during reset in fully expanded mode.
SHEN[1:0] — Show Cycle Enable
This field determines what the external bus interface does with the external bus during internal transfer
operations. A show cycle allows internal transfers to be externally monitored. The table below shows
whether show cycle data is driven externally, and whether external bus arbitration can occur. To prevent
bus conflict, external peripherals must not be enabled during show cycles.
SHEN
00
01
10
11
Action
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places SCIM global registers in either supervisor data space or user data space. Since
the CPU16 in the MC68HC16Y1 operates only in supervisory mode, SUPV has no effect.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
The logic state of M determines the value of ADDR23 in the IMB module address. Because ADDR[23:20] follow the state of ADDR19 in the MC68HC16Y1, M must be set to one — if M is cleared,
IMB modules will be inaccessible. This bit can be written only once after reset.
ABD — Address Bus Disable
0 = Pins ADDR[2:0] operate normally.
1 = Pins ADDR[2:0] are disabled.
ABD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode. ABD
can be written only once after reset.
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RWD — Read/Write Disable
0 = R/W signal operates normally
1 = R/W signal placed in high-impedance state.
RWD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode.
RWD can be written only once after reset.
IARB[3:0] — Interrupt Arbitration
Each module that can generate interrupts, including the SCIM, has an IARB field. Each IARB field can
be assigned a value from $0 to $F. During an interrupt acknowledge cycle, IARB permits arbitration
among simultaneous interrupts of the same priority level. The reset value of the SCIM IARB field is $F.
This prevents SCIM interrupts from being discarded. Initialization software must set the IARB field to a
lower value if lower priority interrupts are to be arbitrated.
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RSR — Reset Status Register
7
EXT
6
POW
$YFFA07
5
SW
4
HLT
3
0
2
LOC
1
SYS
0
TST
The reset status register contains a bit for each reset source in the MCU. A bit set to one indicates what
type of reset has occurred. When multiple reset sources occur at the same time, more than one bit in
RSR can be set. The reset status register is updated by the reset control logic when the MCU comes
out of reset. This register can be read at any time. A write has no effect.
EXT — External Reset
Reset was caused by an external signal.
POW — Power-Up Reset
Reset was caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset was caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset was caused by the system protection submodule halt monitor.
LOC — Loss of Clock Reset
Reset was caused by loss of clock submodule frequency reference. This reset can only occur if the
RSTEN bit in the clock submodule is set and the VCO is enabled.
SYS — System Reset
Reset was caused by the CPU RESET instruction. System reset does not load a reset vector or affect
any internal CPU registers or SIM configuration registers, but does reset external devices and other internal modules.
3.2 Operating Modes
During reset, the SCIM configures itself according to the states of the DATA, BERR, MODCLK, and
BKPT pins. DATA[11:0] provide pin configuration information. BERR, MODCLK, and BKPT determine
basic operation.
The SCIM can be configured to operate in one of three modes: 16-bit expanded, 8-bit expanded, and
single chip. Operating mode is determined by the value of the DATA1 and BERR signals coming out of
reset.
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Table 8 Basic Configuration Options
Select Pin
MODCLK
BKPT
BERR
DATA1 (if BERR = 1)
Default Function
(Pin Left High)
Synthesized system clock
Background Mode Disabled
Expanded Mode
8-Bit Expanded Mode
Alternate Function
(Pin Pulled Low)
External system clock
Background Mode Enabled
Single-Chip Mode
16-Bit Expanded Mode
BERR, BKPT, and MODCLK do not have internal pull-ups and must be driven to the desired state during
reset.
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Operating mode determines which address and data bus lines are used and which general-purpose I/
O ports are available. The table below summarizes bus and port configuration.
Table 9 Bus and Port Configuration Options
Mode
Address Bus
Data Bus
I/O Ports
16-Bit Expanded
ADDR[18:3]
DATA[15:0]
—
8-Bit Expanded
ADDR[18:3]
DATA[15:8]
DATA[7:0] = Port H
Single Chip
None
None
ADDR[18:11] = Port A
ADDR[10:3] = Port B
DATA[15:8] = Port G
DATA[7:0] = Port H
Many pins on the MC68HC16, including data and address bus pins, have multiple functions. Reset value for these pins depends on operating mode. In expanded mode, the values of DATA[11:0] during reset determines the function of these pins. The functions of some pins can be changed subsequently by
writing to the appropriate pin assignment register. Data bus pins have internal pull-ups and must be
pulled low to achieve the desired alternate configuration. The following tables summarize pin configuration options for each operating mode.
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3.2.1 16-Bit Expanded Mode
In 16-bit expanded mode, (BERR = 1, DATA1 = 0) pins ADDR[18:3] and DATA[15:0] are configured as
address and data pins, respectively. The alternate functions for these pins as ports A, B, G, and H are
unavailable.
Table 10 16-Bit Expanded Mode Reset Configuration
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Pin(s) Affected
Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
CSBOOT
DATA0
CSBOOT 16-Bit
CSBOOT 8-Bit
BR/CS0
FC0/CS3
FC1/PC1
FC2/CS5/PC2
DATA2
CS0
CS3
FC1
CS5
BR
FC0
FC1
FC2
ADDR19/CS6/PC3
ADDR20/CS7/PC4
ADDR21/CS8/PC5
ADDR22/CS9/PC6
ADDR23/CS10/ECLK
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DSACK0/PE0
DSACK1/PE1
AVEC/PE2
PE3
DS/PE4
AS/PE5
SIZ0/PE6
SIZ1/PE7
DATA8
DSACK0
DSACK1
AVEC
PE3
DS
AS
SIZ0
SIZ1
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
MODCLK/PF0
IRQ[7:1]/PF[7:1]
DATA9
MODCLK
IRQ[7:1]
PF0
PF[7:1]
BGACK/CSE
BG/CSM
DATA10
BGACK
BG
CSE1
CSM2
DATA11
DATA11
Slave Mode Disabled3
Slave Mode Enabled3
1. CSE is enabled when DATA10 and DATA1 = 0 during reset.
2. CSM is enabled when DATA13, DATA10 and DATA1 = 0 during reset.
3. Slave mode used for factory test only.
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3.2.2 8-Bit Expanded Mode
In 8-bit expanded mode (BERR = 1, DATA1 = 1), pins DATA[7:0] are configured as an 8-bit I/O port.
Pins DATA[15:8] are configured as data pins. Pins ADDR[18:3] are configured as address pins. Emulator mode is always disabled.
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Table 11 8-Bit Expanded Mode Reset Configuration
Pin(s) Affected
Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
CSBOOT
N/A1
CSBOOT 8-Bit
CSBOOT 8-Bit
BR/CS0
FC0/CS3/PC0
FC1/PC1
FC2/CS5/PC2
N/A1
CS0
CS3
FC1
CS5
CS0
CS3
FC1
CS5
ADDR19/CS6/PC3
ADDR20/CS7/PC4
ADDR21/CS8/PC5
ADDR22/CS9/PC6
ADDR23/CS10/ECLK
N/A1
CS[10:6]
CS[10:6]
DSACK0/PE0
DSACK1/PE1
AVEC/PE2
PE3
DS/PE4
AS/PE5
SIZ0/PE6
SIZ1/PE7
DATA8
DSACK0
DSACK1
AVEC
PE3
DS
AS
SIZ0
SIZ1
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
MODCLK/PF0
IRQ[7:1]/PF[7:1]
DATA9
MODCLK
IRQ[7:1]
PF0
PF[7:1]
BGACK/CSE
BG/CSM
N/A1
BGACK
BG
BGACK
BG
1. These pins have only one reset configuration in 8-bit expanded mode.
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3.2.3 Single-Chip Mode
In single-chip mode (BERR = 0), pins DATA[15:0] are configured as two 8-bit I/O ports. ADDR[18:3] are
configured as two 8-bit I/O ports. There is no external data bus path. Expanded mode configuration options are not available: I/O ports A, B, C, E, F, G, and H are always selected. BERR can be tied low
permanently to select single-chip mode.
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Table 12 Single-Chip Mode Reset Configuration
Pin(s) Affected
Function
CSBOOT
CSBOOT 8-Bit
ADDR[18:10]
PA[7:0]
ADDR[9:3]
PB[7:0]
BR/CS0
CS0
FC0/CS3/PC0
FC1/PC1
FC2/CS5/PC2
ADDR19/CS6/PC3
ADDR20/CS7/PC4
ADDR21/CS8/PC5
ADDR22/CS9/PC6
PC[6:0]
ADDR23/CS10/ECLK
—
DSACK0/PE0
DSACK1/PE1
AVEC/PE2
PE3
DS/PE4
AS/PE5
SIZ0/PE6
SIZ1/PE7
PE[7:0]
MODCLK/PF0
IRQ[7:1]/PF[7:1]
PF0
PF[7:1]
DATA[15:8]
PG[7:0]
DATA[7:0]
PH[7:0]
BGACK/CSE
BG/CSM
BGACK
BG
3.3 Emulation Support
The SCIM contains logic that can be used to replace on-chip ports externally. It also contains special
support logic to allow external emulation of internal ROM. This emulation support allows system development of a single-chip application in expanded mode.
Emulator mode is a special type of 16-bit expanded operation. It is entered by holding DATA10 low,
BERR high, and DATA1 low during reset. In emulator mode, all port A, B, E, G, and H data and data
direction registers and the port E pin assignment register are mapped externally. Port C data, port F
data and data direction registers, and port F pin assignment register are accessible normally in emulator
mode.
An emulator chip select (CSE) is asserted whenever any of the externally-mapped registers are addressed. The signal is asserted on the falling edge of AS. The SCIM does not respond to these accesses, allowing external logic, such as a port replacement unit (PRU) to respond. Accesses to externallymapped registers require three clock cycles.
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External ROM emulation is enabled by holding DATA10 and DATA13 low during reset (DATA14 must
be held high during reset to enable the ROM module). While ROM emulation mode is enabled, memory
chip select signal CSM is asserted whenever a valid access to an address assigned to the masked ROM
array is made. The ROM module does not acknowledge IMB accesses while in emulation mode — this
causes the SCIM to run an external bus cycle for each access. See 3.9 Chip Selects and 9 Masked
ROM Module for more information.
3.3.1 System Protection
System protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software
watchdog timer. These functions reduce the number of external components required for a complete
control system.
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SYPCR — System Protection Control Register
7
SWE
RESET:
1
6
SWP
5
MODCLK
0
$YFFA21
4
SWT
0
3
DBE
2
BME
1
0
0
0
0
BMT
0
The system protection control register controls system monitor functions, software watchdog clock
prescaling, and bus monitor timing. In operating modes, this register can be written only once following
power-on or reset, but can be read at any time. In test mode, it is writable at any time.
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
The reset value of SWP is the complement of the state of the MODCLK pin during reset.
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following table gives the ratio for each combination of SWP and SWT bits.
SWP
0
SWT
00
Ratio
0
01
211
0
10
213
0
11
215
1
00
218
1
01
220
1
10
222
1
11
224
29
DBE — Double Bus Fault Enable
0 = Disable double bus fault halt monitor function
1 = Enable double bus fault halt monitor function
BME — Bus Monitor External Enable
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0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the table below.
BMT
Bus Monitor Time-out Period
00
64 System Clocks
01
32 System Clocks
10
16 System Clocks
11
8 System Clocks
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3.3.2 Bus Monitor
The internal bus monitor checks for excessively long response times during normal bus cycles
(DSACKx) and during IACK cycles (AVEC). The monitor asserts BERR if response time is excessive.
DSACKx and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACKx response on the external bus unless it initiates the bus cycle. The
BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a system
contains external bus masters, an external bus monitor must be implemented, and the internal to external bus monitor option must be disabled.
3.3.3 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus, caused by a double bus fault.
This signal is asserted by the CPU after a double bus fault occurs. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhibited by the DBE bit in the SYPCR.
3.3.4 Spurious Interrupt Monitor
The spurious interrupt monitor causes a bus error exception if no interrupt arbitration occurs during interrupt acknowledge cycle.
3.3.5 Software Watchdog
SWSR — Software Service Register
7
6
5
$YFFA27
4
3
2
1
0
0
0
0
0
SWSR
RESET:
0
0
0
0
Register shown with read value.
The software watchdog is controlled by SWE in SYPCR. Once enabled, the watchdog requires that a
service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog
times out and issues a reset. This register can be written at any time, but returns zeros when read.
Perform a software watchdog service sequence as follows:
• Write $55 to SWSR.
• Write $AA to SWSR.
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Both writes must occur in the order listed prior to time-out, but any number of instructions can be executed between the two writes.
Watchdog clock rate is affected by SWP and SWT in SYPCR.
When SWT[1:0] are modified, a watchdog service sequence must be performed before the new timeout period will take effect.
The reset value of SWP is the complement of the state of the MODCLK pin on the rising edge of reset.
Software watchdog time-out period is given by the following equation:
Time-Out Period = Divide Count/EXTAL Frequency
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3.4 System Clock
The system clock in the SCIM provides timing signals for the IMB modules and for an external peripheral
bus. Because the MC68HC16Y1 is a fully static design, register and memory contents are not affected
when clock rate changes. System hardware and software support changes in clock rate during operation.
The system clock signal can be generated in three ways. An internal phase-locked loop can synthesize
the clock from either an internal or an external frequency source, or the clock signal can be input from
an external source.
Following is a block diagram of the clock submodule.
VDDSYN
22 pF2
VSSI
330 k
10M
EXTAL
22 pF2
XFC1
0.1µF
VSSI
0.1µF
.01µF
XTAL
CRYSTAL
OSCILLATOR
XFC PIN
PHASE
COMPARATOR
VSSI
VDDSYN
LOW-PASS
FILTER
FEEDBACK DIVIDER
VCO
W
Y
SYSTEM CLOCK CONTROL
CLKOUT
X
SYSTEM
CLOCK
1. Must be low-leakage capacitor (insulation resistance 30,000 MΩ or greater).
2. Capacitance based on a test circuit constructed with a DAISHINKU DMX-38 32.768-kHz crystal.
SYS CLOCK
BLOCK 32KHZ
Figure 5 System Clock Block Diagram
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3.4.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines clock source. When MODCLK is
held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator or
an external reference input — clock synthesizer control register SYNCR determines operating frequency and various modes of operation. When MODCLK is held low during reset, the clock synthesizer is
disabled, and an external system clock signal must be applied — SYNCR control bits have no effect.
A reference crystal must be connected between the EXTAL and XTAL pins in order to use the internal
oscillator. Use of a 32.768 kHz watch crystal is recommended — these crystals are readily available
and inexpensive.
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If an external reference signal or an external system clock signal is applied via the EXTAL pin, the XTAL
pin must be left floating. External reference signal frequency must be less than or equal to maximum
specified reference frequency. External system clock signal frequency must be less than or equal to
maximum specified system clock frequency.
When an external system clock signal is applied (PLL not used), duty cycle of the input is critical, especially at operating frequencies close to maximum. The relationship between clock signal duty cycle and
clock signal period is expressed:
Minimum external clock period =
minimum external clock high/low time
50% – percentage variation of external clock input duty cycle
3.4.2 Clock Synthesizer Operation
A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator.
The other phase comparator input is a reference signal, either from the internal oscillator or from an
external source. The comparator generates a control signal proportional to the difference in phase between its two inputs. The signal is low-pass filtered and used to correct VCO output frequency.
The synthesizer locks when VCO frequency is identical to reference frequency. Lock time is affected by
the filter time constant and by the amount of difference between the two comparator inputs. Whenever
comparator input changes, the synthesizer must re-lock. Lock status is shown by the SLOCK bit in SYNCR.
The MC68HC16Y1 does not come out of reset state until the synthesizer locks. Crystal type, characteristic frequency, and layout of external oscillator circuitry affect lock time.
The low-pass filter requires an external low-leakage capacitor, typically 0.1 µF, connected between the
XFC and VDDSYN pins.
VDDSYN is used to power the clock circuits. A separate power source increases MCU noise immunity
and can be used to run the clock when the MCU is powered down. A quiet power supply must be used
as the VDDSYN source, since PLL stability depends on the VCO, which uses this supply. Adequate external bypass capacitors should be placed as close as possible to the VDDSYN pin to assure stable operating frequency.
When the clock synthesizer is used, control register SYNCR determines operating frequency and various modes of operation. Because the CPU16 in the MC68HC16Y1 operates only in supervisor mode,
SYNCR can be read or written at any time.
The SYNCR X bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting
X doubles clock speed without changing VCO speed — there is no VCO relock delay. The SYNCR W
bit controls a 3-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four.
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The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide
by a value of Y + 1. When either W or Y value changes, there is a VCO relock delay.
Clock frequency is determined by SYNCR bit settings as follows:
FSYSTEM = FREFERENCE [4(Y + 1)(22W + X)]
In order for the device to perform correctly, the clock frequency selected by the W, X, and Y bits must
be within the limits specified for the MCU. Maximum specified clock frequency with a 32.768 kHz reference is 16.78 kHz.
VCO frequency is determined by:
FVCO = FSYSTEM (2 – X), for 32.768 kHz devices.
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The reset state of SYNCR ($3F00) produces a modulus-64 count.
3.4.3 Clock Control
The clock control circuits determine system clock frequency and clock operation under special circumstances, such as loss of synthesizer reference or low-power mode. Clock source is determined by the
logic state of the MODCLK pin during reset.
SYNCR — Clock Synthesizer Control Register
15
14
W
X
13
12
11
10
9
$YFFA04
8
Y
7
6
5
EDIV
0
0
0
0
0
4
3
2
SLIMP SLOCK RSTEN
1
0
STSCIM
STEXT
0
0
RESET:
0
0
1
1
1
1
1
1
U
U
0
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks.
Because the CPU16 always operates in supervisor mode, SYNCR can be read or written at any time.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO
speed by a factor of four. VCO relock delay is required.
X — Frequency Control Bit (Prescale)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles
clock speed without changing VCO speed. There is no VCO relock delay.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y + 1. Values range from 0 to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. See 3.9 Chip Selects for more information.
SLIMP — Limp Mode Flag
0 = External crystal is VCO reference.
1 = Loss of crystal reference.
When the on-chip synthesizer is used, loss of reference frequency will cause SLIMP to be set. The VCO
continues to run using the base control voltage. Maximum limp frequency is maximum specified system
clock frequency. X-bit state affects limp frequency.
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SLOCK — Synthesizer Lock Flag
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency (or system clock is external).
The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer
lock status until after the user writes to SYNCR.
RSTEN — Reset Enable
0 = Loss of crystal causes the MCU to operate in limp mode.
1 = Loss of crystal causes system reset.
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STSCIM — Stop Mode System Integration Clock
0 = When LPSTOP is executed, the SCIM clock is driven from the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SCIM clock is driven from the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven from the SCIM clock, as determined
by the state of the STSCIM bit.
3.4.4 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing
for the PIT is provided by a programmable prescaler driven by the system clock.
PICR — Periodic Interrupt Control Register
15
14
13
12
11
0
0
0
0
0
0
0
0
0
10
$YFFA22
9
8
7
6
5
4
PIRQL
3
2
1
0
1
1
1
1
PIV
RESET:
0
0
0
0
0
0
0
0
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
The table below shows what interrupt request level is asserted when a periodic interrupt is generated.
If a PIT interrupt and an external IRQ of the same priority occur simultaneously, the PIT interrupt is serviced first. The periodic timer continues to run when the interrupt is disabled.
PIRQL
Interrupt Request Level
000
Periodic Interrupt Disabled
001
Interrupt Request Level 1
010
Interrupt Request Level 2
011
Interrupt Request Level 3
100
Interrupt Request Level 4
101
Interrupt Request Level 5
110
Interrupt Request Level 6
111
Interrupt Request Level 7
PIV[7:0] — Periodic Interrupt Vector
The bits of this field contain the vector generated in response to an interrupt from the periodic timer.
When the SCIM responds, the periodic interrupt vector is placed on the bus.
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PITR — Periodic Interrupt Timer Register
$YFFA24
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
PTP
0
0
0
0
0
0
MODCLK
7
6
5
4
3
2
1
0
0
0
0
0
PITM
RESET:
0
0
0
0
0
PITR contains the count value for the periodic timer. A zero value turns off the periodic timer. This register can be read or written at any time.
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PTP — Periodic Timer Prescaler Control
1 = Periodic timer clock prescaled by a value of 512
0 = Periodic timer clock not prescaled
The reset state of PTP is the complement of the state of the MODCLK signal during reset.
PITM[7:0] — Periodic Interrupt Timing Modulus Field
This is an 8-bit timing modulus. The period of the timer can be calculated as follows:
PIT Period = [(PITM)(Prescale)(4)]/EXTAL
where
PIT Period = Periodic interrupt timer period
PITM = Periodic interrupt timer register modulus (PITR[7:0])
EXTAL = Crystal frequency
Prescale = 512 or 1 depending on the state of the PTP bit in the PITR
3.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external devices when the MC68HC16Y1 is operating in expanded modes. In fully expanded mode, the external
bus has 24 address lines and 16 data lines. In partially expanded mode, the external bus has 24 address lines and 8 data lines. Because the CPU16 in the MC68HC16Y1 drives only 20 of the 24 IMB
address lines, ADDR[23:20] follow the output state of ADDR19.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data
transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). In fully expanded
mode, both 8-bit and 16-bit data ports can be accessed; in partially expanded mode, only 8-bit ports
can be accessed. Multiple bus cycles may be required for a transfer to an 8-bit port.
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip select logic can be synchronized with EBI transfers. Chip select logic can also provide internally-generated bus control signals for
these accesses. See 3.9 Chip Selects for more information.
3.5.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
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size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS) is asserted. The table below shows SIZ0 and SIZ1 encoding. The
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for two
consecutive write cycles.
Table 13 Size Signal Encoding
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SIZ1
0
1
1
0
SIZ0
1
0
1
0
Transfer Size
Byte
Word
3 Byte
Long Word
3.5.2 Function Codes
Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can be
considered address extensions that automatically select one of eight address spaces to which an address applies. These spaces are designated as either user or supervisor, and program or data spaces.
Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 to 3 are
not used. Address space 7 is designated CPU space. CPU space is used for control information not
normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
Table 14 CPU16 Address Space Encoding
FC2
1
1
1
1
FC1
0
0
1
1
FC0
0
1
0
1
Address Space
Reserved
Data Space
Program Space
CPU Space
3.5.3 Address Bus
Address bus signals ADDR[19:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted. Because the CPU16 in the MC68HC16Y1 does not drive ADDR[23:20],
these lines follow the logic state of ADDR19.
3.5.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and of many control
signals. It is asserted one-half clock after the beginning of a bus cycle.
3.5.5 Data Bus
Data bus signals DATA[15:0] comprise a bidirectional, non-multiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During
a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For
a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The
MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.5.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
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3.5.7 Bus Cycle Termination Signals
During bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK1
and DSACK0). During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data.
During a write cycle, the signals indicate that an external device has successfully stored data and that
the cycle may terminate. These signals also indicate to the MCU the size of the port for the bus cycle
just completed. (Refer to the discussion of dynamic bus sizing.)
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The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal and internal-to-external transfers. When BERR and HALT
are asserted simultaneously, the CPU16 takes a bus error exception.
Finally, autovector signal (AVEC) can be used to terminate external IRQ pin interrupt acknowledge cycles. AVEC indicates that the MCU will internally generate a vector number to locate an interrupt handler
routine. If it is continuously asserted, autovectors will be generated for all external interrupt requests.
AVEC is ignored during all other bus cycles.
3.5.8 Data Transfer Mechanism
The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit
data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge
inputs (DSACK1and DSACK0).
3.5.9 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK0
and DSACK1 inputs, as shown in the following table.
Table 15 Effect of DSACK Signals
DSACK1
1
1
0
0
DSACK0
1
0
1
0
Result
Insert Wait States in Current Bus Cycle
Complete Cycle — Data Bus Port Size is 8 Bits
Complete Cycle — Data Bus Port Size is 16 Bits
Reserved
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 for a 16-bit port (regardless of whether the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0], and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word operation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are designated as shown in the figure below. OP0 is the most significant byte of a long-word operand, and OP3
is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1.
The single byte of a byte-length operand is OP0.
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Operand
31
Long Word
Three Byte
Word
Byte
24
OP0
23
Byte Order
16
15
8
OP1
OP2
OP0
OP1
OP0
7
0
OP3
OP2
OP1
OP0
Figure 6 Operand Byte Order
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3.5.10 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address and
data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the
remaining number of bytes to be transferred during the current bus cycle. The number of bytes transferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the
byte offset from the base. Bear in mind the fact that ADDR[23:20] follow the state of ADDR19 in the
MC68HC16Y1.
3.5.11 Misaligned Operands
CPU16 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even address), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address
is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is
misaligned at an odd address.
In the MC68HC16Y1, the largest amount of data that can be transferred by a single bus cycle is an
aligned word. If the MCU transfers a long-word operand via a 16-bit port, the most significant operand
word is transferred on the first bus cycle and the least significant operand word on a following bus cycle.
The CPU16 can perform misaligned word transfers. This capability makes it software compatible with
the MC68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
3.5.12 Operand Transfer Cases
The following table summarizes how operands are aligned for various types of transfers. OPn entries
are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1,
SIZ0, and ADDR0 for that bus cycle.
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Table 16 Operand Transfer Cases
Transfer Case
SIZ1
3 Byte to 8-bit Port (Aligned)2
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
X
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
X
X
0
0
X
X
0
DATA
[15:8]
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
3 Byte to 8-bit Port (Misaligned)2
1
1
1
1
0
OP0
(OP0)
3 Byte to 16-bit Port (Aligned)3
1
1
0
0
X
OP0
OP1
3 Byte to 16-bit Port (Misaligned)2
Long Word to 8-bit Port (Aligned)
1
1
1
0
X
(OP0)
OP0
0
1
0
0
0
1
1
1
0
0
OP0
OP0
(OP1)
(OP0)
0
1
0
0
0
1
0
0
X
X
OP0
(OP0)
OP1
OP0
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Byte to 8-bit Port (Even/Odd)
Byte to 16-bit Port (Even)
Byte to 16-bit Port (Odd)
Word to 8-bit Port (Aligned)
Word to 8-bit Port (Misaligned)
Word to 16-bit Port (Aligned)
Word to 16-bit Port (Misaligned)
(Misaligned)3
Long Word to 8-bit Port
Long Word to 16-bit Port (Aligned)
Long Word to 16-bit Port
(Misaligned)3
SIZ0 ADDR0 DSACK1
DSACK0
DATA
[7:0]
(OP0)
(OP0)
OP0
(OP1)
(OP0)
OP1
OP0
(OP1)
NOTES:
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
3. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
3.6 Reset
Reset procedures handle system initialization and recovery from catastrophic failure. The
MC68HC16Y1 performs resets with a combination of hardware and software. The SCIM determines
whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM selection based on hardware mode-select inputs, then passes control to the CPU16.
Reset occurs when an active low logic level on the RESET pin is clocked into the SCIM. Resets are
gated by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous
reset can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If
there is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are
clocked to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset exception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
SCIM Reset Mode Selection
The logic states of certain MCU pins during reset determine SCIM operating configuration. Refer to 3.2
Operating Modes for more information.
3.6.1 MCU Module Pin Function During Reset
As a general rule, module pins default to port functions, and input/output ports are set to input state.
This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the
appropriate port data direction registers. Refer to individual module sections in this technical summary
for more information. The following table is a summary of module pin functions out of reset.
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Table 17 Module Pin Functions
Module
Pin Mnemonic
Function
ADC
PADA[7:0]/AN[7:0]
DISCRETE INPUT
VRH
REFERENCE VOLTAGE
VRL
REFERENCE VOLTAGE
CPU
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GPT
MCCI
TPU
DSI/IPIPE1
DSI/IPIPE1
DSO/IPIPE0
DSO/IPIPE0
BKPT/DSCLK
BKPT/DSCLK
PGP7/IC4/OC5
DISCRETE INPUT
PGP[6:3]/OC[4:1]
DISCRETE INPUT
PGP[2:0]/IC[3:1]
DISCRETE INPUT
PAI
DISCRETE INPUT
PCLK
DISCRETE INPUT
PWMA, PWMB
DISCRETE OUTPUT
PMC7/TXDA
DISCRETE INPUT
PMC6/RXDA
DISCRETE INPUT
PMC5/TXDB
DISCRETE INPUT
PMC4/RXDB
DISCRETE INPUT
PMC3/SS
DISCRETE INPUT
PMC2/SCK
DISCRETE INPUT
PMC1/MOSI
DISCRETE INPUT
PMC0/MISO
DISCRETE INPUT
TP[15:0]
TPU INPUT
3.6.2 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in an inactive, high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512
cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert
RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cycles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,
reset exception processing begins. If, however, the reset input is at logic level zero, the reset control
logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to highimpedance state for 10 cycles, then it is tested again. The process repeats until RESET is released.
3.6.3 Power-On Reset
When the SCIM clock synthesizer is used to generate system clocks, power-on reset involves special
circumstances related to application of system and clock synthesizer power. Regardless of clock
source, voltage must be applied to clock synthesizer power input pin VDDSYN, so that the MCU can op-
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erate. The following discussion assumes that VDDSYN is applied before and during reset. This minimizes
crystal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific crystal
parameters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset.
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During power-on reset, an internal circuit in the SCIM drives the IMB internal and external reset lines.
The circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SCIM
pins are initialized. When VDD reaches the specified minimum value, the clock synthesizer VCO begins
operation. Clock frequency ramps up to the specified limp mode frequency. The external RESET line
remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SCIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and
VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15
milliseconds. During this period, module port pins may be in an indeterminate state. While input-only
pins can be put in a known state by means of external pull-up resistors, external logic on input/output
or output-only pins must condition the lines during this time. Active drivers require high-impedance buffers or isolation resistors to prevent conflict.
3.6.4 Use of Three State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for ten clock cycles for drivers to change state.
There are certain constraints on use of TSC during power-up reset:
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer rampup time affects how long the ten cycles take. Worst case is approximately 20 milliseconds from TSC
assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-impedance state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin.
When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent
mode selection. Once the output drivers change state, the MCU must be powered down and restarted before normal operation can resume.
3.7 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit, the
system integration module, and a device or module requesting interrupt service.
The CPU16 provides for eight levels of interrupt priority (0–7), seven automatic interrupt vectors, and
200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the interrupt priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asynchronous exception.
Interrupt recognition is based on the states of interrupt request signals IRQ[7:1] and the IP mask value.
Each of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the
highest priority.
The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks.
Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7)
from being recognized and processed. When IP contains %000, no interrupt is masked. During exception processing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Request
lines are connected internally by a wired NOR. Simultaneous requests with different priorities can be
made. Internal assertion of an interrupt request signal does not affect the logic state of the corresponding MCU pin.
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External interrupt requests are routed to the CPU16 through the external bus interface and SCIM interrupt control logic. The CPU treats external interrupt requests as though they had come from the SCIM.
External IRQ[6:1] are active-low level-sensitive inputs. External IRQ7 is an active-low transition-sensitive input. It requires both an edge and a voltage level for validity.
IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive to prevent redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted,
and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
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Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock
periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request of equal or lower priority than the current IP mask value is made, the
CPU does not recognize the occurrence of the request in any way.
3.7.1 Interrupt Acknowledge and Arbitration
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs
a CPU space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest
priority interrupt request on the address bus, and it acquires an exception vector number from the interrupt source. The mask value also serves two purposes: it is latched into the CCR IP field to mask lowerpriority interrupts during exception processing, and it is decoded by modules that have requested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the
beginning of the interrupt acknowledge cycle. If their requests are at the specified IP level, they respond
to the cycle. Arbitration between simultaneous requests of the same priority is performed by serial contention between module interrupt arbitration (IARB) field bit values.
Each module that can make an interrupt service request, including the SCIM, has an IARB field in its
configuration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111
(highest priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious interrupt
exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SCIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SCIM is %1111. The reset IARB value for all other modules is %0000. Initialization software must assign different IARB values
to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same nonzero
value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable consequences.
Arbitration must always take place, even when a single source requests service. This point is important
for two reasons: the CPU interrupt acknowledge cycle to is not driven on the external bus unless the
SCIM wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data
bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt ac-
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knowledge cycle is transferred to the external bus, an external device must decode the mask value and
respond with a vector number, then generate bus cycle termination signals. If the device does not respond in time, a spurious interrupt exception is taken.
The periodic interrupt timer (PIT) in the SCIM can generate internal interrupt requests of specific priority
at predetermined intervals. By hardware convention, PIT interrupts are serviced before external interrupt service requests of the same priority. Refer to 3.4.4 Periodic Interrupt Timer for more information.
3.7.2 Interrupt Processing Summary
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A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
3. Request priority is latched into the CCR IP field from the address bus.
D. Modules or external peripherals that have requested interrupt service decode the priority value
in ADDR[3:1]. If request priority is the same as the priority value in the address, IARB contention
takes place. When there is no contention, the spurious interrupt monitor asserts BERR, and a
spurious interrupt exception is processed.
E. After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
1. The dominant interrupt source supplies a vector number and DSACKx signals appropriate
to the access. The CPU16 acquires the vector number.
2. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source
or the pin can be tied low), and the CPU16 generates an autovector number corresponding
to interrupt priority.
3. The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector
number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
the exception handler routine.
3.8 General-Purpose Input/Output
The SCIM contains six general-purpose input/output ports: ports A, B, E, F, G, and H. (Port C, an outputonly port, is included under the discussion of chip selects.) Ports A, B, and G are available in single-chip
mode only, and Port H is available in single-chip or 8-bit expanded modes only. Ports E, F, G, and H
have an associated data direction register (DDR) to configure each pin as input or output. Ports A and
B share a DDR that configures each port as input or output. Ports E and F have associated pin assignment registers which configure each pin as digital I/O or an alternate function. Port F has an edge-detect
flag register which indicates whether a transition has occurred on any of its pins.
The following table shows the shared functions of the general-purpose I/O ports and the modes in which
they are available.
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Table 18 General-Purpose I/O Ports
Port
A
B
E
F
G
H
Shared Function
ADDR[18:11]
ADDR[10:3]
Bus control
IRQ[7:1]/MODCLK
DATA[15:8]
DATA[7:0]
Modes
Single chip
Single chip
All
All
Single chip
Single chip, 8-bit expanded
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Access to port A, B, E, G, and H data and data direction registers and port E pin assignment register
requires three clock cycles, to ensure timing compatibility with external port replacement logic. Port registers are byte-addressable and are grouped to allow coherent word access to port data register pairs
A-B and G-H, as well as word-aligned long word coherency of A-B-G-H port data registers. Port registers are not affected by CPU reset.
If emulator mode is enabled, accesses to ports A, B, E, G, and H data and data direction registers and
port E pin assignment register are ignored, and can be replaced with external logic, such as a Motorola
Port Replacement Unit. Port F registers remain accessible.
A write to port A, B, E, F, G, or H data register is stored in the internal data latch, and if any port pin is
configured as an output, the value stored for that bit is driven on the pin. A read of the port data register
returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is
the value stored in the register.
3.8.1 Ports A and B
Ports A and B are available in single-chip mode only. One data direction register controls data direction
for both ports. Port A and B registers can be read or written at any time the MCU is not in emulator mode.
PORTA — Port A Data Register
7
PA7
RESET:
U
$YFFA0A
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
0
PA0
U
U
U
U
U
U
U
PORTB — Port B Data Register
7
PB7
RESET:
U
$YFFA0B
6
PB6
5
PB5
4
PB4
3
PB3
2
PB2
1
PB1
0
PB0
U
U
U
U
U
U
U
DDRAB — Port A/B Data Direction Register
7
0
RESET:
0
$YFFA14
6
0
5
0
4
0
3
0
2
0
1
DDA
0
DDB
0
0
0
0
0
0
0
DDA and DDB control the direction of the pin drivers for ports A and B, respectively, when the pins are
configured for I/O. Setting DDA or DDB configures all pins in the corresponding port as outputs. Clearing DDA or DDB to zero configures all pins in the corresponding port as inputs.
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3.8.2 Port E
Port E can be made available in all operating modes. The state of BERR and DATA8 during reset controls whether the port E pins are used as bus control signals or discrete I/O lines.
If the MCU is in emulator mode, an access of the port E data, data direction, or pin assignment registers
(PORTE, DDRE, PEPAR) is forced to go external. This allows port replacement logic to be supplied externally, giving an emulator access to the bus control signals.
PORTE — Port E Data Register
7
PE7
RESET:
U
$YFFA11, $YFFA13
6
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
0
PE0
U
U
U
U
U
U
U
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PORTE is a single register that can be accessed in two locations. It can be read or written at any time
the MCU is not in emulator mode.
DDRE — Port E Data Direction Register
7
DDE7
RESET:
0
$YFFA15
6
DDE6
5
DDE5
4
DDE4
3
DDE3
2
DDE2
1
DDE1
0
DDE0
0
0
0
0
0
0
0
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input. This register can be read or written at any
time the MCU is not in emulator mode.
PEPAR — Port E Pin Assignment Register
7
6
5
PEPA7
PEPA6
PEPA5
RESET (Expanded, Single-chip):
DATA8
DATA8
DATA8
0
0
0
$YFFA17
4
PEPA4
3
PEPA3
2
PEPA2
1
PEPA1
0
PEPA0
DATA8
0
DATA8
0
DATA8
0
DATA8
0
DATA8
0
The bits in this register control the function of each port E pin. Any bit set to one defines the corresponding pin to be a bus control signal, with the function shown in the following table. Any bit cleared to zero
defines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
Table 19 Port E Pin Assignments
PEPAR Bit
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
Port E Signal
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Bus Control Signal
SIZ1
SIZ0
AS
DS
—*
AVEC
DSACK1
DSACK0
* When PEPA3 is set, the PE3 pin goes to logic level one. The CPU16 does not support the control function for this
pin.
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BERR and DATA8 control the state of this register following reset. If BERR and/or DATA8 are low during
reset, this register is set to $00, defining all port E pins to be I/O pins. If BERR and DATA8 are both high
during reset, the register is set to $FF, which defines all port E pins to be bus control signals.
3.8.3 Port F
Port F pins can be configured as interrupt request inputs, edge-detect input/outputs, or discrete input/
outputs. When port F pins are configured for edge detection, and a priority level is specified by writing
a value to the Port F edge-detect interrupt level register (PFLVR), port F control logic generates an interrupt request when the specified edge is detected. Interrupt vector assignment is made by writing a
value to the Port F edge-detect interrupt vector register (PFIVR). The edge-detect interrupt has the lowest arbitration priority in the SCIM.
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PORTF — Port F Data Register
7
PF7
RESET:
U
$YFFA19, $YFFA1B
6
PF6
5
PF5
4
PF4
3
PF3
2
PF2
1
PF1
0
PF0
U
U
U
U
U
U
U
A write to the port F data register is stored in the internal data latch, and if any port F pin is configured
as an output, the value stored for that bit is driven on the pin. A read of PORTF returns the value on a
pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the
data register.
Port F is a single register that can be accessed in two locations. It can be read or written at any time,
including when the MCU is in emulator mode.
DDRF — Port F Data Direction Register
7
DDF7
RESET:
0
$YFFA1D
6
DDF6
5
DDF5
4
DDF4
3
DDF3
2
DDF2
1
DDF1
0
DDF0
0
0
0
0
0
0
0
The bits in this register control the direction of Port F pin drivers when the pins are configured for I/O.
Setting any bit in this register configures the corresponding pin as an output. Clearing any bit in this register configures the corresponding pin as an input.
PFPAR — Port F Pin Assignment Register
7
6
5
4
PFPA3
PFPA2
RESET (Expanded, Single-chip):
DATA9
DATA9
DATA9
DATA9
0
0
0
0
$YFFA1F
3
2
1
PFPA1
DATA9
0
0
PFPA0
DATA9
0
DATA9
0
DATA9
0
The fields in this register determine the functions of pairs of port F pins as shown in the following tables.
BERR and DATA9 determine the reset state of this register. If BERR and/or DATA9 are low during reset,
this register is set to $00, defining all port F pins to be I/O pins. If BERR and DATA9 are both high during
reset, the register is set to $FF, which defines all port F pins except PF0 to be interrupt signals.
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Table 20 Port F Pin Assignments
PFPAR Field
PFPA3
PFPA2
PFPA1
PFPA0
Port F Signal
PF[7:6]
PF[5:4]
PF[3:2]
PF[1:0]
Alternate Signal
IRQ[7:6]
IRQ[5:4]
IRQ[3:2]
IRQ1, MODCLK*
*MODCLK signal is only recognized during reset
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Table 21 PFPAR Pin Functions
PFPAx Bits
00
01
10
11
Port F Signal
I/O pin without edge detect
Rising edge detect
Falling edge detect
Interrupt request
PORTFE —Port F Edge-Detect Flag Register
7
EF7
RESET:
0
$YFFA2B
6
EF6
5
EF5
4
EF4
3
EF3
2
EF2
1
EF1
0
EF0
0
0
0
0
0
0
0
When the corresponding pin is configured for edge detection, a PORTFE bit is set if an edge is detected.
PORTFE bits remain set, regardless of the subsequent state of the corresponding pin, until cleared. To
clear a bit, first read PORTFE, then write the bit to zero. When a pin is configured for general-purpose
I/O or for use as an interrupt request input, PORTFE bits do not change state.
PFIVR — Port F Edge-Detect Interrupt Vector Register
7
PFIVR7
RESET:
0
$YFFA2B
6
PFIVR6
5
PFIVR5
4
PFIVR4
3
PFIVR3
2
PFIVR2
1
PFIVR1
0
PFIVR0
0
0
0
1
1
1
1
This register determines which vector in the exception vector table is used for interrupts generated by
the port F edge-detect logic. Program PFIVR[7:0] to the value pointing to the appropriate interrupt vector. See the CPU16 section of this summary for interrupt vector assignments.
PFLVR — Port F Edge-Detect Interrupt Level Register
7
0
RESET:
0
$YFFA2D
6
0
5
0
4
0
3
0
2
PFLV2
1
PFLV1
0
PFLV0
0
0
0
0
0
0
0
PFLVR determines the priority level of the port F edge-detect interrupt. The reset value is $00, indicating
that the interrupt is disabled. When several sources of interrupts from the SCIM are arbitrating for the
same level, the port F edge-detect interrupt has the lowest arbitration priority.
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3.8.4 Port G
Port G is available in single-chip mode only. In single-chip mode, these pins are always configured for
general-purpose I/O.
PORTG — Port G Data Register
7
PG7
RESET:
U
$YFFA0C
6
PG6
5
PG5
4
PG4
3
PG3
2
PG2
1
PG1
0
PG0
U
U
U
U
U
U
U
This register can be read or written anytime the MCU is not in emulator mode.
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DDRG — Port G Data Direction Register
7
DDG7
RESET:
0
$YFFA0E
6
DDG6
5
DDG5
4
DDG4
3
DDG3
2
DDG2
1
DDG1
0
DDG0
0
0
0
0
0
0
0
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input.
3.8.5 Port H
Port H is available in single-chip and 8-bit expanded modes only. The function of these pins is determined by operating mode — there is no pin assignment register associated with this port.
PORTH — Port H Data Register
7
PH7
RESET:
U
$YFFA0D
6
PH6
5
PH5
4
PH4
3
PH3
2
PH2
1
PH1
0
PH0
U
U
U
U
U
U
U
This register can be read or written anytime the MCU is not in emulator mode. Reset has no effect.
DDRH — Port H Data Direction Register
7
DDH7
RESET:
0
$YFFA0F
6
DDH6
5
DDH5
4
DDH4
3
DDH3
2
DDH2
1
DDH1
0
DDH0
0
0
0
0
0
0
0
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input.
3.9 Chip Selects
Typical microcontrollers require additional hardware to provide external chip select signals. The
MC68HC16Y1 includes nine programmable chip select circuits that can provide 2 to 13 clock cycle access to external memory and peripherals. Two additional chip selects CSE and CSM provide emulator
support. Address block sizes of 2 Kbytes to 1 Mbyte can be selected. However, because ADDR[23:20]
= ADDR19 in the CPU16, 512-Kbyte blocks are the largest usable size.
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Chip select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single
DSACK generator is shared by all circuits — multiple chip selects assigned to the same address and
control must have the same number of wait states. Chip selects can also be synchronized with the
ECLK signal available on ADDR23.
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When a memory access occurs, chip select logic compares address space type, address, type of access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip select registers. If all parameters match, the appropriate chip select signal is asserted. Select signals are active low. A block diagram of a chip select circuit is shown below.
INTERNAL
SIGNALS
BASE ADDRESS REGISTER
ADDRESS
ADDRESS COMPARATOR
BUS CONTROL
OPTION COMPARE
TIMING
AND
CONTROL
PIN
OPTION REGISTER
1 OF 12
AVEC
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
DSACK
CHIP SEL BLOCK
Figure 7 Chip Select Circuit Block Diagram
If a chip select function is given the same address as a microcontroller module or memory array, an
access to that address will go to the module or array, and the chip select signal will not be asserted.
Each chip select pin can have two or more functions. Chip select configuration out of reset is determined
by operating mode. In all modes, the boot ROM select signal is automatically asserted out of reset. In
single-chip mode, all chip select pins except CS10 and CS0 are configured for alternate functions or
discrete output. In expanded modes, appropriate pins are configured for chip select operation, but chip
select signals cannot be asserted until a transfer size is chosen. In fully expanded mode, data bus pins
can be held low to enable alternate functions for chip select pins.
The following table shows allocation of chip selects and discrete outputs to MCU pins.
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Table 22 Chip Select Pin Allocation
Chip Select
Function
CSBOOT
CS0
CSM
CSE
CS3
—
CS5
CS6
CS7
CS8
CS9
CS10
Alternate
Function
CSBOOT
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
Discrete Outputs
Function
—
—
—
—
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
3.10 Emulation Mode Chip Select Signals
Emulation mode chip select signals are used during external register or ROM emulation. Pin function is
controlled by a chip select pin assignment register, but the other chip select registers do not affect these
signals.
During emulator mode operation, all port A, B, E, G, and H data and data direction registers, and the
port E pin assignment register are mapped externally. The emulator chip select signal CSE is asserted
when any of these registers is addressed. The SCIM does not respond to these accesses — an external
device, such as a port replacement unit, can respond instead. See 3.3 Emulation Support for more
information.
An internal module chip select signal CSM can also be enabled during emulator mode operation. When
the ROM module is enabled, CSM is asserted when an access to an address assigned to the masked
ROM array is made — this allows an external device to emulate the ROM. Internal DSACK is generated
by the ROM module after it has inserted the number of wait states specified by the WAIT field in the
MRMCR. See 9 Masked ROM Module for more information.
3.10.1 Chip Select Registers
Pin assignment registers (CSPAR) determine functions of chip select pins. Pin assignment registers
also determine port size (8- or 16-bit) for dynamic bus allocation.
A pin data register (PORTC) latches discrete output data.
Blocks of addresses are assigned to each chip select function. Block sizes of 2 Kbytes to 1 Mbyte can
be selected by writing values to the appropriate base address register (CSBAR). However, because the
logic state of ADDR20 is always the same as the state of ADDR19 in the MC68HC16Y1, the largest
usable block size is 512 Kbytes. Address blocks for separate chip select functions can overlap.
Chip select option registers (CSOR) determine timing of and conditions for assertion of chip select signals. Eight parameters, including operating mode, access size, synchronization, and wait state insertion
can be specified.
Initialization code often resides in a peripheral memory device controlled by the chip select circuits. A
set of special chip select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap
operation.
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3.10.2 Pin Assignment Registers
The pin assignment registers contain pairs of bits that determine the functions of chip select pins. Alternate functions of the associated pins are shown in parentheses. Reset value depends on the operating
mode.
In the following register diagrams, reset values are shown in the following order: single-chip modes, partially expanded mode, and fully expanded mode. The notation “DATA#” indicates that a bit goes to the
logic level of that data bus pin on reset. DATA lines have weak pull-ups — during reset in fully expanded
mode, an active external device can pull the data lines low to select alternate functions.
CSPAR0 — Chip Select Pin Assignment Register 0
15
14
0
0
13
12
CS5
(FC2)
11
10
0
FC1
9
8
CS3
(FC0)
$YFFA44
7
6
5
CSE
(BGACK)
4
3
CSM
(BG)
2
CS0
(BR)
1
0
CSBOOT
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RESET:
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
0
DATA2
1
0
1
DATA2
1
DATA10
1
DATA10
1
DATA2
1
1
DATA0
CSPAR0[15:14] — Not used.
These bits always read zero; write has no effect.
CSPAR011 — Not used.
CSPAR010 determines whether pin is FC1 or a discrete output.
CSPAR1 — Chip Select Pin Assignment Register 1
8
$YFFA46
15
14
13
12
11
10
9
0
0
0
0
0
0
CS10
(ADDR23)
7
CS9
(ADDR22)
6
5
CS8
(ADDR21)
4
3
CS7
(ADDR20)
2
1
CS6
(ADDR19)
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
RESET:
DATA7
1
DATA6
1
DATA5
1
DATA4
1
DATA3
1
CSPAR1[15:10] — Not used.
These bits always read zero; write has no effect. Clearing both CS10 select bits (CSPAR1[9:8]) enables
the M6800 bus clock (ECLK) on ADDR23.
The table below shows pin assignment register encoding.
Bit Pair
Description
00
Discrete Output
01
Alternate Function
10
Chip Select (8-Bit Port)
11
Chip Select (16-Bit Port)
A pin programmed as a discrete output drives an external signal to the value specified in the Port C data
register (PORTC), with the following exceptions:
• No discrete output function is available on pins BR, BG, or BGACK.
• ADDR23 provides ECLK output rather than a discrete output signal.
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Internal chip select logic is inhibited when discrete output or alternate function are assigned.
Port size is determined when a pin is assigned as a chip select. When a pin is assigned to an 8-bit port,
the chip select is asserted at all addresses within the block range. If a pin is assigned to a 16-bit port,
the upper/lower byte field of the option register selects the byte with which the chip select is associated.
3.10.3 Base Address Registers
A base address is the starting address for the block enabled by a given chip select. Block size determines the extent of the block above the base address. Each chip select has an associated base register,
so that an efficient address map can be constructed for each application. If a chip select is assigned an
address used by a microcontroller module, the module has priority — the chip select does not respond
to an access.
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CSBARBT — Chip Select Base Address Register Boot ROM
$YFFA48
15
14
13
12
11
10
9
8
7
6
5
4
3
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
0
0
0
0
0
0
0
0
0
0
0
2
1
0
BLKSZ
RESET:
0
0
CSBAR0 – CSBAR10 — Chip Select Base Address Registers
1
1
1
$YFFA4C–$YFFA74
15
14
13
12
11
10
9
8
7
6
5
4
3
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
0
0
0
0
0
0
0
0
0
0
0
2
1
0
BLKSZ
RESET:
0
0
0
0
0
ADDR[23:20] will be at the same logic level as ADDR19 during internal CPU master operation. ADDR[23:20] must match ADDR19 for the chip select to be active.
BLKSZ — Block Size Field
This field determines the size of the block above the base address that must be enabled by the chip
select. The table below shows bit encoding for the base address registers block size field.
Block Size Field
000
001
010
011
100
101
110
111
Block Size
2K
8K
16 K
64 K
128 K
256 K
512 K
512 K
Address Lines Compared
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
ADDR[23:20] will be at the same logic level as ADDR19 during normal operation.
ADDR[15:3] — Base Address Field
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block — the value of the base address must be a
multiple of block size. Base address register diagrams show how base register bits correspond to address lines.
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Because ADDR20 = ADDR19 in the CPU16, maximum block size is 512 Kbytes. Because ADDR[23:20]
follow the logic state of ADDR19, if all 24 address lines are used, addresses from $080000 to $F7FFFF
are inaccessible.
3.10.4 Option Registers
The option registers contain eight fields that determine timing of and conditions for assertion of chip select signals. These make the chip selects useful for generating peripheral control signals. Certain constraints set by fields in the base address register and in the option register must be satisfied in order to
assert a chip select signal, and to provide DSACK or autovector support.
CSORBT — Chip Select Option Register Boot ROM
15
14
MODE
13
12
BYTE
11
R/W
10
9
$YFFA4A
8
STRB
7
6
5
DSACK
4
3
SPACE
2
1
IPL
0
AVEC
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RESET:
0
1
1
1
1
0
1
1
0
1
1
1
0
CSOR0 – CSOR10 — Chip Select Option Registers
15
14
MODE
13
12
BYTE
11
R/W
10
9
0
0
$YFFA4E–$YFFA76
8
STRB
0
7
6
5
DSACK
4
3
SPACE
2
1
IPL
0
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The option register for CSBOOT, CSORBT, contains special reset values that support bootstrap operations from peripheral memory devices.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected
1 = Synchronous mode selected
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
In synchronous mode, the DSACK field is not used, because a bus cycle is only performed as a synchronous operation. When a match condition occurs on a chip select programmed for synchronous operation, the chip select signals the EBI that an E-clock cycle is pending.
BYTE — Upper/Lower Byte Option
This field is used only when the chip select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
Byte
00
01
10
11
Description
Disable
Lower Byte
Upper Byte
Both Bytes
R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
The table below shows the options.
R/W
00
01
10
11
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Description
Reserved
Read Only
Write Only
Read/Write
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STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe causes chip select to be asserted synchronized with data strobe.
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DSACK — Data Strobe Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to optimize bus speed in a particular application. The following table shows the DSACK field encoding. A nowait encoding (%0000) corresponds to a three clock-cycle bus. The fast termination encoding (%1110)
corresponds to a two clock-cycle bus — microcontroller modules typically respond at this rate, but fast
termination can also be used to access fast external memory.
DSACK
Description
0000
No Wait States
0001
1 Wait State
0010
2 Wait States
0011
3 Wait States
0100
4 Wait States
0101
5 Wait States
0110
6 Wait States
0111
7 Wait States
1000
8 Wait States
1001
9 Wait States
1010
10 Wait States
1011
11 Wait States
1100
12 Wait States
1101
13 Wait States
1110
Fast Termination
1111
External DSACK
SPACE — Address Space
This option field is used to select an address space to be used by the chip select logic. The CPU16 normally operates in supervisor space — all space types can be used. Interrupt acknowledge cycles take
place in CPU space.
Space Field
Address Space
00
CPU Space
01
User Space
10
Supervisor Space
11
Supervisor/User Space
IPL — Interrupt Priority Level
When the space field is set for CPU space (%00), chip select logic can be used for interrupt acknowledge. During an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared
to the value in the IPL field. If the values are the same, then a chip select can be asserted, provided
other option register conditions are met. When the Space field has any value except %00, the IPL field
determines whether an access takes place in program or data space. The following table shows IPL field
encoding.
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IPL
Space = 00
Space = 01, 10, 11
000
All
Data or Program
001
IPL1
Data
010
IPL2
Program
011
IPL3
Reserved
100
IPL4
Reserved
101
IPL5
Data
110
IPL6
Program
111
IPL7
Reserved
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This field only affects the response of chip selects and does not affect interrupt recognition by the CPU.
“All” means that a chip select signal is asserted regardless of the priority of the interrupt.
AVEC — Autovector Enable
0 = External interrupt vector enabled
1 = Autovector enabled
This field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge
cycle. It is not generally used in conjunction with a chip select pin.
If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE = %00) and the
AVEC field is set to one, the chip select automatically generates an AVEC in response to the interrupt
acknowledge cycle. Otherwise, the vector must be supplied by the requesting device.
PORTC — Port C Data Register
7
0
RESET:
0
$YFFA41
6
PC6
5
PC5
4
PC4
3
PC3
2
PC2
1
PC1
0
PC0
1
1
1
1
1
1
1
The pin data register controls the state of pins programmed as Port C discrete outputs. When a pin is
assigned as a discrete output, the value in this register appears at the output. PC[6:0] correspond to
pins CS[9:3]. This is a read/write register. Bit 7 is not used. Writing to this bit has no effect, and it always
reads zero.
3.10.5 Chip Select Reset Operation
The reset values of the chip select pin assignment fields in CSPAR0 and CSPAR1 depend on the operating mode selected. Refer to the discussion of these registers for more information.
The CSBOOT assignment field in CSPAR0 is configured differently. The MSB, bit 1 of CSPAR0, is always one. This enables the CSBOOT signal to select a boot ROM containing initialization firmware. The
LSB value, determined by the logic level of DATA0 during reset, selects boot ROM port size. When
DATA0 is held low, port size is eight bits. When internal connections pull the LSB high, port size is 16
bits.
After reset, the MCU fetches initialization vectors from addresses $0000 to $0006 in bank 0 of program
space. To support bootstrap operation from reset, the base address field in chip select base register
boot (CSBARBT) has a reset value of all zeros. A ROM device containing vectors located at these addresses can be enabled by CSBOOT after a reset. The block size field in CSBARBT has a reset value
of 512 Kbytes.
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The byte field in option register CSORBT has a reset value of both bytes, but CSOR[10:0] have a reset
value of disable, since they should not select external devices until an initial program sets up the base
and option registers. The following table shows the reset values in the base and option registers for CSBOOT.
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Table 23 Chip Select Reset Values
Field
Base Address
Block Size
Async/Sync Mode
Upper/Lower Byte
Read/Write
AS/DS
DSACK
Address Space
IPL
Autovector
Reset Value
$0000 0000
512 Kbyte
Asynchronous Mode
Both Bytes
Read/Write
AS
13 Wait States
Supervisor/User
All
External Interrupt Vector
3.11 Factory Test
Test functions are integrated into the SCIM to support scan-based testing of the various MCU modules
during production. Test submodule registers are intended for Motorola use. Register names and addresses are provided to show the user that these addresses are occupied.
SCIMTR — Single-Chip Integration Module Test Register
$YFFA02
SCIMTRE — Single-Chip Integration Module Test Register (E Clock)
$YFFA08
TSTMSRA — Master Shift Register A
$YFFA30
TSTMSRB — Master Shift Register B
$YFFA32
TSTSC — Test Module Shift Count
$YFFA34
TSTRC — Test Module Repetition Count
$YFFA36
CREG — Test Submodule Control Register
$YFFA38
DREG — Distributed Register
$YFFA3A
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4 Time Processor Unit
The time processor unit (TPU) provides optimum performance in controlling time-related activity. The
TPU contains a dedicated execution unit, a tri-level prioritized scheduler, data storage RAM, dual-time
bases, and microcode ROM. The TPU controls 16 independent, orthogonal channels, each with an associated I/O pin, and is capable of performing any time function. Each channel also contains a dedicated event register, allowing both match and input capture functions. A block diagram of the TPU follows.
HOST
INTERFACE
CONTROL
SCHEDULER
SERVICE REQUESTS
TIMER
CHANNELS
CHANNEL 0
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IMB
CHANNEL
SYSTEM
CONFIGURATION
TCR1
CHANNEL 1
TCR2
PIN
DEVELOPMENT
SUPPORT AND TEST
PINS
MICROENGINE
CHANNEL
CONTROL
DATA
PARAMETER
RAM DATA
CONTROL
STORE
CONTROL AND DATA
EXECUTION
UNIT
CHANNEL 15
TPU BLOCK
Figure 8 TPU Simplified Block Diagram
Table 24 TPU Address Map
Address
$YFFE00
$YFFE02
$YFFE04
$YFFE06
$YFFE08
$YFFE0A
$YFFE0C
$YFFE0E
$YFFE10
$YFFE12
$YFFE14
$YFFE16
$YFFE18
$YFFE1A
$YFFE1C
$YFFE1E
$YFFE20
$YFFE22
$YFFE24
$YFFE26
15
8 7
TPU MODULE CONFIGURATION REGISTER (TPUMCR)
TEST CONFIGURATION REGISTER (TCR)
DEVELOPMENT SUPPORT CONTROL REGISTER (DSCR)
DEVELOPMENT SUPPORT STATUS REGISTER (DSSR)
TPU INTERRUPT CONFIGURATION REGISTER (TICR)
CHANNEL INTERRUPT ENABLE REGISTER (CIER)
CHANNEL FUNCTION SELECTION REGISTER 0 (CFSR0)
CHANNEL FUNCTION SELECTION REGISTER 1 (CFSR1)
CHANNEL FUNCTION SELECTION REGISTER 2 (CFSR2)
CHANNEL FUNCTION SELECTION REGISTER 3 (CFSR3)
HOST SEQUENCE REGISTER 0 (HSQR0)
HOST SEQUENCE REGISTER 1 (HSQR1)
HOST SERVICE REQUEST REGISTER 0 (HSRR0)
HOST SERVICE REQUEST REGISTER 1 (HSRR1)
CHANNEL PRIORITY REGISTER 0 (CPR0)
CHANNEL PRIORITY REGISTER 1 (CPR1)
CHANNEL INTERRUPT STATUS REGISTER (CISR)
LINK REGISTER (LR)
SERVICE GRANT LATCH REGISTER (SGLR)
DECODED CHANNEL NUMBER REGISTER (DCNR)
0
Y = M111, where M is the state of the MODMAP bit in the SCIMCR (Y = $7 or $F)
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4.1 TPU ROM Functions
4.1.1 Discrete Input/Output (DIO)
When a pin is used as a discrete input, a parameter indicates the current input level and the previous
15 levels of a pin. Bit 15, the most significant bit of the parameter, indicates the most recent state. Bit
14 indicates the next most recent state, and so on.
4.1.2 Input Capture/Input Transition Counter (ITC)
Any channel of the TPU can capture the value of a specified TCR upon the occurrence of each transition, and then generate an interrupt request to notify the bus master.
4.1.3 Output Compare (OC)
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Generates a rising edge, a falling edge, or a toggle of the previous edge in either of two ways:
1. At a user-specified time. The CPU can also force an immediate output, thereby generating a
pulse with a length equal to the programmed delay.
2. When linked to another channel. The OC references a linked parameter, without CPU interaction, and adds an offset to it.
4.1.4 Pulse-Width Modulation (PWM)
Generates a pulse-width modulated waveform with any duty cycle from 0% to 100% (within the resolution and latency capability of the TPU). The CPU provides one parameter that specifies waveform period and another parameter that specifies waveform high time. Updates to one or both of these
parameters can change the output to take effect either immediately, or coherently, at the next low-tohigh transition of the pin.
4.1.5 Synchronized Pulse-Width Modulation (SPWM)
Generates a pulse-width modulated waveform. The CPU can change period and/or high time at any
time. When synchronized to a time function on a second channel, the SPWM low-to-high transitions
have a time relationship to transitions on the second channel.
4.1.6 Period Measurement with Additional Transition Detect (PMA)
Allows special-purpose 16-bit period measurement. Detects the occurrence of an additional transition
indicated by the current measurement being less than a programmed ratio of a previous measurement.
When detected, this condition can be counted and compared to a programmed number of additional
transitions.
4.1.7 Period Measurement with Missing Transition Detect (PMM)
Allows special-purpose 16-bit period measurement. Detects the occurrence of a missing transition indicated by the current measurement being more than a previous measurement multiplied by a programmed ratio. When detected, this condition can be counted and compared to a programmed number
of transitions.
4.1.8 Position-Synchronized Pulse Generator (PSP)
Any channel of the TPU can generate an output transition or pulse, which is a projection in time based
on a reference period previously calculated on another channel.
4.1.9 Stepper Motor (SM)
The stepper motor control algorithm uses a programmable number of step rates to control the linear
acceleration and deceleration of a stepper motor. Any group of up to eight channels can be programmed to generate the control logic necessary to drive a stepper motor. Nominally, only two or four
channels are used for a two-phase motor.
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4.1.10 Period/Pulse-Width Accumulator (PPWA)
The PPWA continuously accumulates the high time or the total elapsed interval of a waveform over a
programmed number of input periods. It continuously tracks current and most recent accumulated
times.
Table 25 Parameter RAM Map
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Channel
—
X
Parameter
0
1
2
3
4
5
6
7
0
X $YFFF00
02
04
06
08
0A
—
—
1
X $YFFF10
12
14
16
18
1A
—
—
2
X $YFFF20
22
24
26
28
2A
—
—
3
X $YFFF30
32
34
36
38
3A
—
—
4
X $YFFF40
42
44
46
48
4A
—
—
5
X $YFFF50
52
54
56
58
5A
—
—
6
X $YFFF60
62
64
66
68
6A
—
—
7
X $YFFF70
72
74
76
78
7A
—
—
8
X $YFFF80
82
84
86
88
8A
—
—
9
X $YFFF90
92
94
96
98
9A
—
—
10
X $YFFFA0
A2
A4
A6
A8
AA
—
—
11
X $YFFFB0
B2
B4
B6
B8
BA
—
—
12
X $YFFFC0
C2
C4
C6
C8
CA
—
—
13
X $YFFFD0
D2
D4
D6
D8
DA
—
—
14
X $YFFFE0
E2
E4
E6
E8
EA
EC
EE
15
X $YFFFF0
F2
F4
F6
F8
FA
FC
FE
= Not Implemented
= Assignable as supervisor accessible only (if SUPV = 1) or unrestricted (if SUPV = 0). Unrestricted allows both user and supervisor access.
= M111, where M is the modmap bit in the module configuration register of the single-chip integration module (Y = $7 or $F).
Y
4.2 TPU Registers
TPUMCR — TPU Module Configuration Register
15
14
STOP
13
12
TCR1P
11
TCR2P
$YFFE00
10
9
8
7
6
5
4
EMU
T2CG
STF
SUPV
PSCK
0
0
0
0
0
1
0
0
0
3
2
1
0
0
0
IARB
RESET:
0
0
0
0
0
0
0
STOP — Stop Bit
0 = Internal clocks not shut down (reset condition)
1 = Internal clocks shut down
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TCR1P — TCR1 Prescaler Control
÷4
DIV4 CLOCK
TCR1
PRESCALER
00 ÷ 1
01 ÷ 2
10 ÷ 4
11 ÷ 8
PSCK
MUX
SYSTEM
CLOCK
1 – DIV4
0 – DIV32
÷ 32
DIV32 CLOCK
0
15
TCR1
PRESCALER CTL BLOCK 1
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TCR2P — TCR2 Prescaler Control
EXTERNAL
TCR2 PIN
SYNCHRONIZER
DIGITAL
FILTER
A
B
INT CLK /8
MUX
CONTROL
TCR2
PRESCALER
00 ÷ 1
01 ÷ 2
10 ÷ 4
11 ÷ 8
(T2CG CONTROL BIT)
0–A
1–B
0
15
TCR2
PRESCALER CTL BLOCK 2
EMU — Emulation Control
0 = TPU and RAM not in emulation mode (reset condition)
1 = TPU and RAM in emulation mode
T2CG — TCR2 Clock/Gate Control
0 = TCR2 pin used as clock source for TCR2 (reset condition)
1 = TCR2 pin used as gate of DIV8 clock for TCR2
STF — Stop Flag
0 = TPU operating (reset condition)
1 = TPU stopped
SUPV — Supervisor Data Space
0 = Assignable registers are unrestricted (FC2 is ignored).
1 = Assignable registers are restricted (FC2 is decoded; reset condition).
PSCK — Prescaler Clock
0 = DIV32 (system clock/32) is input to TCR1 prescaler.
1 = DIV4 (system clock/4) is input to TCR1 prescaler.
IARB — Interrupt Arbitration ID Bits
Each module that generates interrupts has an IARB field. The value in this field is used to arbitrate between simultaneous interrupt requests of the same priority. The reset value of all IARB fields other than
that of the SCIM is $0 (lowest priority), to prevent priority conflict during initialization. The IARB field
must be initialized to a value between $F (highest priority) and $1 (lowest priority), or subsequent interrupt requests will be identified by the CPU as spurious.
TCR — Test Configuration Register
$YFFE02
This register is used for Motorola factory test only.
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DSCR — Development Support Control Register
15
14
13
12
11
10
9
HOT4
0
0
0
0
BLC
CLKS
0
0
0
0
0
0
$YFFE04
8
7
FRZ
6
5
4
3
2
1
0
CCL
BP
BC
BH
BL
BM
BT
0
0
0
0
0
0
0
RESET:
0
0
0
HOT4 — Hang on T4
0 = Exit wait on T4 state caused by assertion of HOT4
1 = Enter wait on T4 state
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DSCR[14:11] — Not Implemented
BLC — Branch Latch Control
1 = Do not latch conditions into branch condition register before exiting the halted state or during
the time-slot transition period.
0 = Latch conditions into branch condition register prior to exiting halted state.
CLKS — Stop Clocks (to TCRs)
0 = Do not stop TCRs.
1 = Stop TCRs during the halted state.
FRZ[1:0] — IMB FREEZE Response
The FRZ bits specify the TPU microengine response to the FREEZE signal.
FRZ[1:0]
00
01
10
11
TPU Response
Ignore Freeze
Reserved
Freeze at End of Current Microcycle
Freeze at Next Time-Slot Boundary
CCL — Channel Conditions Latch
CCL controls the latching of channel conditions (MRL and TDL) when CHAN is written.
0 = Only the pin state condition of the new channel is latched as a result of the write CHAN register
microinstruction.
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write CHAN
register microinstruction.
BP, BC, BH, BL, BM, and BT — Breakpoint Enable Bits
DSCR[5:0] are TPU breakpoint enables. Setting a bit enables a breakpoint condition.
BP —Break if µPC equals µPC breakpoint register.
BC —Break if CHAN register equals channel breakpoint register at beginning of state or when
CHAN is changed through microcode.
BH —Break if host service latch is asserted at beginning of state.
BL —Break if link service latch is asserted at beginning of state.
BM —Break if MRL is asserted at beginning of state.
BT —Break if TDL is asserted at beginning of state.
DSSR — Development Support Status Register
$YFFE06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BKPT
PCBK
CHBK
SRBK
TPUF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
DSSR[15:8, 2:0] — Not Implemented
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BKPT — Breakpoint Asserted Flag
If an internal breakpoint caused the TPU to enter the halted state, the TPU asserts the BKPT signal on
the IMB and the BKPT flag. The TPU continues to assert BKPT until it recognizes a breakpoint acknowledge cycle from a host, or until the FREEZE signal on the IMB is asserted.
PCBK — µPC Breakpoint Flag
PCBK is asserted if a breakpoint occurs because of a µPC register match with the µPC breakpoint register. PCBK is negated when the BKPT flag is negated.
CHBK — Channel Register Breakpoint Flag
CHBK is asserted if a breakpoint occurs because of a CHAN register match with the channel register
breakpoint register. CHBK is negated when the BKPT flag is negated.
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SRBK — Service Request Breakpoint Flag
SRBK is asserted if a breakpoint occurs because of any of the service request latches being asserted
along with their corresponding enable flag in the development support control register. SRBK is negated
when the BKPT flag is negated.
TPUF — TPU FREEZE Flag
TPUF is asserted whenever the TPU is in a halted state as a result of FREEZE being asserted. This
flag is automatically negated when the TPU exits the halted state because of FREEZE being negated.
TICR — TPU Interrupt Configuration Register
15
14
13
12
11
0
0
0
0
0
0
0
0
0
10
9
$YFFE08
8
7
6
CIRL
5
4
CIBV
3
2
1
0
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
TICR[15:11] — Not Implemented
CIRL — Channel Interrupt Request Level
The interrupt request level for all channels is specified by this three-bit encoded field. Level seven for
this field indicates a nonmaskable interrupt; level zero indicates that all channel interrupts are disabled.
CIBV — Channel Interrupt Base Vector
This field specifies the most significant nibble of all 16 TPU channel interrupt vector numbers.
TICR[3:0] — Not Implemented
CIER — Channel Interrupt Enable Register
$YFFE0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
CH[15:0] — Interrupt Enable/Disable for each Channel
0 = Channel interrupts disabled
1 = Channel interrupts enabled
CFSR0–CFSR3 — Channel Function Select Registers
15
14
13
12
11
CH (15) (11) (7) (3)
10
9
8
$YFFE0C–$YFFE12
7
CH (14) (10) (6) (2)
6
5
4
3
CH (3) (9) (5) (1)
2
1
0
CH (12) (8) (4) (0)
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFSR[15:0] — Encoded One of 16 Time Functions for each Channel
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HSQR0 — Host Sequence Register 0
15
14
13
CH 15
12
11
CH 14
10
$YFFE14
9
CH 13
8
7
CH 12
6
5
CH 11
4
3
CH 10
2
1
CH 9
0
CH 8
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSQR1 — Host Sequence Register 1
15
14
13
CH 7
12
11
CH 6
10
0
0
$YFFE16
9
CH 5
8
7
CH 4
6
5
CH 3
4
3
CH 2
2
1
CH 1
0
CH 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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CH[15:0] — Encoded Host Sequence
HSRR0 — Host Service Request Register 0
15
14
13
CH 15
12
11
CH 14
10
$YFFE18
9
CH 13
8
7
CH 12
6
5
CH 11
4
3
CH 10
2
1
CH 9
0
CH 8
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSRR1 — Host Service Request Register 1
15
14
13
CH 7
12
11
CH 6
10
0
$YFFE1A
9
CH 5
0
8
7
CH 4
6
5
CH 3
4
3
CH 2
2
1
CH 1
0
CH 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CH[15:0] — Encoded Type of Host Service
CHX[1:0]
Service
00
No Host Service (Reset Condition)
01
Type 1 Host Service
10
Type 2 Host Service
11
Type 3 Host Service
CPR0 — Channel Priority Register 0
15
14
13
CH 15
12
11
CH 14
$YFFE1C
10
9
CH13
8
7
CH 12
6
5
CH 11
4
3
CH 10
2
1
CH 9
0
CH 8
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPR1 — Channel Priority Register 1
15
14
13
CH 7
12
11
CH 6
0
0
$YFFE1E
10
9
CH 5
8
7
CH 4
6
5
CH 3
4
3
CH 2
2
1
CH 1
0
CH 0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CH[15:0] — Encoded One of Three Channel Priority Levels
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CHX[1:0]
Service
00
Disabled
01
Low
10
Middle
11
High
CISR — Channel Interrupt Status Register
$YFFE20
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
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0
0
CH[15:0] — Interrupt Status Bit
0 = Channel interrupt not asserted
1 = Channel interrupt asserted
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Table 26 Host Service Summary
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Function Name
Function
Host Service Request Code
Code
DIO
$8
1= Force Output High
Discrete Input/
2 = Force Output Low
Output
3 = Initialization, Input Specified
3 = Initialization, Periodic Input
3 = Update Pin Status Parameter
$A
0 = None
ITC
Input Capture/
1 = Initialization
Input Transition
2 = (Not Implemented)
Counter
3 = (Not Implemented)
OC
$E
0 = None
Output Compare
1 = Host-Initiated Pulse Mode
2 = (Not Implemented)
3 = Continuous Pulse Mode
PWM
$9
0 = None
Pulse-Width
1 = Immediate Update Request
Modulation
2 = Initialization
3 = (Not Implemented)
$7
0 = None
SPWM
Synchronized
1 = (Not Implemented)
Pulse-Width Mod2 = Initialization
ulation
3 = Immediate Update Request
$B
0 = None
PMA/PMM
Period Measure1 = Initialization
ment with Addi2 = (Not Implemented)
tional/Missing
3 = (Not Implemented)
Transition Detect
$C
0 = None
PSP
Position-Synchro1 = Immediate Update Request
nized Pulse Gen2 = Initialization
erator
3 = Force Change
SM
$D
0 = None
Stepper Motor
1 = None
2 = Initialization
3 = Step Request
$F
0 = None
PPWA
Period/Pulse1 = (Not Implemented)
Width Accumula2 = Initialization
tor
3 = (Not Implemented)
Host Sequence Code*
0 = Trans Mode — Record Pin on Transition
0 = Trans Mode — Record Pin on Transition
0 = Trans Mode — Record Pin on Transition
1 = Match Mode — Record Pin at Match_Rate
2 = Record Pin State on HSR 11
0 = No Link, Single Mode
1 = No Link, Continuous Mode
2 = Link, Single Mode
3 = Link, Continuous Mode
0 = Execute All Functions
1 = Execute All Functions
2 = Only Update TCRn Parameters
3 = Only Update TCRn Parameters
(None Implemented)
0=
1=
2=
3=
0=
1=
2=
3=
Mode 0
Mode 1
Mode 2
(Not Implemented)
PMA Bank Mode
PMA Count Mode
PMM Bank Mode
PMM Count Mode
0 = Pulse Width Set by Angle
1 = Pulse Width Set by Time
2 = Pulse Width Set by Angle
3 = Pulse Width Set by Time
(None Implemented)
0=
1=
2=
3=
24-Bit Period
16-Bit Period + Link
24-Bit Pulse Width
16-Bit Pulse Width + Link
*Host Sequence Code interpretation is determined by the function; some HSQ codes apply to all HSR codes, some to
only one, such as Init.
LR — Link Register
$YFFE22
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
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CH[15:0] — Test Mode Link Service Request Enable Bit
0 = Link bit not asserted
1 = Link bit asserted
SGLR — Service Grant Latch Register
$YFFE24
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
CH[15:0] — Service Granted Bits
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DCNR — Decoded Channel Number Register
$YFFE26
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
CH[15:0] — Service Status Bits
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5 General-Purpose Timer Module
The GPT is a simple, yet flexible 11-channel timer for use in systems where a moderate degree of external visibility and control is required. The GPT consists of two nearly independent submodules, the
compare/capture unit, and the pulse-width modulator. A block diagram of the GPT appears below.
PGP0/IC1
PGP1/IC2
PGP2/IC3
CAPTURE/COMPARE UNIT
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PULSE ACCUMULATOR
PGP3/OC1
PGP4/OC2/OC1
PGP5/OC3/OC1
PGP6/OC4/OC1
PGP7/IC4/OC5/OC1
PAI
PRESCALER
PCLK
PWM UNIT
PWMA
PWMB
BUS INTERFACE
IMB
GPT BLOCK
Figure 9 GPT Block Diagram
GPT IC/OC pins are bidirectional, and may be used to form an 8-bit parallel port. Pulse-width modulator
outputs can also be used as general-purpose outputs. PAI and PCLK inputs can also be used as general-purpose inputs.
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Table 27 GPT Address Map
Address
$YFF900
$YFF902
$YFF904
$YFFE06
$YFF908
$YFF90A
$YFF90C
$YFF90E
$YFF910
$YFF912
$YFF914
$YFF916
$YFF918
$YFF91A
$YFF91C
$YFF91E
$YFF920
$YFF922
$YFF924
$YFF926
$YFF928
$YFF92A
$YFF92C
$YFF92E $YFF93F
15
8 7
0
GPT MODULE CONFIGURATION (GPTMCR)
(RESERVED FOR TEST)
INTERRUPT CONFIGURATION (ICR)
PGP DATA DIRECTION (DDRGP)
PGP DATA (PORTGP)
OC1 ACTION MASK (OC1M)
OC1 ACTION DATA (OC1D)
TIMER COUNTER (TCNT)
PA CONTROL (PACTL)
PA COUNTER (PACNT)
INPUT CAPTURE 1 (TIC1)
INPUT CAPTURE 2 (TIC2)
INPUT CAPTURE 3 (TIC3)
OUTPUT COMPARE 1 (TOC1)
OUTPUT COMPARE 2 (TOC2)
OUTPUT COMPARE 3 (TOC3)
OUTPUT COMPARE 4 (TOC4)
INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)
TIMER CONTROL 1 (TCTL1)
TIMER CONTROL 2 (TCTL2)
TIMER MASK 1 (TMSK1)
TIMER MASK 2 (TMSK2)
TIMER FLAG 1 (TFLG1)
TIMER FLAG 2 (TFLG2)
FORCE COMPARE (CFORC)
PWM CONTROL C (PWMC)
PWM CONTROL A (PWMA)
PWM CONTROL B (PWMB)
PWM COUNT (PWMCNT)
PWMA BUFFER (PWMBUFA)
PWMB BUFFER (PWMBUFB)
GPT PRESCALER (PRESCL)
RESERVED
Y = M111, where M is the state of the modmap bit in the module configuration register of the single-chip integration module. In an MC68HC16Y1 system, M must always be set to one.
5.1 Compare/Capture Unit
The compare/capture unit features three input capture channels, four output compare channels, and
one input capture/output compare channel (function selected via control register). These channels
share a 16-bit free-running counter (TCNT) which derives its clock from seven stages of a 9-stage prescaler or from external clock input PCLK. This section, which is similar to the timer found on the
MC68HC11F1, also contains one pulse accumulator channel. The pulse accumulator logic includes its
own 8-bit counter and can operate in either event counting mode or gated time accumulation mode.
Block diagrams of the GPT timer and prescaler follow.
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SYSTEM
CLOCK
PCLK
PRESCALER–DIVIDE BY
1, 4, 8, 16, 32, 64, OR 128
TCNT (HI)
TCNT (LO)
16-BIT FREE-RUNNING
COUNTER
1 OF 8 SELECT
CPR3 CPR1 CPR3
TAPS FOR RTI,
COP WATCHDOG,
AND PULSE
ACCUMULATOR
16-BIT TIMER BUS
9
INTERRUPT REQUESTS
(FURTHER QUALIFIED BY
1BIT IN CCR)
TIC2
16-BIT LATCH CLK
TIC2 (HI)
TIC2 (LO)
IC3I
16-BIT TIMER BUS
OC1I
PGP0/
IC1
BIT-1
PGP1/
IC2
BIT-2
PGP2/
IC3
BIT-3
PGP3/
OC1
BIT-4
PGP4/
OC2/
OC1
BIT-5
PGP5/
OC3/
OC1
BIT-6
PGP6/
OC4/
OC1
BIT-7
PGP7/
IC4/
OC5/
OC1
3
IC3F
TOC1
16-BIT COMPARATOR =
TOC1 (HI)
TOC1 (LO)
BIT-0
2
IC2F
TIC3
16-BIT LATCH CLK
TIC3 (HI)
TIC3 (LO)
PIN
FUNCTIONS
1
IC1F
IC2I
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TO PULSE
ACCUMULATOR
TMSK1
IC1I
TFLG1
TIC1
16-BIT LATCH CLK
TIC1 (HI)
TIC1 (LO)
TOI
TOF
4
CFORC
OC1F
FOC1
OC2I
TOC2
16-BIT COMPARATOR =
TOC2 (HI)
TOC2 (LO)
5
OC2F
FOC2
OC3I
TOC3
16-BIT COMPARATOR =
TOC3 (HI)
TOC3 (LO)
6
OC3F
FOC3
OC4I
TOC4
16-BIT COMPARATOR =
TOC4 (HI)
TOC4 (LO)
7
OC4F
FOC4
I4/O5I
TI4/O5
16-BIT COMPARATOR =
IC4/OC5 (HI) IC4/OC5 (LO)
16-BIT LATCH CLK
8
OC5
OC5F
FOC5
IC4
I4/O5
STATUS
FLAGS
FORCE
OUTPUT
COMPARE
INTERRUPT
ENABLES
PORT
GP PIN
CONTROL
NOTE: Parallel port pin functions are controlled by PDDR, OC1M, OC1D, and TCTL1 register.
GPT TIMER BLOCK
Figure 10 GPT Timer Diagram
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SYSTEM CLOCK
÷512
÷4
÷8
÷16
÷32
÷64
÷128
÷256
÷512
÷2
DIVIDER
EXT
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
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CPR2 CPR1 CPR0
÷256
÷128
÷64
÷32
÷16
÷8
÷4
EXT
÷128
÷64
÷32
÷16
÷8
÷4
÷2
EXT
PCLK
PIN
SELECT
SELECT
TO CAPTURE/
COMPARE
TIMER
TO
PWM UNIT
SYNCHRONIZER AND
DIGITAL FILTER
PPR2 PPR1 PPR0
GPT PRESCALER BLOCK
Figure 11 Prescaler Block Diagram
5.2 Pulse-Width Modulator
The pulse-width modulation submodule has two output pins. The outputs are periodic waveforms controlled by a single frequency whose duty cycles may be independently selected and modified by user
software. Each PWM can be independently programmed to run in fast or slow mode. The PWM unit has
its own 16-bit free-running counter which is clocked by an output of the nine-stage prescaler (the same
prescaler used by the compare/capture unit) or by the clock input pin, PCLK. A block diagram of the
PWM submodule follows.
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16-BIT
16-BIT DATA BUS
PWMA REGISTER
PWMB REGISTER
PWMBUFB REGISTER
COMPARATOR A
COMPARATOR B
PWMA
PIN
R
LATCH
S
F1A
BIT
ZERO DETECTOR
SFA
BIT
MULTIPLEXER A
R
LATCH
S
PWMB
PIN
8-BIT
PWMBUFA REGISTER
8-BIT
16-BIT
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16-BIT
ZERO DETECTOR
F1B
BIT
MULTIPLEXER B
SFB
BIT
0–14
16-BIT COUNTER
16-BIT TIMER BUS
FROM
PRESCALER CLOCK
16 PWM BLOCK
Figure 12 PWM Unit Block Diagram
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5.3 GPT Registers
GPTMCR — GPT Module Configuration Register
15
14
STOP
13
FRZ
$YFF900
12
11
10
9
8
7
6
5
4
STOPP
INCP
0
0
0
SUPV
0
0
0
0
0
0
0
0
1
0
0
0
3
2
1
0
0
0
IARB
RESET:
0
0
0
0
0
The GPTMCR contains parameters for interfacing to the CPU and the intermodule bus.
STOP — Stop Clocks
0 = Internal clocks not shut down
1 = Internal clocks shut down
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FRZ1 — FREEZE Response
Reserved; has no effect
FRZ0 — FREEZE Response
0 = Ignore FREEZE
1 = FREEZE the current state of the GPT
STOPP — Stop Prescaler
0 = Normal operation
1 = Stop prescaler and pulse accumulator from incrementing. Ignore changes to input pins.
INCP — Increment Prescaler
0 = Has no meaning
1 = If STOPP is asserted, increment prescaler once and clock input synchronizers once.
SUPV — Supervisor/Unrestricted Data Space
0 = Registers with access controlled by SUPV are unrestricted (FC2 is a don't care).
1 = Registers with access controlled by SUPV are restricted when FC2 = 1.
Because the CPU16 in the MC68HC16Y1 operates in supervisor mode only (FC2 is always logic level
one), this bit has no effect.
IARB[3:0] — Interrupt Arbitration ID
Each module that generates interrupts has an IARB field. The value in this field is used to arbitrate between simultaneous interrupt requests of the same priority. The reset value of all IARB fields other than
that of the SCIM is $0 (lowest priority), to prevent priority conflict during initialization. The IARB field
must be initialized to a value between $F (highest priority) and $1 (lowest priority), or subsequent interrupt requests will be identified by the CPU as spurious.
MTR — GPT Module Test Register (Reserved)
$YFF902
This address is currently unused and will return zeros if read. It is reserved for GPT factory test.
ICR — GPT Interrupt Configuration Register
15
14
13
12
PRIORITY ADJUST
9
$YFF904
11
10
8
0
INT REQUEST LEVEL
7
6
5
4
VECTOR BASE ADDRESS
3
2
1
0
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
Priority Adjust Field — This field specifies an interrupt to be advanced to the highest priority.
Interrupt Request Level — This field specifies the priority level of interrupts generated by the GPT.
Vector Base Address — This is the most significant nibble of interrupt vectors generated by the GPT.
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DDRGP/PORTGP — Port GP Data Direction Register/Port GP Data Register
15
8
$YFF906
7
0
DDRGP
PORTGP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and
PORTGP holds the 8-bit data.
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DDRGP[7:0] — Port GP Data Direction Register
0 = Input only
1 = Output
When PORTGP is used for general-purpose I/O, each bit in DDRGP determines whether the corresponding PORTGP bit is input or output.
OC1M/OC1D — OC1 Action Mask Register/OC1 Action Data Register
15
14
13
12
11
0C1M
10
9
8
0
0
0
0
0
0
7
6
$YFF908
5
4
3
0C1D
2
1
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines which
pins are affected, and OC1D determines what the outputs are.
OC1M[5:1] — OC1 Mask Field
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] — OC1 Data Field
0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1 match.
1 = If OC1 mask bit is set, set the corresponding output compare pin on OC1 match.
OC1D[5:1] correspond to OC[5:1].
TCNT — Timer Counter Register
$YFF90A
TCNT is the 16-bit free-running counter associated with the input capture, output compare, and pulse
accumulator functions of the GPT module.
PACTL/PACNT — Pulse Accumulator Control Register/Counter
15
14
13
PAIS
PAEN
PAMOD
0
0
12
11
PEDGE PCLKS
10
9
I4/O5
8
7
$YFF90C
6
PACLK
5
4
3
2
1
0
0
0
PULSE ACCUMULATOR COUNTER
RESET:
U
0
U
0
0
0
0
0
0
0
0
0
PACTL enables the pulse accumulator and selects either event counting or gated mode. In event counting mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented by an
internal clock.
PAIS — PAI Pin State (Read-Only)
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
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PAMOD — Pulse Accumulator Mode
0 = External event counting
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
The effects of PEDGE and PAMOD are shown in the following table.
PAMOD
PEDGE
Effect
0
0
PAI Falling Edge Increments Counter
0
1
PAI Rising Edge Increments Counter
1
0
Zero on PAI Inhibits Counting
1
1
One on PAI Inhibits Counting
Freescale Semiconductor, Inc...
PCLKS — PCLK Pin State (Read-Only)
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 enabled
1 = Input capture 4 enabled
PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)
PACLK[1:0]
Pulse Accumulator Clock Selected
00
System Clock Divided by 512
01
Same Clock Used to Increment TCNT
10
TOF Flag from TCNT
11
External Clock, PCLK
PACNT — Pulse Accumulator Counter
Eight-bit read/write counter used for external event counting or gated time accumulation.
TIC1–TIC3 — Input Capture Registers 1–3
$YFF90E, $YFF910, $YFF912
The input capture registers are 16-bit read-only registers which are used to latch the value of TCNT
when a specified transition is detected on the corresponding input capture pin. They are reset to $FFFF.
TOC1–TOC4 — Output Compare Registers 1–4
$YFF914, $YFF916, $YFF918, $YFF91A
The output compare registers are 16-bit read/write registers which can be used as output waveform
controls or as elapsed time indicators. For output compare functions, they are written to a desired match
value and compared against TCNT to control specified pin actions. They are reset to $FFFF.
TI4/O5 — Input Capture 4/Output Compare 5 Register
$YFF91C
This register serves either as input capture register 4 or output compare register 5, depending on the
state of I4/O5 in PACTL.
TCTL1/TCTL2 — Timer Control Registers 1–2
$YFF91E
15
14
13
12
11
10
9
8
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
0
0
0
0
0
0
7
6
5
EDGE4
4
3
EDGE3
2
1
EDGE2
0
EDGE1
RESET:
0
0
0
0
0
0
0
0
0
0
TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input
capture to be performed.
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OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
Each pair of bits specifies an action to be taken when output comparison is successful.
OM/OL[5:2]
00
01
10
11
Action Taken
Timer Disconnected from Output Logic
Toggle OCx Output Line
Clear OCx Output Line to zero
Set OCx Output Line to one
Freescale Semiconductor, Inc...
EDGE[4:1] — Input Capture Edge Control Bits
Each pair of bits configures input sensing logic for the corresponding input capture.
EDGE[4:1]
00
01
10
11
Configuration
Capture Disabled
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Any (Rising or Falling) Edge
TMSK1/TMSK2 — Timer Interrupt Mask Registers 1–2
15
14
13
I4/O5I
12
11
10
OCI
9
8
ICI
$YFF920
7
6
5
4
3
TOI
0
PAOVI
PAII
CPROUT
2
0
0
0
0
0
0
CPR
RESET:
0
0
0
0
0
0
0
0
0
0
0
TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts and TCNT functions.
OCI[4:1] — Output Compare Interrupt Enable
0 = OC interrupt disabled
1 = OC interrupt requested when OC flag set
OCI[4:1] correspond to OC[4:1].
ICI[3:1] — Input Capture Interrupt Enable
0 = IC interrupt disabled
1 = IC interrupt requested when IC flag set
ICI[3:1] correspond to IC[3:1].
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
0 = IC4/OC5 interrupt disabled
1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set
TOI — Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Interrupt requested when TOF flag is set
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Interrupt requested when PAOVF flag is set
PAII — Pulse Accumulator Input Interrupt Enable
0 = Pulse accumulator interrupt disabled
1 = Interrupt requested when PAIF flag is set
CPROUT — Compare/Capture Unit Clock Output Enable
0 = Normal operation for OC1 pin
1 = TCNT clock driven out OC1 pin
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CPR[2:0] — Timer Prescaler/PCLK Select Field
This field selects one of seven prescaler taps or PCLK to be TCNT input.
CPR[2:0]
000
001
010
011
100
101
110
111
Prescaler Value
4
8
16
32
64
128
256
PCLK
TFLG1/TFLG2 — Timer Interrupt Flag Registers 1–2
Freescale Semiconductor, Inc...
15
14
13
I4/O5F
12
11
10
9
OCF
8
ICF
$YFF922
7
6
5
4
3
2
1
0
TOF
0
PAOVF
PAIF
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
These registers show condition flags that correspond to various GPT events. If the corresponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt will occur.
OCF[4:1] — Output Compare Flags
An output compare flag is set each time TCNT matches the corresponding TOC register. OCF[4:1] correspond to OC[4:1].
ICF[3:1] — Input Capture Flags
A flag is set each time a selected edge is detected at the corresponding input capture pin. ICF[3:1] correspond to IC[3:1].
I4/O5F — Input Capture 4/Output Compare 5 Flag
When I4/O5 in PACTL is 0, this flag is set each time TCNT matches the value in TOC5. When I4/O5 in
PACTL is 1, the flag is set each time a selected edge is detected at the I4/O5 pin.
TOF — Timer Overflow Flag
This flag is set each time TCNT advances from a value of $FFFF to $0000.
PAOVF — Pulse Accumulator Overflow Flag
This flag is set each time the pulse accumulator counter advances from a value of $FF to $00.
PAIF — Pulse Accumulator Flag
In event counting mode, this flag is set when an active edge is detected on the PAI pin. In gated time
accumulation mode, it is set at the end of the timed period.
CFORC/PWMC — Compare Force Register/PWM Control Register
15
11
FOC
10
9
8
7
0
FPWMA
FPWMB
PPROUT
0
0
0
0
$YFF924
6
4
PPR
3
2
1
0
SFA
SFB
F1A
F1B
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
Setting a bit in CFORC will cause a specific output on OC or PWM pins. PWMC sets PWM operating
conditions.
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FOC[5:1] — Force Output Compare
0 = Has no meaning
1 = Causes pin action programmed for corresponding OC pin, but the OC Flag is not set.
FOC[5:1] correspond to OC[5:1].
FPWMA — Force PWMA Value
0 = Normal PWMA operation
1 = The value of F1A is driven out on the PWMA pin, regardless of the state of PPROUT.
FPWMB — Force PWMB Value
0 = Normal PWMB operation
1 = The value of F1B is driven out on the PWMB pin.
Freescale Semiconductor, Inc...
PPROUT — PWM Clock Output Enable
0 = Normal PWM operation on PWMA
1 = TCNT clock driven out PWMA pin
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps or PCLK to be PWMCNT input.
PPR[2:0]
000
001
010
011
100
101
110
111
System Clock
Divide-by Factor
2
4
8
16
32
64
128
PCLK
SFA — PWMA Slow/Fast Select
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
SFB — PWMB Slow/Fast Select
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
The following table shows the effects of SF settings on PWM frequency (16.78-MHz system clock).
PPR[2:0]
000
001
010
011
100
101
110
111
Prescaler Tap
Div 2 = 8.39 MHz
Div 4 = 4.19 MHz
Div 8 = 2.10 MHz
Div 16 = 1.05 MHz
Div 32 = 524 kHz
Div 64 = 262 kHz
Div 128 = 131 kHz
PCLK
SFA/B = 0
32.8 kHz
16.4 kHz
8.19 kHz
4.09 kHz
2.05 kHz
1.02 kHz
512 Hz
PCLK/256
SFA/B = 1
256 Hz
128 Hz
64.0 Hz
32.0 Hz
16.0 Hz
8.0 Hz
4.0 Hz
PCLK/32768
F1A — Force Logic Level on PWMA
0 = Force logic level zero output on PWMA pin.
1 = Force logic level one output on PWMA pin.
F1B — Force Logic Level on PWMB
0 = Force logic level zero output on PWMB pin.
1 = Force logic level one output on PWMB pin.
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PWMA/PWMB — PWM Registers A/B
$YFF926, $YFF927
These registers are associated with the pulse-width value of the PWM output on the corresponding
PWM pin. A value of $00 loaded into one of these registers results in a continuously low output on the
corresponding pin. A value of $80 results in a 50% duty cycle output. Maximum value ($FF) selects an
output which is high for 255/256 of the period.
PWMCNT — PWM Count Register
$YFF928
PWMCNT is the 16-bit free-running counter associated with the PWM functions of the GPT module.
PWMBUFA/B — PWM Buffer Registers A/B
$YFF92A, $YFF92B
These read-only registers contain values associated with the duty cycles of the corresponding PWM.
Reset state is $0000.
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PRESCL — GPT Prescaler
$YFF92C
The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] will always read as zeros.
Reset state is $0000.
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6 Analog-to-Digital Converter Module
The ADC is a unipolar, successive-approximation converter with eight modes of operation. It has selectable 8- or 10-bit resolution. Accuracy is ±1 count (one LSB) in 8-bit mode and ± 4 counts (two LSB)
in 10-bit mode. Monotonicity is guaranteed in both modes. The ADC can perform an 8-bit single conversion (4-clock sample) in ten microseconds; a 10-bit single conversion in 11 microseconds. The following table is a module address map.
Freescale Semiconductor, Inc...
Table 28 ADC Module Address Map
Address
$YFF700
$YFF702
$YFF704
$YFF706
$YFF708
$YFF70A
$YFF70C
$YFF70E
$YFF710
$YFF712
$YFF714
$YFF716
$YFF718
$YFF71A
$YFF71C
$YFF71E
$YFF720
$YFF722
$YFF724
$YFF726
$YFF728
$YFF72A
$YFF72C
$YFF72E
$YFF730
$YFF732
$YFF734
$YFF736
$YFF738
$YFF73A
$YFF73C
$YFF73E
15
8 7
MODULE CONFIGURATION (ADCMCR)
FACTORY TEST (ADTEST)
(RESERVED)
PORT ADA DATA (PORTADA)
(RESERVED)
ADC CONTROL 0 (ADCTL0)
ADC CONTROL 1 (ADCTL1)
ADC STATUS (ADSTAT)
RIGHT-JUSTIFIED UNSIGNED RESULT 0 (RJURR0)
RIGHT-JUSTIFIED UNSIGNED RESULT 1 (RJURR1)
RIGHT-JUSTIFIED UNSIGNED RESULT 2 (RJURR2)
RIGHT-JUSTIFIED UNSIGNED RESULT 3 (RJURR3)
RIGHT-JUSTIFIED UNSIGNED RESULT 4 (RJURR4)
RIGHT-JUSTIFIED UNSIGNED RESULT 5 (RJURR5)
RIGHT-JUSTIFIED UNSIGNED RESULT 6 (RJURR6)
RIGHT-JUSTIFIED UNSIGNED RESULT 7 (RJURR7)
LEFT-JUSTIFIED SIGNED RESULT 0 (LJSRR0)
LEFT-JUSTIFIED SIGNED RESULT 1 (LJSRR1)
LEFT-JUSTIFIED SIGNED RESULT 2 (LJSRR2)
LEFT-JUSTIFIED SIGNED RESULT 3 (LJSRR3)
LEFT-JUSTIFIED SIGNED RESULT 4 (LJSRR4)
LEFT-JUSTIFIED SIGNED RESULT 5 (LJSRR5)
LEFT-JUSTIFIED SIGNED RESULT 6 (LJSRR6)
LEFT-JUSTIFIED SIGNED RESULT 7 (LJSRR7)
LEFT-JUSTIFIED UNSIGNED RESULT 0 (LJURR0)
LEFT-JUSTIFIED UNSIGNED RESULT 1 (LJURR1)
LEFT-JUSTIFIED UNSIGNED RESULT 2 (LJURR2)
LEFT-JUSTIFIED UNSIGNED RESULT 3 (LJURR3)
LEFT-JUSTIFIED UNSIGNED RESULT 4 (LJURR4)
LEFT-JUSTIFIED UNSIGNED RESULT 5 (LJURR5)
LEFT-JUSTIFIED UNSIGNED RESULT 6 (LJURR6)
LEFT-JUSTIFIED UNSIGNED RESULT 7 (LJURR7)
0
Y = M111, where M is the state of the modmap bit in the SCIMCR. In the MC68HC16Y1, Y must equal $F — if
M is cleared, IMB modules will be inaccessible until a reset occurs. M can be written only once after reset.
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6.1 ADC Operation
ADC functions can be grouped into three basic subsystems: an analog front end, a digital control section, and a bus interface. A block diagram of the converter follows.
VRH
VRL
Freescale Semiconductor, Inc...
RC ARRAY
AND
COMPARATOR
SAR
MODE
AND
TIMING
CONTROL
ANALOG
MUX
AND SAMPLE
BUFFER
AMPLIFIER
PADA7/AN7
PADA6/AN6
PADA5/AN5
PADA4/AN4
PADA3/AN3
PADA2/AN2
PADA1/AN1
PADA0/AN0
RESULT 0
RESULT 1
RESULT 2
RESULT 3
RESULT 4
PORT A
DATA
REGISTER
RESULT 5
RESULT 6
RESULT 7
CLK SELECT/
PRESCALER
BUS INTERFACE UNIT
A/D BLOCK
Figure 13 Analog-to-Digital Converter Block Diagram
6.2 Analog Subsystem
The analog front end consists of a multiplexer, a buffer amplifier, a resistor-capacitor array, and a highgain comparator. The multiplexer selects one of eight internal or eight external signal sources for conversion. The buffer amplifier protects the input channel from the relatively large capacitance of the RC
array. The resistor capacitor (RC) array performs two functions — it acts as a sample/hold circuit, and
it provides the digital-to-analog comparison output necessary for successive approximation conversion.
The comparator indicates whether each successive output of the RC array is higher or lower than the
sampled input.
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6.3 Digital Control Subsystem
The digital control section includes conversion sequence control logic, channel and reference select
logic, successive approximation register, eight result registers, a port data register, and control/status
registers. It controls the multiplexer and the output of the RC array during the sample and conversion
periods, stores the results of comparison in the successive-approximation register, then transfers the
result to a result register.
6.4 Bus Interface Subsystem
The bus interface contains logic necessary to interface the ADC to the intermodule bus. The ADC is
designed to act as a slave device on the bus. The interface must respond with appropriate bus cycle
termination signals and supply appropriate interface timing to the other submodules.
6.5 ADC Registers
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ADCMCR — Module Configuration Register
15
14
STOP
13
12
$YFF700
8
FRZ
NOT USED
7
6
SUPV
0
NOT USED
RESET:
1
0
0
1
The module configuration register is used to initialize the ADC.
STOP — STOP Mode
0 = Normal operation
1 = Low-power operation
STOP places the ADC in low-power state by disabling the ADC clock and powering down the analog
circuitry. Setting STOP will abort any conversion in progress. STOP is set to logic level one at reset,
and may be cleared to logic level zero by the CPU.
Clearing STOP enables normal ADC operation. However, because analog circuitry bias current has
been turned off, there is a period of recovery before output stabilization.
FRZ[1:0] — Freeze 1
The FRZ field is used to determine ADC response to assertion of the IFREEZE signal. The following
table shows possible responses.
FRZ
00
01
10
11
Response
Ignore IFREEZE
Reserved
Finish conversion, then freeze
Freeze immediately
SUPV — Supervisor/Unrestricted
0 = Unrestricted access
1 = Supervisor access
SUPV defines access to assignable ADC registers. Because the CPU16 in the MC68HC16Y1 operates
in supervisor mode only, this bit has no effect.
ADTEST — ADC Test Register
$YFF702
ADTEST is used with the SCIM test register for factory test of the ADC.
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PORTADA — Port Data Register
$YFF706
15
8
7
0
NOT USED
PORT A DATA
RESET:
0
0
0
0
0
0
0
0
INPUT DATA
Port ADA is an input port that shares pins with the A/D converter inputs.
Port ADA Data[7:0]
A read of PORTADA[7:0] will return the logic level of the port A pins. If the input is not an appropriate
voltage (i.e., outside the defined levels), the read will be indeterminate. Use of a port A pin for digital
input does not preclude use as an analog input.
ADCTL0 — A/D Control Register 0
$YFF70A
Freescale Semiconductor, Inc...
15
8
NOT USED
7
6
RES10
5
4
3
STS
2
1
0
1
1
PRS
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADCTL0 is used to select ADC clock source and to set up prescaling. Writes to it have immediate effect.
RES10 — 10-Bit Resolution
0 = 8-bit conversion
1 = 10-bit conversion
Conversion results are appropriately aligned in result registers to reflect conversion status.
STS[1:0] — Sample Time Select Field
The STS field is used to select one of four sample times, as shown in the following table.
STS[1:0]
00
01
10
11
Sample Time
2 A/D Clock Periods
4 A/D Clock Periods
8 A/D Clock Periods
16 A/D Clock Periods
PRS[4:0] — Prescaler Rate Selection Field
ADC clock is generated from system clock using a modulo counter and a divide-by-two circuit. The binary value of this field is the counter modulus. System clock is divided by the PRS value plus one, then
sent to the divide-by-two circuit, as shown in the following table. Maximum ADC clock rate is 2 MHz.
Reset value of PRS in the MC68HC16Y1 is a divisor value of eight — this translates to a nominal 2 MHz
ADC clock.
MC68HC16Y1
MC68HC16Y1TS/D
PRS[4:0]
Divisor Value
00000
Reserved
00001
4
00010
6
...
...
11101
60
11110
62
11111
64
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ADCTL1 — A/D Control Register 1
$YFF70C
15
7
NOT USED
6
5
4
3
2
1
0
SCAN
MULT
S8CM
CD
CC
CB
CA
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
ADCTL1 is used to initiate A/D conversion. It is also used to select conversion modes and conversion
channel. It can be written or read at any time. A write to ADCTL1 initiates a conversion sequence — if
a conversion sequence is already in progress, a write to ADCTL1 will abort it and reset the SCF and
CCF flags in the A/D status register.
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SCAN — Scan Mode Selection Bit
0 = Single conversion sequence
1 = Continuous conversion
Length of conversion sequence(s) is determined by S8CM.
MULT — Multichannel Conversion Bit
0 = Conversion sequence(s) run on single channel (channel selected via [CD:CA])
1 = Sequential conversion of a block of four or eight channels (block selected via [CD:CA])
Length of conversion sequence(s) is determined by S8CM.
S8CM — Select Eight-Conversion Sequence Mode
0 = Four-conversion sequence
1 = Eight-conversion sequence
This bit determines the number of conversions in a conversion sequence.
[CD:CA] — Channel Selection Field
The bits in this field are used to select an input or block of inputs for A/D conversion.
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Freescale Semiconductor, Inc...
The following table summarizes the operation of S8CM and [CD:CA] when MULT is cleared (singlechannel mode). Number of conversions per channel is determined by SCAN.
S8CM
0
0
0
0
0
0
0
0
0
0
0
0
0
CD
0
0
0
0
0
0
0
0
1
1
1
1
1
CC
0
0
0
0
1
1
1
1
0
0
0
0
1
CB
0
0
1
1
0
0
1
1
0
0
1
1
0
CA
0
1
0
1
0
1
0
1
0
1
0
1
0
Input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RESERVED
RESERVED
RESERVED
RESERVED
VRH
Result Register
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
RSLT0 – RSLT3
0
1
1
0
1
VRL
RSLT0 – RSLT3
0
1
1
1
0
(VRH – VRL) / 2
RSLT0 – RSLT3
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
TEST/RESERVED
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RESERVED
RESERVED
RESERVED
RESERVED
VRH
RSLT0 – RSLT3
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
RSLT0 – RSLT7
1
1
1
0
1
VRL
RSLT0 – RSLT7
1
1
1
1
0
(VRH – VRL) / 2
RSLT0 – RSLT7
1
1
1
1
1
TEST/RESERVED
RSLT0 – RSLT7
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The following table summarizes the operation of S8CM and [CD:CA] when MULT is set (multichannel
mode). Number of conversions per channel is determined by SCAN. Channel numbers are given in order of conversion.
S8CM
0
CD
0
CC
0
CB
X
CA
X
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
X
X
X
1
1
X
X
X
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Input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RESERVED
RESERVED
RESERVED
RESERVED
VRH
Result Register
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT0
VRL
RSLT1
(VRH – VRL) / 2
RSLT2
TEST/RESERVED
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RESERVED
RESERVED
RESERVED
RESERVED
VRH
RSLT3
RSLT0
RSLT1
RSLT2
RSLT3
RSLT4
RSLT5
RSLT6
RSLT7
RSLT0
RSLT1
RSLT2
RSLT3
RSLT4
VRL
RSLT5
(VRH – VRL) / 2
RSLT6
TEST/RESERVED
RSLT7
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ADSTAT — ADC Status Register
15
14
SCF
11
$YFF70E
10
NOT USED
8
7
0
CCTR
CCF
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADSTAT contains information related to the status of a conversion sequence.
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SCF — Sequence Complete Flag
0 = Sequence not complete
1 = Sequence complete
SCF is set at the end of the conversion sequence when SCAN is cleared, and at the end of the first
conversion sequence when SCAN is set. SCF is cleared when ADCTL1 is written and a new conversion
sequence begins.
CCTR[2:0] — Conversion Counter Field
This field reflects the contents of the conversion counter pointer in either four or eight count conversion
sequence. The value corresponds to the number of the next result register to be written, and thus indicates which channel is being converted.
CCF[7:0] — Conversion Complete Field
Each bit in this field corresponds to an A/D result register (CCF7 to RSLT7, etc.). A bit is set when conversion for the corresponding channel is complete, and remains set until the result register is read. It is
cleared when the register is read.
RSLT0–RSLT7 — A/D Result Registers
$YFF710–$YFF73E
The result registers are used to store data after conversion is complete. Each register can be read from
three different addresses in the register block. Data format depends on the address from which it is
read.
RJURR — Unsigned Right-Justified Format
$YFF710–$YFF71F
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution, bits [7:0] are
used for 8-bit conversion (bits [9:8] are zero). Bits [15:10] always return zero when read.
LJSRR — Signed Left-Justified Format
$YFF720–$YFF72F
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution, bits [15:8] are
used for 8-bit conversion (bits [7:6] are zero). Although the ADC is unipolar, it is assumed that the zero
point is halfway between low and high reference when this format is used — for positive input, bit 15 =
0, for negative input, bit 15 = 1. Bits [5:0] always return zero when read.
LJURR — Unsigned Left-Justified Format
$YFF730–$YFF73F
Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution, bits [15:8] are
used for 8-bit conversion (bits [7:6] are zero). Bits [5:0] always return zero when read.
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7 Multichannel Communication Interface
The MCCI contains three serial interfaces: two serial communication interfaces (SCI) and a serial peripheral interface (SPI). The figure below is a block diagram of the MCCI.
INTERMODULE BUS (IMB)
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BUS INTERFACE UNIT
PMC0/MISO
PMC1/MOSI
PMC2/SCK
PMC3/SS
SERIAL PERIPHERAL
INTERFACE
(SPI)
SERIAL
COMMUNICATION
INTERFACE B
(SCI–B)
PORT
MC
SERIAL
COMMUNICATION
INTERFACE A
(SCI–A)
PMC4/RXDB
PMC5/TXDB
PMC6/RXDA
PMC7/TXDA
"MCCI BLOCK"
Figure 14 MCCI Block Diagram
The SCI provide standard nonreturn to zero (NRZ) mark/space format. Either will operate in full- or halfduplex mode — there are separate transmitter and receiver enable bits and dual data buffers for each
interface. A modulus-type baud rate generator provides rates from 64 to 524 kbaud (with a 16.78-MHz
system clock). Word length of either 8 or 9 bits is software selectable. Optional parity generation and
detection provide either even or odd parity check capability. Advanced error detection circuitry catches
glitches of up to 1/16 of a bit time in duration. Wakeup functions allow the CPU to run uninterrupted until
meaningful data is available.
The SPI provides easy peripheral expansion or interprocessor communication via a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. The SPI is compatible with SPI interfaces
found in other Motorola devices, but contains enhanced operational features, such as programmable
shift direction.
MCCI pins can also be configured for use in 8-bit general-purpose I/O port MC.
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Table 29 MCCI Address Map
Address
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
$YFFC20
$YFFC22
$YFFC24
$YFFC26
$YFFC28
$YFFC2A
$YFFC2C
$YFFC2E
$YFFC30
$YFFC32
$YFFC34
$YFFC36
$YFFC38
$YFFC3A
$YFFC3C
$YFFC3E
15
8 7
0
MCCI MODULE CONFIGURATION REGISTER (MMCR)
MCCI TEST REGISTER (MTEST)
SCI INTERRUPT REGISTER (ILSCI)
SCI INTERRUPT VECTOR (MIVR)
SPI INTERRUPT REGISTER (ILSPI)
RESERVED
RESERVED
MCCI PIN ASSIGNMENT (PMCPAR)
RESERVED
MCCI DATA DIRECTION (DDRMC)
RESERVED
MCCI PORT DATA REGISTER (PORTMC)
RESERVED
MCCI PORT PIN STATE (PORTMCP)
RESERVED
RESERVED
RESERVED
RESERVED
SCIA CONTROL REGISTER 0 (SCCR0A)
SCIA CONTROL REGISTER 1 (SCCR1A)
SCIA STATUS REGISTER (SCSRA)
SCIA DATA REGISTER (SCDRA)
RESERVED
RESERVED
RESERVED
RESERVED
SCIB CONTROL REGISTER 0 (SCCR0B)
SCIB CONTROL REGISTER 1 (SCCR1B)
SCIB STATUS REGISTER (SCSRB)
SCIB DATA REGISTER (SCDRB)
RESERVED
RESERVED
RESERVED
RESERVED
SPI CONTROL REGISTER (SPCR)
RESERVED
SPI STATUS REGISTER (SPSR)
SPI DATA REGISTER (SPDR)
Y = M111, where M is the state of the modmap bit in the SCIMCR. In the MC68HC16Y1, Y must equal $F — if
M is cleared, IMB modules will be inaccessible until a reset occurs. M can be written only once after reset.
7.1 MCCI Registers
MCCI registers are divided into four categories: MCCI global registers, MCCI pin control registers, SCI
registers, and SPI registers. SPI and SCI registers are defined in separate sections below. Writes to
unimplemented register bits have no meaning or effect, and reads from unimplemented bits always return a logic zero value.
The modmap bit of the single-chip integration module configuration register (SCIMCR) defines the most
significant bit (ADDR23) of the address, shown in each register diagram as “Y”. This bit, concatenated
with the rest of the address given, forms the absolute address of each register. Because the CPU16 in
the MC68HC16Y1 drives only ADDR[19:0], ADDR[23:20] follow the logic state of ADDR19, and “Y”
must equal $F — see the SCIM section of this summary for more information on how the state of MM
affects the system.
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7.1.1 MCCI Global Registers
Global registers contain parameters used by both the SPI and the SCI submodules. These parameters
are used by the MCCI to interface with the CPU and other system modules.
MMCR — MCCI Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
STOP
0
0
0
0
0
0
0
SUPV
0
0
0
0
0
0
0
0
0
0
1
0
0
0
3
2
1
0
0
0
IARB
RESET:
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0
0
0
STOP — Stop Enable
0 = Normal MCCI clock operation
1 = MCCI clock operation stopped
STOP places the MCCI into a low power state by disabling the system clock in most parts of the module.
MMCR is the only register guaranteed to be readable while STOP is asserted. STOP may be negated
by the CPU and by reset.
Bits [14:8] — Not Implemented
SUPV — Supervisor/Unrestricted
0 = Unrestricted access
1 = Supervisor access
In systems with controlled access levels, SUPV places assignable registers in either supervisor-only
data space or unrestricted data space. All MCCI registers reside in supervisor-only space. Because the
CPU16 in the MC68HC16Y1 operates only in supervisor mode, SUPV has no meaning.
Bits [6:4] — Not Implemented
IARB — Interrupt Arbitration Identification Number
Each module that generates interrupts has an IARB field. The value in this field is used to arbitrate between simultaneous interrupt requests of the same priority. The reset value of all IARB fields other than
that of the SCIM is $0 (lowest priority), to prevent priority conflict during initialization. The IARB field
must be initialized to a value between $F (highest priority) and $1 (lowest priority), or subsequent interrupt requests will be identified by the CPU as spurious.
MTEST — MCCI Test Register
$YFFC02
MTEST is used in conjunction with SCIM test functions during factory test of the MCCI. Accesses to
MTEST must be made while the MCU is in test mode.
ILSCI/MIVR — SCI Interrupt Request Level Register/MCCI Interrupt Vector Register
15
14
0
0
13
12
11
10
ILSCIB
9
8
$YFFC04
7
ILSCIA
MIVR
1
0
1
1
1
1
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
ILSCI determines the priority level of interrupts requested by each SCI. Separate fields hold interrupt
priority values for SCIA and SCIB. Priority is used to determine which interrupt is serviced first when two
or more modules or external peripherals simultaneously request an interrupt.
ILSCIA, ILSCIB — Interrupt Level for SCIA, SCIB
ILSCIA, ILSCIB determine the priority levels of SCIA and SCIB interrupts, respectively. This field must
contain a value between $1 (lowest priority) and $7 (highest priority) for interrupts to be recognized.
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MIVR — MCCI Interrupt Vector Register
MIVR determines which vector the CPU uses to service an MCCI interrupt after it is acknowledged. At
reset, MIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the exception
vector table. MIVR must be programmed to one of the user-defined vectors ($40–$FF) during initialization of the MCCI in order for interrupts to be serviced.
MCCI interrupt vectors are adjacent to one another in the exception vector table. MIVR[7:2] are the
same for all three interfaces. The MCCI provides the values for MIVR[1:0] according to the source of
the interrupt (%00 for SCIA, %01 for SCIB, and %10 for the SPI). Writes to MIVR[1:0] have no meaning
or effect. Reads of MIVR[1:0] return a value of %11.
ILSPI — SPI Interrupt Level Register
15
14
0
0
13
12
11
ILSPI
$YFFC06
10
9
8
0
0
0
0
0
0
7
0
RESERVED
RESET:
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0
0
0
0
0
ILSPI determines the priority of interrupts requested by the SPI. The ILSPI field must contain a value
between $1 (lowest priority) and $7 (highest priority) for interrupts to be recognized. If ILSPI, ILSCIA,
and ILSCIB are the same, simultaneous interrupt requests are recognized in SPI, SCIA, SCIB priority.
7.1.2 MCCI Pin Control Registers
MCCI pin control registers determine the use of eight MCU pins. Although these pins are used by the
serial subsystems, any pin may alternately be assigned to use in a general-purpose parallel port. The
MCCI pin assignment register (PMCPAR) determines whether pins are assigned to the SPI or to the
parallel port. Clearing a bit assigns the corresponding pin to the port; setting a bit assigns the pin to the
SPI. PMCPAR does not affect operation of the SCI submodule.
The MCCI data direction register (DDRMC) determines whether pins are inputs or outputs. Clearing a
bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRMC affects both
SPI function and I/O function. DDRMC determines the direction of SCI TXD pins only when an SCI
transmitter is disabled. When an SCI transmitter is enabled, the TXD pin is an output.
MCCI port data register PORTMC latches I/O data; MCCI pin state register PORTMCP allows pin state
to be read regardless of data direction configuration.
PORTMC — MCCI Port Data Register
15
14
13
12
11
10
$YFFC0C
9
8
RESERVED
7
6
5
4
3
2
1
0
PMC7
PMC6
PMC5
PMC4
PMC3
PMC2
PMC1
PMC0
Writes to PORTMC are stored in an internal data latch. If any bit of PORTMC is configured as discrete
output, the latched value is driven onto the corresponding pin. Reads of PORTMC return the value of
the pin only if the pin is configured as a discrete input. Otherwise, the value read is the latched value.
To avoid driving undefined data, first write a byte to PORTMC, then configure DDRMC.
PORTMCP — MCCI Port Pin State Register
15
14
13
12
11
RESERVED
10
9
$YFFC0E
8
7
6
5
4
3
2
1
0
PMC7
PMC6
PMC5
PMC4
PMC3
PMC2
PMC1
PMC0
Reads of PORTMCP always return the state of the pins regardless of whether the pins are configured
as input or output. Writes to PORTMCP have no effect.
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PMCPAR — MCCI Pin Assignment Register
15
14
13
12
11
10
$YFFC08
9
8
RESERVED
7
6
5
4
3
2
1
0
0
0
0
0
SS
0
MOSI
MISO
0
0
0
0
0
0
0
0
RESET:
PMCPAR determines which of the SPI pins, with the exception of the SCK pin (the state of which is
determined by the SPI enable bit), are actually used by the SPI submodule, and which pins are available
for general-purpose I/O. SPI pins designated by PMCPAR as general-purpose I/O are controlled only
by DDRMC and PORTMC; the SPI has no effect on these pins. PMCPAR does not affect the operation
of the SCI submodule.
SS — Slave Select
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MOSI — Master Out Slave In
MISO — Master In Slave Out
0 = Pin is used for general-purpose I/O
1 = Pin is used by SPI
DDRMC — MCCI Data Direction Register
15
14
13
12
11
10
$YFFC0B
9
8
RESERVED
7
6
5
4
3
2
1
0
TXDA
RXDA
TXDB
RXDB
SS
SCK
MOSI
MISO
0
0
0
0
0
0
0
0
RESET:
DDRMC determines whether a general-purpose I/O pin is an input or an output. During reset, all MCCI
pins are configured as general-purpose inputs.
0 = Input
1 = Output
7.2 Serial Peripheral Interface
The SPI submodule communicates with external devices via a synchronous serial bus. The SPI is fully
compatible with SPI systems found on other Motorola products, but has enhanced capabilities. The SPI
can perform full-duplex three-wire or half-duplex two-wire transfers.
7.2.1 SPI Pins
The SPI uses four bidirectional pins. These pins may be configured for general-purpose I/O when not
needed for SPI application. The following table shows SPI pin functions
Table 30 SPI Pin Function
Pin Names
Mode
Function
Master In Slave Out (MISO)
Master
Slave
Provides serial data input to the SPI
Provides serial data output from the SPI
Master Out Slave In (MOSI)
Master
Slave
Provides serial output from the SPI
Provides serial input to the SPI
Serial Clock (SCK)
Master
Slave
Provides clock output from SPI
Provides clock input to SPI
Slave Select (SS)
Master
Slave
Causes mode fault
Initiates serial transfer
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7.2.2 SPI Registers
The programmer's model for the SPI consists of the MCCI global and pin control registers, the SPI control register (SPCR), the SPI status register (SPSR), and the SPI data register (SPSR). All SPI registers
can be read and written by the CPU. SPCR must be initialized before the SPI is enabled to ensure defined operation. The SPI is enabled by setting the SPE bit in SPCR. Reset values are shown below each
register.
SPCR — SPI Control Register
$YFFC38
15
14
13
12
11
10
9
8
SPIE
SPE
WOMP
MSTR
CPOL
CPHA
LSBF
SIZE
0
0
0
0
1
0
0
7
6
5
4
3
2
1
0
0
1
0
0
BAUD
RESET:
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0
0
0
0
0
SPCR contains parameters for configuring the SPI. The CPU has read and write access to all control
bits, but the MCCI has read access only to all bits except SPE. Writing a new value to SPCR while the
SPI is enabled disrupts operation. Writing the same value into SPCR while the SPI is enabled has no
effect on SPI operation.
SPIE — SPI Interrupt Enable
0 = SPI interrupts disabled
1 = SPI interrupts enabled
SPE — SPI Enable
0 = SPI is disabled. SPI pins can be used for general-purpose I/O.
1 = SPI is enabled. Pins allocated by PMCPAR are controlled by the SPI.
WOMP — Wired-OR Mode for SPI Pins
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRMC have open-drain drivers.
WOMP allows SPI pins to be connected for wired-OR operation, regardless of whether they are used
for general-purpose output or for SPI output. WOMP affects the pins whether the SPI is enabled or disabled.
MSTR — Master/Slave Mode Select
0 = SPI is a slave device and only responds to externally generated serial data.
1 = SPI is system master and can initiate transmission to external SPI devices.
MSTR configures the SPI for either master or slave mode operation. This bit is cleared on reset and
may only be written by the CPU.
CPOL — Clock Polarity
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to
produce a desired clock/data relationship between master and slave devices.
CPHA — Clock Phase
0 = Data captured on the leading edge of SCK and changed on the following edge of SCK.
1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.
CPHA determines which edge of SCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave
devices. CPHA is set at reset.
LSBF — Least Significant Bit First
0 = Serial data transfer starts with MSB
1 = Serial data transfer starts with LSB
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SIZE — Transfer Data Size
0 = 8-bit data transfer
1 = 16-bit data transfer
BAUD — Serial Clock Baud Rate
The SPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is
selected by writing a value from 2 to 255 into the BR field. Giving BR a value of zero or one disables
the baud rate generator. The following equations determine the SCK baud rate:
SCK Baud Rate = System Clock/(2 ∗ BR)
or
BR = System Clock/(2 ∗ SCK Baud Rate Desired)
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SPSR — SPI Status Register
$YFFC3C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPIF
WCOL
0
MODF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
SPSR contains SPI status information. Only the SPI can set the bits in this register. The CPU reads the
register to obtain status information and writes it to clear status flags.
SPIF — SPI Finished Flag
0 = SPI not finished
1 = SPI finished
WCOL — Write Collision
0 = No write collision occurred
1 = Write collision occurred
MODF — Mode Fault Flag
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the SPI was enabled in
master mode (SS input taken low).
SPDR — SPI Data Register
15
14
13
12
$YFFC3E
11
10
9
8
7
6
5
4
UPPB
3
2
1
0
U
U
U
U
LOWB
RESET:
U
U
U
U
U
U
U
U
U
U
U
U
A write to SPDR initiates transmission or reception in the master device. At the completion of transmission, the SPIF status bit is set in both master and slave devices. Received data is buffered. SPIF must
be cleared before a subsequent transfer of data from the shift register to the buffer or overrun occurs
— the byte or word that causes overrun is lost. Transmitted data is not buffered — a write to SPDR places data directly into the shift register for transmission.
UPPB — Upper Byte
In 16-bit transfer mode, UPPB is used to access the most significant 8 bits of the data. Bit 15 of the
SPDR is the MSB of the 16-bit data.
LOWB — Lower Byte
In 8-bit transfer mode, data is accessed at the address of LOWB. MSB in 8-bit transfer mode is bit 7 of
the SPDR. In 16-bit transfer mode, LOWB holds the least significant 8 bits of the data.
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7.2.3 SPI Operation
The SPI operates in either master or slave mode. Master mode is used when the SPI originates data
transfers. Slave mode is used when an external device initiates serial transfers to the SPI. Switching
between the modes is controlled by MSTR in SPCR. Prior to entering either mode, appropriate MCCI
and SPI registers must be properly initialized.
In master mode, transmission parameters are set by writing to SPCR, the SPI is enabled by setting
SPE, then operation is initiated by writing data to SPDR. In slave mode, operation proceeds in response
to SS signal assertion by an external bus master. Slave operation is similar to that of master mode.
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Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus
master supplies the clock signal (SCK) to time the transfer of data. Four possible combinations of clock
phase and polarity may be specified by means of the CPHA and CPOL bits in SPCR. Data can be transferred either LSB or MSB first, depending on the value of the LSBF bit in SPCR. The number of bits
transferred per command defaults to eight, but may be set to 16 bits by setting the field in SPCR.
When the SPI finishes a transmission, it sets the SPIF flag, clears SPE and stops. If the SPIE bit in
SPCR is set, an interrupt request is generated when SPIF is set.
Although the SPI inherently supports multimaster operation, no special arbitration mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master arbitration — system software must
provide arbitration.
Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the system. If needed,
the WOMP bit in SPCR can be set to provide wired-OR open-drain outputs. An external pull-up resistor
should be used on each output line. WOMP affects all SPI pins regardless of whether they are assigned
to the SPI or used as general-purpose I/O.
7.3 Serial Communication Interface
There are two identical independent SCI systems, SCIA and SCIB, in the MCCI. Each is a full-duplex
universal asynchronous receiver transmitter (UART). Each SCI system is fully compatible with the SCI
systems found on other Motorola devices, such as the M68HC11 and M68HC05 Families. The following
discussions apply to both SCIA and SCIB — differences in register addresses and pin names are noted.
7.3.1 SCI Pins
Two unidirectional transmit data pins, TXDA and TXDB, and two unidirectional receive data pins, RXDA
and RXDB, are associated with each SCI. Each pin can be used by the associated SCI or for generalpurpose I/O.
SCI pins and their functions are shown below.
Pin Names
Receive Data
A and B
Transmit Data
A and B
Mnemonics
RXDA, RXDB
TXDA, TXDB
Mode
Receiver Disabled
Receiver Enabled
Transmitter Disabled
Transmitter Enabled
Function
General-Purpose I/O
Serial Data Input to SCI
General-Purpose I/O
Serial Data Output from SCI
7.3.2 SCI Registers
The SCI programming model includes the MCCI global and pin control registers, and eight SCI registers. Each of the two SCI units contains two SCI control registers, one status register, and one data register.
All registers may be read or written at any time by the CPU. Rewriting the same value to any SCI register
does not disrupt operation; however, writing a different value into an SCI register when the SCI is running may disrupt operation. To change register values, the receiver and transmitter should be disabled
with the transmitter allowed to finish first. The status flags in register SCSR may be cleared at any time.
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SCCR0A, SCCR0B — SCI Control Register 0
15
14
13
0
0
0
0
0
12
11
10
9
$YFFC18, $YFFC28
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
SCBR
RESET:
0
0
0
0
0
0
0
0
Each SCCR0 contains the baud rate selection field. Baud rate must be set before the SCI is enabled.
The CPU can read and write this register at any time.
Bits [15:13] — Not Implemented
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SCBR — Baud Rate
SCI baud rate is programmed by writing a 13-bit value to this field. Writing a value of zero to BR disables
the baud rate generator.
The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming data stream. The SCI baud rate generator produces a receiver sampling clock with a frequency
16 times that of the expected baud rate of the incoming data. The SCI determines the position of bit
boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. Receiver sampling rate is always 16 times the frequency of the SCI baud
rate, which is calculated as follows:
SCI Baud Rate = System Clock/(32 ∗ BR)
where BR is in the range {1, 2, 3, ..., 8191}.
SCCR1A, SCCR1B — SCI Control Register 1
15
0
14
13
LOOPS WOMS
$YFFC1A, $YFFC2A
12
11
10
9
8
7
6
5
4
3
2
1
0
ILT
PT
PE
M
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
0
0
Each SCCR1 contains SCI configuration parameters. The CPU can read and write this register at any
time. The SCI can modify RWU in some circumstances. In general, interrupts enabled by these control
bits are cleared by reading SCSR, then reading (receiver status bits) or writing (transmitter status bits)
SCDR.
SCCR1A/B15 — Not Implemented
LOOPS — Loop Mode
0 = Normal SCI operation, no looping, feedback path disabled
1 = Test SCI operation, looping, feedback path enabled
LOOPS controls a feedback path on the data serial shifter. When loop mode is enabled, SCI transmitter
output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver
must be enabled prior to entering loop mode.
WOMS — Wired-OR Mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open-drain output.
WOMS determines whether the TXD pin is an open-drain output or a normal CMOS output. This bit is
used only when TXD is an output. If TXD is used as a general-purpose input pin, WOMS has no effect.
ILT — Idle-Line Detect Type
0 = Short idle-line detect (start count on first one)
1 = Long idle-line detect (start count on first one after stop bit(s))
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PT — Parity Type
0 = Even parity
1 = Odd parity
When parity is enabled, PT determines whether parity is even or odd for both the receiver and the transmitter.
PE — Parity Enable
0 = SCI parity disabled
1 = SCI parity enabled
PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the received parity bit is not correct, the SCI sets the PF error flag in SCSR.
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When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which results in either seven or eight bits of user data, depending on the condition of M bit. The following table
lists the available choices.
M
PE
Result
0
0
8 Data Bits
0
1
7 Data Bits, 1 Parity Bit
1
0
9 Data Bits
1
1
8 Data Bits, 1 Parity Bit
M — Mode Select
0 = SCI frame: one start bit, eight data bits, one stop bit (ten bits total)
1 = SCI frame: one start bit, nine data bits, one stop bit (11 bits total)
WAKE — Wakeup by Address Mark
0 = SCI receiver awakened by idle-line detection
1 = SCI receiver awakened by address mark (last bit set)
TIE — Transmit Interrupt Enable
0 = SCI TDRE interrupts inhibited
1 = SCI TDRE interrupts enabled
TCIE — Transmit Complete Interrupt Enable
0 = SCI TC interrupts inhibited
1 = SCI TC interrupts enabled
RIE — Receiver Interrupt Enable
0 = SCI RDRF interrupts inhibited
1 = SCI RDRF interrupts enabled
ILIE — Idle-Line Interrupt Enable
0 = SCI IDLE interrupts inhibited
1 = SCI IDLE interrupts enabled
TE — Transmitter Enable
0 = SCI transmitter disabled (TXD pin may be used for general-purpose I/O)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter)
The transmitter retains control of the TXD pin until completion of any character transfer in progress
when TE is cleared.
RE — Receiver Enable
0 = SCI receiver disabled (status bits inhibited, RXD pin may be used for general-purpose I/O))
1 = SCI receiver enabled (RXD pin dedicated to SCI)
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RWU — Receiver Wakeup
0 = Normal receiver operation (received data recognized)
1 = Wakeup mode enabled (received data ignored until awakened)
Setting RWU enables the wakeup function, which allows the SCI to ignore received data until awakened
by either an idle line or address mark (as determined by WAKE). When in wakeup mode, the receiver
status flags are not set, and interrupts are inhibited. This bit is cleared automatically (returned to normal
mode) when the receiver is awakened.
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SBK — Send Break
0 = Normal operation
1 = Break frame(s) transmitted after completion of current frame
SBK provides the ability to transmit a break code from the SCI. If the SCI is transmitting when SBK is
set, it will transmit continuous frames of zeros after it completes the current frame, until SBK is cleared.
If SBK is toggled (one to zero in less than one frame interval), the transmitter sends only one or two
break frames before reverting to idle line or commencing to send data.
SCSRA, SCSRB — SCI Status Register
15
14
13
12
11
10
$YFFC1C, $YFFC2C
9
NOT USED
8
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
RAF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
Each SCSR contains flags that show SCI operational conditions. These flags can be cleared either by
hardware or by a special acknowledgment sequence. The sequence consists of SCSR read with flags
set, followed by SCDR read (write in the case of TDRE and TC). A long-word read can consecutively
access both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the
read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits,
but before the CPU has written or read register SCDR, the newly set status bit is not cleared — SCSR
must be read again with the bit set, and SCDR must be written or read before the status bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit already set in either
byte will be cleared on a subsequent read or write of register SCDR.
TDRE — Transmit Data Register Empty Flag
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character may now be written to register TDR.
TDRE is set when the byte in register TDR is transferred to the transmit serial shifter. If TDRE is zero,
transfer has not occurred and a write to TDR will overwrite the previous value. New data is not transmitted if TDR is written without first clearing TDRE.
TC — Transmit Complete Flag
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or
queued breaks (logic zero). The interrupt may be cleared by reading SCSR when TC is set and then by
writing the transmit data register (TDR) of SCDR.
RDRF — Receive Data Register Full Flag
0 = Register RDR is empty or contains previously read data.
1 = Register RDR contains new data.
RDRF is set when the content of the receive serial shifter is transferred to the RDR. If one or more errors
are detected in the received word, flag(s) NF, FE, and/or PF are set within the same clock cycle.
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RAF — Receiver Active Flag
0 = SCI receiver is idle.
1 = SCI receiver is busy.
RAF indicates whether the SCI receiver is busy. It is set when the receiver detects a possible start bit
and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in
systems with multiple masters.
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IDLE — Idle-Line Detected Flag
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line
condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF
is set when a break is received, so that a subsequent idle line can be detected.
OR — Overrun Error Flag
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
OR is set when a new byte is ready to be transferred from the receive serial shifter to the RDR, and
RDRF is still set. Data transfer is inhibited until OR is cleared. Previous data in RDR remains valid, but
data received during overrun condition (including the byte that set OR) is lost.
NF — Noise Error Flag
0 = No noise detected on the received data.
1 = Noise occurred on the received data.
NF is set when the SCI receiver detects noise on a valid start bit, on any data bit, or on a stop bit. It is
not set by noise on the idle line or on invalid start bits. Each bit is sampled three times. If all three samples are not the same logic level, the majority value is used for the received data value, and NF is set.
NF is not set until an entire frame is received and RDRF is set.
FE — Framing Error Flag
1 = Framing error or break occurred on the received data.
0 = No framing error on the received data.
FE is set when the SCI receiver detects a zero where a stop bit was to have occurred. FE is not set until
the entire frame is received and RDRF is set. A break can also cause FE to be set. It is possible to miss
a framing error if RXD happens to be at logic level one at the time when the stop bit is expected.
PF — Parity Error Flag
1 = Parity error occurred on the received data.
0 = No parity error on the received data.
PF is set when the SCI receiver detects a parity error. PF is not set until the entire frame is received and
RDRF is set.
SCDRA, SCDRB — SCI Data Register
$YFFC1E, $YFFC2E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R8/T8
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
U
RESET:
0
Each SCDR consists of two data registers at the same address. RDR is a read-only register that contains data received by the SCI serial interface. The data comes into the receive serial shifter and is
transferred to RDR. TDR is a write-only register that contains data to be transmitted. The data is first
written to TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or
the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning or effect.
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8 Standby RAM with TPU Emulation
The standby RAM with TPU emulation module (TPURAM) contains a 2-Kbyte array of fast (two bus cycle) static RAM, which is especially useful for system stacks and variable storage. The RAM can be
used to emulate TPU microcode ROM. The TPURAM can be mapped to any 2-Kbyte boundary in the
address map, but must not overlap the module control registers — overlap makes the registers inaccessible. TPURAM responds to both program and data space accesses. Data can be read or written in
bytes, word, or long words. The RAM is powered by VDD in normal operation. During power-down, the
RAM contents are maintained by power on standby voltage pin VSTBY. Power switching between sources is automatic.
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8.1 TPURAM Register Block
TPURAM control registers occupy a 64-byte block. There are three TPURAM control registers in the
block: the RAM module configuration register (TRAMMCR), the RAM test register (TRAMTST), and the
RAM array base address register (TRAMBAR). The rest of the register block contains unimplemented
register locations. Unimplemented register addresses are read as zeros, and writes to them have no
effect.
Table 31 TPURAM Control Register Address Map
Address
$YFFB00
$YFFB02
$YFFB04
$YFFB06–
$YFFB3F
15
8 7
RAM MODULE CONFIGURATION REGISTER (TRAMMCR)
RAM TEST REGISTER (TRAMTST)
RAM BASE ADDRESS AND STATUS REGISTER (TRAMBAR)
NOT IMPLEMENTED
0
Y = M111, where M is the state of the modmap bit in the module configuration register of the
single-chip integration module. In an MC68HC16Y1 system, M must always be set to one.
8.2 TPURAM Registers
Access to the TPURAM array is controlled by the RASP field in the TRAMMCR.
TRAMMCR — RAM Module Configuration Register
15
12
8
STOP
PDS
RASP
U
U
$YFFB00
7
0
NOT USED
RESET:
0
Bits in TRAMMCR determine whether the RAM is in low-power stop mode or normal mode, indicate failure of standby RAM power, and determine in which address space the array resides. Reads of unimplemented bits always return zeros. Writes do not affect unimplemented bits.
STOP — Stop Control Bit
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in low-power consumption mode or operating normally. Reset
state is zero, for normal operation. In stop mode, the array retains its contents, but cannot be read or
written by the CPU.
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PDS — Standby Power Status Bit
0 = Loss of standby power.
1 = No loss of standby power
The RAM array can be powered by a standby power source (VSTBY) while VDD to the microcontroller is
turned off. PDS indicates when VSTBY has fallen below a reference level for a specified period of time.
To detect power loss, software must first set PDS, then monitor its state during normal operation and
following reset.
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RASP[1:0] — RAM Array Space Field
o = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space.
This bit limits access to the SRAM array in microcontrollers that support separate user and supervisor
operating modes. Because the CPU16 in the MC68HC16Y1 operates in supervisor mode only, RASP
has no effect.
TRAMTST — RAM Test Register
TRAMTST is used for factory test of the TPURAM module.
$YFFB02
TRAMBAR — RAM Base Address and Status Register
$YFFB04
16
ADDR
23
3
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
0
0
0
0
0
0
0
0
0
0
0
0
NOT
USED
RAMDS
RESET:
0
0
0
0
1
TRAMBAR is used to specify an array base address in the system memory map. This prevents accidental remapping of the array. TRAMBAR can be written only once after reset.
TRAMBAR[15:3] — RAM Array Base Address Field
This field specifies bits [23:11] of the array base address. The array must be enabled in order to be accessed. Since the states of ADDR[23:20] follow the state of ADDR19 in the MC68HC16Y1, addresses
in the range $080000 to $F7FFFF cannot be accessed.
RAMDS — RAM Array Disable Status Bit
0 = RAM array is enabled
1 = RAM array is disabled
RAMDS indicates whether the array is active or disabled. The array is disabled after reset. Writing a
valid base address into RAMBAR automatically clears RAMDS and enables the array.
8.3 TPURAM Operation
There are six TPURAM operating modes, as follows.
The RAM module is in normal mode when powered by VDD. The array can be accessed by byte, word,
or long word. A byte or aligned word (high-order byte is at an even address) access only takes one bus
cycle or two system clocks. A long word or misaligned word access requires two bus cycles.
Standby mode is intended to preserve RAM contents when VDD is removed. SRAM contents are maintained by VSTBY. Circuitry within the SRAM module switches to the higher of VDD or VSTBY with no loss
of data. When SRAM is powered by VSTBY, access to the array is not guaranteed.
Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchronous
reset occurs while a byte or word SRAM access is in progress, the access will be completed. If reset
occurs during the first word access of a long-word operation, only the first word access will be completed. If reset occurs during the second word access of a long word operation, the entire access will be
completed. Data being read from or written to the RAM may be corrupted by asynchronous reset.
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Test mode functions in conjunction with the SCIM test functions. Test mode is used during factory test
of the MCU.
Writing the STOP bit of RAMMCR causes the SRAM module to enter stop mode. The RAM array is disabled (which allows external logic to decode SRAM addresses, if necessary), but all data is retained. If
VDD falls below VSTBY during stop mode, internal circuitry switches to VSTBY, as in standby mode. Stop
mode is exited by clearing the STOP bit.
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The TPURAM array may be used to emulate the microcode ROM in the TPU module. This provides a
means of developing custom TPU code. The TPU selects TPU emulation mode. While in TPU emulation mode, the access timing of the TPURAM module matches the timing of the TPU microinstruction
ROM to ensure accurate emulation. Normal accesses via the IMB are inhibited and the control registers
have no effect, allowing external RAM to emulate the TPURAM at the same addresses. See 4 Time
Processor Unit for more information.
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9 Masked ROM Module
The masked ROM module (MRM) is designed to be used with the entire line of Motorola modular microcontrollers. The MRM consists of a fixed-location control register block and a memory array. Configuration information is contained in the register block. Default reset base address of the array in the
system address map is specified by the customer, but the array may be remapped to other addresses.
In addition to the array base address, the register block contains operating parameters, bootstrap code,
and ROM verification information. An address map of the register block follows.
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Table 32 MRM Control Register Address Map
Address
$YFF820
$YFF822
$YFF824
$YFF826
$YFF828
$YFF82A
$YFF82C
$YFF82E
$YFF830
$YFF832
$YFF834
$YFF836
$YFF838
$YFF83A
$YFF83C
$YFF83E
15
8 7
MASKED ROM MODULE CONFIGURATION REGISTER (MRMCR)
NOT IMPLEMENTED
ARRAY BASE ADDRESS REGISTER HIGH (ROMBAH)
ARRAY BASE ADDRESS REGISTER LOW (ROMBAL)
ROM SIGNATURE HIGH REGISTER (RSIGHI)
ROM SIGNATURE LOW REGISTER (RSIGLO)
NOT IMPLEMENTED
NOT IMPLEMENTED
ROM BOOTSTRAP WORD 0 (ROMBS0)
ROM BOOTSTRAP WORD 1 (ROMBS1)
ROM BOOTSTRAP WORD 2 (ROMBS2)
ROM BOOTSTRAP WORD 3 (ROMBS3)
NOT IMPLEMENTED
NOT IMPLEMENTED
NOT IMPLEMENTED
NOT IMPLEMENTED
0
Y = M111, where M is the state of the modmap bit in the module configuration register of the
single-chip integration module. In an MC68HC16Y1 system, M must always be set to one.
The ROM array in the MC68HC16Y1 contains 48 Kbytes. It is arranged in 16-bit words, and is accessed
via the intermodule bus. Bytes, words, and misaligned words can be accessed. Access time depends
upon the number of wait states specified at mask programming time, but can be as fast as two system
clocks for byte and aligned words. The MRM also responds to back-to-back IMB accesses to provide
two bus cycle long word access.
The array base address must be on a 64 Kbyte boundary, must not overlap the control registers of other
microcontroller modules, and should not overlap the control register block. The array occupies the loworder locations in the 64 Kbyte block —accesses to the remaining 16 Kbytes of unimplemented locations in the block are ignored by the MRM, allowing other system resources or external devices to respond to the access. If the array is mapped to overlap the control registers of other modules, accesses
to those registers will be indeterminate; if the array is mapped to overlap the MRM control registers,
accesses to the registers are still possible, but accesses to the overlapping 32 bytes of ROM bytes will
be ignored.
The primary function of the MRM is to serve as nonvolatile memory for the microcontroller. It can be
configured to support system bootstrap during reset. The CPU16 in the MC68HC16Y1 differentiates between program space accesses and data space accesses. The MRM array can be used for program
code only, or for both program code and data. The MRM can also be programmed to insert wait states
to accommodate migration from slower external development memory to the ROM array without retiming.
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The MRM can also operate in a special emulator mode that simplifies emulation of the array by an external device. Emulation mode is enabled by the EMUL bit in the MRMCR. EMUL state is determined
by the state of the DATA10 and DATA13 lines during reset. If both data lines are held low, EMUL is set,
and ROM emulation mode is enabled.
While emulation mode is enabled, the internal module chip select signal (CSM) is asserted whenever a
valid access to an address assigned to the masked ROM module is made. To be valid, an access must
be within the range specified by the ROM base array registers and must meet the address space requirements defined by the ASPC field in MRMCR. CSM is asserted for all valid read accesses; it is asserted for write accesses only in background debug mode. The MRM does not acknowledge an access
on the IMB while in emulation mode — this causes the SCIM to run an external bus cycle. The CSM
signal is asserted on the falling edge of AS. Internal DSACK is generated by the ROM module after it
has inserted the number of wait states specified by the WAIT field in the MRMCR.
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9.1 Masked ROM Control Registers
The 32-byte control register block contains registers that are used to configure the MRM and to control
ROM array function. Configuration information is specified and programmed at the same time as the
ROM content.
MRMCR — Masked ROM Module Configuration Register
9
8
$YFF820
15
14
13
12
11
10
5
4
3
2
1
0
STOP
0
0
BOOT
LOCK
EMUL
ASPC
7
WAIT
6
0
0
0
0
0
0
0
0
USER
SPEC
USER
SPEC
*
USER
SPEC
USER
SPEC
0
0
0
0
0
0
RESET:
*
*Reset state of STOP = DATA14. Reset state of EMUL = (DATA10 • DATA13).
STOP — Stop Bit
0 = Normal ROM operation
1 = Disable ROM and activate emulator mode if enabled
Reset state of STOP is the complement of DATA14 state during reset. ROM array base address cannot
be changed unless STOP is set.
BOOT — Boot ROM Control Bit
0 = CPU16 accesses ROM array addresses after reset
1 = CPU16 cannot access ROM array addresses after reset
Reset state of BOOT is specified by the user. Bootstrap function is overridden if STOP = 1.
LOCK — Lock Registers Bit
0 = Write lock disabled; protected registers and fields can be written
1 = Write lock enabled; protected registers and fields cannot be written
Reset state of LOCK is specified by the user. LOCK protects the ASPC and WAIT fields, as well as the
ROMBAL and ROMBAH registers. ASPC, ROMBAL and ROMBAH are also protected by the STOP bit.
EMUL — Emulator Mode Control Bit
0 = Normal ROM operation
1 = MRM enters emulator mode when STOP is set.
Reset state of EMUL is the complement of DATA10 and DATA13 state during reset. When EMUL is set,
the MRM responds to accesses by asserting the CSM signal.
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ASPC — ROM Array Space Field
Because the MC68HC16Y1 operates only in supervisory mode, ASPC determines whether accesses
are restricted solely to program space, or whether accesses are made to both program and data space.
In systems with restricted access levels, ASPC also determines whether accesses are restricted solely
to supervisor space. The reset state of ASPC is user specified. The table below shows ASPC encoding.
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ASPC[1:0]
X0
X1
State Specified
Program and data access
Program access only
WAIT — Wait States Field
WAIT specifies the number of wait states inserted by the MRM during ROM array accesses. It allows
the user to optimize bus speed in a particular application by controlling the number of wait states that
are inserted prior to internal DSACK generation. Each wait state has a duration of one system clock
cycle. This allows a user to transport code from a slower emulation or development system memory to
the ROM array without retiming the system. The reset state of WAIT is user specified. The table below
shows WAIT encoding. A no-wait encoding (%00) corresponds to a three clock-cycle bus. The fast termination encoding (%11) corresponds to a two clock-cycle bus — microcontroller modules typically respond at this rate, but fast termination can also be used to access fast external memory.
WAIT[1:0]
00
01
10
11
Cycles per Transfer
3
4
5
2
ROMBAH — Array Base Address Register High
15
14
13
12
11
10
9
$YFF824
8
NOT USED
7
6
5
4
3
2
1
0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
RESET:
0
0
0
0
0
0
0
0
USER SPECIFIED
ROMBAL — Array Base Address Register Low
$YFF826
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
0
ROMBAH and ROMBAL are used to specify ROM array base address. They can only be written when
STOP = 1 and LOCK = 0. This prevents accidental remapping of the array. Since the states of ADDR[23:20] follow the state of ADDR19 in the MC68HC16Y1, addresses in the range $080000 to
$F7FFFF cannot be accessed. Because the 48 Kbyte ROM array in the MC68HC16Y1 must be mapped
to a 64 Kbyte boundary, ROMBAL always contains $0000.
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RSIGHI — ROM Signature High Register
15
14
13
12
11
10
$YFF828
9
8
7
6
5
4
3
NOT USED
2
1
0
RSP18
RSP17
RSP16
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
USER SPECIFIED
RSIGLO — ROM Signature Low Register
$YFF82A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSP15
RSP14
RSP13
RSP12
RSP11
RSP10
RSP9
RSP8
RSP7
RSP6
RSP5
RSP4
RSP3
RSP2
RSP1
RSP0
RESET:
Freescale Semiconductor, Inc...
USER SPECIFIED
RSIGHI and RSIGLO are used to specify a ROM signature pattern. A special signature identification
algorithm allows the user to verify the content of the ROM array. The signature is specified by the user
and cannot be changed.
ROMBS0 — ROM Bootstrap Word 0
$YFF830
ROMBS1 — ROM Bootstrap Word 1
$YFF832
ROMBS2 — ROM Bootstrap Word 2
$YFF834
ROMBS3 — ROM Bootstrap Word 3
$YFF836
Typically, reset vectors for the system CPU are contained in nonvolatile memory and are only fetched
when the CPU comes out of reset. The user can specify that these four words be used as reset vectors,
and can specify the content of these locations. The content of these words cannot be changed. In the
MC68HC16Y1, ROMBS0 to ROMBS3 correspond to system addresses $000000 to $000006.
MC68HC16Y1
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10 Summary of Changes
Freescale Semiconductor, Inc...
This is a partial revision. Most of the publication remains the same, but the following changes were
made to improve it. Typographical errors that do not affect content are not annotated.
Page 4
Block diagram revised. All pin functions shown, port mnemonics changed.
Pages 6–8
Corrected port assignments, new notes, changed B driver description.
Pages 9 & 11
Changed ADC analog input mnemonics and parallel port mnemonics to prevent confusion.
Page 15
Added XMSK, YMSK registers to diagram.
Page 36
SCIM address map standardized.
Page 39
Added RSR description.
Pages 56–59
New reset section.
Pages 59–61
New interrupts section.
Page 66
Corrected PORTFE reset state.
Page 77
Removed RSR from test register listing.
Page 79
TPU address map standardized.
Page 90
GPT address map standardized.
Pages 90 & 95
Changed GPT I/O port register mnemonics to reflect port name.
Page 102
ADC address map standardized.
Pages 102–109
Changed ADC analog input mnemonics and parallel port mnemonics
to prevent confusion.
Page 106
Changed prescaler rate selection table to show %00000 setting is reserved.
Page 109
Added Result Register mnemonics.
Page 111
MCCI address map standardized.
Pages 111 & 114
Changed MCCI I/O port register mnemonics to reflect port name.
MOTOROLA
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Freescale Semiconductor, Inc...
NOTES
MC68HC16Y1
MC68HC16Y1TS/D
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