Ordering number: ENA1963 LV4904V Monolithic IC Digital Input Class-D Power Amplifier Overview The LV4904V is a 2-channel class-D amplifier IC that supports digital input. With this single chip and with a minimal number of external components, it is possible to effectively implement class-D amplifiers. The LV4904V incorporates a soft mute function and a gain controller without pop noise, and can be used as a master volume control of the set. Its function settings can be established through an I2C bus interface, but it is also possible to establish these settings simply by pin settings without using the I2C bus. The LV4904V is ideally suited as the power amplifiers in mini components, flat-panel TVs, game machines, electronic musical instruments and other such products. Features • I2S input, 2-channel class-D power amplifier • On-chip variable over-sampler • Gain controller (+12dB to -81dB, in 1.5 dB increments) • Soft mute function • Controllable via I2C bus or pin settings • Under voltage protection circuit, overcurrent protection circuit, thermal protection circuit integrated Functions • Input PCM (Fs): 32 kHz/44.1 kHz/48 kHz/88.1 kHz/96 kHz/176.2 kHz/192 kHz • Master clock input: 256 fs/384 fs/512 fs/768 fs (when Fs=32/44.1/48 kHz) • Input format: I2S/24 bits left justified MSB-first / 24 bits right justified LSB-first / 16/18/20/24 bits right justified MSB-first • Output (THD + N=10%) : 10W × 2 channels (PVD = 15V, RL = 8Ω), 15W × 2 channels (PVD = 18V, RL = 8Ω) • Efficiency : 85% (PVD = 15V, RL = 8Ω, fin = 1 kHz, Po = 10W) • THD + N : 0.1% or less (PVD = 15V, RL = 8Ω, fin = 1 kHz, Po = 1W, filter: AES17) • Power supply voltages : PVD = 8 to 20V, VDD = 3.3V Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 92811 SY 20110606-S00002 No.A1963-1/30 LV4904V Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Power cell power supply PVD Externally applied power supply -0.3 to 24 V Logic power supply VDD Externally applied power supply -0.3 to 4.0 V Maximum junction temperature Tj max 125 °C Operating temperature Topr -30 to +70 °C Storage temperature Tstg -50 to +150 °C Recommended Operating Range at Ta = 25°C Ratings Parameter Symbol Conditions Unit min typ max Power cell power supply PVD Externally applied power supply 8 13 20 V Logic power supply VDD Externally applied power supply 3.0 3.3 3.6 V Load RL Speaker load 8 - - Ω Electrical Characteristics Ratings Parameter Symbol Conditions Unit min typ max Digital/Ta=25°C, VDD=3.3V, PVD=13V Standby current IPD - 1 10 μA Operating current IOP - 12 30 mA V H input voltage VIHHIS 0.8VDD - 5.5 L input voltage VILHIS -0.3 - 0.2VDD V H input current I IH - - 10 μA VIN=VDD L input current II L VIN=GND -10 - - μA Output pin current IOH VOUT=VDD-0.4V -0.8 - - mA IOL VOUT=0.4V 1 - - mA Power/Ta=25°C, VDD=3.3V, PVD=13V, RL=8Ω, L=22μH(TOKO:A7040HN-220M), C=33μF, Fin=1kHz Standby current IST PVD, RSTB=Low - 1 10 μA Mute on current IMUTE PVD, ENABLE=Low - 1 10 mA Quiescent current ICCO PVD, 50% duty - 16 60 mA Power Tr. ON resistance *1 RDSON ID=1A - 300 - mΩ Output power Pout1 8Ω, 15V, THD+N=10%, Modulation index 9 10 - W 12 14 - W - 4 10 mV 87.5% Pout2 8Ω, 18V, THD+N=10%, Modulation index 87.5% Output noise VN IHF-A THD+N THD PO=1W, 1kHz, 8Ω - 0.1 0.3 % Channel separation CHSEP PO=1W, 1kHz, 8Ω 40 60 - dB *1 : The maximum power transistor ON resistance(RDSON) is 360mΩ(design guarantee value). Note : The value of these characteristics were measured in SANYO test environment. The actual value in an end system will vary depending on the printed circuit board pattern, the components used, and other factors. No.A1963-2/25 LV4904V Package Dimensions unit : mm (typ) 3285 TOP VIEW BOTTOM VIEW Exposed Die-Pad 15.0 23 0.5 5.6 7.6 44 1 22 0.22 0.65 0.2 1.7max (0.68) (1.5) SIDE VIEW SANYO : SSOP44J(275mil) Pd max -- Ta Allowable power dissipation, Pd max -- W 3.0 Specified board : 85.0 × 59.0 × 1.5mm3 glass epoxy(2-layer) 2.40 2.0 1.85 The exposed Die-pad is mounted The exposed Die-pad is not mounted 1.32 1.02 1.0 0 --30 0 60 30 90 120 Ambient temperature, Ta -- C SCL SDA GAIN0 GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 MUTEB MODE TEST VDD VSS PTAB1 PVD1 OUT_CH1_P BOOT_CH1_P VDDA1 BOOT_CH1_N OUT_CH1_N PGND1 PGND1 Pin Assignment 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RSTB ENABLE MCK BCK LRCK SDIN DFORM0 DFORM1 DFORM2 MCKFS SRATE VDD VSS PTAB2 PVD2 OUT_CH2_P BOOT_CH2_P VDDA2 BOOT_CH2_N OUT_CH2_N PGND2 PGND2 LV4904V Top view No.A1963-3/25 LV4904V Application Circuit 44 SCL 43 SDA 42 GAIN0 41 GAIN1 40 GAIN2 39 GAIN3 38 GAIN4 37 GAIN5 36 MUTEB 35 MODE 34 TEST 33 32 I2C Bus Control Signal Mute Signal V DD V SS 31 PTAB1 30 PVD1 29 OUT_CH1_P 28 BOOT_CH1_P 27 VDDA1 26 BOOT_CH1_N 25 OUT_CH1_N 24 PGND1 23 PGND1 RL + LV4904V + VDD DC 3.3V 22 PGND2 21 PGND2 20 OUT_CH2_N 19 BOOT_CH2_N 18 V DD A2 RL 17 BOOT_CH2_P 16 OUT_CH2_P 15 PVD2 14 PTAB2 13 V SS 12 V DD 11 SRATE 10 MCKFS 9 DFORM2 8 DFORM1 7 DFORM0 Control Signal 6 SDIN 5 LRCK 4 BCK 3 MCK I2S Inputs 2 ENABLE Enable Signal 1 RSTB Reset Signal - - VD DC 8-20V No.A1963-4/25 LV4904V Block Diagram PVD1 4 5 6 3 2 7 8 9 10 11 42 41 40 39 38 37 36 35 34 OUTPUT STAGE CH1+ PWM RECEIVER VSS BOOT_CH1_P BCK LRCK SDIN MCK BOOT_CH1_N PWM RECEIVER OUTPUT STAGE CH1- OUT_CH1_N PGND1 PGND1 THERMAL OVER CURRENT PGND2 PGND2 ENABLE 26 25 24 23 22 21 DFORM0 DFORM1 DFORM2 OUT_CH2_N OUTPUT STAGE CH2- MCKFS PWM RECEIVER SRATE 20 19 CONTROL DELAY GAIN0 GAIN1 BOOT_CH2_N BOOT_CH2_P CONTROLLER PWM RECEIVER GAIN2 OUTPUT STAGE CH2+ GAIN3 OUT_CH2_P PVD2 GAIN4 17 16 15 GAIN5 VDDA1 MUTEB REGULATOR (5V) MODE VDDA2 27 18 TEST PGND1 PTAB1 PGND2 44 28 SEQUENCE VSS 43 29 CONTROL DELAY PWM_CONVERTER 32 VDD NOISE_SHAPING 33 OUT_CH1_P VSS VOLUME_CONTROLLER 13 30 VDD OVER_SAMPLER 12 RSTB SERIAL/PARALLEL CONVERTER 1 SDA SCL PTAB2 I2C I/F 31 14 No.A1963-5/25 LV4904V Pin Equivalent Circuit Pin No. 1 Pin name I/O Description RSTB DI Reset input (low active) 2 ENABLE DI System enable input 3 MCK DI Master clock input 4 BCK DI 3-wire serial bit clock input 5 LRCK DI 3-wire serial LR clock input 6 SDIN DI 3-wire serial data input 7 DFORM0 DI Input format setting input 0 8 DFORM1 DI Input format setting input 1 9 DFORM2 DI Input format setting input 2 10 MCKFS DI Master clock (MCK) rate setting pin 11 SRATE DI Input data sampling rate setting pin 12 VDD - Digital power supply (3.3V) 13 VSS - Small-signal ground (GND) 14 PTAB2 - Substrate ground 15 PVD2 - Power cell power supply 16 OUT_CH2_P O Output pin, channel 2 (Rch) + Equivalent Circuit PVD 16 GND 17 BOOT_CH2_P I/O 18 VDDA2 O Bootstrap I/O pin, channel 2 (Rch) + De-coupling capacitor connection pin for internal power supply 19 BOOT_CH2_N I/O Bootstrap I/O pin, channel 2 (Rch) - 20 OUT_CH2_N O Output pin, channel 2 negative PVD 20 GND 21 PGND2 - Channel 2 power ground 22 PGND2 - Channel 2 power ground 23 PGND1 - Channel 1 power ground 24 PGND1 - Channel 1 power ground 25 OUT_CH1_N O Output pin, channel 1 (Lch) - PVD 25 GND 26 BOOT_CH1_N I/O Bootstrap I/O pin, channel 1 (Lch) - 27 VDDA1 O De-coupling capacitor connection pin for internal 28 BOOT_CH1_P I/O Bootstrap I/O pin, channel 1 (Lch) + power supply Continued on next page. No.A1963-6/25 LV4904V Continued from preceding page. Pin No. 29 Pin name I/O OUT_CH1_P O Description Output pin, channel 1 (Lch) + Equivalent Circuit PVD 29 GND 30 PVD1 - Power cell power supply 31 PTAB1 - Substrate ground 32 VSS - Small-signal ground 33 VDD - Digital IO power supply (3.3V) 34 TEST DI Test mode setting pin (fixed at a low level) 35 MODE DI Output mode setting pin 36 MUTEB DI Mute setting input (low active) 37 GAIN5 DI Gain setting input 5 38 GAIN4 DI Gain setting input 4 39 GAIN3 DI Gain setting input 3 40 GAIN2 DI Gain setting input 2 41 GAIN1 DI Gain setting input 1 42 GAIN0 43 SDA DIO DI 44 SCL DI Gain setting input 0 [I2C I/F] data [I2C I/F] bit clock 44 No.A1963-7/25 LV4904V 2 1. Mode Switching (combined I C bus and pin setting mode Ù pin setting mode) 1.1 Description of modes Combined I2C bus and pin setting mode In this mode, the function settings can be established according to both the I2C bus and pins. With some pin settings, the settings established according to the I2C bus registers are enabled; with the other pin settings, the settings established according to the pins are enabled. Pin setting mode In this mode, the LV4904V is controlled only by pin settings. This has the advantage of not requiring the I2C bus for control purposes, but the parameters that can be set are limited. Table 1.1 below lists the differences between the items that can be set through the I2C bus and those that can be set using only the pins. Table 1.1 Differences between combined I2C bus and pin setting mode Symbol Description Settings Using the I2C Bus Settings Using the Pin DFORM Input data format 7 formats available 2 formats available MCKFS Master clock (MCK) rate 4 rates available (256fs, 384fs, 512fs, and 768fs) 2 rates available (256fs and 512fs) SRATE Input data sampling rate 32 kHz to 192 kHz 44.1 kHz to 96 kHz Gain controller setting 2-channel independently controllable 2-channel common control GAIN MUTE Muting 2-channel independently controllable 2-channel common control PSTP PWM output stop setting 2-channel independently controllable 2-channel common control IDPEN 50% pulse setting during mute ON or OFF setting enabled ON fixed MDIDX Modulation index setting 87.5% Ù 100% switchable 87.5% fixed NSORD Noise shaping orders Fifth order Ù seventh order switchable Seventh order fixed 1.2 Mode setting methods Combined I2C bus and pin setting mode The combined I2C bus and pin setting mode is established when RSTB is set from low to high in a state other than SCL=SDA=low. However, for this to happen, it is necessary that proper clocks have been input from the MCK pin. SCL SDA RSTB Combined I2C bus and pin setting mode Figure1-1 Placing the IC in combined I2C bus and pin setting mode Pin setting mode The pin setting mode is established when RSTB is set from low to high in the SCL=SDA=low state. However, for this to happen, it is necessary that proper clocks have been input from the MCK pin. SCL SDA RSTB Pin setting mode Figure1-2 Placing the IC in pin setting mode No.A1963-8/25 LV4904V 2. Description of Pin Functions 2.1 Hardware reset pin (RSTB) RSTB is a low active hardware reset pin. The LV4904V is initialized by setting this pin to low. When the pin is set to low, the internal registers are cleared, and the I2C bus registers are also reset to the initial values. Table 2.1 shows the RSTB function settings. Table 2.1 RSTB pin functions RSTB Setting L Hardware reset (registers cleared) H For normal operation 2.2 System enable pin (ENABLE) ENABLE is the system enable pin of the LV4904V. When this pin is set to low, the output is muted regardless of any other settings (mute, gain), and the PWM output is stop(set to high-impedance). ENABLE must be set to high in order to activate the LV4904V. If the ENABLE function does not need to be set to ON or OFF, the ENABLE pin can be fixed at high. Table 2.2 shows the ENABLE function settings. Table 2.2 ENABLE pin function settings ENABLE Setting L System disabled H System enabled 2.3 Master clock input pin (MCK) The master clock is input from the MCK pin. For details on this pin, refer to “8.1 Input data settings.” 2.4 3-wire serial data input pins (BCK, LRCK, SDIN) BCK, LRCK and SDIN are pins used for 3-wire serial data input. For details on these pins, refer to “8.1 Input data settings.” 2.5 I2C bus pins (SCL, SDA) SCL and SDA are the pins used for I2C bus communication. The I2C bus interface of the LV4904V does not function as the master but operates only as a slave. SCL is the I2C bus clock pin and operates only as an input pin. This means that the LV4904V never requests wait by pulling the SCL line to low. SDA is the I2C bus data pin, and since it is an N-channel open drain pin, the data line must be pulled up. For details on the I2C bus interface, refer to “5 I2C Bus Specifications.” No.A1963-9/25 LV4904V 2.6 Input data format setting pins (DFORM0, DFORM1, DFORM2) The DFORM0, DFORM1 and DFORM2 pins are set to high or low to match the data format that is input. In the combined I2C bus and pin setting mode, the data format settings (Table 5.1.1) established according to the I2C register are valid when DFORM0, DFORM1, and DFORM2 are low. Since the initial setting of the I2C register is I2S, I2S is the setting that is established when DFORM0, DFORM1, and DFORM2 are low in the initial state after reset release. Table 2.6 shows the format settings established according to the DFORM0, DFORM1, and DFORM2 pins. Table 2.6 Input data format settings Setting DFORM2 DFORM1 L DFORM0 Combined I2C Bus and Pin setting Mode Pin Setting Mode 2 I 2S L L I C register setting L L H Left justified, MSB first L H L Right justified, LSB first L H H 24-bit, right justified, MSB first H L L 20-bit, right justified, MSB first H L H 18-bit, right justified, MSB first H H L 16-bit, right justified, MSB first 2.7 Master clock setting pin (MCKFS) The MCKFS pin is set to high or low to match the rate of the master clock that is to be input from the MCK pin. In the combined I2C bus and pin setting mode, the master clock settings (Table 8.1.2) established according to the I2C register are valid when MCKFS is low. Since the initial setting of the I2C register is 256fs, 256fs is the setting that is established when MCKFS is low in the initial state after reset release. If the rate of the clock that is input from the MCK pin does not match the MCKFS pin or the setting established according to the I2C register, an abnormal sound is generated or the output is set to off. Table 2.7 shows the MCKFS function settings. Table 2.7 MCKFS pin function settings Setting MCKFS 2 Combined I C Bus and Pin setting mode Pin Setting Mode I2C register setting 256 fs L H 512 fs 2.8 Sample rate setting pin (SRATE) The SRATE pin is set to high or low to match the sample rate of the input data. In the combined I2C bus and pin setting mode, the sample rate settings (Table 8.1.2) established according to the I2C register are valid when SRATE is low. Since the initial setting of the I2C register is 44.1 kHz/48 kHz, 44.1 kHz/48 kHz is the setting that is established when SRATE is low in the initial state after reset release. Table 2.8 shows the SRATE function settings. Table 2.8 SRATE pin function settings Setting SRATE L H Combined I2C Bus and Pin setting mode 2 I C register setting Pin Setting Mode 44.1 kHz/48 kHz 88.2 kHz/96 kHz No.A1963-10/25 LV4904V 2.9 Gain setting pins (GAIN0, GAIN1, GAIN2, GAIN3, GAIN4, GAIN5) The gain can be set by setting the GAIN0 to GAIN5 pins to high or low. In the combined I2C bus and pin setting mode, the gain settings (Table 8.2.1) established according to the I2C register are valid when all the GAIN0 to GAIN5 pins are low. Since the initial setting of the I2C register is in mute state, mute is the setting that is established when GAIN0 to GAIN5 are low in the initial state after reset release. Table 2.9 shows the gain settings established according to the GAIN0 to GAIN5 pins. The gain settings established according to the pin 6 bits and the gain settings established according to the register 6 bits are identical, so refer to Table 8.2.1 for the detailed settings. Table 2.9 Gain settings Gain Setting GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 H H H H H H +12.0dB H H H H H L +10.5dB H H H H L H +9.0dB … … … … … … (settings in increments of 1.5dB) H H H L L L +1.5dB H H L H H H 0dB H H L H H L -1.5dB … … … … … … (settings in increments of 1.5dB) L L L L H L -79.5dB L L L L L H -81.0dB L L L L L L Combined I2C Bus and Pin setting mode I2C register settings Pin Setting Mode Mute 2.10 Mute pin (MUTEB) MUTEB is the low active soft mute pin that controls both the left and right channels. In the combined I2C bus and pin setting mode, the mute setting (Table 8.2.2) established according to the I2C register is valid when MUTEB is low. Since the initial setting of the I2C register is in mute state, mute is the setting that is established when MUTEB is low in the initial state after reset release. Table 2.10 shows the MUTEB function settings. Table 2.10 MUTEB pin function settings Setting MUTEB 2 Combined I C Bus and Pin setting mode 2 L I C register setting H Pin Setting Mode Mute ON Mute OFF 2.11 Test mode setting pins (TEST, MODE) TEST and MODE are the test pins. TEST and MODE must be low while using the LV4904V. Table 2.11 shows the TEST, MODE function settings. Table 2.11 TEST, MODE pin settings TEST, MODE Setting L Setting when using the LV4904V H Inhibited No.A1963-11/25 LV4904V 3. Start and Stop Sequences The start and stop sequences given below are recommended in order to reduce pop noise that occurs when LV4909V is turned on or off. 3.1 Start sequence PVD VDD PVD and VDD may be started up in any sequence. >8.0V >3.0V ENABLE >2ms RSTB MCK I2S Input I2C Bus MUTEB MUTEBL_Reg MUTEBR_Reg >50ms Figure 3.1 Start sequence 3.2 Stop sequence PVD and VDD may be stopped in any sequence. PVD VDD ENABLE >1ms RSTB >200ms MUTEB MUTEBL_Reg MUTEBR_Reg OUT_1P/1N OUT2P/2N Hi-Z OUT1P/1N OUT2P/2N (After demodulation) Figure 3.2 Stop sequence No.A1963-12/25 LV4904V 4. Protection Circuits The LV4904V is provided with under voltage protection circuit, overcurrent protection circuit and thermal protection circuit. 4.1 Under voltage protection circuit In order to prevent unstable operation at low voltages, the under voltage protection circuit monitors the PVD pin voltage, and once the attack voltage (PVD=7V typ.) has been exceeded, it turns on the amplifier. Furthermore, the recovery voltage (6V typ.) is set so that unstable operation is also prevented when the PVD pin voltage has dropped for some reason during operation. Since hysteresis of 1V or so is provided between the attack voltage and recovery voltage, unstable operation near the threshold voltage where the under voltage protection circuit is continuously set to ON and OFF is prevented. Figure 4.1 shows the operating model of the under voltage protection circuit. PVD Pin Voltage Recovery Voltage Internal Control Signal Figure 4.1 Under voltage protection circuit operation The circuit is designed to turn the amplifier OFF in the same sequence as when Mute is set to ON so that this can be used as a measure to prevent pop noise when the primary power for PVD has been turned off. SANYO Semiconductors’ demonstration board is designed so that the above processes are carried out by the charge stored in the power supply capacitor (470 µF) that has been added to the primary power supply line. However, bear in mind that, in the actual products into which this IC has been incorporated, the primary power supply is connected to other blocks as well, so the time constant for the fall may differ. No.A1963-13/25 LV4904V 4.2 Overcurrent protection circuit The overcurrent protection circuit is for protecting the output transistors from overcurrent. When it has detected an overcurrent caused by shorting to power, shorting to ground or load shorting and the current level has reached 6A or so, it turns off the output transistors for approximately 20 µsec. About 20 µsec after the output transistors have been turned off, normal operation is recovered automatically, and if another overcurrent is detected, it performs the protection operation again. However, this protection operation is a function that temporarily prevents an overcurrent trouble state and it does not guarantee that the ICs will not be damaged. Figures 4.2.1 and 4.2.2 show the operating models of the overcurrent protection circuit. Output Current Control Operation Self-recovery & Normal Operation Internal Control Signal Figure 4.2.1 Graphical representation of overcurrent protection circuit operation IDETECT Output Current HOLD TIME Internal Control Signal Figure 4.2.2 Graphical representation of overcurrent protection circuit operation (enlarged) No.A1963-14/25 LV4904V 4.3 Thermal protection circuit The thermal protection circuit is designed to safeguard the ICs from damage or deterioration when the ICs have generated abnormally high levels of heat. When inadequate heat dissipation, a faulty wiring connection or other factor has caused the IC junction temperature (Tj) to rise beyond its rating, the thermal protection circuit sets both the high and low sides of the output transistors to OFF and places the output in the high-impedance state. When, after shutdown, the junction temperature has dropped, the IC is automatically recovered. The attack and recovery temperatures of the circuit are provided with hysteresis to prevent unstable operation near the threshold temperature where the thermal protection circuit is continuously set to ON and OFF. However, the thermal protection circuit is a function that temporarily prevents abnormal internal heat generation and does not guarantee that the ICs will not be damaged. Similarly, the operating temperature of the thermal protection circuit is not a guaranteed value. Figure 4.3 is a graphical representation of the thermal protection circuit. Output Current Control Operation Self-Recovery & Nomal Operation Internal Control Signal Figure 4.3 Thermal protection circuit operation No.A1963-15/25 LV4904V 2 5. I C Bus Specifications 5.1 Overview of I2C bus interface The LV4904V supports the standard I2C bus interface (max. 100 kHz). The device ID of the LV4904V is 11011000 (read) and 11011001 (write). Its I2C bus interface does not function as the master but operates only as a slave. 5.2 I2C bus transfer rules In the bus-free state where there is no I2C transmission or reception, both the SCL and SDA pins must be high. From the state in which both pins are high, by holding the SCL pin state to high and setting the SDA to low, communication is started. This is referred to as the start condition. H SCL Start Condition H Bus Free SDA To end I2C transmission or reception, change the SDA pin state from low to high with the SCL still high. This is referred to as the stop condition. H SCL Stop Condition Bus Free SDA H Data transfer is started after the start condition has been transmitted. The data is transferred in 8-bit units from the master to the LV4904V at the slave, and the LV4904V responds every time 8 bits are received by setting the SDA pin to low. This is referred to as acknowledge (ACK). The master sets the bus free and waits for ACK. SCL SDA ACK ACK Data is transsferred in 8-bit unit. The LV4904V returns ACK each time it has received 8-bit data. 5.3 Data write To write data in the LV4904V, the device ID, write address and data are sent in this sequence after the start condition has been sent, and lastly the stop condition is sent. The read/write flag bit is added to the 7-bit device ID, and the write mode is established according to setting this bit too low. LV4904V start 1 1 0 1 1 Device ID=1101100 0 0 R/W ACK Write address LV4904V LV4904V ACK ACK stop Write Data No.A1963-16/25 LV4904V 5.4 Data read By sending the data read command, the data held in the registers of the LV4904V can be read. To read the data, first the address is sent using a dummy write cycle, and then operation is restarted. Next, after the device ID and read flag has been sent in the read cycle, the LV4904V outputs the data of the address sent in the dummy write cycle to the SDA line. The transmission side establishes the I2C bus-free state to prepare for data reception. After the data has been received, ACK is not returned, and the stop condition is sent to end communication. LV4904V LV4904V Device ID start R/W ACK Read Address Device ID start ACK LV4904V LV4904V R/W ACK stop Read Address Read Data Read Address Read Cycle Dummy Write Cycle 5.5 Internal register initialization The internal registers accessed at address FFh through the I2C bus are write-only registers. By writing the value of FFh into these registers, the internal registers are reset to the initial values. LV4904V start 1 0 1 1 0 1 0 LV4904V 1 R/W ACK 1 1 1 1 1 1 1 ACK 1 LV4904V 1 1 1 1 1 1 1 ACK stop Write Data=0xFF Write Address=0xFF 6. I2C Register Map Register Address STAT 00h DATA 10h 0 GAINL 20h PSTPL MUTEBL GAINL [5:0] GAINR 21h PSTPR MUTEBR GAINR [5:0] MISC 30h RST FFh D7 D6 D5 D4 D3 D2 D1 D0 Last accessed address (read-only) MCKFS_I2C [1:0] SRATE_I2C [1:0] Reserved DFORM [2:0] NSORD MDIDX IDPEN 1 SOFTR [7: 0] (for initializing registers) 7. I2C Command List Register DATA Address 10h Bit Signal Name GAINR 20h 21h [2:0] DFORM SRATE_I2C 3-wire serial PCM input, sampling rate setting 01 [6:5] MCKFS_I2C Master clock rate setting 00 0 (Fixed) 0 GAINL Channel 1 (L channel), gain setting [6] MUTEBL Channel 1 (L channel), mute setting 0 [7] PSTPL Channel 1 (L channel), output disable setting 0 [5:0] GAINR Channel 2 (R channel), gain setting 00000 [6] MUTEBR Channel 2 (R channel), mute setting 0 [7] PSTPR 00000 Channel 2 (R channel), output disable setting 0 1 (Fixed) 1 IDPEN Pulse operation control when muted 1 [2] MDIDX PWM modulation index setting 0 [3] NSORD Noise shaper order setting 0 [1] 30h 000 [5:0] [0] MISC 3-wire serial PCM input, format setting Initial Value [4:3] [7] GAINL Pin Description No.A1963-17/25 LV4904V 2 8. Description of I C Bus Registers 8.1 Input data settings Register Address DATA D7 10h D6 D5 D4 2 0 D3 D2 D1 2 MCKFS_I C [1: 0] D0 2 SRATE_I C [1: 0] DFORM _I C [2: 0] DFORM_I2C is set to match the format of the 3-wire serial input that is to be input. The setting established according to DFORM_I2C is valid only when the DFORM0, DFORM1, and DFORM2 pins are low in the combined I2C bus and pin setting mode. With any other pin settings or when the pin setting mode is established, the settings established according to the pins described in section 2.6 are valid, therefore DFORM_I2C setting described here is ignored. Table 16.1.1 and Figure 16.1.1 to Figure 16.1.4 show the formats that are set by DFORM_I2C. Table 8.1.1 Data format settings (initial setting in bold) DFORM_I2C Data Format 000 I 2S 001 Left justified, MSB first 010 Right justified, LSB first 011 24 bits, right justified, MSB first 100 20 bits, right justified, MSB first 101 18 bits, right justified, MSB first 110 16 bits, right justified, MSB first Figure 16.1.1 [DFORM_I2C = 0000] BCK=64 fs, I2S (24 bits) 23 22 21 20 32fs 32fs Lch Rch 3 2 1 0 23 22 21 3 20 2 1 0 23 22 21 Figure 16.1.2 [DFORM _I2C = 0001] BCK=64 fs, left justified, MSB first (24 bits) 23 22 21 20 3 32fs 32fs Lch Rch 2 1 0 23 22 21 20 3 2 1 0 23 22 21 20 Figure 16.1.3 [DFORM _I2C = 0010] BCK=64 fs, right justified, LSB first (24 bits) 21 22 23 0 32fs 32fs Lch Rch 1 2 3 20 21 22 23 0 1 2 20 21 3 22 23 Figure 8.1.4 [DFORM_I2C = 011/100/101/110] BCK=64 fs, 24/20/18/16 bits, right justified, MSB first 2 1 32fs 32fs Lch Rch 3 0 24/20/18/16 bit 2 1 0 3 2 1 0 24/20/18/16 bit No.A1963-18/25 LV4904V 2 Master clock rate MCKFS_I C and sample rate SRATE_I2C are set in accordance with the master clock and input sample rate. The settings established according to MCKFS_I2C are valid only when the MCKFS pin is set to low in the combined I2C bus and pin setting mode. When MCKFS is high or when the pin setting mode is established, the settings established according to the pins described in section 2.7 are valid, therefore MCKFS_I2C setting described here is ignored. The settings established according to SRATE_I2C are valid only when the SRATE pin is low in the combined I2C bus and pin setting mode. When SRATE is high or when the pin setting mode is established, the settings established according to the pins described in section 2.8 are valid, therefore SRATE_I2C setting described here is ignored. If these settings are illegal and they do not match the input signals, an abnormal sound is generated or the output is set to off. Noise is generated when switching the settings, so mute the output before changing any settings. Table 8.1.2 shows the settings of the master clock that is set by SRATE and MCKFS. Table 8.1.2 Master clock settings (initial values in bold) SRATE_I2C MCKFS_I2C Setting and MCK Rate Sampling Rate [1] [0] [00] [01] [10] [11] 0 0 32 kHz 256 fs 384 fs 512 fs 768 fs 0 1 44.1/48 kHz 256 fs 384 fs 512 fs 768 fs 1 0 88.2/96 kHz 128 fs 192 fs 256 fs 384 fs 1 1 176.4/192 kHz 64 fs 96 fs 128 fs 192 fs 8.2 Gain and mute settings Register Address D7 D6 D5 D4 D3 D2 GAINL 20h PSTPL MUTEBL GAINL [5:0] GAINR 21h PSTPR MUTEBR GAINR [5:0] D1 D0 The left-channel volume and right-channel volume are each set with 6 bits and in 64 steps using the GAINL and GAINR registers, respectively. The volume setting ranges from +12 dB to -81 dB in 1.5 dB increments. The settings established according to GAINL and GAINR are valid only when all the GAIN0 to GAIN5 pins are low in the combined I2C bus and pin setting mode. With any other pin settings or when the pin setting mode is established, the settings established according to the pins described in section 2.9 are valid, therefore GAINL and GAINR setting described here is ignored. Table 8.2.1 shows the volume settings established according to GAINL and GAINR. Table 8.2.1 Gain settings (initial value in bold) No. GAINL Gain (dB) No. 111111 +12.0 41 62 111110 +10.5 61 111101 +9.0 60 111100 59 GAINL GAINL Gain (dB) No. 101001 -21.0 19 010011 -54.0 40 101000 -22.5 18 010010 -55.5 39 100111 -24.0 17 010001 -57.0 +7.5 38 100110 -25.5 16 010000 -58.5 111011 +6.0 37 100101 -27.0 15 001111 -60.0 58 111010 +4.5 36 100100 -28.5 14 001110 -61.5 57 111001 +3.0 35 100011 -30.0 13 001101 -63.0 56 111000 +1.5 34 100010 -31.5 12 001100 -64.5 55 110111 0.0 33 100001 -33.0 11 001011 -66.0 54 110110 -1.5 32 100000 -34.5 10 001010 -67.5 53 110101 -3.0 31 011111 -36.0 9 001001 -69.0 52 110100 -4.5 30 011110 -37.5 8 001000 -70.5 51 110011 -6.0 29 011101 -39.0 7 000111 -72.0 50 110010 -7.5 28 011100 -40.5 6 000110 -73.5 49 110001 -9.0 27 011011 -42.0 5 000101 -75.0 48 110000 -10.5 26 011010 -43.5 4 000100 -76.5 47 101111 -12.0 25 011001 -45.0 3 000011 -78.0 46 101110 -13.5 24 011000 -46.5 2 000010 -79.5 45 101101 -15.0 23 010111 -48.0 1 000001 -81.0 44 101100 -16.5 22 010110 -49.5 0 000000 MUTE 63 GAINR GAINR 43 101011 -18.0 21 010101 -51.0 42 101010 -19.5 20 010100 -52.5 GAINR Gain (dB) No.A1963-19/25 LV4904V Left channel mute is set using MUTEBL and right channel mute is set using MUTEBR. Both MUTEBL and MUTEBR are low active. The settings established according to MUTEBL and MUTEBR are valid only when the MUTEB pin is low in the combined I2C bus and pin setting mode. With any other pin settings or when the pin setting mode is established, the settings established according to the pins described in section 2.10 are valid, therefore MUTEBL and MUTEBR setting described here is ignored. Table 8.2.2 shows the mute settings established according to MUTEBL and MUTEBR. Table 8.2.2 Mute settings (initial value in bold) MUTEBL/MUTEBR Setting 0 Mute 1 Audio output ON The left channel PWM output can be stopped by PSTPL and the right channel PWM output can be stopped by PSTPR. Table 8.2.3 shows the PWM output stop settings established according to PSTPL and PSTPR. Table 8.2.3 PWM output stop settings (initial value in bold) PSTPL/PSTPR Setting 0 Normal output operation mode 1 PWM output stopped 8.3 Other settings Register Address PWM1 41h D7 D6 D5 Reserved D4 D3 D2 D1 D0 NSORD MDIDX IDPEN 1 By setting IDPEN, the PWM output can be fixed to the 50% duty cycle pulse or idled during mute or under no-signal conditions. Table 8.3.1 shows the IDPEN function settings. Table 8.3.1 IDPEN function settings (initial value in bold). IDPEN Setting 0 Idle operation mode 1 50% duty pulse The modulation index of the PWM modulator can be switched by setting MDIDX. Table 8.3.2 shows the MDIDX function settings. Table 8.3.2 MDIDX function settings (initial value in bold). MDIDX Setting 0 87.5% 1 100% The noise shaper order can be switched by setting NSORD. Table 8.3.3 shows the NSORD function settings. Table 8.3.3 NSORD function settings (initial value in bold) NSORD Setting 0 Seventh order 1 Fifth order No.A1963-20/25 LV4904V 8. Characteristics Data: Ta=27°C, Fs=48 kHz, Master Clock=256 fs Ipd -- VDD 0.1 VDD=3.3V RSTB=Low RSTB=Low 0.8 0.08 Standby current, Ipd - μA Standby current, Ipd - μA Ipd -- Ta 0.1 0.06 0.04 0.02 0 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0.6 0.4 0.2 0 -40 4.0 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 4 6 8 10 12 14 18 16 0 -40 20 -20 Imute -- PVD RL=8 RSTB=High ENABLE=Low 5 1 0 8 10 12 14 16 18 Quiescent current, ICC - mA Quiescent current, ICC - mA 10 0 10 12 14 16 Power cell Power Supply, PVD - V 60 80 100 80 100 80 100 VD=15V RL=8 RSTB=High ENABLE=Low 3 2 1 -20 0 20 40 60 ICCO -- Ta 50 20 8 40 Ambient temperature, Ta - C ICCO -- PVD 6 20 4 0 -40 20 RL=8 RSTB=High ENABLE=High MUTEB=Low 4 100 Imute -- Ta Power cell Power Supply, PVD - V 30 0 6 Muting current, Imute - mA Muting current, Imute - mA 2 6 80 Ambient temperature, Ta - C Power cell Power Supply, PVD - V 4 60 PVD=15V RSTB=Low 0.4 2 40 Ist -- Ta 0.5 RSTB=Low 0 20 Ambient temperature, Ta - C Ist -- PVD 0.5 0 -20 Power supply, VDD - V 18 20 40 VD=15V RL=8 RSTB=High ENABLE=High MUTEB=Low 30 20 10 0 -40 -20 0 20 40 60 Ambient temperature, Ta - C No.A1963-21/25 LV4904V Iop -- VDD PVD=15V RSTB=High ENABLE=High MUTE=Low 15 10 5 0 2.6 2.8 3.0 3.2 3.4 ICC -- Ta 20 Quiescent current, ICC - mA Operating current, Iop - mA 20 3.6 3.8 15 10 5 0 -40 4.0 VD=15V RL=8 RSTB=High ENABLE=High MUTEB=Low 0 -20 Power supply, VDD - V VDDA -- PVD 5 5 4 4 3 2 1 0 4 6 8 10 12 14 16 18 0 -40 20 VNO -- PVD 0 -20 4 11 12 13 14 15 16 17 18 19 20 0 -20 Channel separation, CHsep. -- dB Channel separation, CHsep. -- dB RL=8 fIN=1kHz VO=0dBm DIN AUDIO -60 9 10 11 12 13 14 15 16 17 Power cell Power Supply, PVD - V 18 20 40 60 80 100 80 100 CH sep. -- Ta 0 -40 -80 100 Ambient temperature, Ta - C CH sep. -- PVD -20 80 VNO -- Ta Power cell Power Supply, PVD - V 0 60 VD=15V RL=8 VIN=-138dBFS VOL=+12dB IHF-A 0.1 -40 0 10 40 1 2 9 20 10 Noise, VNO -- mVrms Noise, VNO -- mVrms 6 100 Ambient temperature, Ta - C RL=8 RSTB=High ENABLE=High MUTEB=High VOL=+12dB IHF-A 8 80 VD=15V RL=8 RSTB=High ENABLE=High MUTEB=Low Power cell Power Supply, PVD - V 10 60 3 2 RL=8 RSTB=High ENABLE=High MUTEB=Low 1 40 VDDA -- Ta 6 VDDA -V VDDA -V 6 20 Ambient temperature, Ta - C 19 20 -20 VD=15V RL=8 fIN=1kHz VO=0dBm AES17 -40 -60 -80 -40 -20 0 20 40 60 Ambient temperature, Ta - C No.A1963-22/25 LV4904V 20 RL=8 fIN=1kHz 2CH-Drive PCL=0X00 AES17 20 15 15 on lati % 100 10 du mo Power - W Power - W Power -- Ta Power -- PVD 25 on lati 5% 87. du mo 10 5 5 0 9 10 11 12 13 14 15 16 18 17 19 100% modulation 87.5% modulation PVD=15V RL=8 fIN=1kHz THD+N=10% 2CH-Drive AES17 0 -40 20 0 -20 Power supply, VDD - V THD+N -- PVD RL=8 fIN=1kHz PO=1W 2CH-Drive Vol=+12dB AES17 1 CH1 0.1 CH2 0.01 9 10 11 12 13 14 15 16 Total harmonic distortion, THD+N -- % 1 60 80 100 18 17 19 1 80 100 PVD=15V RL=8 PO=1W 2CH-Drive Vol=+12dB AES17 CH2 0.1 CH1 0.01 -40 20 0 -20 20 40 60 Ambient temperature, Ta - C Power cell Power Supply, PVD - V 10 40 THD+N -- Ta 10 Total harmonic distortion, THD+N -- % Total harmonic distortion, THD+N -- % 10 20 Ambient temperature, Ta - C THD+N -- Frequency PVD=15V RL=8 PO=1W 2CH-Drive Vol=+12dB AES17 CH1 0.1 CH2 0.01 10 100 1000 10000 100000 Frequency - Hz THD+N -- Power 1 100Hz 1kHz 0.1 PVD=15V RL=8 2CH-Drive Vol=+12dB AES17 0.01 0.0001 0.001 6.67kHz 0.01 0.1 Power - W THD+N -- Power 10 Total harmonic distortion, THD+N -- % Total harmonic distortion, THD+N -- % 10 1 10 1 0.1 CH2 PVD=15V RL=8 2CH-Drive Vol=+12dB AES17 0.01 0.0001 0.001 CH1 0.01 0.1 1 10 Power - W No.A1963-23/25 LV4904V Power -- Efficiency 100 PVD=15V RL=8 fIN=1kHz 2CH-Drive Vol=+12dB AES17 10 80 1 60 Power - W Efficiency - % Power -- VIN 100 40 PVD=15V RL=8 fIN=1kHz 2CH-Drive AES17 20 0.01 0.001 0 0 2 4 6 8 0.1 10 0.0001 1 PVD=15V RL=8 fIN=1kHz 2CH-Drive AES17 5 4 Pd - W ID - A Pd -- Power 6 PVD=15V RL=8 fIN=1kHz 2CH-Drive AES17 1.5 1000 VIN - mFFS ID -- Power 2 100 10 Power - W 1 3 2 0.5 1 0 0 2 4 6 8 0 10 0 2 4 Power - W 8 6 Response - dB 4 2 PVD=15V RL=8 PO=1W 2CH-Drive Vol=+12dB AES17 Lower 8 -2 -6 4 2 -8 CH1 1000 Frequency - Hz 10000 CH2 100000 Upper 6 -4 100 10 10 0 -10 10 8 Power -- Ta Response -- Frequency Power - W 10 6 Power - W 0 -40 RL=8 RSTB=High ENABLE=High MUTEB=High -20 0 20 40 60 80 100 Ambient temperature, Ta - C No.A1963-24/25 LV4904V SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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