Ordering number : ENA1173B Bi-CMOS LSI LV4912GP Class-D Audio Power Amplifier BTL 2W×1ch Overview The LV4912GP is analog input type digital power amplifier with 2W × 1 channel. By using an original feed back technology, it improves sound quality through it is class-D power amplifier and the LC filter in the output stage can be deleted as application. Features • Enabling output LC filter-less. • Class-D amplifier system of the output BTL type. • Improve the sound quality by the use of original feedback technology. • Realized high efficiency class-D amplifier. • Reduce the pop sound at ON/OFF state by the use of soft mute function. • Full complement of built-in protection circuits : over current protection, thermal protection, and low power supply voltage protection circuits. • Internal oscillation frequency : 280kHz Functions • Output power • THD + N • Noise • Package : 2W(VD = 5V, RL = 4Ω, THD + N = 10%) : 0.4% (VD = 5V, RL = 4Ω, fin = 1kHz, PO = 1W, Filter : AES17) : 70μVrms (Filter : DIN AUDIO) VCT24 (3.5 × 3.5) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 60911 SY/70208 MS / 51408 MS PC 20080331-S00006 No.A1173-1/11 LV4912GP Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage Conditions VD Allowable power dissipation Pd max Ratings Unit Externally applied voltage 6 V Mounted on a board * 1 W Operating temperature Topr -20 to +75 °C Storage temperature Tstg -40 to +150 °C ∗ When mounted on the specified printed circuit board : 40mm×50mm×1.6mm, glass epoxy Recommended Operation Conditions at Ta = 25°C Ratings Parameter Symbol Conditions Unit min Supply voltage range VD Externally applied voltage Load impedance renge RL Speaker load typ 2.7 max 5 5.5 V Ω 4 Electrical Characteristics at Ta = 25°C, VD = 5V, RL = 4Ω, L = 22μH, C = 0.33μF Ratings Parameter Symbol Conditions Unit min typ max Operating current Ist STBY = L, MUTE = L, LC less, RL = OPEN 1 8 μA Mute current Imute STBY = H, MUTE = L, LC less, RL = OPEN 4.5 7.5 mA Quiescent current ICCO STBY = H, MUTE = H, LC less, RL = OPEN 6 10 mA 23.5 25.5 dB 0.4 0.7 Standby current Main amplifier Voltage gain VG Total harmonic distortion fin = 1kHz, VO = 0dBm THD+N Output power PO Ripple rejection ratio SVRR Noise 21.5 PO = 1W, fin = 1kHz, AES17 THD+N = 10%, fin = 1kHz, AES17 1.6 2 fr = 100Hz, Vr = -15dBm, Rg = 0, DIN AUDIO 50 60 VNO Rg = 0, DIN AUDIO High-level output voltage VIH STBY pin, MUTE pin Low-level output voltage VIL STBY pin, MUTE pin % W dB 70 210 μVrms 0.3 V Digital input 3 V Protection circuit Power supply voltage drop protection UV_UPPER VD pin voltage monitor 2.3 V UV_LOWER VD pin voltage monitor 2.2 V circuit upper limit value Power supply voltage drop protection circuit lower limit value Note : The values of these characteristics were measured in the SANYO test environment. The actual values in an end system will vary depending on the printed circuit board pattern, the external components actually used, and other factors. Package Dimensions unit : mm (typ) 3322A Pd max -- Ta TOP VIEW SIDE VIEW BOTTOM VIEW (0.13) (0.125) 3.5 0.4 3.5 (C0.17) 24 2 1 0.5 (0.5) 0.25 (0.035) 0.8 SIDE VIEW Allowable power dissipation, Pd max – W 1.2 1 Specified board 0.8 0.6 0.6 0.4 0.2 Independent IC 0.11 0 – 20 SANYO : VCT24(3.5X3.5) Specified board : 40 × 50 × 1.6mm3 glass epoxy 0 20 40 60 75 80 100 Ambient temperature, Ta – °C No.A1173-2/11 LV4912GP LV4912GP customer bread board rev.1.0 Size : 40mm × 50mm × 1.6mm Pattern Top Layer Bottom Layer No.A1173-3/11 LV4912GP Block Diagram and Application Circuit Example (RL = 4Ω) PWR_VD PRE_VD C3 1μF PRE_GND PWR_GND OUTPUTSTAGE 1μF IN+ C4 IN C5 1μF OUTPUTSTAGE SEQUENCE VBIAS BIASCAP C6 1μF 22μH OUT- C10 1μF VD RL C9 0.33μF L2 Under Voltage Over Current Thermal Protection Protection Protection 0-5V MUTECAP C8 0.33μF CONTROL DELAY RECEIVER STBY MUTE 0-5V 22μH OUT+ L1 C2 + C1 100μF 1μF IREF VCC SUPPLY C7 1μF LV4912GP Application (RL = 4Ω) Part List Parts Name Part No. CVD C1 Description Function CVD C2, C3 High-frequency cut capacitor for VD Input capacitor Power supply capacitor for VD CIN C4, C5 CMUTE C6 Capacitor for soft mute CBIASCAP C7 Input coupling capacitor for Internal power supply (VBIAS) LO L1, L2 CO C8, C9, C10 Output L. P. F. coil Output L. P. F. capacitor OUT- PWR_GND 22 21 NC 23 NC 24 OUT+ NC Pin Assignments 20 19 17 PWR_VD PRE_GND 3 16 TEST2 VIN+ 4 15 TEST1 VIN- 5 14 STBY NC 6 13 MUTE 7 8 9 10 11 12 MUTECAP 2 NC PRE_VD BIASCAP NC NC 18 NC 1 NC NC Top view No.A1173-4/11 LV4912GP Pin Equivalent Circuit Pin No. Pin Name I/O Description 1 NC No connection 2 PRE_VD Power supply pin 3 PRE_GND 4 VIN+ Equivalent Circuit Pre ground I Input plus VD 4 300Ω 30kΩ VBIAS GND 5 VIN- I Input minus VD 5 300Ω 30kΩ VBIAS GND 6 NC No connection 7 NC No connection 8 NC No connection 9 NC No connection 10 BIASCAP O Internal power supply decoupling capacitor VD connection 10 200kΩ 100kΩ 90kΩ GND 11 NC 12 MUTECAP No connection O Mute capacitor connection VCC VD 12 200kΩ GND 13 MUTE I Mute control pin VCC VD 100kΩ 13 200kΩ GND Continued on next page. No.A1173-5/11 LV4912GP Continued from preceding page. Pin No. 14 Pin Name STBY I/O I Description Equivalent Circuit Standby control pin VD 100kΩ 14 200kΩ GND 15 TEST1 Test pin 16 TEST2 Test pin 17 PWR_VD Power supply pin 18 NC No connection 19 NC No connection 20 NC 21 OUT- No connection O Output pin, minus VD 21 GND 22 PWR_GND 23 OUT+ Power ground O Output pin, plus VD 23 GND 24 NC No connection No.A1173-6/11 LV4912GP Description functions 1. System Standby Each bias can be turned on/off by switching the STBY pin (pin 14) into high or low. The bias is turned off when the STBY pin is low. Conversely, the bias is turned on when the STBY pin is high. STBY pin (pin 14) Bias condition High ON Low OFF 2. Mute Function The mute of the output and reduction of power-on popping noise are mainly performed by the use of this function. By switching between high and low on the MUTE pin (pin 13), the output can be muted. The MUTE pin enters the mute mode (PWM output stops) when the MUTE pin is low. Also the MUTE pin enters the operation mode (normal operations) when the MUTE pin is high. MUTE pin (pin 13) Conditions High Operation mode Low Mute mode We recommend the following sequence for reduction of the popping noise when power is on/off. Also, we recommend the following ON Time and OFF Time when P.4 the application circuit is used. (1) Power On sequence The ON Time should secure more than 150msec for reduction of the popping noise. STBY Internal power supply MUTE MUTECAP Output pin ON Time No.A1173-7/11 LV4912GP (2) Power Down sequence The OFF Time should secure more than 100msec for reduction of the popping noise. STBY Internal power supply MUTE MUTECAP Output pin OFF Time Capacitors for Power supply and pin arrangement 1. Capacitors for power supply The capacitors C2 and C3 for power supply connected between IC pins must be inserted using the shortest lines possible. 17 PWR_VD C2 1μF 22 PWR_GND 2 PRE_VD C3 1μF 3 PRE_GND 2. Pin arrangement of the test pins (pins 15 and 16) The test pins (pins 15 and 16) are used as pins for testing before shipment. These pins are not used normally. Therefore, these pins must be left open if the pin arrangement is not performed. Please make sure to connect these pins to GNDs if the pin arrangement is performed. No.A1173-8/11 LV4912GP General Characteristics Ist – VD 0.18 0.16 Imute – VD RL = 4Ω STBT = L, MUTE = L 6 0.14 Mute current, Imute – mA Standby current, Ist – μA 7 RL = 4Ω STBT = L, MUTE = L 0.12 0.1 0.08 0.06 0.04 5 4 3 2 1 0.02 0 2.5 3 3.5 4 4.5 5 5.5 0 2.5 6 3 3.5 Supply voltage, VD – V ICCO – VD 16 Output power, PO – W Quiescent current, ICCO – mA 12 10 8 6 4 3 3.5 4 4.5 5 5.5 1 7 5 3 2 6 PCA02904 RL = 8Ω 2 3 5 7 2 100 3 5 7 1000 Input voltage, VIN – mVp PO – VD PO – VD 2.5 VD = 5V RL = 4Ω AES17 3 6 5.5 RL = 4Ω 0.1 7 5 3 2 Supply voltage, VD – V 3.5 5 VD = 5V AES17 0.01 7 5 3 2 0.001 10 2 0 2.5 4.5 PO – VIN 10 7 5 3 2 RL = 4Ω STBT = H, MUTE = H 14 4 Supply voltage, VD – V VD = 5V RL = 8Ω AES17 Output power, PO – W Output power, PO – W 2 2.5 2 THD = 10% 1.5 THD = 1% 1 1.5 THD = 10% 1 THD = 1% 0.5 0.5 0 0 2 3 4 5 6 7 2 3 10 7 5 3 2 THD+N – PO VD = 5V RL = 4Ω AES17 1 7 5 f = 6.67kHz 3 2 f = 1kHz 0.1 7 5 f = 100Hz 3 2 0.01 0.001 2 3 5 70.01 2 3 5 7 0.1 2 3 5 7 1 Output power, PO – W 4 5 7 6 Supply voltage, VD – V Total harmonic distortion, THD+N – % Total harmonic distortion, THD+N – % Supply voltage, VD – V 2 3 5 7 10 10 7 5 3 2 THD+N – PO VD = 5V RL = 8Ω AES17 0.1 7 5 f = 6.67kHz 3 2 f = 1kHz 0.1 7 5 f = 100Hz 3 2 0.01 0.001 2 3 5 70.01 2 3 5 7 0.1 2 3 5 7 1 2 3 5 7 10 Output power, PO – W No.A1173-9/11 THD+N – f 10 7 5 3 2 10 VD = 5V RL = 4Ω PO = 1W AES17 5 1 7 5 3 2 Response – dB Total harmonic distortion, THD+N – % LV4912GP 0.1 7 5 3 2 0.01 7 5 3 2 0.001 10 Response – f VD = 5V RL = 4Ω PO = 1W AES17 0 –5 – 10 – 15 – 20 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k 2 3 5 7 100k 10 2 3 5 7 100 Frequency, f – Hz 10 Ripple rejection ratio, SVRR – dB 20 Phase – deg 0 – 10 – 20 – 30 – 40 – 50 – 60 2 3 5 7 100 2 3 5 7 1k 2 3 5 7 10k 2 3 Efficiency – PO 2 3 5 71000 30 20 VD = 5V RL = 4Ω Vr = -15dBm DIN AUDIO 10 2 3 5 7 1 2 3 5 7 10 2 3 5 7 100 Bias capacitance, Bias Cap – μF Pd – PO VD = 5V AES17 1 Power dissipation, Pd – W Efficiency – % 5 7 100k 40 1.2 RL = 8Ω RL = 4Ω 60 2 3 50 0 0.1 5 7100k VD = 5V AES17 80 5 7 10k 60 Frequency, f – Hz 100 2 3 SVRR – BIASCAP 70 VD = 5V RL = 4Ω PO = 1W AES17 10 5 7 1k Frequency, f – Hz Phase – f 30 2 3 40 20 0.8 RL = 4Ω 0.6 0.4 RL = 8Ω 0.2 0 0 0 0.5 Temperature Characteristics 1 1.5 2 0.5 0 Output power, PO – W Imute – Ta 6 1 1.5 2 Output power, PO – W ICCO – Ta 20 18 Quiescent current, ICCO – mA Mute current, Imute – mA 5 4 3 2 1 VD = 5V RL = 4Ω Rg = 0 STBY = H MUTE = L 0 – 50 – 25 16 14 12 10 8 6 4 2 0 25 50 Allowable temperature, Ta – °C 75 100 VD = 5V RL = 4Ω Rg = 0 STBY = H MUTE = H 0 – 50 – 25 0 25 50 75 100 Allowable temperature, Ta – °C No.A1173-10/11 LV4912GP 0.7 0.6 THD+N – Ta PO – Ta 3.0 VD = 5V RL = 4Ω PO = 1W fin = 1kHz AES17 RL = 4Ω fin = 1kHz THD+N = 10% AES17 2.5 Output power, PO – W Total harmonic distortion, THD+N – % 0.8 0.5 0.4 0.3 0.2 VD = 5V 2.0 1.5 VD = 3.6V 1.0 VD = 3V 0.5 0.1 0 – 50 – 25 0 25 50 75 0 – 50 100 – 25 Allowable temperature, Ta – °C VG – Ta 25 0 25 50 75 100 Allowable temperature, Ta – °C Vno – Ta 90 80 70 Noise, Vno – μVrms Voltage gain, VG – dB 24 23 22 21 – 25 50 40 30 20 VD = 5V RL = 4Ω VIN = 0dBm DIN AUDIO 20 – 50 60 10 0 25 50 Allowable temperature, Ta – °C 75 100 VD = 5V RL = 4Ω Rg = 0 0 – 50 – 25 0 25 50 75 100 Allowable temperature, Ta – °C SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2011. Specifications and information herein are subject to change without notice. PS No.A1173-11/11