FAIRCHILD FT3001

FT3001
Reset Timer with Configurable Delay
Features
Description








Delay Times: 3.0, 3.75, 4.5, 6.0 Seconds
The FT3001 is a timer for resetting a mobile device
where long reset times are needed. The long delay
helps avoid unintended resets caused by accidental key
presses. Four timer values can be selected by hardwiring the DSR0 and DSR1 pins.

ESD Protection Exceeds:
≤ 1 µA ICC Current Consumption in Standby
Primary and Secondary Input Reset Pins
Push-Pull and Open-Drain Output Pins
1.65 V to 5.0 V Operation at TA = 0C to +85C
1.7 V to 5.0 V Operation at TA = 0C to +85C
1.8 V to 5.0 V Operation at TA = -40C to +85C
Available in 8-Lead MLP and 10-Lead UMLP
Packages
The FT3001 has two inputs for single- or dual-button
resetting capability. The device has two outputs: a pushpull output with 0.5 mA drive and an open-drain output
with 0.5 mA pull-down drive.
The FT3001 draws minimal supply current when
inactive and functions over a power supply range of
1.65 V to 5.0 V.
- 4 kV HBM
(per JESD22-A114 & Mil Std 883e 3015.7)
- 2 kV CDM (per ESD STM 5.3)
Figure 1. Block Diagram
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing Method
FT3001UMX
-40C to +85C
10-Lead, Ultrathin MLP, 1.4 x 1.8 x 0.55mm
Package, 0.40 mm Pitch
5000 Units
Tape and Reel
FT3001MPX
-40C to +85C
8-Lead, Molded Leadless Package (MLP),
Dual JEDEC, MO-229 2.0 x 2.0 mm
3000 Units
Tape and Reel
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
FT3001 — Reset Timer with Configurable Delay
October 2012
RST2
10
DSR1
VCC
9
8
GND
1
7
/SR0
/SR1
2
6
TRIG
3
/RST1
4
5
NC
DSR0
Figure 2. UMLP (Top Through View)
Figure 3. MLP (Top Through View)
FT3001 — Reset Timer with Configurable Delay
Pin Configurations
Pin Definitions
UMLP
Pin#
MLP
Pin#
Name
1
2
GND
Ground
2
3
/SR1
Secondary Reset Input, Active LOW
3
4
/RST1
4
NC
Description
Open-Drain Output, Active LOW
No Connect
DSR0
Delay Selection Input (Must be tied directly to GND or VCC; do not use pull-up or
pull-down resistors.)
6
TRIG
Test Pin; tied to ground in normal use
7
7
/SR0
Primary Reset Input, Active LOW
8
8
VCC
Power Supply
5
6
5
9
10
1
DSR1
Delay Selection Input (Must be tied directly to GND or VCC; do not use pull-up or
pull-down resistors.)
RST2
Push-Pull Output, Active HIGH
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Supply Voltage
VIN
DC Input Voltage
VOUT
Output Voltage(1)
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IOH/IOL
ICC
TSTG
Condition
Min.
Max.
Unit
-0.5
7.0
V
-0.5
7.0
V
/RST1, RST2 HIGH or LOW
-0.5
VCC+0.5
/RST1, RST2, VCC=0 V
-0.5
7.0
/SR0, /SR1, TRIG, DSR0
VIN < 0 V
-50
mA
VOUT < 0 V
-50
VOUT > VCC
+50
DC Output Source/Sink Current
-50
DC VCC or Ground Current per Supply Pin
Storage Temperature Range
-65
V
mA
+50
mA
100
mA
+150
C
C
VCC
Junction Temperature Under Bias
+150
VIN
Junction Lead Temperature, Soldering 10 Seconds
+260
C
PD
Power Dissipation
5
mW
ESD
Electrostatic Discharge Capability
Human Body Model, JESD22-A114
4
Charged Device Model, JESD22-C101
2
FT3001 — Reset Timer with Configurable Delay
Absolute Maximum Ratings
kV
Note:
1. IO absolute maximum rating must be observed.
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
3
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
tVCC_REC
VIN
VOUT
Parameter
Supply Voltage
Vcc Recovery Time After Power
Down
(2)
Input Voltage
Output Voltage
IOH
DC Output Source Current
IOL
DC Output Sink Current
TA
Free Air Operating Temperature
JA
Thermal Resistance
Conditions
Min.
Max.
TA = 0C to +85C
1.65
5.00
TA = -25C to +85C
1.7
5.0
TA = -40C to +85C
1.8
5.0
Vcc = 0 V after power down, then rising to
0.5 V
5
/SR0, /SR1
0
5.0
/RST1, RST2 High or Low
0
VCC
/RST1, RST2, VCC = 0 V
0
5.0
Unit
V
ms
RST2, 1.8 V ≤ VCC ≤ 3.0 V
-100
RST2, 3.0 V ≤ VCC ≤ 5.0 V
-500
/RST1, RST2, VCC = 1.8V to 5.0 V
+500
V
V
µA
-40
+85
MLP-8
245
UMLP-10
200
FT3001 — Reset Timer with Configurable Delay
Recommended Operating Conditions
C
°C/W
Notes:
2. All unused inputs must be held at VCC or GND.
DC Electrical Characteristics
Unless otherwise specified, conditions of TA=-40 to 80C with VCC=1.8 - 5.0V OR TA=-25 to 85C with VCC=1.7 – 5V OR
TA=0 to 85C with VCC=1.65 – 5V produce the performance characteristics below.
Symbol
Parameter
(3)
Condition
VIH
Input High Voltage
/SR0, /SR1
VIL
Input Low Voltage
/SR0, /SR1
VIH
Input High Voltage
DSR0, DSR1
VIL
Input Low Voltage
DSR0, DSR1
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
Min.
Max.
0.8 x VCC
V
0.2 x VCC
0.8 x VCC
0.8 x VCC
RST2, IOH=-500 µA, VCC=3.0
to 5.0V
0.8 x VCC
V
V
0.2 x VCC
RST2, IOH=-100 µA
Unit
V
V
RST2, IOL=500 µA
0.3
/RST1, IOL=500 µA
0.3
V
IIN
Input Leakage Current
VIN =0.0 V or 5.0 V
1
µA
ICC
Quiescent Supply Current (Timer
Inactive)
/SR0 or /SR1=VCC
1
µA
ICC
Dynamic Supply Current (Timer Active)
/SR0 and /SR1=0 V
100
µA
Note:
3. /SR0 and /SR1 HIGH levels should be referenced to the same VCC rail supplying the FT3001.
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
4
Unless otherwise specified, conditions of TA=-40 to 80°C with VCC=1.8 - 5.0 V OR TA=-25 to 85°C with VCC=1.7 – 5 V OR
TA=0 to 85°C with VCC=1.65 – 5 V produce the performance characteristics below.
Symbol
tPHL1,
tPLH1
tREC
Parameter
Condition
Min.
Typ.
Max.
Timer Delay, /SRn to /RST1
(DSR0=0, DSR1=0)
CL=5 pF, RL=5 k,
Figure 9, Figure 4, Figure 5
2.40
3.00
3.60
Timer Delay, /SRn to /RST1
(DSR0=0, DSR1=1)
CL=5 pF, RL=5 k, Figure 9, Figure
4, Figure 5
3.00
3.75
4.50
Timer Delay, /SRn to RST2
(DSR0=1, DSR1=0)
CL=5 pF, RL=10 k, Figure 6, Figure
7
3.60
4.50
5.40
Timer Delay, /SRn to RST2
(DSR0=1, DSR1=1),
CL=5 pF, RL=10 k, Figure 6, Figure
7
4.80
6.00
7.20
Reset Timeout Delay, /RST1 and
RST2
Figure 4, Figure 5, Figure 6, Figure 7
Unit
s
400
ms
Capacitance Specifications
FT3001 — Reset Timer with Configurable Delay
AC Electrical Characteristics
TA = +25C.
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCC=GND
4.0
pF
COUT
Output capacitance
VCC=5.0 V
5.0
pF
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
5
Figure 4. AC Test Circuit, RST1 Output
Figure 5. RST1 Output Waveform
Figure 6. AC Test Circuit, RST2 Output
Figure 7. RST2 Output Waveform
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
FT3001 — Reset Timer with Configurable Delay
AC Test Circuits and Waveforms
www.fairchildsemi.com
6
Application Information
The reset timer uses an internal oscillator and a twostage 21-bit counter to determine when the output pins
switch. The time, n, is set by the hard-wired logic level
of the DSR0 and DSR1 pins. See Table 1 & 2.
IMPORTANT: The DSR0 and DSR1 pins must be tied
directly to VCC or GND to provide a HIGH or LOW
voltage level. The voltage level on the DSR pin
determines the length of the configurable delay. The
voltage level on the DSR pins must not change during
normal operation. Do not use pull-up or pull-down
resistors on DSR pins.
Table 1.
FT3001UMX Truth Table
DSR0
DSR1
Reset Time (20%)
in Seconds
0
0
3.00
0
1
3.75
1
0
4.50
1
1
6.00
Table 2.
Short Duration (Button Press Time < n)
In this case, both input /SR0 and /SR1 are LOW for a
duration (tW ) that is shorter than time n. When an input
goes LOW, the internal timer starts counting. If the input
goes HIGH before time n, the timer stops counting and
resets and no changes occur on the outputs.
FT3001MPX Truth Table
DSR0
Reset Time (20%)
in Seconds
0
3.0
1
4.5
Long Duration (tW > n)
In this case, both input /SR0 and /SR1 are LOW for a
duration (tW ) that is longer than time n. When an input
goes LOW, the internal timer starts counting.
After time n, the outputs switch and the timer stops
counting. After time tREC, the outputs return to their
original states.
The two CMOS input pins, /SR0 and /SR1, control the
reset function. A low input signal on both /SR0 and /SR1
starts the oscillator. Both /SR0 and /SR1 pins must be
held LOW for time n before the /RST1 and RST2
outputs are activated. The TRIG pin should be tied LOW
during normal operation. The TRIG pin is used for
SCAN testing.
Table 3.
/SR0
Short Duration
/SR1
/RST1
RST2
L
H
L
Description
The timer starts counting when both inputs go LOW. The timer stops
counting and resets when either input goes high. No changes occur on the
outputs. Both /SR0 and /SR1 need to be LOW to activate (start) the timer.
Figure 8. Short Duration
Table 4.
/SR0
FT3001 — Reset Timer with Configurable Delay
Functional Description
Figure 9. Long Duration
Long Duration
/SR1
/RST1
L
L
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
RST2
Description
The timer starts counting when both inputs go LOW. After time n, the
outputs switch. After time tREC, the outputs return to their original states.
Both /SR0 and /SR1 need to be LOW to activate (start) the timer.
www.fairchildsemi.com
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FT3001 — Reset Timer with Configurable Delay
Physical Dimensions
1.40
0.15 C
A
1.70
B
2X
(9X)
0.563
0.663
1
2.10
1.80
PIN#1 IDENT
0.40
0.15 C
TOP VIEW
0.10 C
0.55 MAX.
(10X) 0.225
2X
RECOMMENDED
LAND PATTERN
0.152
1.45
0.08 C
0.55
SEATING C
PLANE
0.05
SIDE VIEW
9X
0.45
0.40
1.85
0.35
(9X)
0.45
3
(10X) 0.225
6
DETAIL A
OPTIONAL MINIMIAL
TOE LAND PATTERN
0.40
1
NOTES:
PIN#1 IDENT
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP10Arev3.
0.15
(10X)
0.25
10
BOTTOM VIEW
0.55
0.45
0.10 C A B
0.05 C
0.10
0.10
0.10
DETAIL A
SCALE : 2X
PACKAGE
EDGE
LEAD
OPTION 2
SCALE : 2X
LEAD
OPTION 1
SCALE : 2X
Figure 10.
10-Lead, Ultrathin MLP, 1.4 x 1.8 x 0.55 mm Package, 0.40 mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
8
TOP LAYER
CU KEEP
OUT AREA
0.10 C
2.00
2X
A
0.90
1.80
B
E
(0.90) 8X
PIN1
IDENT
(0.25) 8X
0.50
2.00
OPTION #1: NO CENTER PAD
0.10 C
2X
(1.35)
TOP VIEW
0.10 C
(0.35)
0.90
0.80 MAX
1.80
(0.20)
(0.90) 8X
0.08 C
0.05
0.00
SEATING
PLANE
C
0.50
SIDE VIEW
1
FT3001 — Reset Timer with Configurable Delay
Physical Dimensions (Continued)
(0.25) 8X
OPTION #2: WITH CENTER PAD
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
A
0.25
0.15 8X
0.65 8X
4
0.45
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO-229,
VARIATION W2020D EXCEPT WHERE NOTED.
0.40 MAX
PIN 1
IDENT
B. DIMENSIONS ARE IN MILLIMETERS.
0.50
8
0.10
0.05
5
C A B
C
1.35 MAX
C. DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION BASED
ON PCB MATRIX CALCULATOR V2009.
E. IF CENTER PAD IS NOT SOLDERED TO, NO
EXPOSED METAL IS ALLOWED IN THE TOP
LAYER OF THE BOARD IN THE AREA SHOWN.
BOTTOM VIEW
F. DRAWING FILENAME: MKT-MLP08Rrev2.
Figure 11.
8-Lead, Molded Leadless Package (MLP), Dual JEDEC, MO-229 2.0 x 2.0 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
9
FT3001 — Reset Timer with Configurable Delay
© 2011 Fairchild Semiconductor Corporation
FT3001 • Rev. 1.0.4
www.fairchildsemi.com
10