SEMTECH SX8805RXXX

XE8805/05A Sensing Machine
Data Acquisition MCU
with Zooming ADC and DACs
XE8805/05A – SX8805R
Sensing
Machine – Data Acquisition with 16+10 bit
ZoomingADC™ and buffered DACs
General Description
Key product Features
The XE8805A is a data acquisition ultra lowpower low-voltage system on a chip (SoC) with a
high efficiency microcontroller unit embedded
(MCU), allowing for 1 MIPS at 300uA and 2.4 V,
and multiplying in one clock cycle.
•
The XE8805A includes a high resolution
acquisition path with the 16+10 bits ZoomingADC
and two buffered DACs.
The XE8805A is available with on chip ROM (the
SX8805) or Multiple-Time-Programmable (MTP)
program memory.
Applications
•
•
•
•
•
•
•
Portable, battery operated instruments
Current loop powered instruments
Wheatstone bridge interfaces
Pressure and chemical sensors
HVAC control
Metering
Sports watches, wrist instruments
Rev 1 January 2006
•
•
•
•
•
•
•
Low-power, high resolution ZoomingADC
•
•
•
0.5 to 1000 gain with offset cancellation
up to 16 bits analog to digital converter
up to 13 inputs multiplexer
Low-voltage low-power controller operation
•
•
2 MIPS with 2.4 V to 5.5 V operation
300 µA at 1 MIPS over voltage range
22 kByte (8 kInstruction) MTP
520 Byte RAM data memory
RC and crystal oscillators
5 reset, 22 interrupt, 8 event sources
8 bit and 16 bit buffered DACs
100 years MTP Flash retention at 55°C
Ordering Information
Product
Temperature range
Memory type
Package
XE8805MI028*
-40°C to 85 °C
MTP
XE8805AMI000
-40°C to 85 °C
MTP
LQFP64
die
XE8805AMI028LF
-40°C to 85 °C
MTP
LQFP64
SX8805Rxxx
-40°C to 85 °C**
ROM
*Not for new designs
**Extended temperature range on request
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XE8805/05A Sensing Machine
Data Acquisition MCU
with Zooming ADC and DACs
TABLE OF CONTENTS
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
© Semtech 2006
XE8805/05A Overview
XE8805/05A Performance
XE8805/05A CPU
XE8805/05A Memory
System Block
Reset generator
Clock generation
Interrupt handler
Event handler
Low power RAM
Port A
Port B
Port C
Universal Asynchronous Receiver/Transmitter (UART)
Universal Synchronous Receiver/Transmitter (USRT)
Acquisition Chain (ZoomingADC™)
Voltage multiplier
Signal D/A (DAS)
Bias D/A (DAB)
Counters/Timers/PWM
The Voltage Level Detector
XE8805/05A Dimensions
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XE8805/05A
1. General Overview
CONTENTS
1.1
1.1.1
1.1.2
Top schematic
General description
XE8805 vs XE8805A
1-2
1-2
1-4
1.2
1.2.1
1.2.2
Pin map
Bare die
LQFP-64
1-4
1-4
1-5
1.3
Pin assignment
1-6
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1-1
XE8805/05A
1.1 Top schematic
1.1.1 General description
The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the
Coolrisc816® CPU core. This core includes an 8x8 multiplier and 16 internal registers.
The bus controller generates all control signals for access to all data registers other than the CPU internal
registers.
The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained
in its control registers. Possible reset sources are the power-on-reset (POR), the external pin RESET, the
watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low
power modes are implemented.
The clock generation and power management block sets up the clock signals and generates internal supplies for
different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal
oscillator (XTAL) or an external clock source (given on the OSCIN pin).
The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8
low power data registers. If power consumption is important for the application, the variables that need to be
accessed very often should be stored in these registers rather than in the RAM.
The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows
masking of the interrupt sources and it flags which interrupt source is active.
Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e.
the program execution resumes with the instruction following the HALT instruction. The EVN handler routes the
event signals of the different peripherals to the EVN inputs of the CPU core. It allows masking of the interrupt
sources and it flags which interrupt source is active.
The Port B is an 8 bit parallel IO port with analog capabilities. The URST, UART, and PWM block also make use of
this port.
The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. Flash and ROM
versions have both 8k instruction memory. The data memory of this product is 512 byte SRAM.
The Acquisition Chain is a high resolution acquisition path with the 16+10 bit fully differential ZoomingADC™. The
VMULT (voltage multiplier) powers a part of the Acquisition Chain.
The signal D/A (DAS) is a 16 bit D/A based on sigma-delta modulation. It includes a stand-alone amplifier that can
be used for analog output filtering.
The bias D/A (DAB) is an 8 bit low frequency D/A. It includes a stand-alone amplifier that is used to drive large
currents. It can be used to bias a sensor.
The Port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input
external clocks for the timer/counter/PWM block.
The Port C is a general purpose 8 bit parallel I/O port.
The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to
simplify the software implementation of a synchronous serial link.
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1-2
XE8805/05A
DATA
MEMORY
INSTRUCTION MEMORY
VPP/TEST
CPU
COOLRISC816
VBAT
VSS
8 X 8 MULTIPLIER
B
U
S
C
O
N
T
R
O
L
L
E
R
address
control
PORT A
PA(7:0)
datain
dataout
PORT C
PC(7:0)
16 CPU REGISTERS
RESET
RESET BLOCK
WD
reset
control
ACQUISITION
CHAIN
ZoomingADC
CLOCK
GENERATION/
POWER
MANAGEMENT
RC
OSCIN
OSCOUT
VREG
AC_R(3:0)
POR
XTAL
VREG
TM
AC_A(7:0)
clocks
test
control
VMULT
VMULT
TEST CONTROLLER
DAS_OUT
DAS_AI_P
DAS_AI_M
DAS_AO
DAS
Signal D/A
8 DATA REGISTERS
irq
IRQ HANDLING
DAB_R_P
DAB_R_M
DAB_OUT
DAB_AI_P
DAB_AI_M
DAB_AO_P
DAB_AO_M
DAB
Bias D/A
EVN HANDLING
evn
COUNTERS
TIMERS
PWM
VLD
PB(7:6)
UART
PB(1:0) PA(3:0)
USRT
PB(7:0)
PB(5:4)
PORT B
Figure 1-1. Block schematic of the XE8805/05A circuit.
The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the
asynchronous serial link.
The counters/timers/PWM can take their clocks from internal or external sources (on Port A) and can generate
interrupts or events. The PWM is output on Port B.
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1-3
XE8805/05A
The VLD (voltage level detector) detects the battery end of life with respect to a programmable threshold.
1.1.2 XE8805 vs XE8805A
The XE8805A has a new RESET pin function. The action of the RESET pin of the XE8805A resets the clock
registers too and creates an additional short delay. See the RESET chapter for more information.
1.2 Pin map
( 428.5, 4453.4)
( 593.5, 4453.4)
( 758.5, 4453.4)
( 923.5, 4453.4)
(1088.5, 4453.4)
(1252.9, 4453.4)
(1418.5, 4453.4)
(1588.5, 4453.4)
(1753.5, 4453.4)
(1923.5, 4453.4)
(3114.6, 4453.4)
(3293.5, 4453.4)
(3458.5, 4453.4)
(3628.5, 4453.4)
VSS
OSCIN
VSS
OSCOUT
RESET
VMULT
VREG
VSS_REG
VSS
VBAT
DAS_AO
DAS_AI_M
DAS_AI_P
DAS_OUT
1.2.1 Bare die
(52.6,4123.5)
PA(0)
AC_R(0)
(3958.4, 4118.5)
(52.6, 3908.5)
PA(1)
AC_R(1)
(3958.4, 3858.5)
(52.6,3693.5)
PA(2)
VSS
(3958.4, 3603.5)
AC_A(0)
(3958.4, 3343.5)
PA(3)
VBAT
(52.6, 3048.5)
PA(4)
AC_A(1)
(3958.4, 3088.5)
(52.6, 2833.5)
PA(5)
AC_A(2)
(3958.4, 2828.5)
(52.6, 2618.5)
PA(6)
AC_A(3)
(3958.4, 2573.5)
(52.6, 2403.5)
PA(7)
(52.6, 2188.5)
PC(0)
(52.6, 1973.5)
PC(1)
(52.6, 1758.5)
PC(2)
AC_A(5)
(3958.4,1798.5)
(52.6, 1543.5)
PC(3)
AC_A(6)
(3958.4, 1543.5)
AC_A(7)
(3958.4, 1283.5)
AC_R(2)
(3958.4, 1028.5)
AC_R(3)
(3958.4, 768.5)
VPP/TEST
(3958.4, 508.5)
(52.6, 898.5)
PC(5)
(52.6, 683.5)
PC(6)
PC(7)
(3958.4, 2313.5)
VBAT
(3958.4, 2058.5)
4100
( 398.5, 47.6)
( 533.5, 47.6)
( 668.5, 47.6)
( 798.5, 47.6)
( 933.5, 47.6)
(1063.5, 47.6)
(1198.5, 47.6)
(1328.5, 47.6)
(1463.5, 47.6)
(1593.5, 47.6)
(1728.5, 47.6)
(1858.5, 47.6)
(2042.4, 47.6)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
VBAT
PB(5)
PB(6)
PB(7)
DAB_R_P
DAB_R_M
DAB_OUT
DAB_AO_P
(52.6, 468.5)
AC_A(4)
(3363.5,47.6)
VSS
(3498.5, 47.6) DAB_AI_P
(3628.4, 47.6) DAB_AI_M
VSS
PC(4)
(2683.3, 47.6) DAB_AO_M
(52.6, 1328.5)
(52.6, 1113.5)
4600
(52.6, 3478.5)
(52.6, 3263.5)
Figure 1-2. Die dimensions and pin coordinates (in µm)
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1-4
XE8805/05A
1.2.2 LQFP-64
PC(7)
15
NC
AC_R(3)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
DAB_R_P
DAB_R_M
PB(7)
20
VPP/TEST
25
DAB_OUT
DAB_AO_P
DAB_AO_M
DAB_AI_P
DAB_AI_M
30
NC
The XE8805/05A is delivered in a LQFP-64 package. The pin map is given below.
PC(6)
PC(5)
35
AC_R(2)
PC(4)
AC_A(7)
PC(3)
PC(2)
AC_A(6)
AC_A(5)
AC_A(4)
10
PC(1)
PC(0)
40
AC_A(3)
PA(7)
AC_A(2)
PA(6)
PA(5)
AC_A(1)
5
AC_A(0)
AC_R(1)
PA(4)
PA(3)
45
PA(2)
AC_A(0)
PA(1)
1
PA(0)
NC
OSCIN
OSCOUT
RESET
60
VMULT
NC
VREG
VSS_REG
VSS
VBAT
DAS_AO
DAS_AI_M
DAS_AI_P
DAS_OUT
NC
NC
50
NC
55
NC
Figure 1-3. LQFP-64 pin map
Package pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
name
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PC(0)
PC(1)
PC(2)
PC(3)
PC(4)
PC(5)
PC(6)
PC(7)
PB(0)
PB(1)
PB(2)
PB(3)
Package pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
name
VPP/TEST
NC
AC_R(3)
AC_R(2)
AC_A(7)
AC_A(6)
AC_A(5)
AC_A(4)
AC_A(3)
AC_A(2)
AC_A(1)
AC_A(0)
AC_R(1)
AC_R(0)
NC
NC
NC
NC
DAS_OUT
DAS_AI_P
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1-5
XE8805/05A
Package pin
21
22
23
24
25
26
27
28
29
30
31
32
name
PB(4)
PB(5)
PB(6)
PB(7)
DAB_R_P
DAB_R_M
DAB_OUT
DAB_AO_P
DAB_AO_M
DAB_AI_P
DAB_AI_M
NC
Package pin
53
54
55
56
57
58
59
60
61
62
63
64
name
DAS_AI_M
DAS_AO
VBAT
VSS
VSS_REG
VREG
NC
VMULT
RESET
OSCOUT
OSCIN
NC
Table 1-1. Bonding plan of the LQFP-64 package (LQFP 64L 10x10mm thick 1.6 mm)
1.3 Pin assignment
The table below gives a short description of the different pin assignments.
Pin
Assignment
VBAT
VSS VSS_REG
VREG
VPP/TEST
RESET
OSCIN/OSCOUT
PA(7:0)
PB(7:0)
PC(7:0)
AC_A(7:0)
AC_R(3:0)
VMULT
DAB_OUT
DAB_R_x
DAB_Ax_y
DAS_OUT
DAS_AI_x
DAS_AO
Positive power supply
Negative power supply
Connection for the mandatory external capacitor of the voltage regulator
High voltage supply for flash memory programming (NC in ROM versions)
Resets the circuit when the voltage is high
Quartz crystal connections, also used for flash memory programming
Parallel input port A pins
Parallel I/O port B pins
Parallel I/O port C pins
Acquisition chain input pins
Acquisition chain reference pins
Connection for the external capacitor if VBAT is below 3V
Bias D/A output
Bias D/A reference (x=P: plus, x=M: minus)
Bias D/A amplifier IO (x=I: input, x=O: output ; y=P: plus, y=M: minus)
Signal D/A output
Signal D/A amplifier inputs (x=P: plus, x=M: minus)
Signal D/A amplifier output
Table 1-2. Pin assignment
Table 1-3 gives a more detailed pin map for the different pins. It also indicates the possible I/O configuration of
these pins. The indications in blue bold are the configuration at start-up.
The pins CNTx pins are possible counter inputs, PWMx are possible PWM outputs.
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1-6
XE8805/05A
PWM0
PWM1
USRT_S0
USRT_S1
UART_Tx
UART_Rx
X
X
X
X
X
X
X
X
X
X
POWER
PU
OD
DI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CNTA
CNTB
CNTC
CNTD
DO
AO
AI
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PC(0)
PC(1)
PC(2)
PC(3)
PC(4)
PC(5)
PC(6)
PC(7)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
DAB_R_P
DAB_R_M
DAB_OUT
DAB_AO_P
DAB_AO_M
DAB_AI_P
DAB_AI_M
VPP
AC_R(3)
AC_R(2)
AC_A(7)
AC_A(6)
AC_A(5)
AC_A(4)
AC_A(3)
AC_A(2)
AC_A(1)
AC_A(0)
AC_R(1)
AC_R(0)
DAS_OUT
DAS_AI_P
DAS_AI_M
DAS_AO
VBAT
third
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
35
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
I/O configuration
second
first
function
lqfp-64
pin
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TEST
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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1-7
XE8805/05A
POWER
PU
OD
DO
DI
AO
AI
VSS
VSS_REG
VREG
VMULT
RESET
OSCOUT
OSCIN
third
56
57
58
60
61
62
63
I/O configuration
second
first
function
lqfp-64
pin
X
X
X
X
X
X
X
Pin map table legend:
blue bold: configuration at start up
AI: analog input
AO: analog output
DI: digital input
DO: digital output
OD: nMOS open drain output
PU: pull-up resistor
POWER: power supply
Table 1-3. Pin description table
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1-8
XE8805/05A
2 XE8805/05A Performance
2.1
Absolute maximum ratings
2-2
2.2
Operating range
2-2
2.3
2.3.1
2.3.2
Supply configurations
Flash circuit
ROM circuit
2-3
2-3
2-3
2.4
Current consumption
2-5
2.5
2.5.1
2.5.2
Operating speed
Flash version
ROM circuit version
2-6
2-6
2-6
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2-1
XE8805/05A
2.1
Absolute maximum ratings
Table 2-1. Absolute maximum ratings
Voltage applied to VBAT with respect to VSS
Voltage applied to VPP with respect to VSS
Voltage applied to all pins except VPP and VBAT
Storage temperature (ROM device or unprogrammed
flash device)
Storage temperature (programmed flash device)
Min.
Max.
Note
-0.3
VBAT-0.3
VSS-0.3
-55
6.0
12
VBAT+0.3
150
V
V
V
°C
-40
85
°C
Stresses beyond the absolute maximal ratings may cause permanent damage to the device. Functional operation
at the absolute maximal ratings is not implied. Exposure to conditions beyond the absolute maximal ratings may
affect the reliability of the device.
2.2
Operating range
Table 2-2. Operating range for the flash device
Voltage applied to VBAT with respect to VSS
Voltage applied to VBAT with respect to VSS during
the flash programming
Voltage applied to VPP with respect to VSS
Voltage applied to all pins except VPP and VBAT
Operating temperature range
Capacitor on VREG (flash version)
Capacitor on VMULT
1.
2.
3.
Min.
Max.
Note
2.4
3.3
5.5
5.5
V
V
1
VBAT
VSS
-40
0.8
1.0
11.5
VBAT
85
1.2
3.0
V
V
°C
µF
nF
2
3
During the programming of the device, the supply voltage should at least be equal to the supply voltage
used during normal operation.
The capacitor on VREG is mandatory.
The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The
multiplier has to be enabled if VBAT<3.0V.
Table 2-3. Operating range for the ROM device
Min.
Voltage applied to VBAT with respect to VSS
Voltage applied to all pins except VPP and VBAT
Operating temperature range
Capacitor on VREG
Capacitor on VMULT
1.
2.
2.4
VSS
-40
0.1
1.0
Max.
5.5
VBAT
125
1.2
3.0
Note
V
V
°C
µF
nF
1
2
The capacitor may be omitted when VREG is connected to VBAT.
The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The
multiplier has to be enabled if VBAT<3.0V.
All specifications in this document are valid for the complete operating range unless otherwise specified.
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2-2
XE8805/05A
Table 2-4. Operating range of the Flash memory
Min.
Retention time at 85°C
Retention time at 55°C
Number of programming cycles
1.
2.
2.3
Max.
10
100
10
Note
years
years
1
1
2
Valid only if programmed using a programming tool that is qualified
Circuits can be programmed more than 10 times but after that, the retention time is no longer guaranteed.
All qualification tests have been done after 10 cycles.
Supply configurations
2.3.1
Flash circuit
The flash version of the circuit can be run from a supply between 2.4V and 5.5V (Figure 2-1). The capacitor on
VREG has to be connected at all times (value in Table 2-2) to guarantee proper operation of the device. The
capacitor on VMULT is only required if the circuit is to be operated below 3V.
VBAT
VREG
2.4V – 5.5V
VMULT
Cvreg
Cvmult
VSS
Figure 2-1. Supply configuration for the flash circuit.
2.3.2
ROM circuit
For the ROM version, two possible operating modes exist: with and without voltage regulator. Using the voltage
regulator, low power consumption will be obtained even with supply voltages above 2.4V. Without the voltage
regulator (i.e. VREG short-circuited to VBAT), a higher speed can be obtained.
2.3.2.1
Low power operation
In this case, the internal voltage regulator is used in order to maintain low power consumption independent from
the supply voltage. The capacitor on VREG has to be connected at all times (value in Table 2-3) to guarantee
proper operation of the device. The capacitor on VMULT has to be connected only when VBAT<3V.
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2-3
XE8805/05A
VBAT
VREG
2.4V – 5.5V
VMULT
Cvreg
Cvmult
VSS
Figure 2-2. Supply voltage connections for low power operation of the ROM version.
2.3.2.2
High speed operation
In this case, the internal voltage regulator is not used. The operation speed of the circuit can be increased with
increasing supply voltage but the supply current will also increase. The capacitor on VMULT has to be connected
only when VBAT<3V. In this case, the supply voltage can decrease down to 2.15V. Beware however that the
zoomingADCTM will not run below 2.4V (see Figure 2-4). In this configuration, the circuit can not be used above
3.3V.
VBAT
VREG
2.15V – 3.3V
VMULT
Cvmult
VSS
Figure 2-3. Supply voltage connections for high speed operation of the ROM version.
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2-4
XE8805/05A
acquisition chain
voltage multiplier
DAB
CPU
parallel and serial ports
RC and crystal oscillator
VLD
Counters and PWM
DAS (without amplifier)
0
2.15
2.4
3.3
VBAT (V)
Figure 2-4. Operation range of the different circuit blocks
2.4
Current consumption
The tables below give the current consumption for the circuit in different configurations. The figures are indicative
only and may change as a function of the actual software implemented in the circuit.
Table 2-5 gives the current consumption for the flash version of the circuit. The peripherals are disabled. The
parallel ports A and B are configured in input with pull up, the parallel port C is configured as an output. Their pins
are not connected externally. The pin RESET is connected to VSS and the pin VPP/TEST is connected to VBAT.
The inputs of the acquisition chain are connected to VSS.
Table 2-5. Typical current consumption of the XE8805 version (8k instructions flash memory)
Operation mode
CPU
RC
Xtal
Consumption
comments
Note
High speed CPU
Low power CPU
Low power time
keeping
Fast
wake-up
time keeping
Immediate wakeup time keeping
VLD static current
16 bit resolution
data acquisition
12 bit , gain 100,
data acquisition
1 MIPS
32 kIPS
HALT
1 MHz
Off
Off
Off
32 kHz
32 kHz
310 µA
10 µA
1.0 µA
2.4V<>5.5V, 27°C
2.4V <>5.5V, 27°C
2.4V <>5.5V, 27°C
HALT
Ready
32kHz
1.7 µA
2.4V <>5.5V, 27°C
HALT
100 kHz
Off
1.4 µA
2.4V <>5.5V, 27°C
HALT
2 MHz
Off
15 µA
190 µA
2.4V <>5.5V, 27°C
3.0V, 27°C
1
HALT
2 MHz
Off
460 µA
3.0V, 27°C
2
1. PGA disabled, ADC enabled, 16 bit resolution
2. PGA 1 disabled, PGA 2 and 3 enabled, ADC enabled, 12 bit resolution
For more information concerning the current consumption of the zoomingADCTM, see the chapter power
consumption in the acquisition chain documentation which shows the current consumption of this block as a
function of temperature and voltage and for different configurations of the PGA and ADC.
The power consumption of the ROM version of the circuit is identical if it is configured as shown in Figure 2-2. In
the high speed configuration, the current consumption will increase proportional with VBAT.
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2.5
Operating speed
2.5.1
Flash version
The speed of the devices is not highly dependent upon the supply voltage. However, by limiting the temperature
range, the speed can be increased. The minimal guaranteed speed as a function of the supply voltage and
maximal temperature operating temperature is given in Figure 2-5.
speed (MIPS)
4
3
2
1
85°C
45°C
0
2
2.5
3
3.5
4
4.5
5
5.5
supply voltage VBAT (V)
Figure 2-5. Guaranteed speed as a function of the supply voltage and maximal temperature.
2.5.2
ROM circuit version
2.5.2.1
Low power supply configuration
In the low power supply configuration as shown in Figure 2-2, the operating speed does not depend highly on the
supply voltage as shown in Figure 2-6.
speed (MIPS)
85°C
45°C
125°C
3.5
3
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
supply voltage VBAT (V)
Figure 2-6. Guaranteed speed as a function of supply voltage and for different maximal temperatures using the
voltage regulator.
2.5.2.2
High speed supply configuration
In the high speed supply configuration of Figure 2-3, the guaranteed speed of the circuit is shown in Figure 2-7.
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2-6
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85°C
45°C
125°C
speed (MIPS)
4
3
2
1
0
2
2.2
2.4
2.6
2.8
3
3.2
3.4
supply voltage VBAT (V)
Figure 2-7. Guaranteed speed as a function of supply voltage and for three temperature ranges when
VREG=VBAT.
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XE8805/05A
3. CPU
CONTENTS
3.1
CPU description
3-2
3.2
CPU internal registers
3-2
3.3
CPU instruction short reference
3-4
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3-1
XE8805/05A
3.1
CPU description
The CPU of the XE8000 series is a low power RISC core. It has 16 internal registers for efficient implementation of
the C compiler. Its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing
modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. The
circuit therefore runs on 1 MIPS on a 1MHz clock.
The CPU hardware and software description is given in the document “Coolrisc816 Hardware and Software
Reference Manual”. A short summary is given in the following paragraphs.
The
good
code
efficiency
of
the
CPU
core
makes
it
possible
to
compute
a
polynomial
like
Z = ( A0 + A1 ⋅ Y ) ⋅ X + B0 + B1 ⋅ Y in less than 300 clock cycles (software code generated by the XEMICS Ccompiler, all numbers are signed integers on 16 bits).
3.2
CPU internal registers
As shown in Figure 3-1, the CPU has 16 internal 8-bit registers. Some of these registers can be concatenated to a
16-bit word for use in some instructions. The function of these registers is defined in Table 3-1. The status register
stat (Table 3-2) is used to manage the different interrupt and event levels. An interrupt or an event can both be
used to wake up after a HALT instruction. The difference is that an interrupt jumps to a special interrupt function
whereas an event continues the software execution with the instruction following the HALT instruction.
The program counter (PC) is a 16 bit register that indicates the address of the instruction that has to be executed.
The stack (STn) is used to memorise the return address when executing subroutines or interrupt routines.
ST4
ST3
ST1
ST2
r0
r1
Data memory
r2
data bus
22bit
CPU
CPU internal registers
Instruction
memory
instruction bus
PC
program counter stack
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
iph
ipl
stat
a
Figure 3-1. CPU internal registers
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Register name
r0
r1
r2
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
iph
ipl
stat
a
Register function
general purpose
general purpose
general purpose
data memory offset
MSB of the data memory index i0
LBS of the data memory index i0
MSB of the data memory index i1
LBS of the data memory index i1
MSB of the data memory index i2
LBS of the data memory index i2
MSB of the data memory index i3
LBS of the data memory index i3
MSB of the program memory index ip
LBS of the program memory index ip
status register
accumulator
Table 3-1. CPU internal register definition
bit
7
6
5
4
name
IE2
IE1
GIE
IN2
3
IN1
2
IN0
1
EV1
0
EV0
function
enables (when 1) the interrupt request of level 2
enables (when 1) the interrupt request of level 1
enables (when 1) all interrupt request levels
interrupt request of level 2. The interrupts labelled “low” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
interrupt request of level 1. The interrupts labelled “mid” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
interrupt request of level 0. The interrupts labelled “hig” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
event request of level 1. The events labelled “low” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
event request of level 1. The events labelled “hig” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
Table 3-2. Status register description
The CPU also has a number of flags that can be used for conditional jumps. These flags are defined in Table 3-3.
symbol
Z
C
V
name
zero
carry
overflow
function
Z=1 when the accumulator a content is zero
This flag is used in shift or arithmetic operations.
For a shift operation, it has the value of the bit that was shifted out (LSB for shift
right, MSB for shift left).
For an arithmetic operation with unsigned numbers:
it is 1 at occurrence of an overflow during an addition (or equivalent).
it is 0 at occurrence of an underflow during a subtraction (or equivalent).
This flag is used in shift or arithmetic operations.
For arithmetic or shift operations with signed numbers, it is 1 if an overflow or
underflow occurs.
Table 3-3. Flag description
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3-3
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3.3
CPU instruction short reference
Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The notation cc in the
conditional jump instruction refers to the condition description as given in Table 3-6. The notation reg, reg1, reg2,
reg3 refers to one of the CPU internal registers of Table 3-1. The notation eaddr and DM(eaddr) refer to one of the
extended address modes as defined in Table 3-5. The notation DM(xxx) refers to the data memory location with
address xxx.
Instruction
Modification
Operation
Jump addr[15:0]
Jump ip
Jcc addr[15:0]
Jcc ip
Call addr[15:0]
Call ip
Calls addr[15:0]
Calls ip
-,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -
PC := addr[15:0]
PC := ip
if cc is true then PC := addr[15:0]
if cc is true then PC := ip
STn+1 := STn (n>1); ST1 := PC+1; PC := addr[15:0]
STn+1 := STn (n>1); ST1 := PC+1; PC := ip
ip := PC+1; PC := addr[15:0]
ip := PC+1; PC := ip
Ret
Rets
Reti
Push
Pop
-,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -
PC := ST1; STn := STn+1 (n>1)
PC := ip
PC := ST1; STn := STn+1 (n>1); GIE :=1
PC := PC+1; STn+1 := STn (n>1); ST1 := ip
PC := PC+1; ip := ST1; STn := STn+1 (n>1)
Move reg,#data[7:0]
Move reg1, reg2
Move reg, eaddr
Move eaddr, reg
Move addr[7:0],#data[7:0]
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-,-, -,-,-, -
a := data[7:0]; reg := data[7:0]
a := reg2; reg1 := reg2
a := DM(eaddr); reg := DM(eaddr)
DM(eaddr) := reg
DM(addr[7:0]) := data[7:0]
Cmvd reg1, reg2
Cmvd reg, eaddr
Cmvs reg1, reg2
Cmvs reg, eaddr
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
a := reg2; if C=0 then reg1 := a;
a := DM(eaddr); if C=0 then reg := a
a := reg2; if C=1 then reg1 := a;
a := DM(eaddr); if C=1 then reg := a
Shl reg1, reg2
Shl reg
Shl reg, eaddr
Shlc reg1, reg2
Shlc reg
Shlc reg, eaddr
Shr reg1, reg2
Shr reg
Shr reg, eaddr
Shrc reg1, reg2
Shrc reg
Shrc reg, eaddr
Shra reg1, reg2
Shra reg
Shra reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg2<<1; a[0] := 0; C := reg2[7]; reg1 := a
a := reg<<1; a[0] := 0; C := reg[7]; reg := a
a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]; reg := a
a := reg2<<1; a[0] := C; C := reg2[7]; reg1 := a
a := reg<<1; a[0] := C; C := reg[7]; reg := a
a := DM(eaddr)<<1; a[0] := C; C := DM(eaddr)[7]; reg := a
a := reg2>>1; a[7] := 0; C := reg2[0]; reg1 :=a
a := reg>>1; a[7] := 0; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := 0; C := DM(eaddr)[0]; reg := a
a := reg2>>1; a[7] := C; C := reg2[0]; reg1 := a
a := reg>>1; a[7] := C; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := C; C := DM(eaddr)[0]; reg := a
a := reg2>>1; a[7] := reg2[7]; C := reg2[0]; reg1 := a
a := reg>>1; a[7] := reg[7]; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0]; reg := a
Cpl1 reg1, reg2
Cpl1 reg
Cpl1 reg, eaddr
Cpl2 reg1, reg2
Cpl2 reg
Cpl2 reg, eaddr
Cpl2c reg1, reg2
Cpl2c reg
Cpl2c reg, eaddr
-,-, Z, a
-,-, Z, a
-,-, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := NOT(reg2); reg1 := a
a := NOT(reg); reg := a
a := NOT(DM(eaddr)); reg := a
a := NOT(reg2)+1; if a=0 then C:=1 else C := 0; reg1 := a
a := NOT(reg)+1; if a=0 then C:=1 else C := 0; reg := a
a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0; reg := a
a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0; reg1 := a
a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
Inc reg1, reg2
Inc reg
Inc reg, eaddr
Incc reg1, reg2
Incc reg
Incc reg, eaddr
Dec reg1, reg2
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg2+1; if a=0 then C := 1 else C := 0; reg1 := a
a := reg+1; if a=0 then C := 1 else C := 0; reg := a
a := DM(eaadr)+1; if a=0 then C := 1 else C := 0; reg := a
a := reg2+C; if a=0 and C=1 then C := 1 else C := 0; reg1 := a
a := reg+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a
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3-4
XE8805/05A
Dec reg
Dec reg, eaddr
Decc reg1, reg2
Decc reg
Decc reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg-1; if a=hFF then C := 0 else C := 1; reg := a
a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1; reg := a
a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg1 := a
a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
And reg,#data[7:0]
And reg1, reg2, reg3
And reg1, reg2
And reg, eaddr
Or reg,#data[7:0]
Or reg1, reg2, reg3
Or reg1, reg2
Or reg, eaddr
Xor reg,#data[7:0]
Xor reg1, reg2, reg3
Xor reg1, reg2
Xor reg, eaddr
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
a := reg and data[7:0]; reg := a
a := reg2 and reg3; reg1 := a
a := reg1 and reg2; reg1 := a
a := reg and DM(eaddr); reg := a
a := reg or data[7:0]; reg := a
a := reg2 or reg3; reg1 := a
a := reg1 or reg2; reg1 := a
a := reg or DM(eaddr); reg := a
a := reg xor data[7:0]; reg := a
a := reg2 xor reg3; reg1 := a
a := reg1 xor reg2; reg1 := a
a := reg or DM(eaddr); reg := a
Add reg,#data[7:0]
Add reg1, reg2, reg3
Add reg1, reg2
Add reg, eaddr
Addc reg,#data[7:0]
Addc reg1, reg2, reg3
Addc reg1, reg2
Addc reg, eaddr
Subd reg,#data[7:0]
Subd reg1, reg2, reg3
Subd reg1, reg2
Subd reg, eaddr
Subdc reg,#data[7:0]
Subdc reg1, reg2, reg3
Subdc reg1, reg2
Subdc reg, eaddr
Subs reg,#data[7:0]
Subs reg1, reg2, reg3
Subs reg1, reg2
Subs reg, eaddr
Subsc reg,#data[7:0]
Subsc reg1, reg2, reg3
Subsc reg1, reg2
Subsc reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg+data[7:0]; if overflow then C:=1 else C := 0; reg := a
a := reg2+reg3; if overflow then C:=1 else C := 0; reg1 := a
a := reg1+reg2; if overflow then C:=1 else C := 0; reg1 := a
a := reg+DM(eaddr); if overflow then C:=1 else C := 0; reg := a
a := reg+data[7:0]+C; if overflow then C:=1 else C := 0; reg := a
a := reg2+reg3+C; if overflow then C:=1 else C := 0; reg1 := a
a := reg1+reg2+C; if overflow then C:=1 else C := 0; reg1 := a
a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0; reg := a
a := data[7:0]-reg; if underflow then C := 0 else C := 1; reg := a
a := reg2-reg3; if underflow then C := 0 else C := 1; reg1 := a
a := reg2-reg1; if underflow then C := 0 else C := 1; reg1 := a
a := DM(eaddr)-reg; if underflow then C := 0 else C := 1; reg := a
a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg2-reg3-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg2-reg1-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg-data[7:0]; if underflow then C := 0 else C := 1; reg := a
a := reg3-reg2; if underflow then C := 0 else C := 1; reg1 := a
a := reg1-reg2; if underflow then C := 0 else C := 1; reg1 := a
a := reg-DM(eaddr); if underflow then C := 0 else C := 1; reg := a
a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg3-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg1-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1; reg := a
Mul reg,#data[7:0]
Mul reg1, reg2, reg3
Mul reg1, reg2
Mul reg, eaddr
Mula reg,#data[7:0]
Mula reg1, reg2, reg3
Mula reg1, reg2
Mula reg, eaddr
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
Mshl reg,#shift[2:0]
Mshr reg,#shift[2:0]
Mshra reg,#shift[2:0]
u, u, u, a
u, u, u, a
u, u, u, a*
a := (reg*2 )[7:0]; reg := (reg*2 )[15:8]
(8-shift
(8-shift
a := (reg*2
)[7:0]; reg := (reg*2
)[15:8]
(8-shift
(8-shift
a := (reg*2
)[7:0]; reg := (reg*2
)[15:8]
Cmp reg,#data[7:0]
Cmp reg1, reg2
Cmp reg, eaddr
Cmpa reg,#data[7:0]
Cmpa reg1, reg2
Cmpa reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Tstb reg,#bit[2:0]
Setb reg,#bit[2:0]
Clrb reg,#bit[2:0]
Invb reg,#bit[2:0]
-, -, Z, a
-, -, Z, a
-, -, Z, a
-, -, Z, a
a[bit] := reg[bit]; other bits in a are 0
reg[bit] := 1; other bits unchanged; a := reg
reg[bit] := 0; other bits unchanged; a := reg
reg[bit] := not reg[bit]; other bits unchanged; a := reg
shift
shift
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Sflag
-,-,-, a
a[7] := C; a[6] := C xor V; a[5] := ST full; a[4] := ST empty
Rflag reg
Rflag eaddr
C, V, Z, a
C, V, Z, a
a := reg << 1; ; a[0] := 0; C := reg[7]
a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]
Freq divn
-,-,-, -
reduces the CPU frequency (divn=nodiv, div2, div4, div8, div16)
Halt
-,-,-, -
halts the CPU
Nop
-,-,-, -
no operation
- = unchanged, u = undefined, *MSHR reg,# 1 doesn’t shift by 1
Table 3-4. Instruction short reference
The Coolrisc816 has 8 different addressing modes. These modes are described in Table 3-5. In this table, the
notation ix refers to one of the data memory index registers i0, i1, i2 or i3. Using eaddr in an instruction of Table 3-4
will access the data memory at the address DM(eaddr) and will simultaneously execute the index operation.
extended address
eaddr
addr[7:0]
(ix)
(ix, offset[7:0])
(ix,r3)
(ix)+
(ix,offset[7:0])+
-(ix)
-(ix,offset[7:0])
accessed data memory
location
DM(eaddr)
DM(h00&addr[7:0])
DM(ix)
DM(ix+offset)
DM(ix+r3)
DM(ix)
DM(ix+offset)
DM(ix-1)
DM(ix-offset)
index
operation
ix := ix+1
ix := ix+offset
ix := ix-1
ix := ix -offset
direct addressing
indexed addressing
indexed addressing with immediate offset
indexed addressing with register offset
indexed addressing with index post-increment
indexed addressing with index post-increment by the offset
indexed addressing with index pre-decrement
indexed addressing with index pre-decrement by the offset
Table 3-5. Extended address mode description
Eleven different jump conditions are implemented as shown in Table 3-6. The contents of the column CC in this
table should replace the CC notation in the instruction description of Table 3-4.
CC
condition
CS
CC
ZS
ZC
VS
VC
EV
C=1
C=0
Z=1
Z=0
V=1
V=0
(EV1 or EV0)=1
After CMP op1,op2
EQ
NE
GT
GE
LT
LE
op1=op2
op1≠op2
op1>op2
op1≥op2
op1<op2
op1≤op2
Table 3-6. Jump condition description
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3-6
XE8805/05A
4 Memory Mapping
4.1
Memory organisation
4-2
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
4.2.15
4.2.16
4.2.17
Quick reference data memory register map
Low power data registers (h0000-h0007)
System, clock configuration and reset configuration (h0010-h001F)
Port A (h0020-h0027)
Port B (h0028-h002F)
Port C (h0030-h0033)
Flash programming (h0038-003B)
Event handler (h003C-h003F)
Interrupt handler (h0040-h0047)
USRT (h0048-h004F)
UART (h0050-h0057)
Counter/Timer/PWM registers (h0058-h005F)
Acquisition chain registers (h0060-h0067)
Signal D/A registers (h0074-h0077)
Bias D/A registers (h0078-h0079)
Voltage multiplier (h007C)
Voltage Level Detector registers (h007E-h007F)
RAM (h0080-h027F)
4-2
4-3
4-4
4-4
4-4
4-5
4-5
4-5
4-6
4-7
4-7
4-7
4-8
4-8
4-8
4-8
4-9
4-9
© Semtech 2006
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4-1
XE8805/05A
4.1
Memory organisation
The XE8805 CPU is built with a Harvard architecture. The Harvard architecture uses separate instruction and data
memories. The instruction bus and data bus are also separated. The advantage of such a structure is that the CPU
can get a new instruction and read/write data simultaneously. The circuit configuration is shown in Figure 4-1. The
CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit instructions. The data
memory space has 8 low power registers, the peripheral register space and 512 bytes of RAM.
µF0h1FFF
µF
0h027F
CPU
capacity:
512 bytes
instruction bus
r2
r3
i0l
i1h
i1l
i2h
i2l
i3h
i3l
0h007F
Peripheral
registers
iph
ipl
0h0008
stat
0h0000
0h0080
i0h
Data memory
r1
data bus
capacity:
8k x 22bit
r0
CPU internal registers
Instruction
memory
RAM
Low power
RAM
0h0000
a
Figure 4-1. Memory mapping
The CPU internal registers are described in the CPU chapter. A short reference of the low power registers and
peripheral registers is given in 4.2.
4.2
Quick reference data memory register map
The data register map is given in the tables below. A more detailed description of the different registers is given in
the detailed description of the different peripherals.
The tables give the following information:
1. The register name and register address
2. The different bits in the register
3. The access mode of the different bits (see Table 4-1 for code description)
4. The reset source and reset value of the different bits
The reset source coding is given in Table 4-2. To get a full description of the reset sources, please refer to the
reset block chapter.
© Semtech 2006
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4-2
XE8805/05A
code
r
w
r0
r1
c
c1
ca
s
access mode
bit can be read
bit can be written
bit always reads 0
bit always reads 1
bit is cleared by writing any value
bit is cleared by writing a 1
bit is cleared after reading
special function, verify the detailed description in the respective peripherals
Table 4-1. Access mode codes used in the register definitions
code
sys
cold
pconf
sleep
reset source
resetsystem
resetcold
resetpconf
resetsleep
Table 4-2. Reset source coding used in the register definitions
4.2.1
Low power data registers (h0000-h0007)
Name
Address
7
6
Reg00
h0000
Reg01
h0001
Reg02
h0002
Reg03
h0003
Reg04
h0004
Reg05
h0005
Reg06
h0006
Reg07
h0007
5
4
3
Reg00[7:0]
rw, xxxxxxxx,Reg01[7:0]
rw,xxxxxxxx,Reg02[7:0]
rw,xxxxxxxx,Reg03[7:0]
rw,xxxxxxxx,Reg04[7:0]
rw,xxxxxxxx,Reg05[7:0]
rw,xxxxxxxx,Reg06[7:0]
rw,xxxxxxxx,Reg07[/:0]
rw,xxxxxxxx,-
2
1
0
Table 4-3. Low power data registers
© Semtech 2006
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4-3
XE8805/05A
4.2.2
System, clock configuration and reset configuration (h0010-h001F)
Name
Address
7
RegSysCtrl SleepEn
h0010
rw,0,cold
RegSysReset
Sleep
h0011
rw,0,sys
RegSysClock
CpuSel
h0012
rw,0,sleep
RegSysMisc
h0013
r0
RegSysWd
h0014
r0
RegSysPre0
r0
h0015
RegSysRcTrim1
h001B
r0
RegSysRcTrim2
h001C
r0
6
EnResPConf
rw,0,cold
5
EnBusError
rw,0,cold
r0
r0
r0
r0
r0
3
2
1
0
r0
r0
r0
ResPad
ResPadSleep
rc, 0, cold
rc, 0, cold
rc,0,cold
r0
rc,0,cold
EnExtClock
ColdXtal
ColdRC
EnableXtal EnableRC
rw,0,cold
r,1,sleep
r,1,sleep
rw,0,sleep rw,1,sleep
RCOnPA0
DebFast
OutputCkXtal OutputCpuCk
r0
r0
rw,0,sleep rw,0,sleep rw,0,sleep rw,0,sleep
WatchDog[3:0]
r0
r0
s,0000,cold
ResPre
r0
r0
r0
r0
r0
c1r0,0,Reserved RcFreqRange
RcFreqCoarse[3:0]
rw,0,cold
rw,0000,cold
rw,0,cold
RcFreqFine[5:0]
rw,10000,cold
ResetBusError
ExtClk
r,0,cold
4
EnResWD
rw,0,cold
ResetWD
rc, 0, cold
BiasRC
rw,1,cold
r0
ResetfromportA
Table 4-4. Reset block and clock block registers
4.2.3
Port A (h0020-h0027)
Name
Address
7
6
5
RegPAIn
h0020
RegPADebounce
h0021
RegPAEdge
h0022
RegPAPullup
h0023
RegPARes0
h0024
RegPARes1
h0025
4
3
PAIn[7:0]
r
PADebounce[7:0]
rw,00000000,pconf
PAEdge[7:0]
rw,00000000,sys
PAPullup[7:0]
rw,00000000,pconf
PARes0[7:0]
rw, 00000000, sys
PARes1[7:0]
rw,00000000,sys
2
1
0
4
2
1
0
r0
PBAna[3:0]
rw,0000,pconf
Table 4-5. Port A registers
4.2.4
Port B (h0028-h002F)
Name
Address
7
6
5
r0
r0
r0
RegPBOut
h0028
RegPBIn
h0029
RegPBDir
h002A
RegPBOpen
h002B
RegPBPullup
h002C
RegPBAna
h002D
3
PBOut[7:0]
rw,00000000,pconf
PBIn[7:0]
r
PBDir[7:0]
rw,00000000,pconf
PBOpen[7:0]
rw,00000000,pconf
PBPullup[7:0]
rw,00000000,pconf
Table 4-6. Port B registers
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4-4
XE8805/05A
4.2.5
Port C (h0030-h0033)
Name
Address
7
6
5
4
3
PCOut[7:0]
rw,00000000,pconf
PCIn[7:0]
r,-,PD1Dir[7:0]
rw,00000000,pconf
RegPCOut
h0030
RegPCIn
h0031
RegPCDir
h0032
2
1
0
Table 4-7. Port C registers
4.2.6
Flash programming (h0038-003B)
These four registers are used during flash programming only. Refer to the flash programming algorithm
documentation for more details.
4.2.7
Event handler (h003C-h003F)
Name
Address
RegEvn
h003C
RegEvnEn
h003D
RegEvnPriority
h003E
RegEvnEvn
h003F
7
CntIrqA
rc1,0,sys
6
CntIrqC
rc1,0,sys
5
128Hz
rc1,0,sys
r0
r0
r0
4
3
PAEvn[1]
CntIrqB
rc1,0,sys
rc1,0,sys
EvnEn[7:0]
rw,00000000,sys
EvnPriority[7:0]
r,11111111,sys
r0
r0
2
CntIrqD
rc1,0,sys
1
1Hz
rc1,0,sys
0
PAEvn[0]
rc1,0,sys
r0
EvnHigh
r,0,sys
EvnLow
r,0,sys
Table 4-8. Event handler registers
The origin of the different events is summarised in the table below.
Event
CntIrqA
CntIrqB
CntIrqC
CntIrqD
128Hz
1Hz
PAEvn[1:0]
Event source
Counter/Timer A (counter block)
Counter/Timer B (counter block)
Counter/Timer C (counter block)
Counter/Timer D (counter block)
Low prescaler (clock block)
Low prescaler (clock block)
Port A
Table 4-9. Event source description
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4-5
XE8805/05A
4.2.8
Interrupt handler (h0040-h0047)
Name
Address
7
IrqAC
h0040
rc1,0,sys
RegIrqMid UsrtCond1
h0041
rc1,0,sys
RegIrqLow PAIrq[7]
h0042
rc1,0,sys
RegIrqEnHig
h0043
RegIrqEnMid
h0044
RegIrqEnLow
h0045
RegIrqPriority
h0046
RegIrqIrq
h0047
r0
RegIrqHig
6
128Hz
rc1,0,sys
UrstCond2
rc1,0,sys
PAIrq[6]
rc1,0,sys
5
r0
PAIrq[5]
rc1,0,sys
CntIrqB
rc1,0,sys
r0
r0
4
3
CntIrqA
CntIrqC
rc1,0,sys
rc1,0,sys
PAIrq[4]
1Hz
rc1,0,sys
rc1,0,sys
CntIrqD
PAIrq[3]
rc1,0,sys
rc1,0,sys
IrqEnHig[7:0]
rw,0000000,sys
IrqEnMid[7:0]
rw,0000000,sys
IrqEnLow[7:0]
rw,0000000,sys
IrqPriority[7:0]
r,11111111,sys
r0
r0
2
r0
VldIrq
rc1,0,sys
PAIrq[2]
rc1,0,sys
IrqHig
r,0,sys
1
UartIrqTx
rc1,0,sys
PAIrq[1]
rc1,0,sys
0
UartIrqRx
rc1,0,sys
PAIrq[0]
rc1,0,sys
r0
r0
IrqMid
r,0,sys
IrqLow
r,0,sys
Table 4-10. Interrupt handler registers
The origin of the different interrupts is summarised in the table below.
Event
CntIrqA
CntIrqB
CntIrqC
CntIrqD
128Hz
1Hz
PAIrq[7:0]
UartIrqRx
UartIrqTx
UrstCond1
UsrtCond2
VldIrq
IrqAC
Event source
Counter/Timer A (counter block)
Counter/Timer B (counter block)
Counter/Timer C (counter block)
Counter/Timer D (counter block)
Low prescaler (clock block)
Low prescaler (clock block)
Port A
UART reception
UART transmission
USRT condition 1
USRT condition 2
Voltage level detector
Acquisition chain end of conversion interrupt
Table 4-11. Interrupt source description
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4-6
XE8805/05A
4.2.9
USRT (h0048-h004F)
Name
Address
7
6
5
4
3
2
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
UsrtEnWaitCond1
RegUsrtS1
h0048
RegUsrtS0
h0049
RegUsrtCond1
h004A
RegUsrtCond2
h004B
RegUsrtCtrl
h004C
RegUsrtBufferS1
h004D
RegUsrtEdgeS0
h004E
r0
r0
r0
r0
r0
UsrtWaitS0
r,0,sys
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
rw,0,sys
1
0
UsrtS1
r0
s,1,sys
UsrtS0
r0
s,1,sys
UsrtCond1
r0
rc,0,sys
UsrtCond2
r0
rc,0,sys
UsrtEnWaitS0 UsrtEnable
rw,0,sys
rw,0,sys
UsrtBufferS1
r0
r,0,sys
UsrtEdgeS0
r0
r,0,sys
Table 4-12. USRT register description
4.2.10
UART (h0050-h0057)
Name
Address
RegUartCtrl
h0050
RegUartCmd
h0051
RegUartTx
h0052
RegUartTxSta
h0053
RegUartRx
h0054
RegUartRxSta
h0055
7
UartEcho
rw,0,sys
SelXtal
rw,0,sys
6
UartEnRx1
rw,0,sys
UartEnRx2
rw,0,sys
r0
r0
r0
r0
5
UartEnTx
rw,0,sys
4
3
UartXRx
UartXTx
rw,0,sys
rw,0,sys
UartRcSel[2:0]
rw,000,sys
UartTx[7:0]
rw,0000000,sys
2
UartPM
rw,0,sys
1
UartBR[2:0]
rw,101,sys
UartPE
rw,0,sys
0
UartWL
rw,1,sys
UartTxBusy UartTxFull
r0
r0
r0
r,0,sys
r,0,sys
UartRx[7:0]
r,00000000,sys
UartRxSErr UartRxPErr UartRxFErr UartRxOerr UartRxBusy UartRxFull
r,0,sys
r,0,sys
r,0,sys
rc,0,sys
r,0,sys
r,0,sys
r0
Table 4-13. UART register description
4.2.11
Counter/Timer/PWM registers (h0058-h005F)
Name
Address
7
RegCntA
h0058
RegCntB
h0059
RegCntC
h005A
RegCntD
h005B
RegCntCtrlCk
h005C
RegCntConfig1
h005D
RegCntConfig2
h005E
RegCntOn
h005F
6
5
4
3
2
1
0
CounterA[7:0]
s,xxxxxxxx,CounterB[7:0]
s,xxxxxxxx,CounterC[7:0]
s,xxxxxxxx,CounterD[7:0]
s,xxxxxxxx,CntDCkSel[1:0]
CntCCkSel[1:0]
CntBCkSel[1:0]
CntACkSel[1:0]
rw,xx,rw,xx,rw,xx,rw,xx,CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0
rw,x,rw,x,rw,0,sys
rw,0,sys
rw,x,rw,x,rw,x,rw,x,CapSel[1:0]
CapFunc[1:0]
Pwm1Size[1:0]
Pwm0Size[1:0]
rw,00,sys
rw,00,sys
rw,xx,rw,xx,CntDEnable CntCEnable CntBEnable CntAEnable
r0
r0
r0
rw,0,sys
rw,0,sys
rw,0,sys
rw,0,sys
r0
Table 4-14. Counter/timer/PWM register description.
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4-7
XE8805/05A
4.2.12
Acquisition chain registers (h0060-h0067)
Name
Address
7
6
5
4
3
2
1
RegAcOutLsb
OUT[7:0]
h0060
r,0,sys
RegAcOutMsb
OUT[15:8]
h0061
r,0,sys
RegAcCfg0
START
SET_NELCONV[1:0]
SET_OSR[2:0]
CONT
h0062
w r0,0,sys
rw,01,sys
rw,010,sys
rw,0,sys
RegAcCfg1
IB_AMP_ADC[1:0]
IB_AMP_PGA[1:0]
ENABLE[3:0]
h0063
rw,11,sys
rw,11,sys
rw,0000,sys
RegAcCfg2
FIN
PGA2_GAIN[1:0]
PGA2_OFFSET[3:0]
h0064
rw,00,sys
rw,00,sys
rw,0000,sys
RegAcCfg3 PGA1_GAIN
PGA3_GAIN[6:0]
h0065
rw,0000000,sys
Rw,0,sys
RegAcCfg4
PGA3_OFFSET
h0066
r0
rw,0000000,sys
RegAcCfg5
BUSY
DEF
AMUX[4:0]
h0067
r,0,sys
w r0
rw,00000,sys
0
r0
VMUX
rw,0,sys
Table 4-15. Acquisition chain register description.
4.2.13
Signal D/A registers (h0074-h0077)
Name
Address
RegDasInLsb
h0074
RegDasInMsb
h0075
RegDasCfg0
h0076
RegDasCfg1
h0077
7
6
5
NsOrder(1:0)
rw,00,sys
r0
r0
r0
4
3
DasInLsb(7:0)
rw,00000000,sys
DasInMsb(7:0)
rw,00000000,sys
CodeLmax(2:0)
rw,000,sys
r0
r0
2
1
0
Enable(1:0)
rw,00,sys
BW
r0
rw,0,sys
Fin
rw,0,sys
Inv
rw,0,sys
Table 4-16. Signal D/A register description
4.2.14
Bias D/A registers (h0078-h0079)
Name
Address
7
6
5
r0
r0
r0
r0
r0
r0
5
4
3
2
Enable
rw,0,sys
RegDabIn
h0078
4
3
DabIn(7:0)
rw,00000000,sys
2
1
Enable(1:0)
rw,00,sys
RegDabCfg
h0079
0
Table 4-17. Bias D/A register description
4.2.15
Voltage multiplier (h007C)
Name
Address
RegVmultCfg0
h007C
7
r0
6
r0
r0
r0
r0
1
0
Fin[1:0]
rw,00,sys
Table 4-18. VMULT register.
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4-8
XE8805/05A
4.2.16
Voltage Level Detector registers (h007E-h007F)
Name
Address
7
6
5
4
r0
r0
r0
r0
3
VldRange
rw,0,sys
r0
r0
r0
r0
r0
RegVldCtrl
h007E
RegVldStat
h007F
2
1
VldTune[2:0]
rw,000,sys
VldResult
VldValid
r,0,sys
r,0,sys
0
VldEn
rw,0,sys
Table 4-19. Voltage level detector register description
4.2.17
RAM (h0080-h027F)
The 512 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables
stored in the RAM should be initialised before use since they can have any value at circuit start up.
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4-9
XE8805/05A
5 System Block
5.1
Overview
5-2
5.2
Operating mode
5-2
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5-1
XE8805/05A
5.1
Overview
The XE8000 chips have three operating modes. There is the normal, the low current and the very low current
modes (see Figure 5-1). The different modes are controlled by the reset and clock blocks (see the documentation
of the respective blocks).
5.2
Operating mode
Start-up
All bits are reset in the design when a POR (power-on-reset) is active.
RC is enabled, Xtal is disabled and the CPU is reset (pmaddr = 0000).
If Port A is used to return from the sleep mode, all bits with resetcold don’t change (see sleep mode).
Reset
All bits with resetsystem and resetpconf (if enabled) are reset. Clock configuration doesn’t change except cpuck.
The CPU is reset.
Active mode
This is the mode where the CPU and all peripherals can work and execute the embedded software.
Standby mode
Executing a HALT instruction moves the XE8805 into the Standby mode. The CPU is stopped, but the clocks
remain active. Therefore, the enabled peripherals remain active e.g. for time keeping. A reset or an interrupt/event
request (if enabled) cancels the standby mode.
Sleep mode
This is a very low-power mode because all circuit clocks and all peripherals are stopped. Only some service blocks
remain active. No time-keeping is possible. Two instructions are necessary to move into sleep mode. First, the
SleepEn (sleep enable) bit in RegSysCtrl has to be set to 1. The sleep mode can then be activated by setting the
Sleep bit in RegSysReset to 1.
There are three possibe ways to wake-up from the sleep mode:
1. The por (power-on-reset caused by a power-down followed by power-on). The RAM information is lost.
2. The padreset
3. The Port A reset combination (if the Port A is present in the product). See Port A documentation for
more details.
Note:
If the Port A is used to return from the sleep mode, all bits with resetcold don’t change (RegSysCtrl,
RegSysReset (except bit sleep), EnExtClock and BiasRc in RegSysClock, RegSysRcTrim1 and
RegSysRcTrim2). The SleepFlag bit in RegSysReset, reads back a 1 if the circuit was in sleep mode
since the flag was last cleared (see reset block for more details).
Note:
For a lower power consumption, disable the BiasRc bit in RegSysClock before to going to sleep mode.
The start-up time of the oscillator will then be longer however.
Note:
It is recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode
because this instruction can be executed when the sleep mode is left using the resetfromportA.
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5-2
XE8805/05A
START-UP
without
condition
por
por
RESET
por
padreset
portA reset
padreset
portA reset
watchdog reset
por
without
condition
padreset
portA reset
watchdog reset
buserror reset
Halt instruction
ACTIVE
Interrupt/event
STAND-BY
SLEEP
set bit sleep
normal mode
low current
very low current
Figure 5-1. XE8805 operating modes.
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5-3
XE8805/05A
6 Reset Block
6.1
Features
6-2
6.2
Overview
6-2
6.3
Register map
6-2
6.4
Reset handling capabilities
6-3
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
Reset source description
Power On Reset
RESET pin
Programmable Port A input combination
Watchdog reset
BusError reset
Sleep mode
6-4
6-4
6-4
6-4
6-4
6-4
6-4
6.6
Control register description and operation
6-4
6.7
Watchdog
6-5
6.8
Start-up and watchdog specifications
6-5
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6-1
XE8805/05A
6.1
•
•
•
•
•
•
Features
Power On Reset (POR)
External reset from the RESET pin
Programmable Watchdog timer reset
Programmable BusError reset
Sleep mode management
Programmable Port A input combination reset
6.2
Overview
The reset block is the reset manager. It handles the different reset sources and distributes them through the
system. It also controls the sleep mode of the circuit.
6.3
Register map
Pos.
7
RegSysCtrl
SleepEn
Rw
rw
Reset
0 resetcold
6
EnResPConf
rw
0 resetcold
5
EnBusError
rw
0 resetcold
4
EnResWD
rw
0 resetcold
-
r
0000
3–0
Function
enables Sleep mode
0: sleep mode is disabled
1: sleep mode is enabled
enables the resetpconf signal when the
resetglobal is active
0: resetpconf is disabled
1: resetpconf is enabled
enables reset from BusError
0: BusError reset source is disabled
1: BusError reset source is enabled
enables reset from Watchdog
0: Watchdog reset source is disabled
1: Watchdog reset source is enabled
this bit can not be set to 0 by SW
unused
Table 6-1. RegSysCtrl register.
Pos.
7
6
5
4
3
2
1
0
RegSysReset
Sleep
ResetBusError
ResetWD
ResetfromportA
ResPad
ResPadSleep
-
Rw
rw
r
rc
rc
rc
rc
rc
r
Reset
0 resetsystem
0
0 resetcold
0 resetcold
0 resetcold
0 resetcold
0 resetcold
0
Function
Sleep mode control (reads always 0)
unused
reset source was BusError
reset source was Watchdog
reset source was Port A combination
reset source was reset pad
reset source was reset pad in sleep mode
unused
Table 6-2. RegSysReset register
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6-2
XE8805/05A
Pos.
7–4
3
2
1
0
RegSysWD
WDKey[3]
WDCounter[3]
WDKey[2]
WDCounter[2]
WDKey[1]
WDCounter[1]
WDKey[0]
WDCounter[0]
Rw
r
w
r
w
r
w
r
w
r
Reset
0000
0 resetcold
0 resetcold
0 resetcold
0 resetcold
Function
unused
Watchdog Key bit 3
Watchdog counter bit 3
Watchdog Key bit 2
Watchdog counter bit 2
Watchdog Key bit 1
Watchdog counter bit 1
Watchdog Key bit 0
Watchdog counter bit 0
Table 6-3. RegSysWD register
6.4
Reset handling capabilities
There are 5 reset sources:
• Power On Reset (POR)
• External reset from the RESET pin
• Programmable Port A input combination
• Programmable watchdog timer reset
• Programmable BusError reset on processor access outside the allocated memory map
Another reset source is the bit Sleep in the RegSysReset register. This source is fully controlled by software and
is only used during the sleep mode.
Four internal reset signals are generated from these sources and distributed through the system:
• resetcold:
is asserted on POR
• resetsystem: is asserted when resetcold or any other enabled reset source is active
• resetpconf: is asserted when resetsystem is active and if the EnResPConf bit in the RegSysCtrl register
is set. This reset is generally used in the different ports. It allows to maintain the port
configuration unchanged while the rest of the circuit is reset.
• resetsleep:
is asserted when the circuit is in sleep mode
For the circuits XE8801A and XE8805A
(2) For the circuits XE8801 and XE8805
Table 6-4 shows a summary of the dependency of the internal reset signals on the various reset sources. In all the
tables describing the different registers, the reset source is indicated.
Internal reset signals
Asserted
reset source
resetsystem
POR
RESET pin (1)
RESET pin (2)
PortA input
Watchdog
BusError
Sleep
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
-
(1)
resetpconf
when
when
EnResPConf=0 EnResPConf=1
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
-
resetsleep
resetcold
Asserted
Asserted
Asserted
Asserted
Asserted
-
For the circuits XE8801A and XE8805A
(2) For the circuits XE8801 and XE8805
Table 6-4. Internal reset assertion as a function of the reset source.
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6-3
XE8805/05A
6.5
6.5.1
Reset source description
Power On Reset
The power on reset (POR) monitors the external supply voltage. It activates a reset on a rising edge of this supply
voltage. The reset is inactivated only if the internal voltage regulator has started up. No precise voltage level
detection is performed by the POR block.
6.5.2
RESET pin
The reset can be activated by applying a high input state on the RESET pin.
6.5.3
Programmable Port A input combination
A reset signal can be generated by Port A. See the description of the Port A for further information.
6.5.4
Watchdog reset
The Watchdog will generate a reset if the EnResetWD bit in the RegSysCtrl register has been set and if the
watchdog is not cleared in time by the processor. See chapter 6.7 describing the watchdog for further information.
6.5.5
BusError reset
The address space is assigned as shown in the register map of the product. If the EnBusError bit in the
RegSysCtrl register is set and a non-existant address is accessed by the software, a reset is generated.
6.5.6
Sleep mode
Entering the sleep mode will reset a part of the circuit. The reset is used to configure the circuit for correct wake-up
after the sleep mode. If the SleepEn bit in the RegSysCtrl register has been set, the sleep mode can be entered
by setting the bit Sleep in RegSysReset. During the sleep mode, the resetsleep signal is active. For detailed
information on the sleep mode, see the system documentation.
6.6
Control register description and operation
Two registers are dedicated for reset status and control, RegSysReset and RegSysCtrl. The bits Sleep, and
SleepEn are also located in those registers and are described in the chapter dedicated to the different operating
modes of the circuit (system block).
The RegSysReset register gives information on the source which generated the last reset. It can be read at the
beginning of the application program to detect if the circuit is recovering from an error or exception condition, or if
the circuit is starting up normally.
• when ResBusError is 1, a forbidden address access generated the reset.
• when ResWD is 1, the watchdog generated the reset.
• when ResPortA is 1, a PortA combination generated the reset.
• when ResPad is 1, a reset pin generated the reset.
• when ResPadSleep is 1, a reset pin in sleep mode generated the reset.
Note: If no bit is set to 1, the reset source was the internal POR.
Note: Several bits might be set or not, if the register was not cleared in between 2 reset occurrences. Write
any value in RegSysReset to clear it.
Note: When a reset pin wakes up the chip from the sleep mode, ResPad and ResPadSleep bits are equal
at 1.
The last bit concerns the sleep mode control (see system documentation for the sleep mode description).
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6-4
XE8805/05A
• when Sleep is set to 1, and SleepEn is 1, the sleep mode is entered. The bit always reads back a 0.
The RegSysCtrl register enables the different available reset sources and the sleep mode.
• EnResWD enables the reset due to the watchdog (can not be disabled once enabled).
• EnBusError enables the reset due to a bus error condition.
• EnResPConf enables the reset of the port configurations when reset by Port A, a Bus Error or the
watchdog.
• SleepEn unlocks the Sleep bit. As long as SleepEn is 0, the Sleep bit has no effect.
6.7
Watchdog
The watchdog is a timer which has to be cleared at least every 2 seconds by the software to prevent a reset being
generated by the timeout condition.
The watchdog can be enabled by software by setting the EnResWD bit in the RegSysCtrl register to 1. It can then
only be disabled by a power on reset.
The watchdog timer can be cleared by writing consecutively the values Hx0A and Hx03 to the RegSysWD register.
The sequence must strictly be respected to clear the watchdog.
In assembler code, the sequence to clear the watchdog is:
move AddrRegSysWD, #0x0A
move AddrRegSysWD, #0x03
Only writing Hx0A followed by Hx03 resets the WD. If some other write instruction is done to the RegSysWD
between the writing of the Hx0A and Hx03 values, the watchdog timer will not be cleared.
It is possible to read the status of the watchdog in the RegSysWD register. The watchdog is a 4 bit counter with a
count range between 0 and 7. The system reset is generated when the counter is reaching the value 8.
6.8
Start-up and watchdog specifications
At start-up of the circuit, the POR (power-on-reset) block generates a reset signal during tPOR. The circuit starts
software execution after this period (see system chapter). The POR is intended to force the circuit in a correct state
at start-up. For precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used.
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6-5
XE8805/05A
Symbol
Parameter
Min
Typ
Max
Unit
Comments
TPOR
POR reset duration
5
20
ms
TRESET
RESET pin reset duration
20
200
µs
3
TRESET
RESET pin reset duration
5
20
ms
4
Vbat_sl_M
Supply ramp up of MTP version
20
V/ms
1
Vbat_sl_R
Supply ramp up of ROM version
0.25
V/ms
1
2
s
2
WDtime
Watchdog timeout period
Table 6-5. Electrical and timing specifications
Note: 1) The Vbat_sl defines the minimum slope required on VBAT. Correct start-up of the circuit is not guaranteed
if this slope is too slow. In such a case, a delay has to be built using the RESET pin.
Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. The watchdog
takes its clock from the low prescaler. In case an external clock source is used, the RC oscillator must be enabled
also (EnRC=1 in RegSysClock). Otherwise, the watchdog is stopped (see the clock block documentation).
Note: 3) For the circuit versions XE8801 and XE8805. Gives the time the reset is active after the falling edge of the
RESET pin.
Note: 4) For the circuit versions XE8801A and XE8805A. Gives the time the reset is active after the falling edge of
the RESET pin.
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6-6
XE8805/05A
7 Clock Generator
7.1
Features
7-2
7.2
Overview
7-2
7.3
Register map
7-2
7.4
Interrupts and events map
7-3
7.5
7.5.1
7.5.2
7.5.3
Clock sources
RC oscillator
Xtal oscillator
External clock
7-4
7-4
7-6
7-7
7.6
Clock source selection
7-8
7.7
RegSysMisc Description
7-8
7.8
Prescalers
7-9
7.9
32 kHz frequency selector
7-9
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7-1
XE8805/05A
7.1
Features
•
•
•
7.2
3 available clock sources (RC oscillator, quartz oscillator and external clock).
2 divider chains: high-prescaler (8 bits) and low-prescaler (15 bits).
CPU clock disabling in halt mode.
Overview
The XE8805 chips can work on different clock sources (RC oscillator, quartz oscillator and external clock). The
clock generator block is in charge of distributing the necessary clock frequencies to the circuit. Figure 7-1
represents the functionality of the clock block.
The internal RC oscillator drives the high prescaler. This prescaler generates frequency divisions down to 1/256 of
its input frequency. A 32kHz clock is generated by enabling the quartz oscillator (if present in the product) or by
selecting the appropriate tap on the high prescaler. The low prescaler generates clock signals from 32kHz down to
1Hz. The clock source for the CPU can be selected from the RC oscillator, the external clock or the 32kHz clock.
7.3
Register map
pos.
7
RegSysClock
CpuSel
rw
rw
Reset
0 resetsleep
6
5
4
3
2
1
0
Extclk
EnExtClock
BiasRc
ColdXtal
ColdRC
EnableXtal
EnableRc
r
rw
rw
r
r
rw
rw
0 resetcold
0 resetcold
1 resetcold
1 resetsleep
1 resetsleep
0 resetsleep
1 resetsleep
function
Select speed for cpuck, 0=RC, 1=xtal or
external clock
External clock detected, 1=available
Enable for external clock, 1=enabled
Enable Rcbias (reduces start-up time of RC).
Xtal in start phase
RC in start phase
Enable Xtal oscillator, 0=disabled, 1=enabled
Enable RC oscillator, 0=disabled, 1=enabled
Table 7-1: RegSysClock register
pos.
7-4
3
2
1
RegSysMisc
-RCOnPA0
DebFast
OutputCkXtal
rw
r
rw
rw
rw
Reset
0000
0 resetsleep
0 resetsleep
0 resetsleep
0
OutputCpuCk
rw
0 resetsleep
Function
Unused
Start RC on PA[0], 0=disabled, 1=enabled
Debouncer clock speed, 0=256Hz, 1=8kHz
Output Xtal Clock on PB[3], 0=disabled,
1=enabled if EnXtal=1 else PB[3]=0
Output CPU clock on PB[2], 0=disabled,
1=enabled
Table 7-2: RegSysMisc register
pos.
7-1
0
RegSysPre0
-ResPre
rw
r
w1
r0
reset
0000000
0
Function
Unused
Write 1 to reset low prescaler, but always
reads 0
Table 7-3: RegSysPre0 register
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7-2
XE8805/05A
pos.
7-4
5
4
3
2
1
0
RegSysRcTrim1
-Reserved
RcFreqRange
RcFreqCoarse[3]
RcFreqCoarse[2]
RcFreqCoarse[1]
RcFreqCoarse[0]
rw
r
rw
rw
rw
rw
rw
rw
reset
00
0 resetcold
0 resetcold
0 resetcold
0 resetcold
0 resetcold
0 resetcold
Function
Unused
Reserved
Low/high freq. range (low=0)
RC coarse trim bit 3
RC coarse trim bit 2
RC coarse trim bit 1
RC coarse trim bit 0
Table 7-4: RegSysRCTrim1 register
pos.
7-6
5
4
3
2
1
0
RegSysRcTrim2
-RcFreqFine[5]
RcFreqFine[4]
RcFreqFine[3]
RcFreqFine[2]
RcFreqFine[1]
RcFreqFine[0]
Rw
r
rw
rw
rw
rw
rw
rw
reset
00
1 resetcold
0 resetcold
0 resetcold
0 resetcold
0 resetcold
0 resetcold
function
Unused
RC fine trim bit 5
RC fine trim bit 4
RC fine trim bit 3
RC fine trim bit 2
RC fine trim bit 1
RC fine trim bit 0
Table 7-5: RegSysRCTrim2 register
RegSysRcTrim1
RegSysRcTrim2
CkRc
to
CkRc/256
CkRc
RC
High prescaler
External
Clock
CkXtal
OSCIN
Xtal
0
0
1
1
CpuSel
0
Low prescaler
32kHz
to
1Hz
1
EnXtal and
not(ExtClk or EnExtClk)
CpuCk
Figure
7-1. Clock block structure
7.4
Interrupts and events map
Interrupt
IrqPre1
Interrupt source
Ck128Hz
IrqPre2
Ck1Hz
Mapping in the interrupt manager
RegIrqHig(6)
Mapping in the event manager
RegEvn(5)
RegIrqMid(3)
RegEvn(1)
Table 7-6: Interrupts and events map
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7-3
XE8805/05A
7.5
Clock sources
7.5.1
RC oscillator
7.5.1.1
Configuration
The RC oscillator is always turned on and selected for CPU and system operation at power-on reset and when
exiting sleep mode. It can be turned off after the Xtal (quartz oscillator) has been started, after selection of the
external clock or by entering sleep mode.
The RC oscillator has two frequency ranges: sub-MHz (100 kHz to 1 MHz) and above-MHz (1 MHz to 10 MHz).
Inside a range, the frequency can be tuned by software for coarse and fine adjustment. See registers
RegSysRcTrim1 and RegSysRcTrim2.
Bit EnableRC in register RegSysClock controls the propagation of the RC clock signal and the operation of the
oscillator. The user can stop the RC oscillator by resetting the bit EnableRC. Entering the sleep mode disables the
RC oscillator.
Note: Before turning off the RC oscillator, the cpusel bit in RegSysClock must be set to one.
Note: The RC oscillator bias can be maintained while the oscillator is switched off by setting the bit BiasRc in
RegSysClock. This allows a faster restart of the RC oscillator at the cost of increased power consumption when
the oscillator is disabled (see section 7.5.1.3).
7.5.1.2
RC oscillator frequency tuning
The RC oscillator frequency can be set using the bits in the RegSysRcTrim1 and RegSysRcTrim2 registers.
Figure 7-2 shows the nominal frequency of the RC oscillator as a function of these bits. The absolute value of the
frequency for a given register content may change by ±50% from chip to chip due to the tolerances on the
integrated capacitors and resistors. However, the modification of the frequency as a function of a modification of
the register content is fairly precise for frequencies below 2MHz. This means that the curves in Figure 7-2 can shift
up and down but that the slope remains unchanged.
The bit RcFreqRange modifies the oscillator frequency by a factor of 10. The upper curve in the figure
corresponds to RcFreqRange=1.
The RcFreqCoarse modifies the frequency of the oscillator by a factor (RcFreqCoarse+1). The figure represents
the frequency for 5 different values of the bits RcFreqCoarse: for each value the frequency is multiplied by 2.
Incrementing the RcFreqFine code increases the frequency by about 1.4%.
The frequency of the oscillator is therefor given by:
fRC=fRcmin⋅(1+9⋅RcFreqRange)⋅(1+RcFreqCoarse)⋅(1.014)RcFreqFine
with fRcmin the RC oscillator frequency if the registers are all 0. At higher frequencies, the frequency may deviate
from the value predicted by the equation.
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7-4
XE8805/05A
1E+08
RcFreqRange='1'
RcFreqRange='0'
1
11
1
00
0
0
1
0
00
1
11
1
00
00
0
00
00
11
11
11
00
RcFreqFine(5:0)
11
00
11
00
00
01
11
00
00
00
11
00
00
0
1
00
00
0
00
0
00
00
0
01
0
10
00
11
00
00
0
01
11
1
11
00
10
00
11
11
00
01
11
00
10
00
11
00
00
00
10
00
00
00
00
0
00
01
11
00
10
00
11
1
00
11
00
00
1
11
00
00
00
1
00
10
01
00
1E+05
0
00
1
11
0
00
00
00
11
00
00
11
00
00
10
01
11
11
10
1
11
11
00
11
01
1E+06
0
00
01
11
11
10
01
11
11
RcFreqFine(5:0)
00
Nominal RC oscillator frequency [Hz]
11
00
11
10
1E+07
00
RcFreqCoarse(3:0)
1E+04
0000
0001
0011
0111
1111
Figure 7-2. RC oscillator nominal frequency tuning.
7.5.1.3
RC oscillator specifications
symbol
fRCmin
RcFreqFine
RC_su
description
Lowest RC frequency
fine tuning step
startup time
PSRR @ DC
Supply voltage
dependence
Temperature
dependence
∆f/∆T
min
40
typ
80
1.4
30
3
TBD
TBD
0.1
max
120
2.0
50
5
unit
kHz
%
us
us
%/V
%/V
%/°C
Comments
Note 1
BiasRc=0
BiasRc=1
Note 2
Note 3
Table 7-7. RC oscillator specifications
Note 1: this is the frequency tolerance when all trimming codes are 0.
Note 2: frequency shift as a function of VBAT with normal regulator function.
Note 3: frequency shift as a function of VBAT while the regulator is short-circuited to VBAT.
The tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the
software DFLL (digital frequency locked loop) which uses the crystal oscillator as a reference frequency.
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7-5
XE8805/05A
7.5.2
Xtal oscillator
7.5.2.1
Xtal configuration
The Xtal operates with an external crystal of 32’768 Hz.
During Xtal oscillator start-up, the first 32768 cycles are masked. The two bits EnableXtal and ColdXtal in register
RegSysClock control the oscillator.
At power-on reset or during sleep mode, EnableXtal is reset and ColdXtal is set (Xtal oscillator is not selected at
start-up). The user can start Xtal oscillator by setting EnableXtal. When the Xtal oscillator starts, bit ColdXtal is
reset after 32768 cycles. Before ColdXtal is reset by the system, the Xtal frequency precision is not guaranteed.
The Xtal oscillator can be stopped by the user by resetting bit EnableXtal.
When the user enters into sleep mode, the Xtal is stopped.
When an external clock is detected (ExtClk = 1) or the EnExtClock is set 1, the EnableXtal bit can not be set to 1.
7.5.2.2
Xtal oscillator specifications
The crystal oscillator has been designed for a crystal with the specifications given in Table 7-8. The oscillator
precision can only be guaranteed for this crystal.
Symbol
Fs
CL
Rm
Cm
C0
Rmp
Q
Description
Resonance frequency
CL
for
nominal
frequency
Motional resistance
Motional capacitance
Shunt capacitance
Motional resistance of
6th overtone (parasitic)
Quality factor
Min
Typ
32768
8.2
Max
1.8
0.7
4
40
2.5
1.1
8
100
3.2
2.0
kΩ
fF
pF
kΩ
30k
50k
400k
-
15
Unit
Hz
pF
Comments
Table 7-8. Crystal specifications.
For safe operation, low power consumption and to meet the specified precision, careful board layout is required:
Keep lines OSCIN and OSCOUT short and insert a VSS line in between them.
Connect the crystal package to VSS.
No noisy or digital lines near OSCIN or OSCOUT.
Insert guards where needed.
Respect the board specifications of Table 7-9.
Symbol
Rh_oscin
Rh_oscout
Rh_oscin_oscout
Cp_oscin
Cp_oscout
Cp_oscin_oscout
Description
Resistance OSCIN-VSS
Resistance OSCOUT-VSS
Resistance OSCIN-OSCOUT
Capacitance OSCIN-VSS
Capacitance OSCOUT-VSS
Capacitance OSCIN-OSCOUT
Min
10
10
50
0.5
0.5
0.2
Typ
Max
3.0
3.0
1.0
Unit
MΩ
MΩ
MΩ
pF
pF
pF
Comments
Table 7-9. Board layout specifications.
The oscillator characteristics are given in Table 7-10. The characteristics are valid only if the crystal and board
layout meet the specifications above.
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7-6
XE8805/05A
Symbol
fXtal
St_xtal
Fstab
Description
Nominal frequency
Start-up time
Frequency deviation
Min
Typ
32768
1
-100
Max
2
300
Unit
Hz
s
ppm
Comments
Note 1
Table 7-10. Crystal oscillator characteristics.
Note 1. This gives the relative frequency deviation from nominal for a crystal with CL=8.2pF and within the
temperature range -40°C to 85°C. The crystal tolerance, crystal aging and crystal temperature drift are not included
in this figure.
7.5.3
External clock
7.5.3.1
External clock configuration
The user can provide an external clock instead of the internal oscillators. Only the CPU can use the external clock.
The external clock input pin is OSCIN.
The system is configured for external clock by bit EnExtClock in register RegSysClock.
When EnExtClock is set to 1, the external clock is detected after 4 pulses on pin OSCIN. The ExtClk bit shows
when the external clock is available.
Note: when using the external clock, the Xtal is not available.
7.5.3.2
External clock specification
The external clock has to satisfy the specifications in the table below. Correct behavior of the circuit can not be
guaranteed if the external clock signal does not respect the specifications below.
Symbol
FEXT
PW_1
PW_0
Description
External
frequency
Pulse 1 width
Pulse 0 width
Min
Typ
clock
Max
2
Unit
MHz
Comments
µs
µs
0.2
0.2
Table 7-11. External clock specifications.
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7-7
XE8805/05A
7.6
Clock source selection
There are three possible clock sources available for the CPU clock. The RC clock is always selected after powerup or after Sleep mode. The CPU clock selection is done with the bit CpuSel in RegSysClock (0= RC clock, 1= 32
kHz from Xtal if EnableXtal =1, ExtClk = 0 and EnExtClk = 0 else external clock).
Switching from one clock source to another is glitch free.
The next table summarizes the different clock configurations of the circuit:
Clock Sources
Clock targets
EnableRc
EnableXtal
Cpuck Note 1
EnExtClk
Mode
name
Sleep
Xtal
RC
0
0
0
0
0
1
0
1
0
Off
Off
RC
Off
Xtal
RC
Off
Off
RC
Off
Xtal
High presc.
RC + Xtal
0
1
1
RC
Xtal
RC
Xtal
External
RC
+
External
1
0
X
Off
External
Off
Off
1
1
X
RC
External
RC
High presc.
CpuSel=0
CpuSel=1
High
Prescaler
Clock
input
Low
Prescaler
Clock
input
Table 7-12: Table of clocking modes.
Note 1: The CPU clock can be divided by using the freq instruction (see coolrisc instruction set)
Switching from one clock source to another and stopping the unused clock source must be performed using 3
MOVE instructions to RegSysClock. First select the new clock source, secondly change the CpuSel bit and finally
stop the unused one.
7.7
RegSysMisc Description
The RCOnPA0 bit in RegSysMisc can be used to enable the RC oscillator on an event external to the circuit. If
RCOnPA0 is 1, the RC oscillator is enabled (EnableRC bit is set to 1) as soon as the value on port A pin PA[0] is
equal to 1. The port A pin can be debounced (see port A documentation).
Bit DebFast in the RegSysMisc register allows to chose the debouncer clock between 256Hz and 8kHz (DebFast
= 0 and DebFast = 1 respectively). The Debouncer clock is used to debounce PA inputs (see port A
documentation).
Bit OutputCkXtal allows to show the Xtal clock on PB[3]. The EnableXtal bit must be set to 1 else PB[3] equals 0
(see port B documentation to set up the port B).
Bit OutputCpuCk allows to show the CpuClock on PB[2] (see port B documentation).
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7-8
XE8805/05A
7.8
Prescalers
The clock generator block embeds two divider chains: the high prescaler and the low prescaler.
The high prescaler is made of an 8 stage dividing chain and the low prescaler of a 15 stage dividing chain.
Features:
• High prescaler can only be driven with RC clock (bit EnableRc have to be set, see Table 7-12).
• Low prescaler can be driven from the high prescaler or directly with the Xtal clock when bit EnableXtal is set to
1, bit EnExtClock is set to 0 and ExtClk is equal at 0.
• Bit ResPre in the RegSysPre0 register allows to reset synchronously the low prescaler, the low prescaler is
also automatically cleared when bit EnableXtal is set. Both dividing chains are reset asynchronously by the
resetsleep signal.
• Bit ColdXtal=1 indicates the Xtal is in its start up phase. It is active for 37268 Xtal cycles after setting
EnableXtal.
7.9
32 kHz frequency selector
A decoder is used to select from the high prescaler the frequency tap that is the closest to 32 kHz to operate the
low prescaler when the Xtal is not running. In this case, the RC oscillator frequency of ±50% will also be valid for
the low prescaler frequency outputs.
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7-9
XE8805/05A
8 IRQ - Interrupt handler
8.1
Features
8-2
8.2
Overview
8-2
8.3
Register map
8-2
© Semtech 2006
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8-1
XE8805/05A
8.1
Features
The XE8000 chips support 24 interrupt sources, divided into 3 levels of priority.
8.2
Overview
A CPU interruption is generated and memorized when an interrupt becomes active. The 24 interrupt sources are
divided into 3 levels of priority: High (8 interrupt sources), Mid (8 interrupt sources), and Low (8 interrupt sources).
Those 3 levels of priority are directly mapped to those supported by the CoolRisc® (IN0, IN1 and IN2; see
CoolRisc® documentation for more information).
RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags
are set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or
RegIrqEnLow is set) and a rising edge is detected on the corresponding interrupt source.
Once memorized, an interrupt flag can be cleared by writing a ‘1’ in the corresponding bit of RegIrqHig, RegIrqMid
or RegIrqLow. Writing a ‘0’ does not modify the flag. To definitively clear the interrupt, one has to clear the
CoolRisc interrupt in the CoolRisc status register. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number
of the highest priority interrupt set (its value is 0xFF when no interrupt is set). RegIrqIrq indicates the priority level
of the current interrupts. RegIrqIrq and RegIrqPriority ‘s values are dependent upon the memorized state of the
interrupts (as reflected in flags in RegIrqHig, RegIrqMid and RegIrqLow).
8.3
Register map
pos.
7
RegIrqHig
RegIrqHig[7]
6
RegIrqHig[6]
5
RegIrqHig[5]
4
RegIrqHig[4]
3
RegIrqHig[3]
2
RegIrqHig[2]
1
RegIrqHig[1]
0
RegIrqHig[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
interrupt #23 (high priority)
clear interrupt #23 when 1 is written
interrupt #22 (high priority)
clear interrupt #22 when 1 is written
interrupt #21 (high priority)
clear interrupt #21 when 1 is written
interrupt #20 (high priority)
clear interrupt #20 when 1 is written
interrupt #19 (high priority)
clear interrupt #19 when 1 is written
interrupt #18 (high priority)
clear interrupt #18 when 1 is written
interrupt #17 (high priority)
clear interrupt #17 when 1 is written
interrupt #16 (high priority)
clear interrupt #16 when 1 is written
Table 8-1: RegIrqHig
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8-2
XE8805/05A
pos.
7
RegIrqMid
RegIrqMid[7]
6
RegIrqMid[6]
5
RegIrqMid[5]
4
RegIrqMid[4]
3
RegIrqMid[3]
2
RegIrqMid[2]
1
RegIrqMid[1]
0
RegIrqMid[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
interrupt #15 (mid priority)
clear interrupt #15 when 1 is written
interrupt #14 (mid priority)
clear interrupt #14 when 1 is written
interrupt #13 (mid priority)
clear interrupt #13 when 1 is written
interrupt #12 (mid priority)
clear interrupt #12 when 1 is written
interrupt #11 (mid priority)
clear interrupt #11 when 1 is written
interrupt #10 (mid priority)
clear interrupt #10 when 1 is written
interrupt #9 (mid priority)
clear interrupt #9 when 1 is written
interrupt #8 (mid priority)
clear interrupt #8 when 1 is written
Table 8-2: RegIrqMid
pos.
7
RegIrqLow
RegIrqLow[7]
6
RegIrqLow[6]
5
RegIrqLow[5]
4
RegIrqLow[4]
3
RegIrqLow[3]
2
RegIrqLow[2]
1
RegIrqLow[1]
0
RegIrqLow[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
interrupt #7 (low priority)
clear interrupt #7 when 1 is written
interrupt #6 (low priority)
clear interrupt #6 when 1 is written
interrupt #5 (low priority)
clear interrupt #5 when 1 is written
interrupt #4 (low priority)
clear interrupt #4 when 1 is written
interrupt #3 (low priority)
clear interrupt #3 when 1 is written
interrupt #2 (low priority)
clear interrupt #2 when 1 is written
interrupt #1 (low priority)
clear interrupt #1 when 1 is written
interrupt #0 (low priority)
clear interrupt #0 when 1 is written
Table 8-3: RegIrqLow
pos.
7
6
5
4
3
2
1
0
RegIrqEnHig
RegIrqEnHig[7]
RegIrqEnHig[6]
RegIrqEnHig[5]
RegIrqEnHig[4]
RegIrqEnHig[3]
RegIrqEnHig[2]
RegIrqEnHig[1]
RegIrqEnHig[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
1= enable interrupt #23
1= enable interrupt #22
1= enable interrupt #21
1= enable interrupt #20
1= enable interrupt #19
1= enable interrupt #18
1= enable interrupt #17
1= enable interrupt #16
Table 8-4: RegIrqEnHig
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8-3
XE8805/05A
pos.
7
6
5
4
3
2
1
0
RegIrqEnMid
RegIrqEnMid[7]
RegIrqEnMid[6]
RegIrqEnMid[5]
RegIrqEnMid[4]
RegIrqEnMid[3]
RegIrqEnMid[2]
RegIrqEnMid[1]
RegIrqEnMid[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
1= enable interrupt #15
1= enable interrupt #14
1= enable interrupt #13
1= enable interrupt #12
1= enable interrupt #11
1= enable interrupt #10
1= enable interrupt #9
1= enable interrupt #8
Table 8-5: RegIrqEnMid
pos.
7
6
5
4
3
2
1
0
RegIrqEnLow
RegIrqEnLow[7]
RegIrqEnLow[6]
RegIrqEnLow[5]
RegIrqEnLow[4]
RegIrqEnLow[3]
RegIrqEnLow[2]
RegIrqEnLow[1]
RegIrqEnLow[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
1= enable interrupt #7
1= enable interrupt #6
1= enable interrupt #5
1= enable interrupt #4
1= enable interrupt #3
1= enable interrupt #2
1= enable interrupt #1
1= enable interrupt #0
Table 8-6: RegIrqEnLow
pos.
7-0
RegIrqPriority
RegIrqPriority
rw
r
reset
11111111
resetsystem
function
code of highest priority set
Table 8-7: RegIrqPriority
pos.
7-3
2
RegIrqIrq
IrqHig
rw
r
r
Reset
00000
0 resetsystem
1
IrqMid
r
0 resetsystem
0
IrqLow
r
0 resetsystem
function
unused
one or more high priority interrupt is
set
one or more mid priority interrupt is
set
one or more low priority interrupt is
set
Table 8-8: RegIrqIrq
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8-4
XE8805/05A
9 Event Handler
9.1
Features
9-2
9.2
Overview
9-2
9.3
Register map
9-2
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9-1
XE8805/05A
9.1
Features
The XE8000 chips support 8 event sources, divided into 2 levels of priority.
9.2
Overview
A CPU event is generated and memorized when an event source becomes active. The 8 event sources are divided
into 2 levels of priority: High (4 event sources) and Low (4 event sources). Those 2 levels of priority are directly
mapped to those supported by the CoolRisc (EV0 and EV1; see CoolRisc documentation for more information).
RegEvn is an 8-bit register containing flags for the event sources. Those flags are set when the event is enabled
(i.e. if the corresponding bit in the registers RegEvnEn is set) and a rising edge is detected on the corresponding
event source.
Once memorized, writing a ‘1’ in the corresponding bit of RegEvn clears an event flag. Writing a ‘0’ does not
modify the flag. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of event service software. RegEvnPriority contains the number
of the highest priority event set (its value is 0xFF when no event is set). RegEvnEvn indicates the priority level of
the current interrupts. RegEvnEvn and RegEvnPriority ‘s values are dependent upon the memorized state of the
events (as reflected in flags in RegEvn).
9.3
Register map
pos.
7
RegEvn
RegEvn[7]
6
RegEvn[6]
5
RegEvn[5]
4
RegEvn[4]
3
RegEvn[3]
2
RegEvn[2]
1
RegEvn[1]
0
RegEvn[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
event #7 (high priority)
clear event #7 when written 1
event #6 (high priority)
clear event #6 when written 1
event #5 (high priority)
clear event #5 when written 1
event #4 (high priority)
clear event #4 when written 1
event #3 (low priority)
clear event #3 when written 1
event #2 (low priority)
clear event #2 when written 1
event #1 (low priority)
clear event #1 when written 1
event #0 (low priority)
clear event #0 when written 1
Table 9-1: RegEvn
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9-2
XE8805/05A
pos.
7
6
5
4
3
2
1
0
RegEvnEn
RegEvnEn[7]
RegEvnEn[6]
RegEvnEn[5]
RegEvnEn[4]
RegEvnEn[3]
RegEvnEn[2]
RegEvnEn[1]
RegEvnEn[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
function
1= enable event #7
1= enable event #6
1= enable event #5
1= enable event #4
1= enable event #3
1= enable event #2
1= enable event #1
1= enable event #0
Table 9-2: RegEvnEn
pos.
7-0
RegEvnPriority
RegEvnPriority
rw
r
reset
11111111
resetsystem
function
code of highest event set
Table 9-3: RegEvnPriority
pos.
7-2
1
0
RegEvnEvn
EvnHig
EvnLow
rw
r
r
r
reset
00000
0 resetsystem
0 resetsystem
function
unused
one or more high priority event is set
one or more low priority event is set
Table 9-4: RegEvnEvn
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9-3
XE8805/05A
10 Low Power RAM
10.1
Features
10-2
10.2
Overview
10-2
10.3
Register map
10-2
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10-1
XE8805/05A
10.1 Features
•
Low power RAM locations.
10.2 Overview
In order to save power consumption, 8 8-bit registers are provided in page 0. These memory locations should be
reserved for often-updated variables. Accessing these register locations requires much less power than the other
general purpose RAM locations.
10.3 Register map
pos.
7-0
Reg00
Reg00
rw
rw
reset
XXXXXXXX
function
low-power data memory
Table 10-1: Reg00
pos.
7-0
Reg01
Reg01
rw
rw
reset
XXXXXXXX
function
low-power data memory
Table 10-2: Reg01
pos.
7-0
Reg02
Reg02
rw
rw
reset
XXXXXXXX
function
low-power data memory
Table 10-3: Reg02
pos.
7-0
Reg03
Reg03
rw
rw
reset
XXXXXXXX
function
low-power data memory
Table 10-4: Reg03
pos.
7-0
Reg04
Reg04
rw
rw
reset
XXXXXXXX
function
low-power data memory
Table 10-5: Reg04
pos.
7-0
Reg05
Reg05
rw
rw
reset
XXXXXXXX
function
low-power data memory
Table 10-6: Reg05
pos.
7-0
Reg06
Reg06
rw
rw
¨reset
XXXXXXXX
function
low-power data memory
Table 10-7: Reg06
pos.
7-0
Reg07
Reg07
rw
rw
reset
XXXXXXXX
function
low-power data memory
Table 10-8: Reg07
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10-2
XE8805/05A
11 Port A
11.1
Features
11-2
11.2
Overview
11-2
11.3
Register map
11-3
11.4
Interrupts and events map
11-3
11.5
Port A (PA) Operation
11-4
11.6
Port A electrical specification
11-5
© Semtech 2006
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11-1
XE8805/05A
11.1 Features
•
•
•
•
•
•
•
•
Input port, 8 bits wide
Each bit can be set individually for debounced or direct input
Each bit can be set individually for pull-up or not
Each bit is an interrupt request source on the rising or falling edge
A system reset can be generated on an input pattern
PA[0] and PA[1] can generate two events for the CPU, individually maskable
PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM (product dependent)
PA[0] can be used to enable the RC oscillator
11.2 Overview
Port A is a general purpose 8 bit wide digital input port, with interrupt capability. Figure 11-1 shows its structure.
Port A
VBat
8
RegPAPullup
8
RegPADebounce
8x
debounce
8
0
RegPACtrl
8
RegPAIn
8
1
RegPAEdge
1
0
RC
1
DebFast
(RegSysMisc(2))
8
interrupts
0
events
8x
cntclocks
256 Hz
8 kHz
8
8
RegPARes1
RegPARes0
1
11
PAReset[x]
10
01
0
resetfromporta
00
8x
Figure 11-1:structure of Port A
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11-2
XE8805/05A
11.3 Register map
There are six registers in the Port A (PA), namely RegPAIn, RegPADebounce, RegPAEdge, RegPAPullup,
RegPARes0 and RegPARes1. Table 11-1 to Table 11-6 show the mapping of control bits and functionality.
pos.
7:0
RegPAIn
PAIn[7:0]
rw
r
reset
description
pad PA[7] to PA[0] input value
Table 11-1: RegPAIn
pos.
7:0
RegPADebounce
rw
PADebounce[7:0]
rw
reset
description
PA[7] to PA[0]
1: debounce enabled
0: debounce disabled
00000000
resetpconf
Table 11-2: RegPADebounce
pos.
7:0
RegPAEdge
PAEdge[7:0]
rw
rw
reset
description
PA[7] to PA[0] edge configuration
0: positive edge
1: negative edge
00000000
resetsystem
Table 11-3: RegPAEdge
pos.
7:0
RegPAPullup
PAPullup[7:0]
rw
rw
reset
description
PA[7] to PA[0] pullup enable
0: pullup disabled
1: pullup enabled
00000000
resetpconf
Table 11-4: RegPAPullup
pos.
RegPARes0
7:0
PARes0[7:0]
rw
rw
Reset
00000000
resetsystem
description
PA[7] to PA[0] reset configuration
Table 11-5: RegPARes0
pos.
7:0
RegPARes1
PARes1[7:0]
rw
rw
reset
00000000
resetsystem
Description
PA[7] to PA[0] reset configuration
Table 11-6: RegPARes
11.4 Interrupts and events map
Interrupt source
pa_irqbus[5]
pa_irqbus[4]
pa_irqbus[1]
pa_irqbus[0]
pa_irqbus[7]
pa_irqbus[6]
pa_irqbus[3]
pa_irqbus[2]
Default mapping in
the interrupt manager
RegIrqMid[5]
RegIrqMid[4]
RegIrqMid[1]
RegIrqMid[0]
RegIrqLow[7]
RegIrqLow[6]
RegIrqLow[3]
RegIrqLow[2]
Default mapping in the
event manager
RegEvn[4]
RegEvn[0]
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11-3
XE8805/05A
11.5 Port A (PA) Operation
The Port A input status (debounced or not) can be read from RegPAin.
Debounce mode:
Each bit in Port A can be individually debounced by setting the corresponding bit in RegPADebounce. After reset,
the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if
the input value is identical at two consecutive sampling on the rising edge of the selected clock. Selection of the
clock is done by the bit DebFast in Register RegSysMisc (see clock block documentation for more precision on
the frequency).
DebFast
Clock filter
0
256 Hz
1
8 kHz
Table 11-7: debounce frequency selection
Input
CkDebounce
1
1
2
1
1
2
Debounced
Figure 11-2: digital debouncer
Pull-ups:
When the corresponding bit in RegPAPullup is set to 0, the inputs are floating (pull-up resistors are disconnected).
When the corresponding bit in RegPAPullup is set to 1, a pull-up resistor is connected to the input pin. Port A
starts up with the pull-up resistors disconnected.
Port A as an interrupt source:
Each Port A input is an interrupt request source and can be set on rising or falling edge with the corresponding bit
in RegPAEdge. After reset, the rising edge is selected for interrupt generation by default. The interrupt source can
be debounced by setting register RegPADebounce.
Note: care must be taken when modifying RegPAEdge because this register performs an edge selection. The
change of this register may result in a transition which may be interpreted as a valid interruption.
Port A as an event source:
The interrupt signals of the pins PA[0] and PA[1] are also available as events on the event controller.
Port A as a clock source (product dependent):
Images of the PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the
counter/timer/PWM peripheral (see the counter block documentation for more information).
Port A as a reset source:
Port A can be used to generate a system reset by placing a predetermined word on Port A externally. The reset is
built using a logical and of the 8 PARes[x] signals:
resetfromportA = PAReset[7] AND PAReset[6] AND PAReset[5] AND ... AND PAReset[0]
PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected
for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 11-8.
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11-4
XE8805/05A
PARes1[x]
0
0
1
1
PARes0[x]
0
1
0
1
PAReset[x]
0
PA[x]
not(PA[x])
1
Table 11-8: Selection bits for reset signal
A reset from Port A can be inhibited by placing a 0 on both PARes1[x] and PARes0[x] for at least 1 pin. Setting
both PARes1[x] and PARes0[x] to 1, makes the reset independent of the value on the corresponding pin. Setting
both registers to hFF, will reset the circuit independent from the Port A input value. This makes it possible to do a
software reset.
Note: depending of the value of PA[0] to PA[7], the change of RegPARes0 and RegPARes1 can cause a reset.
Therefore it is safe to have always one (RegPARes0[x], RegPARes1[x]) equal to ‘00’ during the setting operations.
Port A as a RC enable:
PA[0] can be used to enable the RC oscillator. When RCOnPA0 bit in RegSysMisc is set to 1 and the value of
PA[0] (debounced or not) is equal to 1, the EnRc bit in RegSysClock is automatically set to 1.
11.6 Port A electrical specification
Sym
VINH
VINL
RPU
Cin
description
Input high voltage
Input low voltage
Pull-up resistance
Input capacitance
min
0.7*VBAT
VSS
20
typ
50
3.5
max
VBAT
0.2*VBAT
80
unit Comments
V
VBAT≥2.4V
V
VBAT≥2.4V
kΩ
pF
Note 1
Note 1: this value is indicative only since it depends on the package.
Table 11-9. Port A electrical specification.
© Semtech 2006
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11-5
XE8805/05A
12 Port B
12.1
Features
12-2
12.2
Overview
12-2
12.3
Register map
12-2
12.4
Port B capabilities
12-3
12.5
12.5.1
12.5.2
Port B analog capability
Port B analog configuration
Port B analog function specification
12-3
12-3
12-4
12.6
Port B function capability
12-4
12.7
12.7.1
12.7.2
Port B digital capabilities
Port B digital configuration
Port B digital function specification
12-5
12-5
12-6
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12-1
XE8805/05A
12.1 Features
• Input / output / analog port, 8 bits wide
• Each bit can be set individually for input or output
• Each bit can be set individually for open-drain or push-pull
• Each bit can be set individually for pull-up or not (for input or open-drain mode)
• In open-drain mode, pull-up is not active when corresponding pad is set to zero
• The 8 pads can be connected by pairs to four internal analog lines (4 line analog bus)
• Two internal freq. (cpuck and 32 kHz) can be output on PB[2] and PB[3]
Product dependant:
• Two PWM signal can be output on pads PB[0] and PB[1]
• The synchronous serial interface (USRT) uses pads PB[5], PB[4]
• The UART interface uses pads PB[6] and PB[7] for Tx and Rx
12.2 Overview
Port B is a multi-purpose 8 bit Input/output port. In addition to digital functions, all pins can be used for analog
signals. All port terminals can be selected by pairs as digital input or output or as analog to share one of four
possible analog lines.
12.3 Register map
Pos.
7–0
RegPBOut
PBOut[7-0]
rw
rw
reset
description in digital mode
0 resetpconf
Pad PB[7-0] output value
description in analog mode
Analog bus selection for pad PB[7-0]
Table 12-1: RegPBOut
RegPBIn
Pos.
7–0
PBIn[7-0]
rw
reset
description in digital mode
rw
Pad PB[7-0] input status
description in analog mode
Unused
Table 12-2: RegPBIn
RegPBDir
Pos.
7–0
PBDir [7-0]
rw
rw
reset
description in digital mode
0 resetpconf
Pad PB[7-0] direction (0=input)
description in analog mode
Analog bus selection for pad PB[7-0]
Table 12-3: RegPBDir
Pos.
7–0
RegPBOpen
PBOpen[7-0]
rw
rw
reset
description in digital mode
0 resetpconf
Pad PB[7-0] open drain (1 = open
drain)
description in analog mode
Unused
Table 12-4: RegPBOpen
Pos.
7 –0
RegPBPullup
PBPullup[7]
rw
rw
reset
description in digital mode
0 resetpconf
Pull-up for pad PB[7-0] (1=active)
description in analog mode
Connect pad PB[7-0] on selected ana
bus
Table 12-5: RegPBPullup
Pos.
7–4
3
2
1
0
RegPBAna
-PBAna [3]
PBAna [2]
PBAna [1]
PBAna [0]
rw
r
rw
rw
rw
rw
reset
0000
0 resetpconf
0 resetpconf
0 resetpconf
0 resetpconf
description in digital mode
Unused
Set PB[7:6] in analog mode
Set PB[5:4] in analog mode
Set PB[3:2] in analog mode
Set PB[1:0] in analog mode
description in analog mode
Unused
Set PB[7:6] in analog mode
Set PB[5:4] in analog mode
Set PB[3:2] in analog mode
Set PB[1:0] in analog mode
Table 12-6: RegPBAna
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Note: Depending on the status of the EnResPConf bit in RegSysCtrl, the reset conditions of the registers are
different. See the reset block documentation for more details on the resetpconf signal.
12.4 Port B capabilities
Port B
name
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
usage (priority)
functions
(medium)
uart Rx
uart Tx
usrt S1
usrt S0
32 kHz
clock CPU
PWM1 Counter C (C+D)
PWM0 Counter A (A+B)
analog
(high)
analog
analog
analog
analog
digital
(low) (default)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 12-7: Different Port B functionality
Table 12-7 shows the different usage that can be made of the port B with the order of priority. If a pair of pins is
selected to be analog, it overwrites the function and digital set-up. If the pin is not selected as analog, but a
function is enabled, it overwrites the digital set-up. If neither the analog nor function are selected for a pin, it is used
as an ordinary digital I/O. This is the default configuration at start-up.
12.5 Port B analog capability
12.5.1
Port B analog configuration
Port B terminals can be attached to a 4 line analog bus by setting the PBAna[x] bits to 1 in the RegPBAna
register.
The other registers then define the connection of these 4 analog lines to the different pads of Port B. This can be
used to implement a simple LCD driver or A/D converter. Analog switching is available only when the circuit is
powered with sufficient voltage (see specification below). Below the specified supply voltage, only voltages that are
close to VSS or VBAT can be switched.
When PBAna[x] is set to 1, a pair of Port B terminals is switched from digital I/O mode to analog mode. The usage
of the registers RegPBPullup, RegPBOut and RegPBDir define the analog configuration (see Table 12-8).
When PBAna[x] = 1, then PBPullup[x] connects the pin to the analog bus. PBDir[x] and PBPOut[x] select which
of the 4 analog lines is used. For odd values of x, the selection bits are in the register RegPBOut (see Table 12-8).
For even values of x, the selection bits are in the register RegPBDir (see Table 12-9).
if x is odd, PBOut[x, x-1]
PBPullup[x]
PB[x] selection on
00
01
10
11
XX
1
1
1
1
0
analog line 0
analog line 1
analog line 2
analog line 3
High impedance
Table 12-8: Selection of the analog lines for PB[x] when x is odd and PBAna[x] = 1
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if x is even, PBDir[x+1, x]
PBPullup[x]
PB[x] selection on
00
01
10
11
XX
1
1
1
1
0
analog line 0
analog line 1
analog line 2
analog line 3
High impedance
Table 12-9: Selection of the analog lines for PB[x] when x is even and PBAna[x] = 1
Example:
Set the pads PB[2] and PB[3] on the analog line 3. (the values X depend on the configuration of others
pads)
- apply high impedance in the analog mode (move RegPBPullup,#0bXXXX00XX)
- go to analog mode (move RegPBAna,#0bXXXXXX1X)
- select the analog line3 (move RegPBDir,#0bXXXX11XX and move RegPBOut,#0bXXXX11XX)
- connect the analog line to the pins (move RegPBPullup,#0bXXXX11XX)
12.5.2
Port B analog function specification
The table below defines the on-resistance of the switches between the pin and the analog bus for different
conditions. The series resistance between 2 pins of Port B connected to the same analog line is twice the
resistance given in the table.
sym
Ron
Ron
Cin
Cin
description
switch resistance
switch resistance
input capacitance (off)
input capacitance (on)
min
typ
3.5
4.5
max
11
15
unit
kΩ
kΩ
pF
pF
Comments
Note 1
Note 2
Note 3
Note 4
Table 12-10. Analog input specifications.
Note 1: This is the series resistance between the pad and the analog line in 2 cases
1. VBAT ≥ 2.4V and the VMULT peripheral is present on the circuit and enabled.
2. VBAT ≥ 3.0V and the VMULT peripheral is not present on the circuit.
Note 2: This is the series resistance in case VBAT ≥ 2.8V and the peripheral VMULT is not present on the circuit.
Note 3: This is the input capacitance seen on the pin when the pin is not connected to an analog line. This value is
indicative only since it is product and package dependent.
Note 4: This is the input capacitance seen on the pin when the pin is connected to an analog line and no other pin
is connected to the same analog line. This value is indicative only since it is product and package dependent.
12.6 Port B function capability
The Port B can be used for different functions implemented by other peripherals. The description below is
applicable only in so far the circuit contains these peripherals.
When the counters are used to implement a PWM function (see the documentation of the counters), the PB[0] and
PB[1] terminals are used as outputs (PB[0] is used if CntPWM0 in RegCntConfig1 is set to 1, PB[1] is used if
CntPWM1 in RegCntConfig1 is set to 1) and the PWM generated values overwrite the values written in
RegPBout. However, PBDir(0) and PBDir(1) are not automatically overwritten and have to be set to 1.
If OutputCkXtal is set in RegSysMisc, the Xtal clock is output on PB[3] (EnableXtal in RegSysClock must be set
to 1). This overrides the value contained in PBOut(3). However, PBDir(3) must be set to 1. The duty cycle of the
clock signal is about 50%.
Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value
contained in PBOut(2). However, PBDir(2) must be set to 1.
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The frequency of the CPU clock depends on the selection of the CpuSel bit in the RegSysClock register (see
clock_gen_ff).
Pins PB[5] and PB[4] can be used for S1 and S0 of the USRT (see USRT documentation) when the UsrtEnable bit
is set in RegUsrtCtrl. The PB[5] and PB[4] then become open-drain. This overrides the values contained in
PBOpen(5:4), PBOut(5:4) and PBDir(5:4). If there is no external pull-up resistor on these pins, internal pull-ups
should be selected by setting PBPullup(5:4). When S0 is an output, the pin PB[4] takes the value of UsrtS0 in
RegUrstS0. When S1 is an output, the pin PB[5] takes the value of UsrtS1 in RegUrstS1.
Pins PB[6] and PB[7] can be used by the UART (see UART documentation). When UartEnTx in RegUartCtrl is set
to 1, PB[6] is used as output signal Tx. When UartEnRx in RegUartCtrl is set to 1, PB[7] is used as input signal
Rx. This overrides the values contained in PBOut(7:6) and PBDir(7:6).
12.7 Port B digital capabilities
12.7.1
Port B digital configuration
The direction of each bit within Port B (input only or input/output) can be individually set using the RegPBDir
register. If PBDir[x] = 1, both the input and output buffer are active on the corresponding Port B. If PBDir[x] = 0,
the corresponding Port B pin is an input only and the output buffer is in high impedance. After reset (resetpconf)
Port B is in input only mode (PBDir[x] are reset to 0).
The input values of Port B are available in RegPBIn (read only). Reading is always direct - there is no debounce
function in Port B. In case of possible noise on input signals, a software debouncer with polling or an external
hardware filter have to be realized. The input buffer is also active when the port is defined as output and allows to
read back the effective value on the pin.
Data stored in RegPBOut are output at Port B if PBDir[x] is 1. The default value after reset is low (0).
When a pin is in output mode (PBDir[x] is set to 1), the output can be a conventional CMOS (Push-Pull) or a Nchannel Open-drain, driving the output only low. By default, after reset (resetpconf) the PBOpen[x] in RegPBOpen
is cleared to 0 (push-pull). If PBOpen[x] in RegPBOpen is set to 1 then the internal P transistor in the output buffer
is electrically removed and the output can only be driven low (PBOut[x]=0). When PBOut[x]=1, the pin is high
Impedance. The internal pull-up or an external pull-up resistor can be used to drive the pin high.
Note: Because the P transistor actually exists (this is not a real Open-drain output) the pull-up range is limited to
VDD + 0.2V (avoid forward bias the P transistor / diode).
Each bit can be set individually for pull-up or not using register RegPBPullup. Input is pulled up when its
corresponding bit in this register is set to 1. Default status after (resetpconf) is 0, which means without pull up. To
limit power consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an Nchannel open-drain output with the pad set to 1. In the other cases (push-pull output or open-drain output driven
low), the pull up resistors are disabled independent of the value in RegPBPullup.
After power-on reset, the Port B is configured as an input port without pull-up.
The input buffer is always active, except in analog mode. This means that the Port B input should be a valid digital
value at all times unless the pin is set in analog mode. Violating this rule may lead to higher power consumption.
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12-5
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12.7.2
Sym
VINH
VINL
VOH
Port B digital function specification
description
Input high voltage
Input low voltage
Output high voltage
min
0.7*VBAT
VSS
VBAT-0.4
VOL
Output low voltage
VSS
RPU
Cin
Pull-up resistance
Input capacitance
20
typ
max
VBAT
0.2*VBAT
VBAT
VSS+0.4
50
3.5
80
unit Comments
V
VBAT≥2.4V
V
VBAT≥2.4V
V
VBAT=1.2V, IOH =0.3mA
VBAT=2.4V, IOH =5.0mA
VBAT=4.5V, IOH =8.0mA
V
VBAT=1.2V, IOL =0.3mA
VBAT=2.4V, IOL
=12.0mA
VBAT=4.5V, IOL
=15.0mA
kΩ
pF
Note 1
Note 1: this value is indicative only since it depends on the package.
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13 Port C
13.1
Features
13-2
13.2
Overview
13-2
13.3
Port C (PC) Operation
13-2
13.4
Register map
13-2
13.5
Port C electrical specification
13-3
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13-1
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13.1 Features
•
•
Input / output port, 8 bits wide
Each bit can be set individually for input or output
13.2 Overview
Port C (PC) is a general purpose 8 bit input/output digital port.
Figure 13-1 shows its structure.
Port C
8
RegPCOut
8
RegPCDir
8
RegPCIn
Figure 13-1: structure of Port C
13.3 Port C (PC) Operation
The direction of each bit within Port C (input or output) can be individually set by using the RegPCDir register. If
PCDir[x] = 1, the corresponding Port C pin becomes an output. After reset, Port C is in input mode (PCDir[x] are
reset to 0).
Output mode:
Data is stored in RegPCOut prior to output at Port C.
Input mode:
The status of Port C is available in RegPCIn (read only). Reading is always direct - there is no digital debounce
function associated with Port C. In case of possible noise on input signals, a software debouncer or an external
filter must be realized.
By default after reset, Port C is configured as an input port.
13.4 Register map
There are three registers in the Port C (PC), namely RegPCIn, RegPCOut and RegPCDir. Table 13-1 to Table
13-3 show the mapping of control bits and functionality of these registers.
Pos.
7-0
RegPCIn
PCIn
Rw
r
Reset
-
Description
pad PC input value
Table 13-1. RegPCIn
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Pos.
7-0
RegPCOut
PCOut
Rw
rw
Reset
0 resetpconf
Description
pad PC output value
Rw
rw
Reset
0 resetpconf
Description
pad PC direction (0=input)
Table 13-2. RegPCOut
Pos.
7-0
RegPCDir
PCDir
Table 13-3. RegPCDir
13.5 Port C electrical specification
Sym
VINH
VINL
VOH
description
Input high voltage
Input low voltage
Output high voltage
min
0.7*VBAT
VSS
VBAT-0.4
VOL
Output low voltage
VSS
Cin
Input capacitance
typ
max
VBAT
0.2*VBAT
VBAT
VSS+0.4
3.0
unit Comments
V
VBAT≥2.4V
V
VBAT≥2.4V
V
VBAT=1.2V, IOH =0.3mA
VBAT=2.4V, IOH =5.0mA
VBAT=4.5V, IOH =8.0mA
V
VBAT=1.2V, IOL =0.3mA
VBAT=2.4V, IOL
=12.0mA
VBAT=4.5V, IOL
=15.0mA
pF
Note 1
Note 1: this value is indicative only since it depends on the package.
Table 13-4. Port C electrical specification
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14 UART
14.1
Features
14-2
14.2
Overview
14-2
14.3
Registers map
14-2
14.4
Interrupts map
14-3
14.5
14.5.1
14.5.2
Uart baud rate selection
Uart on the RC oscillator
Uart on the crystal oscillator
14-3
14-3
14-4
14.6
14.6.1
14.6.2
14.6.3
Function description
Configuration bits
Transmission
Reception
14-4
14-4
14-5
14-5
14.7
Interrupt or polling
14-6
14.8
Software hints
14-7
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14.1 Features
•
•
•
•
•
•
•
•
•
•
Full duplex operation with buffered receiver and transmitter.
Internal baud rate generator with 12 programmable baud rates (300 - 115200).
7 or 8 bits word length.
Even, odd, or no-parity bit generation and detection
1 stop bit
Error receive detection: Start, Parity, Frame and Overrun
Receiver echo mode
2 interrupts (receive full and transmit empty)
Enable receive and/or transmit
Invert pad Rx and/or Tx
14.2 Overview
The UART pins are PB[7], which is used as Rx - receive and PB[6] as Tx - transmit.
14.3 Registers map
pos.
7
6
5-3
2
1
0
RegUartCmd
SelXtal
UartEnRx2
UartRcSel(2:0)
UartPM
UartPE
UartWL
rw
rw
rw
rw
rw
rw
rw
Reset
0 resetsystem
0 resetsystem
000 resetsystem
0 resetsystem
0 resetsystem
1 resetsystem
Description
Select input clock: 0 = RC, 1 = xtal
Enable Uart Reception
RC prescaler selection
Select parity mode: 0 = odd, 1 = even
Enable parity: 1 = with parity, 0 = no parity
Select word length: 1 = 8 bits, 0 = 7 bits
Table 14-1: RegUartCmd
Pos.
7
RegUartCtrl
UartEcho
rw
rw
reset
0 resetsystem
6
5
4
3
2-0
UartEnRx1
UartEnTx
UartXRx
UartXTx
UartBR(2:0)
rw
rw
rw
rw
rw
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
101 resetsystem
Description
Enable echo mode:
1 = echo Rx->Tx, 0 = no echo
Enable uart reception
Enable uart transmission
Invert pad Rx
Invert pad Tx
Select baud rate
Table 14-2: RegUartCtrl
pos.
7-0
RegUartTx
UartTx
rw
rw
reset
00000000
resetsystem
Description
Data to be sent
Table 14-3: RegUartTx
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pos.
7-2
1
0
RegUartTxSta
UartTxBusy
UartTxFull
rw
r
r
r
reset
000000
0 resetsystem
0 resetsystem
description
Unused
Uart busy transmitting
RegUartTx full
Set by writing to RegUartTx
Cleared when transferring RegUartTx into
internal shift register
Table 14-4: RegUartTxSta
pos.
7-0
RegUartRx
UartRx
rw
r
reset
00000000
resetsystem
description
Received data
Table 14-5: RegUartRx
pos.
7-6
5
4
3
2
RegUartRxSta
UartRxSErr
UartRxPErr
UartRxFErr
UartRxOErr
rw
r
r
r
r
rc
Reset
00
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
1
0
UartRxBusy
UartRxFull
r
r
0 resetsystem
0 resetsystem
description
Unused
Start error
Parity error
Frame error
Overrun error
Cleared by writing RegUartRxSta
Uart busy receiving
RegUartRx full
Cleared by reading RegUartRx
Table 14-6: RegUartRxSta
14.4 Interrupts map
interrupt source
Irq_uart_Tx
Irq_uart_Rx
default mapping in the interrupt manager
IrqHig(1)
IrqHig(0)
Table 14-7: Interrupts map
14.5 Uart baud rate selection
In order to have correct baud rates, the Uart interface has to be fed with a stable and trimmed clock source. The
clock source can be the RC oscillator or the crystal oscillator. The precision of the baud rate will depend on the
precision of the selected clock source.
14.5.1
Uart on the RC oscillator
To select the RC oscillator for the Uart, the bit SelXtal in RegUartCmd has to be 0.
In order to obtain a correct baud rate, the RC oscillator frequency has to be set to one of the frequencies given in
the table on the next page. The precision of the obtained baud rate is directly proportional to the frequency
deviation with respect to the values in the table.
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Frequency selection for correct Uart
baud rate with RC oscillator (Hz)
2’457’600
1’843’200
1’228’800
614’400
For each of these frequencies, the baud rate can be selected with the bits UartBR(2:0) in RegUartCtrl and
UartRcSel(2:0) in RegUartCmd as shown in Table 14-8
RC frequency (Hz)
UartRcSel
111
110
UartBR
101
100
2’457’600
010
1’228’800
001
38400
19200
9600
Not possible
614’400
000
4800
1’843’200
000
115200
57600
28800
14400
Table 14-8: Uart baud rate with RC clock
Note: The precision of the baud rate is directly proportional to the frequency deviation of the used clock from the
ideal frequency given in the table. In order to increase the precision and stability of the RC oscillator, the DFLL
(digital frequency locked loop) can be used with the crystal oscillator as a reference.
14.5.2
Uart on the crystal oscillator
In order to use the crystal oscillator as the clock source for the Uart, the bit SelXtal in RegUartCmd has to be set.
The crystal oscillator has to be enabled by setting the EnableXtal bit in RegSysClock. The baud rate selection is
done using the UartBR and UartRcSel bits as shown in Table 14-9.
Xtal freq. (Hz)
UartRcSel
32768
001
UartBR
011
010
001
000
Baud rate
2400
1200
600
300
Table 14-9: Uart baud rate with Xtal clock
Due to the odd ratio between the crystal oscillator frequency and the baud rate, the generated baud rate has a
systematic error of –2.48%.
14.6 Function description
14.6.1
Configuration bits
The configuration bits of the Uart serial interface can be found in the registers RegUartCmd and RegUartCtrl.
The bit SelXtal is used to select the clock source (see chapter 14.5). The bits UartSelRc and UartBR select the
baud rate (see chapter 14.5).
The bits UartEnTx is used to enable or disable the transmission.
The bits UartEnRx1 and UartEnRx2 are used to enable or disable the reception. When one is set to 1, the
reception is enabled.
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The word length (7 or 8 data bits) can be chosen with UartWL. A parity bit is added during transmission or checked
during reception if UartPE is set. The parity mode (odd or even) can be chosen with UartPM.
Setting the bits UartXRx and UartXTx inverts the Rx respectively Tx signals.
The bit UartEcho is used to send the received data automatically back. The transmission function becomes then:
Tx = Rx XOR UartXTx.
14.6.2
Transmission
In order to send data, the transmitter has to be enabled by setting the bit UartEnTx. Data to be sent has to be
written to the register RegUartTx. The bit UartTxFull in RegUartTxSta then goes to 1, indicating to the transmitter
that a new word is available. As soon as the transmitter has finished sending the previous word, it then loads the
contents of the register RegUartTx to an internal shift register and clears the UartTxFull bit. An interrupt is
generated on Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows
that the transmitter is busy transmitting a word.
A timing diagram is shown in Figure 14-1. Data are first sent LSB.
New data should be written to the register RegUartTx only while UartTxFull is 0, otherwise data will be lost.
Asynchronous Transmission
write to RegUartTx
word 1
RegUartTx
reguarttx_shift
word 1
shift clock
Tx
start
b0
b1
b6/7
parity
stop
UartTxBusy
UartTxFull
Irq_uart_Tx
Asynchronous Transmission (back to back)
word 1
word 2
write to RegUartTx
RegUartTx
reguarttx_shift
word 1
word 2
word 1
word 2
shift clock
Tx
start
b0
b6/7
stop
start
UartTxBusy
UartTxFull
Irq_uart_Tx
Figure 14-1. Uart transmission timing diagram.
14.6.3
Reception
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are
transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set
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and an interrupt is generated on Irq_uart_Rx. This indicates that new data is available in RegUartRx. The timing
diagram is shown in Figure 14-2.
The UartRxFull bit is cleared when RegUartRx is read. If the register was not read before the receiver transfers a
new word to it, the bit UartRxOErr (overflow error) is set and the previous contents of the register is lost.
UartRxOErr is cleared by writing any data to RegUartRxSta.
The bit UartRxSErr is set if a start error has been detected. The bit is updated at data transfer to RegUartRx.
The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the
calculated parity of the received data. The bit is updated at data transfer to RegUartRx.
The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. No stop bit has been detected.
Asynchronous Reception
read of RegUartRx (software)
reguartrx_shift
word 1
word 1
RegUartRx
shift clock
Rx
start
b0
b6/7
parity
stop
UartRxBusy
UartRxFull
Irq_uart_Rx
Figure 14-2. Uart reception timing diagram.
14.7 Interrupt or polling
The transmission and reception software can be driven by interruption or by polling the status bits.
Interrupt driven reception: each time an Irq_uart_Rx interrupt is generated, a new word is available in RegUartRx.
The register has to be read before a new word is received.
Interrupt driven transmission: each time the contents of RegUartTx is transferred to the transmission shift register,
an Irq_uart_Tx interrupt is generated. A new word can then be written to RegUartTx.
Reception driven by polling: the UartRxFull bit is to be read and checked. When it is 1, the RegUartRx register
contains new data and has to be read before a new word is received.
Transmission driven by polling: the UartTxFull bit is to read and checked. When it is 0, the RegUartTx register is
empty and a new word can be written to it.
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14.8 Software hints
Example of program for a transmission with polling:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart transmission).
2. Write a byte to RegUartTx.
3. Wait until the UartTxFull bit in RegUartTxSta register equals 0.
4. Jump to 2 to write the next byte if the message is not finished.
5. End of transmission.
Example of program for a transmission with interrupt:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart transmission).
2. Write a byte to RegUartTx.
3. After an interrupt and if the message is not finished, jump to 2
4. End of transmission.
Example of program for a reception with polling:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart reception).
2. Wait until the UartRxFull bit in the RegUartRxSta register equals 1.
3. Read the RegUartRxSta and check if there is no error.
4. Read data in RegUartRx.
5. If data is not equal to End-Of-Line, then jump to 2.
6. End of reception.
Example of program for a reception with interrupt:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart reception).
2. When there is an interrupt, jump to 3
3. Read RegUartRxSta and check if there is no error.
4. Read data in RegUartRx.
5. If data is not equal to End-Of-Line, then jump to 2.
6. End of reception.
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15 USRT
15.1
Features
15-2
15.2
Overview
15-2
15.3
Register map
15-2
15.4
Interrupts map
15-4
15.5
Conditional edge detection 1
15-4
15.6
Conditional edge detection 2
15-4
15.7
Interrupts or polling
15-5
15.8
Function description
15-5
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15.1 Features
The USRT implements a hardware support for software implemented serial protocols:
• Control of two external lines S0 and S1 (read/write).
• Conditional edge detection generates interrupts.
• S0 rising edge detection.
• S1 value is stored on S0 rising edge.
• S0 signal can be forced to 0 after a falling edge on S0 for clock stretching in the low state.
• S0 signal can be stretched in the low state after a falling edge on S0 and after a S1 conditional detection.
15.2 Overview
The USRT block supports software universal synchronous receiver and transmitter mode interfaces.
External lines S0 and S1 respectively correspond to clock line and data line. S0 is mapped to PB[4] and S1 to
PB[5] when the USRT block is enabled. It is independent from RegPBdir (Port B can be input or output). When
USRT is enabled, the configurations in port B for PB[4] and PB[5] are overwritten by the USRT configuration.
Internal pull-ups can be used by setting the PBPullup[5:4] bits.
Conditional edge detections are provided.
RegUsrtS1 can be used to read the S1 data line from PB[5] in receive mode or to drive the output S1 line PB[5] by
writing it when in transmit mode. It is advised to read S1 data when in receive mode from the RegUsrtBufferS1
register, which is the S1 value sampled on a rising edge of S0.
15.3 Register map
Block configuration registers:
pos.
7-1
0
RegUsrtS1
UsrtS1
rw
r
rw
reset
function
0000000
1 resetsystem
Unused
Write: data S1 written to pad PB[5]),
Read: value on PB[5] (not UsrtS1 value).
Table 15-1: RegUsrtS1
pos.
7-1
0
RegUsrtS0
UsrtS0
rw
r
rw
Reset
0000000
1 resetsystem
function
Unused
Write: clock S0 written to pad PB[4],
Read: value on PB[4] (not UsrtS0 value).
Table 15-2: RegUsrtS0
The values that are read in the registers RegUsrtS1 and RegUsrtS0 are not necessarily the same as the values
that were written in the register. The read value is read back on the circuit pins, not in the registers. Since the
outputs are open drain, a value different from the register value may be forced by an external circuit on the circuit
pins.
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pos.
7-4
3
RegUsrtCtrl
UsrtWaitS0
rw
r
r
reset
“0000”
0 resetsystem
2
UsrtEnWaitCond1
rw
0 resetsystem
1
0
UsrtEnWaitS0
UsrtEnable
rw
rw
0 resetsystem
0 resetsystem
function
Unused
Clock stretching flag (0=no stretching),
cleared by writing RegUsrtBufferS1
Enable stretching on UsrtCond1 detection
(0=disable)
Enable stretching operation (0=disable)
Enable USRT operation (0=disable)
Table 15-3: RegUsrtCtrl
pos.
7-1
0
RegUsrtCond1
UsrtCond1
rw
r
r/c
reset
0000000
0 resetsystem
function
Unused
State of condition 1 detection (1 =detected),
cleared when written.
Table 15-4: RegUsrtCond1
pos.
7-1
0
RegUsrtCond2
UsrtCond2
rw
r
r/c
reset
0000000
0 resetsystem
function
Unused
State of condition 2 detection (1 =detected),
cleared when written.
Table 15-5: RegUsrtCond2
pos.
7-1
RegUsrtBufferS1
-
0
UsrtBufferS1
rw
r
r
w
reset
0000000
function
Unused
Value on S1 at last S0 rising edge.
Clear RegUsrtEdgeS0 bit in RegUsrtEdgeS0
Clear UsrtWaitS0 bit in RegUsrtCtrl with any
value
x
Table 15-6: RegUsrtBufferS1
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pos.
7-1
0
RegUsrtEdgeS0
UsrtEdgeS0
rw
r
r
reset
0000000
0 resetsystem
function
Unused
State of rising edge detection
(1=detected).
Cleared
by
RegUsrtBufferS1
on S0
reading
Table 15-7: RegUsrtEdgeS0
15.4 Interrupts map
interrupt
source
Irq_cond1
Irq_cond2
default mapping in the interrupt manager
RegIrqMid(7)
RegIrqMid(6)
Table 15-8: Interrupts map
15.5 Conditional edge detection 1
S1
S0
Figure 15-1: Condition 1
Condition 1 is satisfied when S0=1 at the falling edge of S1. The bit UsrtCond1 in RegUsrtCond1 is set when the
condition 1 is detected and the USRT interface is enabled (UsrtEnable=1). Condition 1 is asserted for both modes
(receiver and transmitter). The UsrtCond1 bit is read only and is cleared by all reset conditions and by writing any
data to its address.
Condition 1 occurrence also generates an interrupt on Irq_cond1.
15.6 Conditional edge detection 2
S1
S0
Figure 15-2: Condition 2
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Condition 2 is satisfied when S0=1 at the rising edge of S1. The bit UsrtCond2 in RegUsrtCond2 is set when the
condition 2 is detected and the USRT interface is enabled. Condition 2 is asserted for both modes (receiver and
transmitter). The UsrtCond2 bit is read only and is cleared by all reset conditions and by writing any data to its
address.
Condition 2 occurrence also generates an interrupt on Irq_cond2.
15.7 Interrupts or polling
In receive mode, there are two possibilities for detecting condition 1 or 2: the detection of the condition can
generate an interrupt or the registers can be polled (reading and checking the RegUsrtCond1 and RegUsrtCond2
registers for the status of USRT communication).
15.8 Function description
The bit UsrtEnable in RegUsrtCtrl is used to enable the USRT interface and controls the PB[4] and PB[5] pins.
This bit puts these two port B lines in the open drain configuration requested to use the USRT interface.
If no external pull-ups are added on PB[4] and PB[5], the user can activate internal pull-ups by setting PBPullup[4]
and PBPullup[5] in RegPBPullup.
The bits UsrtEnWaitS0, UsrtEnWaitCond1, UsrtWaitS0 in RegUsrtCtrl are used for transmitter/receiver control
of USRT interface.
Figure 15-3 shows the unconditional clock stretching function which is enabled by setting UsrtEnWaitS0.
S0
UsrtWaitS0
write Reg UsrtBufferS1
Figure 15-3: S0 Stretching (UsrtEnWaitS0=1)
When UsrtEnWaitS0 is 1, the S0 line will be maintained at 0 after its falling edge (clock stretching). UsrtWaitS0 is
then set to 1, indicating that the S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1
register.
The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4
shows the conditional clock stretching function which is enabled by setting UsrtEnWaitCond1.
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S1
S0
UsrtWaitS0
write Reg UsrtBufferS1
Figure 15-4: Conditional stretching (UsrtEnWaitCond1=1)
When UsrtEnWaitCond1 is 1, the S0 signal will be stretched in its low state after its falling edge if the condition 1
has been detected before (UsrtCond1=1). UsrtWaitS0 is then set to 1, indicating that the S0 line is forced low.
One can release S0 by writing to the RegUsrtBufferS1 register.
Figure 15-5 shows the sampling function implemented by the UsrtBufferS1 bit. The bit UsrtBufferS1 in
RegUsrtBufferS1 is the value of S1 sampled on PB[4] at the last rising edge of S0. The bit UsrtEdgeS0 in
RegUsrtEdgeS0 is set to one on the same S0 rising edge and is cleared by a read operation of the
RegUsrtBufferS1 register. The bit therefore indicates that a new value is present in the RegUsrtBufferS1 which
has not yet been read.
S1
S0
UsrtBufferS1
read Reg UsrtBufferS1
UsrtEdgeS0
Figure 15-5: S1 sampling
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16.
Acquisition
Chain
16.1
ZoomingADC™ Features ....................................................................................................... 16-2
16.2
Overview ................................................................................................................................. 16-2
16.3
Register map .......................................................................................................................... 16-2
16.4
16.4.1
16.4.2
16.4.3
ZoomingADC™ Description................................................................................................... 16-4
Acquisition Chain ..................................................................................................................... 16-4
Peripheral Registers................................................................................................................. 16-6
Continuous-Time vs. On-Request ............................................................................................ 16-8
16.5
Input Multiplexers .................................................................................................................. 16-9
16.6
16.6.1
16.6.2
16.6.3
16.6.4
Programmable Gain Amplifiers........................................................................................... 16-10
PGA & ADC Enabling............................................................................................................. 16-12
PGA1 ..................................................................................................................................... 16-12
PGA2 ..................................................................................................................................... 16-12
PGA3 ..................................................................................................................................... 16-12
16.7
16.7.1
16.7.2
16.7.3
16.7.4
16.7.5
16.7.6
16.7.7
16.7.8
ADC Characteristics ............................................................................................................ 16-13
Conversion Sequence............................................................................................................ 16-13
Sampling Frequency .............................................................................................................. 16-14
Over-Sampling Ratio.............................................................................................................. 16-14
Elementary Conversions ........................................................................................................ 16-14
Resolution .............................................................................................................................. 16-15
Conversion Time & Throughput ............................................................................................. 16-16
Output Code Format .............................................................................................................. 16-16
Power Saving Modes ............................................................................................................. 16-18
16.8
16.8.1
16.8.2
16.8.3
16.8.3.1
16.8.3.2
16.8.4
16.8.5
16.8.6
16.8.7
Specifications and Measured Curves................................................................................. 16-18
Default Settings...................................................................................................................... 16-19
Specifications......................................................................................................................... 16-20
Linearity ................................................................................................................................. 16-21
Integral non-linearity............................................................................................................... 16-21
Differential non-linearity ......................................................................................................... 16-25
Noise...................................................................................................................................... 16-26
Gain Error and Offset Error .................................................................................................... 16-27
Power Consumption............................................................................................................... 16-28
Power Supply Rejection Ratio................................................................................................ 16-30
16.9
16.9.1
16.9.2
16.9.3
16.9.4
16.9.5
Application Hints.................................................................................................................. 16-31
Input Impedance .................................................................................................................... 16-31
PGA Settling or Input Channel Modifications.......................................................................... 16-31
PGA Gain & Offset, Linearity and Noise................................................................................. 16-31
Frequency Response ............................................................................................................. 16-32
Power Reduction.................................................................................................................... 16-33
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16-1
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16.1 ZoomingADC™ Features
The ZoomingADC™ is a complete and versatile low-power analog front-end interface typically intended for sensing
applications. The key features of the ZoomingADC™ are:
Programmable 6 to 16-bit dynamic range oversampled ADC
• Flexible gain programming between 0.5 and 1000
• Flexible and large range offset compensation
• 4-channel differential or 8-channel single-ended input multiplexer
• 2-channel differential reference inputs
• Power saving modes
• Direct interfacing to CoolRisc™ microcontroller
16.2 Overview
Analog
Inputs
MUX
fS
0
1
2
3
4
5
6
7
VIN
fS
PGA1
PGA2
VD1
GD1
Input
Selection
MUX
0
Reference 1
Inputs 2
PGA3
VIN,ADC
VD2
GD2
GD3
OFF2
OFF3
ADC
16
VREF
3
Offset2
Reference
Selection
Offset3
Gain1 Gain2
Gain3
ZOOM
Figure 16-1. ZoomingADC™ general functional block diagram
The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an
oversampled A/D converter. The reference voltage can be selected on two different channels. Two offset
compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset allow one
to zoom in on a small portion of the reference voltage defined input range.
16.3 Register map
There are eight registers in the acquisition chain (AC), namely RegAcOutLsb, RegAcOutMsb, RegAcCfg0,
RegAcCfg1, RegAcCfg2, RegAcCfg3, RegAcCfg4 and RegAcCfg5. Table 16-2 to Table 16-9 show the mapping
of control bits and functionality of these registers while Table 16-1 gives an overview of these eight.
The register map only gives a short description of the different configuration bits. More detailed information is found
in subsequent sections.
© Semtech 2006
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16-2
XE8805/05A
register name
RegAcOutLsb
RegAcOutMsb
RegAcCfg0
RegAcCfg1
RegAcCfg2
RegAcCfg3
RegAcCfg4
RegAcCfg5
Table 16-1: AC registers
pos.
7:0
RegAcOutLsb
Out[7:0]
rw
r
reset
00000000
resetsystem
description
LSB of the output code
Table 16-2: RegAcOutLsb
pos.
7:0
RegAcOutMsb
Out[15:8]
rw
r
reset
00000000
resetsystem
description
MSB of the output code
Table 16-3: RegAcOutMsb
pos.
7
6:5
RegAcCfg0
Start
SET_NELCONV[1:0]
rw
w r0
rw
reset
0 resetsystem
01 resetsystem
4:2
SET_OSR[2:0]
rw
010 resetsystem
1
0
CONT
reserved
rw
rw
0 resetsystem
0 resetsystem
description
starts a conversion
sets the number of elementary conversions
sets the oversampling rate of an elementary
conversion
continuous conversion mode
Table 16-4: RegAcCfg0
pos.
7:6
5:4
3:0
RegAcCfg1
IB_AMP_ADC[1:0]
IB_AMP_PGA[1:0]
ENABLE[3:0]
rw
rw
rw
rw
reset
11 resetsystem
11 resetsystem
0000
resetsystem
description
Bias current selection of the ADC converter
Bias current selection of the PGA stages
Enables the different PGA stages and the ADC
Table 16-5: RegAcCfg1
pos.
7:6
5:4
3:0
RegAcCfg2
FIN[1:0]
PGA2_GAIN[1:0]
PGA2_OFFSET[3:0]
rw
rw
rw
rw
reset
00 resetsystem
00 resetsystem
0000
resetsystem
description
Sampling frequency selection
PGA2 stage gain selection
PGA2 stage offset selection
Table 16-6: RegAcCfg2
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pos.
7
6:0
RegAcCfg3
PGA1_GAIN
PGA3_GAIN[6:0]
rw
rw
rw
reset
0 resetsystem
0000000
resetsystem
description
PGA1 stage gain selection
PGA3 stage gain selection
Table 16-7: RegAcCfg3
pos.
7
6:0
RegAcCfg4
reserved
PGA3_OFFSET[6:0]
rw
r
rw
reset
0
0000000
resetsystem
description
Unused
PGA3 stage offset selection
Table 16-8: RegAcCfg4
pos.
7
6
5:1
0
RegAcCfg5
BUSY
DEF
AMUX[4:0]
VMUX
rw
r
w r0
rw
rw
reset
0 resetsystem
0
00000
resetsystem
0 resetsystem
description
Activity flag
Selects default configuration
Input channel configuration selector
Reference channel selector
Table 16-9: RegAcCfg5
16.4 ZoomingADC™ Description
Figure 16-2 gives a more detailed description of the acquisition chain.
16.4.1
Acquisition Chain
Figure 16-1 shows the general block diagram of the acquisition chain (AC). A control block (not shown in Figure
16-1) manages all communications with the CoolRisc™ microcontroller.
Analog inputs can be selected among eight input channels, while reference input is selected between two
differential channels.
The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of a
combination of input and reference signals VIN and VREF, the input voltage is modulated and amplified through
stages 1 to 3. Fine gain programming up to 1'000V/V is possible. In addition, the last two stages provide
programmable offset. Each amplifier can be bypassed if needed.
The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal
VIN,ADC into digital.
Like most ADCs intended for instrumentation or sensing applications, the ZoomingADC™ is an over-sampled
converter (See Note1). The ADC is a so-called incremental converter, with bipolar operation (the ADC accepts both
positive and negative input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers
the quantity:
1 Note: Over-sampled converters are operated with a sampling frequency f much higher than the input signal's Nyquist rate (typically f is 20S
S
1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital
decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications.
© Semtech 2006
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OUT ADC V IN , ADC
≅
FS / 2
V REF / 2
(Eq. 1)
in two's complement (see Sections 16.4 and 16.7 for details). The output code OUTADC is -FS/2 to +FS/2 for VIN,ADC
≅ -VREF/2 to +VREF/2 respectively. As will be shown in section 16.6, VIN,ADC is related to input voltage VIN by the
relationship:
V IN , ADC = GDTOT ⋅ V IN − GDoff TOT ⋅ V REF (V)
(Eq. 2)
where GDTOT is the total PGA gain, and GDoffTOT is the total PGA offset.
0
1
AC_R 2
fS
fS
PGA1
PGA2
PGA3
GD1
GD2
GD3
OFF2
OFF3
VIN
VIN,ADC
ADC
VREF
MUX
0
1
2
3
AC_A 4
5
6
7
MUX
Inputs
3
5
2
4
7
7
Acquisition Chain
Register Bank
RegACCfg5
RegACCfg4
8
RegACCfg3
RegACOutLSB
RegACCfg2
RegACOutMSB
RegACCfg1
RegACCfg0
Power Saving Modes
PGA Enabling
Conversion Start
Nbr of Elementary Cycles
Over-Sampling Ratio
Continuous vs. On-Request
8
ADC Busy Flag
Default Settings
Sampling Frequency fS
Figure 16-2. ZoomingADC™ detailed functional block diagram
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16-5
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16.4.2
Peripheral Registers
Figure 16-2 shows a detailed functional diagram of the ZoomingADC™.
In table 16-10 the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit
registers: six registers are used to configure the acquisition chain (RegAcCfg0 to 5), and two registers are used
to store the output code of the analog-to-digital conversion (RegAcOutMsb & Lsb). The register coding of the
ADC parameters and performance characteristics are detailed in Section 16.7.
Table 16-10. Peripheral registers to configure the acquisition chain (AC)
and to store the analog-to-digital conversion (ADC) result
Register
Name
Bit Position
7
6
5
4
3
RegAcOutLsb
OUT[7:0]
RegAcOutMsb
OUT[15:8]
RegAcCfg0
Default values:
RegAcCfg1
Default values:
RegAcCfg2
Default values:
RegAcCfg3
Default values:
RegAcCfg4
Default values:
RegAcCfg5
Default values:
START
0
SET_NELC[1:0]
01
IB_AMP_ADC[1:0]
11
FIN[1:0]
00
PGA1_G
0
0
BUSY
0
DEF
0
2
1
0
SET_OSR[2:0]
010
CONT
TEST
0
0
IB_AMP_PGA[1:0]
ENABLE[3:0]
11
0001
PGA2_GAIN[1:0]
PGA2_OFFSET[3:0]
00
0000
PGA3_GAIN[6:0]
0000000
PGA3_OFFSET[6:0]
0000000
AMUX[4:0]
VMUX
00000
0
With:
•
OUT: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
•
START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
SET_NELC[1:0]
. To compensate for offsets, the input signal
•
SET_NELC: (rw) sets the number of elementary conversions to 2
is chopped between elementary conversions (1,2,4,8).
(3+SET_OSR[2:0])
. OSR = 8, 16, 32, ...,
•
SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2
512, 1024.
•
CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1.
•
TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten.
•
IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation current (25,
50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
•
IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the normal operation current (25,
50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
•
ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages
that are disabled are bypassed.
•
FIN: (rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency,
the sampling frequency is given as: 00 Æ 1/4 fRC, 01 Æ 1/8 fRC, 10 Æ 1/32 fRC, 11Æ ~8kHz.
•
PGA1_GAIN: (rw) sets the gain of the first stage: 0 Æ 1, 1 Æ 10.
•
PGA2_GAIN: (rw) sets the gain of the second stage: 00 Æ 1, 01 Æ 2, 10 Æ 5, 11 Æ 10.
•
PGA3_GAIN: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]⋅1/12.
•
PGA2_OFFSET: (rw) sets the offset of the second stage between –1 and +1, with increments of 0.2. The MSB gives the sign
(0 → positive, 1 → negative); amplitude is coded with the bits PGA2_OFFSET[5:0].
•
PGA3_OFFSET: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the
sign (0 → positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0].
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16-6
XE8805/05A
•
•
•
•
BUSY: (r) set to 1 if a conversion is running. Note that the flag is set at the effective start of the conversion. Since the ADC is
generally synchronized on a lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC
sampling frequency) between the writing of the START or CONT bits and the appearance of BUSY flag.
DEF: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary
conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one.
AMUX(4:0): (rw) AMUX[4] sets the mode (0 Æ 4 differential inputs, 1 Æ 7 inputs with A(0) = common reference)
AMUX(3) sets the sign (0 Æ straight, 1Æ cross) AMUX[2:0] sets the channel.
VMUX: (rw) sets the differential reference channel (0 Æ R(1) and R(0), 1 Æ R(3) and R(2)).
(r = read; w = write; rw = read & write)
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16.4.3
Continuous-Time vs. On-Request
The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit
CONT).
In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new
one is automatically initiated. The new value is then written in the result register, and the corresponding internal
trigger pulse is generated. This operation is sketched in Figure 16-3. The conversion time in this case is defined as
TCONV.
TCONV
Internal Trig
Ouput Code
RegACOut[15:0]
BUSY
IRQ
Figure 16-3. ADC "continuous-time" operation
T CONV
Internal Trig
Request
START
Ouput Code
RegACOut[15:0]
BUSY
IRQ
Figure 16-4. ADC "on-request" operation
In the "on-request" mode, the internal behaviour of the converter is the same as in the "continuous-time" mode, but
the conversion is initiated on user request (with the START bit). As shown in Figure 16-4, the conversion time is
also TCONV. Note that the flag is set at the effective start of the conversion. Since the ADC is generally synchronized
on a lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC sampling
frequency) between the writing of the START or CONT bits and the appearance of BUSY flag.
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16.5 Input Multiplexers
The ZoomingADC™ has eight analog inputs AC_A(0) to AC_A(7) and four reference inputs AC_R(0) to
AC_R(3). Let us first define the differential input voltage VIN and reference voltage VREF respectively as:
VIN = VINP − VINN
(V)
(Eq. 3)
VREF = VREFP − VREFN
(V)
(Eq. 4)
and:
As shown in Table 16-11 the inputs can be configured in two ways: either as 4 differential channels (VIN1 =
AC_A(1) - AC_A(0),..., VIN4 = AC_A(7) - AC_A(6)), or AC_A(0) can be used as a common reference, providing
7 signal paths all referred to AC_A(0). The control word for the analog input selection is AMUX[4:0]. Notice that
the bit AMUX[3] controls the sign of the input voltage.
AMUX[4:0]
(RegAcCfg5[5:1])
VINP
VINN
AMUX[4:0]
(RegAcCfg5[5:1])
VINP
VINN
00x00
00x01
00x10
00x11
AC_A(1)
AC_A(3)
AC_A(5)
AC_A(7)
AC_A(0)
AC_A(2)
AC_A(4)
AC_A(6)
01x00
01x01
01x10
01x11
AC_A(0)
AC_A(2)
AC_A(4)
AC_A(6)
AC_A(1)
AC_A(3)
AC_A(5)
AC_A(7)
10000
10001
10010
10011
10100
10101
10110
10111
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_A(0)
11000
11001
11010
11011
11100
11101
11110
11111
AC_A(0)
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
Table 16-11. Analog input selection
Similarly, the reference voltage is chosen among two differential channels (VREF1 = AC_R(1)-AC_R(0) or VREF2 =
AC_R(3)-AC_R(2)) as shown in Table 16-12. The selection bit is VMUX. The reference inputs VREFP and VREFN
(common-mode) can be up to the power supply range.
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16-9
XE8805/05A
VMUX
(RegAcCfg5[0])
0
1
VREFP
VREFN
AC_R(1)
AC_R(3)
AC_R(0)
AC_R(2)
Table 16-12. Analog Reference input selection
16.6
Programmable Gain Amplifiers
As seen in Figure 16-1, the zooming function is implemented with three programmable gain amplifiers (PGA).
These are:
•
PGA1: coarse gain tuning
•
PGA2: medium gain and offset tuning
•
PGA3: fine gain and offset tuning
All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation
and gain, as well as the offset of stages 2 and 3. These functions are examined hereafter.
ENABLE[3:0]
Block
xxx0
xxx1
xx0x
xx1x
x0xx
x1xx
0xxx
1xxx
ADC disabled
ADC enabled
PGA1 disabled
PGA1 enabled
PGA2 disabled
PGA2 enabled
PGA3 disabled
PGA3 enabled
Table 16-13. ADC & PGA enabling
PGA1 Gain
GD1 (V/V)
1
10
PGA1_GAIN
0
1
Table 16-14. PGA1 Gain Settings
PGA2 Gain
GD2 (V/V)
1
2
5
10
PGA2_GAIN[1:0]
00
01
10
11
Table 16-15. PGA2 gain settings
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PGA2_OFFSET[3:0]
0000
0001
0010
0011
0100
0101
1001
1010
1011
1100
1101
PGA2 Offset
GDoff2 (V/V)
0
+0.2
+0.4
+0.6
+0.8
+1
-0.2
-0.4
-0.6
-0.8
-1
Table 16-16. PGA2 offset settings
PGA3 Gain
GD3 (V/V)
0
1/12(=0.083)
...
6/12
...
12/12
16/12
PGA3_GAIN[6:0]
0000000
0000001
...
0000110
...
0001100
0010000
...
0100000
...
1000000
...
1111111
32/12
64/12
127/12(=10.58)
Table 16-17. PGA3 gain settings
PGA3_OFFSET[6:0]
0000000
0000001
0000010
...
0010000
...
0100000
...
0111111
1000000
1000001
1000010
...
1010000
...
1100000
...
1111111
PGA3 Offset
GDoff3 (V/V)
0
+1/12(=+0.083)
+2/12
...
+16/12
...
+32/12
...
+63/12(=+5.25)
0
-1/12(=-0.083)
-2/12
...
-16/12
...
-32/12
...
-63/12(=-5.25)
Table 16-18. PGA3 offset settings
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16.6.1
PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to
the word ENABLE and the coding given in Table 16-13. To reduce power dissipation, the ADC can also be
inactivated while idle.
16.6.2
PGA1
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 16-14). The voltage VD1 at
the output of PGA1 is:
V D1 = GD1 ⋅ V IN
(V)
(Eq. 5)
where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN.
16.6.3
PGA2
The second PGA has a finer gain and offset tuning capability, as shown in Table 16-15 and Table 16-16. The
voltage VD2 at the output of PGA2 is given by:
V D 2 = GD2 ⋅ V D1 − GDoff 2 ⋅ V REF
(V)
(Eq. 6)
where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words
PGA2_GAIN[1:0] and PGA2_OFFSET[3:0].
As shown in equation 6, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
16.6.4
PGA3
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table
16-17 and Table 16-18. The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the
voltage entering the ADC is given by:
V IN , ADC = GD3 ⋅ V D 2 − GDoff 3 ⋅ V REF
(V)
(Eq. 7)
where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are
PGA3_GAIN[6:0] and PGA3_OFFSET[6:0] . To remain within the signal compliance of the PGA stages, the
condition:
V D1 , V D 2 < V DD
(V)
(Eq. 8)
must be verified.
As shown in equation 7, the offset correction is directly proportional to the reference voltage. All drifts and
perturbations on the reference voltage will affect the precision of the offset compensation.
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16-12
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Finally, combining equations Eq. 5 to Eq. 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related
to VIN by:
V IN , ADC = GDTOT ⋅ V IN − GDoff TOT ⋅ V REF (V)
(Eq. 9)
where the total PGA gain is defined as:
GDTOT = GD3 ⋅ GD2 ⋅ GD1
(V/V)
(Eq. 10)
and the total PGA offset is:
GDoff TOT = GDoff 3 + GD3 ⋅ GDoff 2
(V/V)
(Eq. 11)
16.7 ADC Characteristics
The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three
programmable parameters:
•
•
•
sampling frequency fS,
over-sampling ratio OSR, and
number of elementary conversions NELCONV.
The setting of these parameters and the resulting performances are described hereafter.
16.7.1
Conversion Sequence
A conversion is started each time the bit START or the bit DEF is set. As depicted in Figure 16-5, a complete
analog-to-digital conversion sequence is made of a set of NELCONV elementary incremental conversions and a final
quantization step. Each elementary conversion is made of (OSR+1) sampling periods TS=1/fS, i.e.:
TELCONV = (OSR + 1) / f S
(s)
(Eq. 12)
The result is the mean of the elementary conversion results. An important feature is that the elementary
conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the
other to the output code. Thus, converter internal offset is eliminated if at least two elementary sequences are
performed (i.e. if NELCONV ≥ 2). A few additional clock cycles are also required to initiate and end the conversion
properly.
TELCONV= (OSR+1)/f S
Init
Elementary
Conversion
Conversion index
Offset
1
+
Elementary
Conversion
Elementary
Conversion
Elementary
Conversion
2
-
NELCONV- 1
+
N ELCONV
-
TCONV
End
Conversion
Result
Figure 16-5. Analog-to-digital conversion sequence
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16.7.2
Sampling Frequency
The word FIN[1:0] is used to select the sampling frequency fS (Table 16-19). Three sub-multiples of the internal
RC-based frequency fRCEXT can be chosen. For FIN = "11", sampling frequency is about 8kHz. Additional
information on oscillators and their control can be found in the clock block documentation.
FIN[1:0]
00
01
10
11
Sampling Frequency fS (Hz)
01/05
02
1/4⋅fRC
1/8⋅fRCEXT
1/16⋅fRCEXT
1/8⋅fRC
1/64⋅fRCEXT
1/32⋅fRC
∼8kHz
∼4kHz
Table 16-19. Sampling frequency settings (fRC= RC-based frequency)
16.7.3
Over-Sampling Ratio
The over-sampling ratio (OSR) defines the number of integration cycles per elementary conversion. Its value is set
with the word SET_OSR[2:0] in power of 2 steps (see Table 16-20) given by:
3 + SET_OSR[2 : 0]
OSR = 2
(-)
SET_OSR[2:0]
(RegAcCfg0[4:2])
000
001
010
011
100
101
110
111
(Eq. 13)
Over-Sampling Ratio
OSR (-)
8
16
32
64
128
256
512
1024
Table 16-20. Over-sampling ratio settings
16.7.4
Elementary Conversions
As mentioned previously, the whole conversion sequence is made of a set of NELCONV elementary incremental
conversions. This number is set with the word SET_NELC[1:0] in power of 2 steps (see Table 16-21) given by:
SET_NELC[1: 0]
N ELCONV = 2
(-)
(Eq. 14)
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16-14
XE8805/05A
# of Elementary
Conversions
NELCONV (-)
1
2
4
8
SET_NELC[1:0]
(RegAcCfg0[6:5])
00
01
10
11
Table 16-21. Number of elementary conversion settings
As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier offsets.
16.7.5
Resolution
The theoretical resolution of the ADC, without considering thermal noise, is given by:
n = 2 ⋅ log 2 (OSR) + log 2 ( N ELCONV )
(Bits)
(Eq. 15)
17
Resolution - n [Bits]
15
13
11
SET_NELC= 11
10
01
00
9
7
5
000
001
010
011
100
101
110
111
SET_OSR
Figure 16-6. Resolution vs. SET_OSR[2:0] and SET_NELC[2:0]
SET_OSR
[2:0]
00
SET_NELC
01
10
11
000
001
010
011
100
101
110
111
6
8
10
12
14
16
16
16
7
9
11
13
15
16
16
16
9
11
13
15
16
16
16
16
8
10
12
14
16
16
16
16
(shaded area: resolution truncated to 16 bits
due to output register size RegAcOut[15:0])
Table 16-22. Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] settings
Using look-up Table 16-22 or the graph plotted in Figure 16-6, resolution can be set between 6 and 16 bits. Notice
that, because of 16-bit register use for the ADC output, practical resolution is limited to 16 bits, i.e. n ≤ 16. Even
if the resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and NELCONV to
higher values in order to reduce the influence of the thermal noise in the PGA (see section 16.8.4).
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16.7.6
Conversion Time & Throughput
As explained using Figure 16-5, conversion time is given by:
TCONV = ( N ELCONV ⋅ (OSR + 1) + 1) / f S (s)
(Eq. 16)
and throughput is then simply 1/TCONV. For example, consider an over-sampling ratio of 256, 2 elementary
conversions, and a sampling frequency of 500kHz (SET_OSR = "101", SET_NELC = "01", fRC = 2MHz, and FIN =
"00"). In this case, using Table 16-23, the conversion time is 515 sampling periods, or 1.03ms. This corresponds to
a throughput of 971Hz in continuous-time mode. The plot of Figure 16-7 illustrates the classic trade-off between
resolution and conversion time.
SET_OSR
[2:0]
000
001
010
011
100
101
110
111
SET_NELC[1:0]
01
10
19
37
35
69
67
133
131
261
259
517
515
1029
1027
2053
2051
4101
00
10
18
34
66
130
258
514
1026
11
73
137
265
521
1033
2057
4105
8201
Table 16-23. Normalized conversion time (TCONV ⋅fS) vs. SET_OSR[2:0] and
SET_NELC[1:0](normalized to sampling period 1/fS)
Resolution - n [Bits]
16.0
14.0
12.0
10.0
8.0
6.0
10
00
11
SET_NELC
01
4.0
10.0
100.0
1000.0
10000.0
Normalized Conversion Time - TCONV*fS [-]
Figure 16-7. Resolution vs. normalized conversion time for different SET_NELC[1:0]
16.7.7
Output Code Format
The ADC output code is a 16-bit word in two's complement format (see Table 16-24). For input voltages outside the
range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller
than 16 bits, the non-significant bits are forced to the values shown in Table 16-25. The output code, expressed in
LSBs, corresponds to:
OUTADC = 216 ⋅
VIN , ADC OSR + 1
(LSB)
⋅
VREF
OSR
(Eq.17)
Recalling equation Eq. 9, this can be rewritten as:
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16-16
XE8805/05A
OUTADC = 216 ⋅
VIN
VREF
⎛
V
⋅ ⎜⎜ GDTOT − GDoff TOT ⋅ REF
VIN
⎝
⎞ OSR + 1
⎟⎟ ⋅
OSR
⎠
(LSB) (Eq. 18)
where, from Eq. 10 and Eq. 11, the total PGA gain and offset are respectively:
GDTOT = GD3 ⋅ GD2 ⋅ GD1
(V/V)
and:
GDoff TOT = GDoff 3 + GD3 ⋅ GDoff 2
(V/V)
ADC Input
Voltage
VIN,ADC
% of
Full
Scale
(FS)
+2.49505V
+0.5⋅FS
+2.49497V
...
...
+76.145µV
0V
-76.145µV
...
...
...
0
...
...
-2.49505V
...
-2.49513V
-0.5⋅FS
Output in
LSBs
+215-1
=+32'767
15
+2 -2
=+32'766
...
+1
0
-1
...
15
-2 -1
=-32'767
-215
=-32'768
Output
Code
in Hex
7FFF
7FFE
...
0001
0000
FFFF
...
8001
8000
Table 16-24. Basic ADC Relationships (example for: VREF = 5V, OSR = 512, n = 16 bits)
SET_OSR
[2:0]
000
001
010
011
100
101
110
111
SET_NELC = 00
SET_NELC = 01
SET_NELC = 10
SET_NELC = 11
1000000000
10000000
100000
1000
10
-
100000000
1000000
10000
100
1
-
10000000
100000
1000
10
-
1000000
10000
100
1
-
Table 16-25. Last forced LSBs in conversion output registers for resolution settings smaller than 16
bits (n < 16) (RegAcOutMsb[7:0] & RegAcOutLsb[7:0])
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16-17
XE8805/05A
The equivalent LSB size at the input of the PGA chain is:
LSB =
1 V REF
OSR
⋅
⋅
n
2 GDTOT OSR + 1
(V)
(Eq. 19)
Notice that the input voltage VIN,ADC of the ADC must satisfy the condition:
VIN , ADC ≤
1
OSR
⋅ (V REFP − VREFN ) ⋅
2
OSR + 1
(V)
(Eq. 20)
to remain within the ADC input range.
16.7.8
Power Saving Modes
During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the
control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0] (see Table 16-26). If the system is idle, the PGAs and
ADC can even be disabled, thus, reducing power consumption to its minimum. This can considerably improve
battery lifetime.
ADC
PGA
[1:0]
Bias
Current
Bias
Current
00
01
10
11
x
1/4⋅IADC
1/2⋅IADC
3/4⋅IADC
IADC
x
x
00
01
10
11
x
1/4⋅IPGA
1/2⋅IPGA
3/4⋅IPGA
IPGA
IB_AMP_ADC
[1:0]
IB_AMP_PGA
Max. fS
[kHz]
62.5
125
250
500
62.5
125
250
500
Table 16-26. ADC & PGA power saving modes and maximum sampling frequency
16.8 Specifications and Measured Curves
This section presents measurement results for the acquisition chain. A summary table with circuit specifications
and measured curves are given.
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16-18
XE8805/05A
16.8.1
Default Settings
Unless otherwise specified, the measurement conditions are the following:
•
•
•
•
•
•
Temperature TA = +25°C
VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V
RC frequency fRC = 2MHz, sampling frequency fS = 500kHz
Offsets GDOff2 = GDOff3 = 0
Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '11')
Resolution:
for n = 12 bits: OSR = 32 and NELCONV = 4
for n = 16 bits: OSR = 512 and NELCONV = 2
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16-19
XE8805/05A
16.8.2
Specifications
Unless otherwise specified: Temperature TA = +25°C, VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V, RC frequency fRC = 2MHz, sampling
frequency fS = 500kHz, Overall PGA gain GDTOT = 1, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IB_AMP_ADC[1:0] =
IB_AMP_PGA[1:0] = '11'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2.
VALUE
PARAMETER
UNITS
COMMENTS/CONDITIONS
MIN
TYP
MAX
ANALOG
INPUT
CHARACTERISTICS
-2.42
+2.42
V
Gain = 1, OSR = 32 (Note 1)
Differential Input Voltage Ranges
-24.2
+24.2
mV
Gain = 100, OSR = 32
VIN = (VINP - VINN)
-2.42
+2.42
mV
Gain = 1000, OSR = 32
Reference Voltage Range
VREF = (VREFP – VREFN)
PROGRAMMABLE
GAIN
AMPLIFIERS (PGA)
Total PGA Gain, GDTOT
PGA1 Gain, GD1
PGA2 Gain, GD2
PGA3 Gain, GD3
Gain Setting Precision (each stage)
Gain Temperature Dependence
Offset
PGA2 Offset, GDoff2
PGA3 Offset, GDoff3
Offset Setting Precision (PGA2 or 3)
Offset Temperature Dependence
Input Impedance
PGA1
PGA2, PGA3
Output RMS Noise
PGA1
PGA2
PGA3
ADC STATIC PERFORMANCE
Resolution, n
No Missing Codes
Gain Error
Offset Error
0.5
1
1
0
-3
-1
-127/12
-3
Throughput Rate (Continuous Mode),
1/TCONV
Nbr of Initialization Cycles, NINIT
Nbr of End Conversion Cycles, NEND
PGA Stabilization Delay
DIGITAL OUTPUT
ADC Output Data Coding
±0.5
±5
V
1000
10
10
127/12
+3
V/V
V/V
V/V
V/V
%
ppm/°C
+1
+127/12
+3
V/V
V/V
%
ppm/°C
kΩ
kΩ
kΩ
1500
150
150
µV
µV
µV
205
340
365
6
Integral Non-Linearity, INL
Resolution n = 16 Bits
Differential Non-Linearity, DNL
Resolution n = 16 Bits
Power Supply Rejection Ratio, PSRR
DYNAMIC PERFORMANCE
Sampling Frequency, fS
Conversion Time, TCONV
±0.5
±5
VDD
16
Bits
See Table 16-14
See Table 16-15
Step=1/12 V/V,
16-17
See
Step=0.2 V/V, See Table 16-16
Step=1/12 V/V, See Table
16-18
(Note 2)
PGA1 Gain = 1 (Note 3)
PGA1 Gain = 10 (Note 3)
Maximal gain (Note 3)
(Note 4)
(Note 5)
(Note 6)
(Note 7)
(Note 8)
(Note 9)
n = 16 bits (Note 10)
±0.15
±1
% of FS
LSB
±1.0
LSB
(Note 11)
±0.5
78
72
LSB
dB
dB
(Note 12)
VDD = 5V ± 0.3V (Note 13)
VDD = 3V ± 0.3V (Note 13)
3
133
1027
3.76
0.49
0
0
2
5
OSR
kHz
cycles/fS
cycles/fS
kSps
kSps
cycles
cycles
cycles
Table
n = 12 bits (Note 14)
n = 16 bits (Note 14)
n = 12 bits, fS = 500kHz
n = 16 bits, fS = 500kHz
(Note 15)
Binary Two’s Complement
See Table 16-24 and Table
16-25
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XE8805/05A
Specifications (Cont’d)
PARAMETER
POWER SUPPLY
Voltage Supply Range, VDD
Analog
Quiescent
Current
Consumption, Total (IQ)
ADC Only
PGA1
PGA2
PGA3
Analog Power Dissipation
Normal Power Mode
3/4 Power Reduction Mode
1/2 Power Reduction Mode
1/4 Power Reduction Mode
TEMPERATURE
Specified Range
Operating Range
MIN
VALUE
TYP
MAX
+2.4
+5
+5.5
-40
-40
UNITS
V
720/620
250/190
165/150
130/120
175/160
µA
µA
µA
µA
µA
3.6/1.9
2.7/1.4
1.8/0.9
0.9/0.5
mW
mW
mW
mW
+85
+125
COMMENTS/CONDITIONS
Only Acquisition Chain
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
All PGAs & ADC Active
VDD = 5V/3V (Note 16)
VDD = 5V/3V (Note 17)
VDD = 5V/3V (Note 18)
VDD = 5V/3V (Note 19)
°C
°C
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
=
GD1⋅GD2⋅GD3.
Maximum
input
voltage
is
given
by:
Gain
defined
as
overall
PGA
gain
GDTOT
VIN,MAX = ±(VREF/2)⋅(OSR/OSR+1).
Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS =
512kHz. This figure must be multiplied by 2 for fS = 256kHz, 4 for fS = 128kHz. Input impedance is proportional to 1/fS.
See
model
of
Figure
16-18(a).
Figure
independent
from
PGA1
gain
and
sampling
frequency
fS.
See equation Eq. 21 to calculate equivalent input noise.
Figure independent on PGA2 gain and sampling frequency fS. See model of Figure 16-18(a). See equation Eq. 21 to calculate
equivalent input noise.
Figure independent on PGA3 gain and sampling frequency fS. See model of Figure 16-18(a) and equation Eq. 21 to calculate
equivalent input noise.
Resolution is given by n = 2⋅log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to
1, 2, 4 or 8.
If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function
(with the offset error removed). (See Figure 16-19)
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For ± 1 LSB offset, NELCONV must be ≥2.
INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds
over the full scale.
DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
Figures for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage
changes.
Conversion time is given by: TCONV = (NELCONV ⋅ (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can
be set to 1, 2, 4 or 8.
PGAs are reset after each writing operation to registers RegAcCfg1-5. The ADC must be started after a PGA or inputs commonmode stabilisation delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching.
Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of
cycles. This delay does not apply to conversions made without the PGAs.
Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = ‘11’ and IB_AMP_ADC[1:0] = ‘11’.
Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘10’, IB_AMP_ADC[1:0] = ‘10’.
Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘01’, IB_AMP_ADC[1:0] = ‘01’.
Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘00’, IB_AMP_ADC[1:0] = ‘00’.
16.8.3
Linearity
16.8.3.1
Integral non-linearity
The integral non-linearity depends on the selected gain configuration. First of all, the non-linearity of the ADC (all
PGA stages bypassed) is shown in Figure 16-8.
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XE8805/05A
Figure 16-8. Integral non-linearity of the ADC (PGA disabled, reference voltage of 4.8V)
The different PGA stages have been designed to find the best compromise between the noise performance, the
integral non-linearity and the power consumption. To obtain this, the first stage has the best noise performance and
the third stage the best linearity performance. For large input signals (small PGA gains, i.e. up to about 50), the
noise added by the PGA is very small with respect to the input signal and the second and third stage of the PGA
should be used to get the best linearity. For small input signals (large gains, i.e. above 50), the noise level in the
PGA is important and the first stage of the PGA should be used.
The following figures give the non-linearity for different gain settings of the PGA, selecting the appropriate stage to
get the best noise and linearity performance. Figure 16-9 shows the non-linearity when the third stage is used with
a gain of 1. It is of course not very useful to use the PGA with a gain of 1 unless it is used to compensate offset. By
increasing the gain, the integral non-linearity becomes even smaller since the signal in the amplifiers reduces.
Figure 16-10 shows the non-linearity for a gain of 2. Figure 16-11 shows the non-linearity for a gain of 5. Figure
16-12 shows the non-linearity for a gain of 10. By comparing these figures to Figure 16-8, it can be seen that the
third stage of the PGA does not add significant integral non-linearity.
Figure 16-13 shows the non-linearity for a gain of 20 and Figure 16-14 shows the non-linearity for a gain of 50. In
both cases the PGA2 is used at a gain of 10 and the remaining gain is realized by the third stage. It can be seen
again that the second stage of the PGA does not add significant non-linearity.
For gains above 50, the first stage PGA1 should be selected in stead of PGA2. Although the non-linearity in the first
stage of the PGA is larger than in stage 2 and 3, the gain in stage 3 is now sufficiently high so that the non-linearity
of the first stage does become negligible as is shown in Figure 16-15 for a gain of 100. Therefor, the first stage is
preferred over the second stage since it has less noise.
Increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the
first two stages. The signal is full scale at the output of stage 3 and as shown in Figure 16-9 to Figure 16-12, this
stage has very good linearity.
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Figure 16-9. Integral non-linearity of the ADC and with gain of 1 (PGA1 and PGA2 disabled, PGA3=1,
reference voltage of 5V)
Figure 16-10. Integral non-linearity of the ADC and gain of 2 (PGA1 and PGA2 disabled, PGA3=2
reference voltage of 5V)
Figure 16-11. Integral non-linearity of the ADC and gain of 5 (PGA1 and PGA2 disabled, PGA3=5,
reference voltage of 5V)
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Figure 16-12. Integral non-linearity of the ADC and gain of 10 (PGA1 and PGA2 disabled, PGA3=10,
reference voltage of 5V)
Figure 16-13. Integral non-linearity of the ADC and gain of 20 (PGA1 and PGA2=10, PGA3=2,
reference voltage of 5V)
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Figure 16-14. Integral non-linearity of the ADC and gain of 50 (PGA1 disabled, PGA2=10, PGA3=5,
reference voltage of 5V)
Figure 16-15. Integral non-linearity of the ADC and gain of 100 (PGA1=10 and PGA3=10, PGA2
disabled, reference voltage of 5V)
16.8.3.2
Differential non-linearity
The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure
16-16 shows the differential non-linearity.
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Figure 16-16. Differential non-linearity of the ADC converter.
16.8.4
Noise
Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the
output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions
for a constant input voltage was performed to derive the equivalent noise levels of PGA1, PGA2, and PGA3. The
extracted rms output noise of PGA1, 2, and 3 are given in Table 16-27: standard output deviation and output rms
noise voltage. Figure 16-17 shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed). Quantization
noise is dominant in this case, and, thus, the ADC thermal noise is below 16 bits.
The simple noise model of Figure 16-18(a) is used to estimate the equivalent input referred rms noise VN,IN of the
acquisition chain in the model of Figure 16-18(b). This is given by the relationship:
V N , IN =
2
(V N 1 / GD1 ) 2 + (V N 2 /(GD1 ⋅ GD2 )) 2 + (V N 3 /(GD1 ⋅ GD2 ⋅ GD3 )) 2
(OSR ⋅ N ELCONV )
(V2rms)
(Eq. 21)
where VN1, VN2, and VN3 are the output rms noise figures of Table 16-27, GD1, GD2, and GD3 are the PGA gains of
stages 1 to 3 respectively. As shown in this equation, noise can be reduced by increasing OSR and NELCONV
(increases the ADC averaging effect, but reduces noise).
Parameter
Standard deviation at
ADC output (LSB)
Output rms noise (µV)
1
PGA1
PGA2
PGA3
0.85
1.4
1.5
205 (VN1)
340 (VN2)
365 (VN3)
Note: see noise model of Figure 16-18 and equation Eq. 21.
Table 16-27. PGA noise measurements (n = 16 bits, OSR = 512, NELCONV = 2, VREF = 5V)
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Occurences
[% of total samples]
80
60
40
20
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
Output Code Deviation From Mean Value [LSB]
Figure 16-17. ADC noise (PGA1, 2 & 3 bypassed, OSR=512,NELCONV=2)
fS
PGA1
VN1
GD1
PGA2
VN2
GD2
PGA3
VN3
GD3
ADC
(a)
fS
PGA1
PGA2
PGA3
GD1
GD2
GD3
VN,IN
ADC
(b)
Figure 16-18. (a) Simple noise model for PGAs and ADC
and (b) total input referred noise
As an example, consider the system where: GD2 = 10 (GD1 = 1; PGA3 bypassed), OSR = 512, NELCONV = 2, VREF =
5V. In this case, the noise contribution VN1 of PGA1 is dominant over that of PGA2. Using equation Eq. 21, we get:
VN,IN = 6.4µV (rms) at the input of the acquisition chain, or, equivalently, 0.85 LSB at the output of the ADC.
Considering a 0.2V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB.
Noise can also be reduced by implementing a software filter. By making an average on a number of subsequent
measurements, the apparent noise is reduced the square root of the number of measurement used to make the
average.
16.8.5
Gain Error and Offset Error
Gain error is defined as the amount of deviation between the ideal transfer function (theoretical equation Eq. 18)
and the measured transfer function (with the offset error removed).
The actual gain of the different stages can vary depending on the fabrication tolerances of the different elements.
Although these tolerances are specified to a maximum of ±3%, they will be most of the time around ±0.5%.
Moreover, the tolerances between the different stages are not correlated and the probability to get the maximal
error in the same direction in all stages is very low. Finally, these gain errors can be calibrated by the software at
the same time with the gain errors of the sensor for instance.
Figure 16-19 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of FullScale Range (FSR) normalized to 25°C.
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Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC
and the PGA1 stage are completely suppressed if NELCONV > 1.
The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 16-20. The output
offset error, expressed in LSB for 16-bit setting, is normalized to 25°C. Notice that if the ADC is used alone, the
output offset error is below ±1 LSB and has no drift.
NORMALIZED TO 25°C
Gain Error [% of FSR]
0.2
0.1
0.0
-0.1
1
5
20
100
-0.2
-0.3
-0.4
-50
-25
0
25
50
75
100
Temperature [°C]
Figure 16-19. Gain error vs. temperature for different PGA gains
Output Offset Error [LSB]
NORMALIZED TO 25°C
100
1
5
20
100
80
60
40
20
0
-20
-40
-50
-25
0
25
50
75
100
Temperature [°C]
Figure 16-20. Offset error vs. temperature for different PGA gains
16.8.6
Power Consumption
Figure 16-21 plots the variation of quiescent current consumption with supply voltage VDD, as well as the
distribution between the 3 PGA stages and the ADC (see Table 16-28). As shown in Figure 16-22, if lower
sampling frequency is used, the quiescent current consumption can be lowered by reducing the bias currents of the
PGAs and the ADC with registers IB_AMP_PGA [1:0] and IB_AMP_ADC [1:0]. (In Figure 16-22,
IB_AMP_PGA/ADC[1:0] = '11', '10', '00' for fS = 500, 250, 62.5kHz respectively.)
Quiescent current consumption vs. temperature is depicted in Figure 16-23, showing a relative increase of nearly
40% between -45 and +85°C. Figure 16-24 shows the variation of quiescent current consumption for different
frequency settings of the internal RC oscillator. It can be seen that the quiescent current varies by about 20%
between 100kHz and 2MHz.
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XE8805/05A
800
Quiescent Current - IQ [µ A]
700
PGA1, 2 & 3 + ADC
600
500
PGA1 & 2 + ADC
400
PGA1 + ADC
300
200
No PGAs, ADC only
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage - VDDA [V]
Figure 16-21. Quiescent current consumption vs. supply voltage
800
Sampling Frequency fS : 500kHz
Quiescent Current - IQ [µ A]
700
600
250kHz
500
400
300
62.5kHz
200
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage - VDDA [V]
Figure 16-22. Quiescent current consumption vs. supply voltage for different sampling frequencies
20
Relative Quiescent Current Change
IQ / IQ,25°C [%]
Quiescent Current - IQ [µ A]
900
850
800
750
700
650
600
550
15
10
5
0
-5
-10
-15
-20
-25
500
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
(a)
(b)
Figure 16-23. (a) Absolute and (b) relative change inquiescent current consumption vs. temperature
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Supply
VDD = 5V
VDD = 3V
ADC
PGA1
PGA2
PGA3
TOTAL
Unit
250
190
165
150
130
120
175
160
720
620
µA
µA
15
850
10
800
Quiescent Current - IQ [µ A]
Relative Quiescent Current Change
∆ IQ / IQ,2MHz [%]
Table 16-28. Typical quiescent current distributions in acquisition chain (n = 16 bits, fS = 500kHz)
5
0
-5
-10
-15
750
700
650
600
550
500
-20
0
500
1000
1500
2000
2500
3000
0
3500
500
1000
1500
2000
2500
3000
3500
Frequency - fRC [kHz]
Frequency - fRC [kHz]
(a)
(b)
Figure 16-24. (a) Absolute and (b) relative change in quiescent curent consumption vs. RC oscillator
frequency (all PGAs active, VDD = 5V)
16.8.7
Power Supply Rejection Ratio
Figure 16-25 shows power supply rejection ratio (PSRR) at 3V and 5V supply voltage, and for various PGA gains.
PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the change in the converter output (in V).
PSRR depends on both PGA gain and supply voltage VDD.
105
100
VDD=3V
VDD=5V
PSRR [dB]
95
90
85
80
75
70
65
60
1
5
10
20
100
PGA Gain [V/V]
Figure 16-25. Power supply rejection ratio (PSRR)
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XE8805/05A
Supply
VDD = 5V
VDD = 3V
GAIN = 1
GAIN =5
GAIN = 10
GAIN = 20
GAIN =100
Unit
79
72
78
79
100
90
99
90
97
86
dB
dB
Table 16-29. PSRR (n = 16 bits, VIN = VREF = 2.5V, fS = 500kHz)
16.9 Application Hints
16.9.1
Input Impedance
The PGAs of the acquisition chain employ switched-capacitor techniques. For this reason, while a conversion is
done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency
fS and to stage gain as given in equation 22.
768 ⋅ 10 9 ΩHz
Z in ≥
f s ⋅ gain
(Eq. 22)
The input impedance observed is the input impedance of the first PGA stage that is enabled or the input
impedance of the ADC if all three stages are disabled.
PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input
impedance of 150kΩ at fS = 512kHz (see Specification Table). Larger input impedance can be obtained by
reducing the gain and/or by reducing the sampling frequency. Therefor, with a gain of 1 and a sampling frequency
of 100kHz, Zin > 7.6MΩ.
The input impedance on channels that are not selected is very high (>100MΩ).
16.9.2
PGA Settling or Input Channel Modifications
PGAs are reset after each writing operation to registers RegAcCfg1-5. Similarly, input channels are switched after
modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA or
inputs common-mode stabilization delay. This is done by writing bit START several cycles after PGA settings
modification or channel switching. Delay between PGA start or input channel switching and ADC start should be
equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without
the PGAs.
If the ADC is not settled within the specified period, there is most probably an input impedance problem (see
previous section).
16.9.3
PGA Gain & Offset, Linearity and Noise
Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC™:
1)
2)
3)
4)
Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but
degrades noise performance.
Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset.
Bypass unnecessary PGAs.
For high gains (>50), use PGA stage 1. For low gains (<50) use stages 2 and 3.
For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For
example, in an application where a gain of 20 is needed, set the gain of PGA2 to 10, set the gain of PGA3
to 2.
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4)
For highest linearity and lowest noise performance, bypass all PGAs and use the ADC alone (applications
where no "zooming" is needed); i.e. set ENABLE[3:0] = '0001'.
For low-noise applications where power consumption is not a primary concern, maintain the largest bias
currents in the PGAs and in the ADC; i.e. set IB_AMP_PGA[1:0] = IB_AMP_ADC[1:0] = '11'.
For lowest output offset error at the output of the ADC, bypass PGA2 and PGA3. Indeed, PGA2 and
PGA3 typically introduce an offset of about 5 to 10 LSB (16 bit) at their output. Note, however, that the
ADC output offset is easily calibrated out by software.
5)
6)
16.9.4
Frequency Response
The incremental ADC is an over-sampled converter with two main blocks: an analog modulator and a low-pass
digital filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator.
As shown in Figure 16-26, this filter determines the frequency response of the transfer function between the output
of the ADC and the analog input VIN. Notice that the frequency axes are normalized to one elementary conversion
period OSR/fS. The plots of Figure 16-26 also show that the frequency response changes with the number of
elementary conversions NELCONV performed. In particular, notches appear for NELCONV ≥ 2. These notches occur at:
f NOTCH (i) =
i ⋅ fS
OSR ⋅ N ELCONV
for i = 1,2,..., ( N ELCONV − 1)
(Hz)
(Eq. 23)
and are repeated every fS/OSR.
1.2
1
Normalized Magnitude [-]
Normalized Magnitude [-]
Information on the location of these notches is particularly useful when specific frequencies must be filtered out by
the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection is
needed. Using the above equation and the plots below, we set the 4th notch for NELCONV = 4 to 50Hz, i.e.
1.25⋅fS/OSR = 50Hz. The sampling frequency is then calculated as fS = 20.48kHz for OSR = 512. Notice that this
choice yields also good attenuation of 50Hz harmonics.
NELCONV = 1
0.8
0.6
0.4
0.2
0
1.2
1
N ELCONV = 2
0.8
0.6
0.4
0.2
0
0
1
2
3
4
0
1.2
1
NELCONV = 4
0.8
0.6
0.4
0.2
0
0
1
2
3
1
2
3
4
Normalized Frequency - f *(OSR/fS) [-]
Normalized Magnitude [-]
Normalized Magnitude [-]
Normalized Frequency - f *(OSR/fS) [-]
4
1.2
N ELCONV = 8
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
Normalized Frequency - f *(OSR/fS) [-]
Normalized Frequency - f *(OSR/fS) [-]
Figure 16-26. Frequency response: normalized magnitude vs. frequency for different NELCONV
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16.9.5
Power Reduction
The ZoominADC™ is particularly well suited for low-power applications. When very low power consumption is of
primary concern, such as in battery operated systems, several parameters can be used to reduce power
consumption as follows:
1)
2)
3)
4)
5)
Operate the acquisition chain with a reduced supply voltage VDD.
Disable the PGAs which are not used during analog-to-digital conversion with ENABLE[3:0].
Disable all PGAs and the ADC when the system is idle and no conversion is performed.
Use lower bias currents in the PGAs and the ADC using the control words IB_AMP_PGA[1:0] and
IB_AMP_ADC[1:0]. (This reduces the maximum sampling frequency according to Table 16-26.)
Reduce internal RC oscillator frequency and/or sampling frequency.
Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower
maximum sampling speed.
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17.
Vmult (Voltage Multiplier)
17.1
Features
17-2
17.2
Overview
17-2
17.3
Control register
17-2
17.4
External component
17-2
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17.1 Features
•
•
Generates a voltage that is higher or equal to the supply voltage.
Can be easily enabled or disabled
17.2 Overview
The Vmult block generates a voltage (called “Vmult”) that is higher or equal to the supply voltage. This output
voltage is used in the acquisition chain.
The voltage multiplier should be on (bit ENABLE in RegVmultCfg0) when using the acquisition chain or analog
properties of the Port B while VBAT is below 3V. If the multiplier is enabled, the external capacitor on the pin
VMULT is mandatory.
The source clock of Vmult is selected by FIN[1:0] in RegVmultCfg0. It is strongly recommended to use the same
settings as in the ADC.
17.3 Control register
There is only one register in the Vmult. Table 177-1 describes the bits in the register.
Pos.
2
RegVmultCfg0
Enable
rw
rw
Reset
0
resetsystem
1-0
Fin
rw
0
resetsystem
Function
enable of the vmult
‘1’ : enabled
‘0’ : disabled
system clock division factor
‘00’ : 1/2,
‘01’ : 1/4,
‘10’ : 1/16,
‘11’ : 1/64
Table 177-1. RegVmultCfg0
17.4 External component
When the multiplier is enabled, a capacitor has to be connected to the VMULT pin. If the multiplier is disabled, the
pin may remain floating.
Min.
Max.
1.0
3.0
Capacitor on VMULT
© Semtech 2006
Note
nF
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17-2
XE8805/05A
18.
Signal D/A (DAS)
18.1
Features
18-2
18.2
Overview of Signal DAC - The generic DAC
18-2
18.3
Registers Map
18-3
18.4
18.4.1
18.4.2
18.4.3
The D/A description
What is a noise shaper ?
Advantages/disadvantages
D/A setup and resolution
18-4
18-4
18-4
18-5
18.5
Amplifier
18-7
18.6
18.6.1
18.6.2
Low pass filter
First order low pass filter
Second order low pass filter
18-8
18-8
18-9
18.7
18.7.1
18.7.2
4-20mA loop
2-wire loop with first order filtering
2-wire loop with second order filtering
18-10
18-10
18-12
© Semtech 2006
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18-1
XE8805/05A
18.1 Features
•
•
•
•
•
•
•
16-bits maximum input word width
Synchronization mechanism to guarantee data integrity when writing LSB and MSB 8-bits data
Programmable noise shaper order: second, first or order zero
Programmable PWM modulation between 4 and 11-bits
Programmable clock input frequency: fin or fin/2
Programmable output polarity: active high or low
On chip amplifier for analog filtering, voltage output or 4-20 mA loop
18.2 Overview of Signal DAC - The generic DAC
The generic DAC block consists of two major parts: the noise shaper (sigma-delta modulator) and the PWM
modulator as shown in Figure 18-1.
control
CPU
bus
16
PWM
modulator
Sigma-delta
modulator
DAS Out
4-11
m
amp
Figure 18-1. General block diagram
A D/A converter that is built with a digital PWM modulator needs a high clock frequency for a small signal
bandwidth. For a 10 bit digital PWM modulator for instance, a 10 bit counter is needed in order to create a pulse
with a resolution of 1024. This means that, in case an infinitely sharp analog output filter is used, the clock
frequency has to be at least 1024 times the output bandwidth. In practice however, in order to be able to build the
analog filter, the clock frequency needs to be much higher.
In order to reduce this frequency requirement, the input digital word is broken down into n words with a smaller
width m by a noise shaper so that the “average” (average for first order noise shaper, more complicated for higher
order noise shapers) value of the n m-bit words represents the full width input code. Instead of 1 pulse with the full
resolution, the PWM modulator now generates n pulses with a smaller resolution m. This increases the output
pulse repetition frequency with a factor n for identical clock frequency. Therefore, the analog output filtering is
easier to implement. Higher order noise shapers (order >1) allow to decrease the clock frequency for identical
signal bandwidth.
Another advantage is that the signal distortion is less dependent on the signal value. A disadvantage is however,
that the output signal after filtering is more dependent on the rise and fall times of the PWM output since there are
many more pulses.
The maximum word width at the input is 16-bit. If the word is narrower, 0’s have to be added after the LSB. In order
to maintain maximum flexibility, the order of the noise shaper and the resolution of the PWM modulation are
programmable by writing the codes CodeLmax and NsOrder to the configuration register. The possible noise
shaper order is 0 (which means no noise shaping), 1 or 2. The possible PWM modulation resolution m can be set
between 4 and 11.
© Semtech 2006
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18-2
XE8805/05A
18.3
Registers Map
All registers are reset with the system reset.
The contents of the registers RegDasInLsb and RegDasInMsb are transferred to the D/A converter when after
data have been written into RegDasInMsb. Therefore, in order to maintain the synchronisation between the LSB
and MSB, the LSB should always be written before the MSB.
Pos.
7-0
RegDasInLsb
DasInLsb(7:0)
rw
rw
reset
0
resetsystem
function
Data to convert LSB
Table 18-1. RegDasInLsb
Pos.
7-0
RegDasInMsb
DasInMsb(7:0)
rw
rw
reset
0
resetsystem
function
Data to convert MSB
Table 18-2. RegDasInMsb
Pos.
7:6
RegDasCfg0
NsOrder(1:0)
rw
rw
reset
00
resetsystem
5:3
CodeLmax(2:0)
rw
000
resetsystem
2:1
Enable(1:0)
rw
0
Fin
rw
00
resetsystem
0
resetsystem
function
Noise Shaper order
00 : order 0
01 : order 1
1x : order 2
PWM pulse resolution :
000 : 4 bits
001 : 5 bits
010 : 6 bits
011 : 7 bits
100 : 8 bits
101 : 9 bits
110 : 10 bits
111 : 11 bits
Bit 0 : enables the D/A
Bit 1 : enables the amplifier
Input frequency of modulator as a fraction of
oscillator frequency
0 : 1.fRC, 1 : ½.fRC
Table 18-3. RegDasCfg0
Pos.
7:2
1
RegDasCfg1
BW
rw
rw
rw
reset
000000
0
resetsystem
0
INV
rw
0
resetsystem
function
Unused
Amplifier bandwidth
0 : small bandwidth
1 : large bandwidth
Inverts the PWM output
0 : normal, active high
1 : inverted, active low
Table 18-4. RegDasCfg1
© Semtech 2006
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18-3
XE8805/05A
18.4 The D/A description
The D/A converter consists of 2 parts: a classic PWM modulator which is preceded by a noise shaper (Figure
18-1). The PWM signal has then to be low pass filtered using the amplifier and external components to obtain the
analog signal.
18.4.1
What is a noise shaper?
The major disadvantage of using a PWM modulator to generate a high resolution analog signal is that it requires a
high ratio between the PWM switching frequency and the useful bandwidth of the output analog signal after low
pass filtering.
Example: assuming the switching frequency of the PWM modulator is 1MHz and one wants to resolve 16 bit, i.e.
16
2 =65536 steps. In this case, the PWM has to code each step in increments of 1µs=1/1MHz and needs therefore
65536µs per pulse. This means that the PWM pulse repetition rate is 1/65536µs=15.25Hz. So, even with a higher
order low pass filter, more than 1 frequency decade will be required to filter the PWM signal down to a 16 bit
accurate analog signal. This leaves a useful bandwidth below 1Hz.
The goal of the noise shaper is to reduce the ratio between the PWM switching frequency and the useful
bandwidth. The noise shaper will not reduce the “truncation noise” and “PWM modulation noise” but move it to
higher frequencies. It “shapes” the frequency spectrum (“noise”) of the generated PWM signal, hence its name. In
practice, the noise shaper allows the generation of a signal with a given resolution using a PWM modulator that
has a lower resolution. The noise shaper then generates a series of different subsequent low resolution codes for
the PWM so that the average value corresponds to the high resolution code.
The first order noise shaper interpolates between two adjacent PWM codes to obtain a higher resolution. The
second order noise shaper can use non-adjacent PWM codes.
Example for first order noise shaper: assuming again the resolution of 16 bits using a 1MHz PWM switching
frequency using the noise shaper with order 1. If a PWM modulator with 4 bits, i.e. 16 steps is used, the PWM
repetition frequency becomes then 1MHz/16=62.5kHz. The PWM modulator can convert only the 4 MSB’s of the
16 bit input such as h0000, h1000 until hF000. In order to convert the code h5800, which is between h5000 and
h6000? In this case, the first order noise shaper will interpolate by presenting alternatively the code h5 and h6 to
the PWM so that after filtering a signal is obtained halfway between the normal PWM steps. To convert the code
h5400, it will present h5 3 times and h6 once to the PWM and so on. It is clear from this that the PWM repetition
frequency is much higher than for the simple PWM and can be filtered out more easily. The quantization noise
frequency will depend on the code to be converted: for this example for instance we need two PWM pulses to
implement the code h5800, but we need four to implement h5400 etc.
Example for second order noise shaper: if we use the same conditions as for the example above, we will obtain the
same PWM repetition frequency. However, to implement the code h5400, the noise shaper now can present the
following sequence to the PWM modulator: h6, h5, h6, h4. This increases the frequency components at the PWM
pulse repetition frequency and ½ of the PWM pulse repetition frequency but at the same time reduces energy at ¼
of the PWM pulse repetition frequency with respect to the first order noise shaper. The low pass cut-off frequency
can therefore be higher than for a first order noise shaper.
A disadvantage of the second order noise shaper is however that the resolution will drop when the code is very
close to h0000 or hFFFF.
Example: if we assume the same conditions as above, but we want to convert the code h0400. It is now impossible
to use a similar sequence as above (which would be h1, h0, h1, h(-1) ) due to saturation of the code. There is no
choice left but the sequence h1 h0 h0 h0 which is the same sequence as in the first order noise shaper.
18.4.2
Advantages/disadvantages
Advantages:
Using a high order noise shaper together with a PWM modulator with low resolution reduces the ratio between the
low pass cut off frequency and the PWM switching frequency for the same total resolution. This can be used to
© Semtech 2006
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18-4
XE8805/05A
increase the output signal bandwidth or to reduce the PWM switching frequency and therefore the power
consumption of the D/A. Signal distortion is less dependent on the signal value.
Disadvantages:
Using a high order noise shaper together with a PWM modulator with low resolution will use lots of short pulses in
stead of 1 long pulse. The D/A is therefore more sensitive to rise and fall times of the PWM resulting in a slightly
higher non-linearity and temperature dependence. The second order noise shaper also has a reduced resolution
for codes very close to zero or full scale.
18.4.3
D/A setup and resolution
In this section, the resolution that can be obtained with the D/A as a function of settings is calculated. These
calculations are based on the quantization and PWM modulation noise. Noise on the reference, i.e. the supply
voltage is not taken into account. High frequency noise on the supply voltage can be filtered by the output low pass
filter, but in band noise on the reference will show up in the output signal with amplitude that will depend on the
signal value. Therefore, when using the D/A, one should take care to minimize the switching activity on the digital
ports and/or to limit the load on these ports.
18.4.3.1
Noise shaper of order 0
Setting the noise shaper to order 0 (NsOrder=00), reduces the D/A to a regular PWM. Two parameters are setting
the resolution of the D/A: the resolution of the modulator itself and the amount of low pass filtering at the output.
The modulation width
m of the PWM modulator is given by:
m = 4 + CodeLmax
The cut-off frequency f c of the low pass filter required to get the resolution is calculated below. The PWM
modulator repetition frequency f PWM can be calculated as a function of the selected modulation width m , the
frequency of the RC oscillator of the circuit f RC and the selected frequency division set by Fin :
f PWM
⎛ 1 ⎞
f RC ⋅ ⎜
⎟
1 + Fin ⎠
⎝
=
2m
To obtain an analog signal with the required solution, the PWM signal has to be low pass filtered. The resolution
that can be obtained depends on the filter order and the ratio between the PWM modulation frequency f PWM and
the filter cut-off frequency f c . For a low pass filter of LpOrder, we obtain:
⎛f
resolution PWM = LpOrder ⋅ log 2 ⎜⎜ PWM
⎝ fc
⎞
⎟⎟
⎠
The total resolution of the D/A is then the minimal value of both criteria:
resolution = min(m, resolution PWM )
In Table 18-5 the required cut-off frequency of the low pass filter is shown for a noise shaper of order 0 as a
function of the desired resolution for both a first and second order low pass filter. The PWM modulation factor m
should be chosen equal to the desired resolution.
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18-5
XE8805/05A
resolution (bit)
4
5
6
7
8
9
10
11
m
4
5
6
7
8
9
10
11
fc for LpOrder=1 (Hz)
7812
1953
488
122
30
7.6
1.9
0.48
fc for LpOrder=2 (Hz)
31250
11048
3906
1381
488
172
61
22
Table 18-5. Signal bandwidth as a function of the required resolution for the PWM without noise shaper (Fin=0,
NsOrder=00, fRC=2MHz).
18.4.3.2
Noise shaper of order 1 or 2
The calculation on the required low pass cut-off frequency given in 18.4.3.1 remains valid in this case. However,
the noise shaper allows using smaller PWM modulation for the same resolution. This increases the PWM
modulation frequency and as a consequence increases the output bandwidth.
An additional criterion however shows up: the filtering of the quantization noise. As can be seen from the examples
in 18.4.1, the interpolation between PWM codes generated by the noise shaper introduce sequences at
frequencies below the PWM modulation frequency. Assuming a low pass filter that has at least the same order as
the noise shaper, the resolution is given by (NsOrder≥1) :
⎞
⎛
f
resolution quant = 0.359 + m + NsOrder ⋅ ⎜⎜ log 2 ( PWM ) − 2.65 ⎟⎟
fc
⎠
⎝
The total resolution of the D/A is then the minimal of both criteria:
resolution = min(resolutionquant , resolution PWM )
Table 18-6 and Table 18-7 show the signal bandwidth that can be obtained as a function of required resolution and
PWM modulation for first and second order noise shapers. It can be seen that these options are useful to obtain
high resolution using low PWM modulation m. For high PWM modulation m, the resolution is limited by the PWM
modulator and adding a noise shaper does not change anything.
NsOrder=1, fRC=2MHz, Fin=0, LpOrder=2
Resolution
PWM modulation m
(bit)
4
5
6
8
1596.4
1596.4
1596.4
9
798.2
798.2
798.2
10
399.1
399.1
399.1
11
199.5
199.5
199.5
12
99.8
99.8
99.8
13
49.9
49.9
49.9
14
24.9
24.9
24.9
15
12.5
12.5
12.5
16
6.2
6.2
6.2
7
976.6
690.5
399.1
199.5
99.8
49.9
24.9
12.5
6.2
8
488.3
345.3
244.1
172.6
99.8
49.9
24.9
12.5
6.2
9
244.1
172.6
122.1
86.3
61.0
43.2
24.9
12.5
6.2
10
122.1
86.3
61.0
43.2
30.5
21.6
15.3
10.8
6.2
11
61.0
43.2
30.5
21.6
15.3
10.8
7.6
5.4
3.8
Table 18-6. Low pass cut-off frequency as a function of the selected PMW modulation and required resolution for a
first order noise shaper.
© Semtech 2006
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18-6
XE8805/05A
NsOrder=2, fRC=2MHz, Fin=0, LpOrder=2
Resolution
PWM modulation m
(bit)
4
5
6
8
5638.4
3906.3
1953.1
9
3986.9
2762.1
1381.1
10
2819.2
1953.1
976.6
11
1993.5
1381.1
690.5
12
1409.6
976.6
488.3
13
996.7
690.5
345.3
14
704.8
488.3
244.1
15
498.4
345.3
172.6
16
352.4
244.1
122.1
7
976.6
690.5
488.3
345.3
244.1
172.6
122.1
86.3
61.0
8
488.3
345.3
244.1
172.6
122.1
86.3
61.0
43.2
30.5
9
244.1
172.6
122.1
86.3
61.0
43.2
30.5
21.6
15.3
10
122.1
86.3
61.0
43.2
30.5
21.6
15.3
10.8
7.6
11
61.0
43.2
30.5
21.6
15.3
10.8
7.6
5.4
3.8
Table 18-7. Low pass cut-off frequency as a function of the selected MPW modulation and required resolution for a
second order noise shaper.
The output range of the D/A is for code 0h0000 is VSS and for code 0hFFFF is (VBAT-VSS)(2m-1)/2m.
18.5 Amplifier
The amplifier can be used to implement the low pass filter and/or a 4-20mA loop. The amplifier is enabled using the
bit Enable(1)=1. The amplifier has two different modes selected by the bit BW: a low frequency mode (BW=0) that
allows driving a high capacitive load and a high frequency mode (BW=1).
The first mode is particularly adapted when a voltage output is used. The second mode is more adapted for a 420mA loop since loads are small and higher bandwidth is required to reject current consumption changes in the
loop.
Table 18-8 shows the specification of the amplifier.
Note that the amplifier can not be used to generate signals that are larger than the supply voltages VBAT and VSS
since the amplifier inputs and outputs are clamped to these voltages. The amplifier inputs and outputs should stay
within the input and output ranges specified below.
© Semtech 2006
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18-7
XE8805/05A
sym
gain
GBW0
CL0
GBW1
CL1
φm
RL
SR
CMR
OR
Voff
CMRR
noise
PSRR
Iquie
Ioff
1.
2.
3.
4.
5.
6.
7.
8.
9.
description
gain at DC
gain bandwidth product
capacitive load
gain bandwidth product
capacitive load
phase margin
resistive load
slew rate
common mode input range
output range
offset
common mode rejection
integrated input noise
power supply rejection
ratio
quiescent bias current
off current
min
80
25
typ
100
70
250
450
55
5
10
VSS-0.2
VSS+0.2
65
max
5
200
30
VBAT-1.2
VBAT-0.2
±5
60
20
50
60
100
150
1
unit
dB
kHz
nF
kHz
pF
°
kΩ
kV/s
V
V
mV
dB
uVrms
dB
Comment
1
6
6
7
7
8
5
9
2
3
4
uA
uA
For the minimal resistive load and the maximal capacitive load
The amplifier common mode is VSS in the 4-20mA loop.
At DC
At DC. Only a low rejection ratio is needed since the D/A output refers directly to the power supplies.
Short circuit protection at >3mA.
GBW when the maximal load is cl0 and with the bit BW=0
GBW when the maximal load is cl1 and with the bit BW=1
In both cases BW=0 and BW=1 for the maximal capacitive load and the minimal resistive load.
For maximal load CL0, BW=0 and maximal resistive load RL
Table 18-8. Specification of the amplifier.
18.6 Low pass filter
Several low pass filters are proposed here as examples. Other filter types are possible depending on the features
or constraints of the application.
If the filter is inverting the signal, the bit INV can be used to invert the D/A output. This inversion does not need to
be done by calculation.
A first or second order low pas filter can be built with the amplifier. If higher order filters are needed, additional first
or second order sections can be added using external amplifiers.
18.6.1
First order low pass filter
Figure 18-2 shows a possible implementation of a first order low pass filter. Ideally, the analog ground should be
halfway between VBAT and VSS. The gain G and cut-off frequency fc of such a filter are given by:
G=
R2
R1
fc =
1
2πR2 C
As an example, to obtain a 1kHz filter with unity gain, we can choose C=1nF and R1=R2=150kΩ.
© Semtech 2006
www.semtech.com
18-8
XE8805/05A
XE88xx
c
o
n
t
r
o
l
D
DAS_OUT
A
R1
DAS_AI_M
C
R2
amp
DAS_AO
DAS_AI_P
analog ground
Figure 18-2. First order low pass filter.
18.6.2
Second order low pass filter
Figure 18-3 shows an example of a second order low pass filter using the multi-feedback architecture. The gain G,
cut-off frequency fc and the damping factor ξ (or quality factor Q) as a function of the factors k and m (see Figure
18-3) are given by:
G = −k
1
(n + 1) km
=
2Q
2 n
1
fc =
2πRC kmn
ξ=
For a second order Butterworth filter, ξ = 2 2 . For smaller damping factors, the filter is under damped resulting
in overshoots on the step response. For higher damping factors, the filter is over damped resulting in a smooth but
slower step response.
An example of a 1dB ripple Chebychev filter with a cut-off frequency of about 1.5kHz and a DC gain of 1 is given
by choosing m=0.22, k=1, n=0.5, R=330kΩ and C=1nF. The resistor nR can be rounded to 180kΩ.
A 60Hz unity gain low pass Butterworth filter can be built choosing R=180kΩ, C=12nF, k=1, m=0.183, n=8.33.
Note that parasitic capacitors between the DAS_OUT node and the filter output DAS_AO will adversely affect the
high frequency behavior of the filter. Care should be taken when routing these signals.
© Semtech 2006
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18-9
XE8805/05A
XE88xx
c
o
n
t
r
o
l
D
DAS_OUT
A
R
C
nR
DAS_AI_M
DAS_AO
mC
kR
amp
DAS_AI_P
analog ground
Figure 18-3. Second order low pass filter.
18.7 4-20mA loop
18.7.1
2-wire loop with first order filtering
The amplifier can be used to build a 4-20mA loop externally. Figure 18-4 shows the principle of such a 2-wire loop
using a first order low pass filter.
In a 2-wire loop, the current consumption of the sensor and read-out electronics is drawn on the same wires as the
signal current. The current consumption of the sensor and read-out electronics should therefore remain below
4mA. The signal current is then added by the bipolar transistor. The resistors Rlim1 and Rlim2 are added to protect
the bipolar transistor against high transient currents during power-up. Rlim1 is generally set to a few kΩ. The value
of Rlim2 is chosen as a function of the external loop voltage VEXT and the transistor saturation voltage VCEsat.
Rlim 2 = (V EXT − VCEsat − Rsense ⋅ 20mA) 20mA
If VEXT is larger than 5.5V, a voltage regulator has to be inserted. Since the quiescent current of the regulator adds
up to the 4mA budget, a component with sufficiently low quiescent current has to be selected.
The resistor Rsense measures the total current in the loop (if Rsense<<Rf2). The resistors Rf1 and Rf2 are used to set
the gain and Rf2 and Cf to set the bandwidth of the filter. The resistor Roffset adds an offset to the filter voltage so
that the code 0 of the D/A corresponds to 4mA. The amplifier will force a current through the bipolar transistor so
that the voltage on the filter Vf and VSS on Rsense is equal. This transforms the filter voltage into a loop current
Iloop=(VSS-VEXT-)/Rsense.
© Semtech 2006
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18-10
XE8805/05A
The resistor value Rsense is generally chosen between 50Ω and 150Ω resulting in a 1V to 3V voltage drop at
maximal loop current. The resistor Rf2 is then chosen much larger depending on the current error requirement.
Allowing for an error of 0.1% gives Rf2=Rsense/0.001.
The resistor Roffset may be omitted but it will reduce the useful code range of the D/A.
Using the large bandwidth of the amplifier is recommended since this increases the rejection of supply current
variations of the other components in the loop. A bypass capacitor between VBAT and VSS will also reduce the
high frequency current variations. Values will depend on the voltage regulator used. The software in the XE8805
should keep the current supply of the circuit as stable as possible. This means that the clock frequency should kept
constant, peripherals should not be switched on and off, the current in the sensor is kept constant, the processor
should not use the halt or sleep modes, etc.
XE88xx
4-20mA
Voltage
regulator
VBAT
VEXT+
VBAT
c
o
n
t
r
o
l
D
DAS_OUT
Roffset
A
Rf1
Rlim2
DAS_AI_P
Vf
Rlim1
DAS_AO
amp
Sensor
DAS_AI_M
VSS
VSS
Cf
Rf2
Rsense
VEXT4-20mA
Figure 18-4. 2-wire 4-20mA loop with first order filter
The resistor Rf1 can then be calculated to set the full scale D/A code range (depends on the PWM modulation m,
see section 18.4.3.2) equal to the full scale signal current of 16mA:
Rf1 ≤
(VBAT − VSS ) ⋅ (2 m − 1) ⋅ R f 2
2 m ⋅ Rsense ⋅ 16mA
The resistor Roffset can be calculated in order to obtain a 4mA current while the D/A code is 0:
Roffset ≤
(VBAT − VSS ) ⋅ R f 2
Rsense ⋅ 4mA
© Semtech 2006
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18-11
XE8805/05A
The capacitor Cf can be calculated from the first order filter cut-off frequency fc :
Cf =
Rf1 + Rf 2
2πf c R f 1 R f 2
As an example, for VBAT-VSS=5V, m=4, Rsense=50Ω, VEXT=30V and a 1kHz low pass filter, we can use:
Rlim1=1kΩ, Rlim2=1kΩ, Rf1=560kΩ, Rf2=100kΩ, Roffset=2.4MΩ, Cf=1.8nF.
18.7.2
2-wire loop with second order filtering
A second order filter function can be implemented by replacing the resistor Rf1 in Figure 18-4 by another first order
filter section as shown in Figure 18-5. The value of Rf1a+Rf2a has to be chosen the same way as Rf1 in the first order
schematic.
XE88xx
VBAT
c
o
n
t
r
o
l
4-20mA
Voltage
regulator
VBAT
VEXT+
Roffset
D
DAS_OUT
Rf1a
A
Rf1b
Rlim2
Cf1
Vf
DAS_AI_P
Rlim1
DAS_AO
amp
Sensor
DAS_AI_M
VSS
VSS
Cf2
Rf2
Rsense
VEXT4-20mA
Figure 18-5. 2-wire 4-20mA loop with second order filtering.
Another possibility is shown in Figure 18-6. The advantage this solution is that it is easier to stabilize depending on
the component parasitics and board layout. But since it limits the bandwidth of the current regulation loop, it
reduces the rejection of the supply current variations.
For this schematic, all the equations of the first order schematic remain valid. The values of Rfs and Cfs can be
calculated from the cut-off frequency:
R fs C fs =
1
2πf c
For the 1kHz example, we can chose Rfs=150kΩ and Cfs=1nF (set BW=0 in this case).
© Semtech 2006
www.semtech.com
18-12
XE8805/05A
XE88xx
VBAT
c
o
n
t
r
o
l
4-20mA
Voltage
regulator
VBAT
VEXT+
Roffset
D
DAS_OUT
Rf1
A
Rlim2
Vf
DAS_AI_P
Rlim1
DAS_AO
amp
Sensor
Cfs
DAS_AI_M
Rfs
VSS
VSS
Cf
Rf2
Rsense
VEXT4-20mA
Figure 18-6. 2-wire 4-20mA with second order filter and increased stability
© Semtech 2006
www.semtech.com
18-13
XE8805/05A
19.
Bias D/A (DAB)
19.1
Features
19-2
19.2
General description
19-2
19.3
Register map
19-2
19.4
D/A specification
19-3
19.5
Amplifier specification
19-3
19.6
19.6.1
19.6.2
Application examples
Voltage controlled sensor bias
Current controlled sensor bias
19-4
19-4
19-4
© Semtech 2006
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19-1
XE8805/05A
19.1 Features
•
•
•
8 bit low frequency A/D
On-chip amplifier with 2 terminals MOS output
Current and voltage controlled applications can be implemented
19.2 General description
XE8805A – Bias D/A block
DAB R P
DAB OUT
DAB AIP
control
registers
D/A
VBATT
amp
DAB AOP
MOS
VSS
DabIn
DAB AOM
Enable
DAB AIM
DAB R M
As the amplifier is attacking a MOS, effective polarity of the feedback loop
depends on load and network.
Figure 19-1. General block diagram
Figure 19-1 shows the general block diagram of the D/A peripheral. It consists of a control block that manages all
communication with the CPU and sets the configuration of the peripheral. The D/A converts the digital data in an
analog output signal. An amplifier is added that can be used to drive the large sensor currents.
19.3 Register map
The bias D/A has two registers.
Pos.
7-0
RegDabIn
DabIn(7:0)
rw
rw
reset
0
resetsystem
function
Data to convert
Table 19-1. RegDabIn
Pos.
7-2
1-0
RegDabCfg
Enable(1:0)
rw
r
rw
reset
0
00
resetsystem
function
Unused
bit 1: enables the amplifier when 1
bit 0: enables the D/A when 1
Table 19-2. RegDabCfg
© Semtech 2006
www.semtech.com
19-2
XE8805/05A
19.4 D/A specification
The D/A generates a voltage on node DAB_OUT that is proportional to the code RegDabIn in between the positive
reference voltage DAB_R_P and the negative reference voltage DAB_R_M. The voltage on DAB_R_P always has
to be larger than the voltage on DAB_R_M. The DAB is intended for very low frequency use. The specification is
given in Table 19-3.
The DAB is based on a resistive ladder. Capacitors larger than 100pF are allowed on the node DAB_OUT, but the
step response will increase proportionally.
sym
wda
tstep
OR
refp
refn
Rdab
description
number of input bits
step response
D/A output range
DAB_R_P range
DAB_R_M range
impedance between
DAB_R_P and DAB_R_M
min
typ
8
0.25
max
1
DAB_R_P
VBAT
VBAT-2.3
DAB_R_M
VSS+2.3
VSS
1.6
unit
bits
ms
note
1
V
V
Mohm
1. Time to reach the final value within 5%, CL on DAB_OUT smaller than 100pF.
Table 19-3. D/A specification.
19.5 Amplifier specification
The amplifier output stage is a single transistor follower that is able to drive large currents. This transistor is not
connected internally so that different circuit configurations are possible (see next section). In order to guarantee
correct functionality, the voltage on the output pins has to respect the specifications VRAOP and VRAOM as indicated
in Table 19-4.
sym
gain
GBW
φm
RL
CL
CMR
VRAOM
VRAOP
Voff
noise
description
gain at DC
gain bandwidth product
phase margin
resistive load
capacitive load
common mode input range
DAB_AOM voltage range
DAB_AOP voltage range
offset
integrated input noise
Isource
PSRR
Ibias
Ioff
max source current
power supply rejection ratio
quiescent bias current
off current
min
60
100
60
300
typ
90
4500
80
100000
1
VBAT
DAB_AOP-0.2
VBAT
VSS
VSS+0.2
VSS+2.3
10
max
±10
60
100
40
80
5
0.1
10
1
unit
dB
Hz
°
Ω
nF
V
V
V
mV
µVrm
s
mA
dB
µA
µA
Note
1
1
1
1
1
2
1. For all possible combinations of resistive load and capacitive load.
2. At DC.
Table 19-4. Amplifier specification.
© Semtech 2006
www.semtech.com
19-3
XE8805/05A
19.6 Application examples
19.6.1
Voltage controlled sensor bias
Figure 19-2 shows the basic connectivity to have a voltage controlled sensor bias. The D/A will generate a voltage
between vrep and vrefn proportional to the input code. The amplifier will copy the D/A voltage to the sensor. The
D/A code can be used to do a software temperature calibration of the sensor for instance.
Filter capacitors can be added in parallel with the sensor reference and signal, on Vrefp, Vrefn and DAB_OUT.
The voltages Vrefp and Vrefn can be filtered before being connected to the D/A reference inputs. The reference
voltages can be connected directly to VBAT and VSS for simplicity. They can also be connected to VBAT and VSS
through a low pass filter that rejects the high frequency supply noise. Finally, in most cases, the voltage range of
interest for the voltage Vsensor on the sensor is only a fraction of the supply voltage. By generating Vrefp and Vrefn
equal to the limits of the voltage range of interest, the resolution of the D/A can be increased. Example: if a supply
of 5V is used and the reference voltage is equal to the supply, the D/A can generate a sensor voltage between 0V
and 5V in steps of about 5V/255≈20mV. If the sensor voltage is always to be between 3V and 4V, and by
connecting Vrefn=3V and Vrefp=4V, the sensor voltage is adjustable between 3V and 4V with steps of about
1V/255≈4mV.
XE8805A – DAB block
Vrefp
DAB_R_P
DAB_R_M
D/A
VBAT or a Reference voltage source
Vrefn
VSS
* High impedance node,
impedance depends on D/A code
DAB_OUT
DAB_AIP
DAB_AOP
amp
VBAT
* Needs a 300 Ω – 100 kΩ load
* Max capacitive load is 1 nF
Vsensor
DAB_AOM
DAB_AIM
reference input
of the
ZoomingADC
* In this configuration the bridge current and DAB_AOM
increase when DAB_OUT increases.
VSS
signal input
of the
ZoomingADC
Figure 19-2. Voltage controlled bridge bias principle.
Note that the voltage on the sensor can not be higher than VBAT-0.2V in the example of Figure 19-2 (specification
VRAOM in Table 19-4).
19.6.2
Current controlled sensor bias
Figure 19-3 shows the principle of a current controlled sensor bias schematic. In this case, the amplifier forces the
voltage VR to be equal to the D/A output voltage VD/A. The current Isensor through the sensor is given by:
© Semtech 2006
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19-4
XE8805/05A
I sensor =
Vrefp − V R
Rsense
=
Vrefp − VD / A
Rsense
=
(Vrefp − Vrefn ) ⋅ (1 − code 255)
Rsense
The voltage Vsensor can be calculated as a function of the current Isensor and the sensor impedance.
Note that the voltage VR>VSS+2.3V and VR-Vsensor>0.2V (VRAOP and VRAOM specifications in Table 19-4) to
guarantee correct functionality of this schematic.
Choosing the Vrefp equal to the supply voltage or close to the supply voltage in order to have the highest possible
voltage on the sensor is recommended. From the equation, it can be seen that the sensor current step per LSB can
be made smaller by reducing the voltage between Vrefp and Vrefn or by increasing the sense resistor value.
As for the voltage controlled sensor bias, capacitors can be added on several nodes to filter out the noise.
XE8805A
DAB_R_P
D
* Voltage must remain above VSS + 2.3 V
Vrefp
DAB_R_M
Vrefn
DAB_OUT
VD/A
* Voltage must remain below VBAT - 2.3 V
VSS
DAB_AIM
A
Rsense
* Voltage must remain above VSS + 2.3 V
DAB_AOP
VR
* Needs a 300 Ω – 100 kΩ load
* Max capacitive load is 1 nF
amp
DAB_AOM
Vsensor
DAB_AIP
reference
* In this configuration, the bridge current and DAB_AOM
decrease when DAB_OUT increases.
signal
VSS
Figure 19-3. Current controlled bridge bias
In Figure 19-4, the sense resistor is inserted between the negative reference voltage and the sensor. This
schematic has the same principle as above, but it is easier to respect the limits on VRAOP when VBAT is low. The
sensor current is now:
I sensor =
VR − Vrefn
Rsense
=
V D / A − Vrefn
Rsense
=
(Vrefp − Vrefn ) ⋅ (code 255)
Rsense
In this case, it is recommended to choose Vrefn equal to VSS or close to VSS in order to have the highest possible
voltage on the sensor. The only limit is now Vsensor<VBAT-0.2V.
© Semtech 2006
www.semtech.com
19-5
XE8805/05A
XE8805A
DAB_R_P
D
Vrefp
DAB_R_M
Vrefn
DAB_OUT
VD/A
VBAT or another reference voltage
* Vrefp must remain above VSS + 2.3 V
VSS
DAB_AIP
A
VBAT
DAB_AOP
amp
Vsensor
* Needs a 300 Ω – 100 kΩ kohm load
* Max capacitive load is 1 nF
DAB_AOM
DAB_AIM
reference input of
ZoomingADC
* In this configuration, the bridge current and DAB_AOM increase
when DAB_OUT increases
signal input of
ZoomingADC
VR
Rsense
VSS
Figure 19-4. Current controlled sensor bias.
.
© Semtech 2006
www.semtech.com
19-6
XE8805/05A
20.
Counters/Timers/PWM
20.1
Features
20-2
20.2
Overview
20-2
20.3
Register map
20-2
20.4
Interrupts and events map
20-3
20.5
Block schematic
20-4
20.6
General counter registers operation
20-4
20.7
Clock selection
20-5
20.8
Counter mode selection
20-5
20.9
Counter / Timer mode
20-6
20.10
PWM mode
20-8
20.11
Capture function
20-9
© Semtech 2006
www.semtech.com
20-1
XE8805/05A
20.1 Features
•
•
•
•
•
•
•
•
•
•
4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules
Each with 4 possible clock sources
Up/down counter modes
Interrupt and event generation
Capture function (internal or external source)
Rising, falling or both edge of capture signal
PA[3:0] can be used as clock inputs (debounced or direct)
2 x 8 bits PWM or 2 x 16 bits PWM
PWM resolution of 8, 10, 12, 14 or 16 bits
Complex mode combinations are possible between counter, capture and PWM modes
20.2 Overview
CounterA and CounterB are 8-bit counters and can be combined to form a 16-bit counter. CounterC and CounterD
exhibit the same features.
The counters can also be used to generate two PWM outputs on PB[0] and PB[1]. In PWM mode one can generate
PWM functions with 8, 10, 12, 14 or 16 bit wide counters.
The counters A and B can be captured by events on an internal or an external signal. The capture can be
performed on both 8-bit counters running individually on two different clock sources or on both counters chained to
form a 16-bit counter. In any case, the same capture signal is used for both counters.
When the counters A and B are not chained, they can be used in several configurations: A and B as counters, A
and B as captured counters, A as PWM and B as counter, A as PWM and B as captured counter.
When the counters C and D are not chained, they can be used either both as counters or counter C as PWM and
counter D as counter.
20.3 Register map
Bit
7-0
7-0
RegCntA
CounterA
CounterA
rw
r
w
reset
xxxxxxxx
xxxxxxxx
function
8-bits counter value
8-bits comparison value
Table 20-1. RegCntA
bit
7-0
7-0
RegCntB
CounterB
CounterB
rw
r
w
reset
xxxxxxxx
xxxxxxxx
function
8-bits counter value
8-bits comparison value
Table 20-2. RegCntB
Note: When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading
these locations, the processor reads back either the actual counter value or the last captured value if the capture
mode is active.
bit
7-0
7-0
RegCntC
CounterC
CounterC
rw
r
w
reset
xxxxxxxx
xxxxxxxx
function
8-bits counter value
8-bits comparison value
Table 20-3. RegCntC
© Semtech 2006
www.semtech.com
20-2
XE8805/05A
bit
7-0
7-0
RegCntD
CounterD
CounterD
rw
r
w
reset
xxxxxxxx
xxxxxxxx
function
8-bits counter value
8-bits comparison value
Table 20-4. RegCntD
Note: When writing RegCntC or RegCntD, the processor writes the counter comparison values. When reading
these locations, the processor reads back the actual counter value.
bit
7-6
5-4
3-2
1-0
RegCntCtrlCk
CntDCkSel(1:0)
CntCCkSel(1:0)
CntBCkSel(1:0)
CntACkSel(1:0)
rw
rw
rw
rw
rw
reset
xx
xx
xx
xx
function
Counter d clock selection
Counter c clock selection
Counter b clock selection
Counter a clock selection
Table 20-5. RegCntCtrlCk
bit
7
6
5
4
3
2
1
0
RegCntConfig1
CntDDownUp
CntCDownUp
CntBDownUp
CntADownUp
CascadeCD
CascadeAB
CntPWM1
CntPWM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
x
x
x
x
x
x
0 resetsystem
0 resetsystem
function
Counter d up or down counting (0=down)
Counter c up or down counting (0=down)
Counter b up or down counting (0=down)
Counter a up or down counting (0=down)
Cascade counter c & d (1=cascade)
Cascade counter a & b (1=cascade)
Activate pwm1 on counter c or c+d (PB(1))
Activate pwm0 on counter a or a+b (PB(0))
Table 20-6. RegCntConfig1
bit
7-6
5-4
3-2
1-0
RegCntConfig2
CapSel(1:0)
CapFunc(1:0)
Pwm1Size(1:0)
Pwm0Size(1:0)
rw
rw
rw
rw
rw
Reset
00 resetsystem
00 resetsystem
xx
xx
function
Capture source selection
Capture function
Pwm1 size selection
Pwm0 size selection
Table 20-7. RegCntConfig2
bit
7-4
3
2
1
0
RegCntOn
-CntDEnable
CntCEnable
CntBEnable
CntAEnable
rw
r
rw
rw
rw
rw
Reset
0000
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
Function
Reserved
Enable counter d
Enable counter c
Enable counter b
Enable counter a
Table 20-8. RegCntOn
20.4 Interrupts and events map
Interrupt source
IrqA
IrqB
IrqC
IrqD
Mapping in the
interrupt manager
RegIrqHigh(4)
RegIrqLow(5)
RegIrqHigh(3)
RegIrqLow(4)
Mapping in the event
manager
RegEvn(7)
RegEvn(3)
RegEvn(6)
RegEvn(2)
Table 20-9. Interrupt and event mapping.
© Semtech 2006
www.semtech.com
20-3
XE8805/05A
20.5 Block schematic
ck1k
ck32k
ck128
ckrcext/4
ckrcext
RegCntA (write)
RegCntA (read)
Counter A
PA(0)
Capture
RegCntB (write)
RegCntB (read)
Counter B
PA(1)
RegCntC (write)
ck1k
ck32k
RegCntC (read)
Counter C
PA(2)
RegCntD (write)
RegCntD (read)
Counter D
PA(3)
PB(0)
PWM
PB(1)
Figure 20-1: Counters/timers block schematic
20.6
General counter registers operation
Counters are enabled by CntAEnable, CntBEnable, CntCEnable, and CntDEnable in RegCntOn.
To stop the counter X, CntXEnable must be reset. To start the counter X, CntXEnable must be set. When
counters are cascaded, CntAEnable and CntCEnable also control respectively the counters B and D.
In the control registers, all registers must be written in this order: RegCntCtrlCk, RegCntConfig1, RegCntConfig2
and all RegCntX because several bits have no default values at reset.
All counters have a corresponding 8-bit read/write register: RegCntA, RegCntB, RegCntC, and RegCntD. When
read, these registers contain the counter value (or the captured counter value). When written, they modify the
counter comparison values.
For a correct acquisition of the counter value, use one of the three following methods:
1) Stop the concerned counter, perform the read operation and restart the counter. While stopped, the
counter content is frozen and the counter does not take into account the clock edges delivered on the
external pin.
© Semtech 2006
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20-4
XE8805/05A
2) For slow operating counters (typically at least 8 times slower than the CPU clock), oversample the counter
content and perform a majority operation on the consecutive read results to select the correct actual
content of the counter.
3) Use the capture mechanism.
When a value is written into the counter register while the counter is in counter mode, both the comparison value is
updated and the counter value is modified. In upcount mode, the register value is reset to zero. In downcount
mode, the comparison value is loaded into the counter. Due to the synchronization mechanism between the
processor clock domain and the external clock source domain, this modification of the counter value can be
postponed until the counter is enabled and it receives it’s first valid clock edge.
In the PWM mode, the counter value is not modified by the write operation in the counter register. Changing the
counter mode, does not update the counter value (no load in downcount mode).
20.7 Clock selection
The clock source for each counter can be individually selected by writing the appropriate value in the register
RegCntCtrlCk.
Table 20-10 gives the correspondence between the binary codes used for the configuration bits CntACkSel(1:0),
CntBCkSel(1:0), CntCCkSel(1:0) or CntDCkSel(1:0) and the clock source selected respectively for the counters
A, B, C or D.
Clock source for
CntXCkSel(1:0)
11
10
01
00
CounterA
CounterB
CounterC
CounterD
Ck128
CkRc/4
CkRc
PA(0)
Ck1k
Ck32k
PA(1)
PA(2)
PA(3)
Table 20-10: Clock sources for counters A, B, C and D
The CkRc clock is the RC oscillator. The clocks below 32kHz can be derived from the RC oscillator or the crystal
oscillator (see the documentation of the clock block). A separate external clock source can be delivered on Port A
for each individual counter.
The external clock sources can be debounced or not by setting the Port A configuration registers.
The clock source can be changed only when the counter is stopped.
20.8 Counter mode selection
Each counter can work in one of the following modes:
1) Counter, downcount & upcount
2) Captured counter, downcount & upcount (only counters A&B)
3) PWM, downcount
The counters A and B or C and D can be cascaded or not. In cascaded mode, A and C are the LSB counters while
B and D are the MSB counters.
Table 20-11 shows the different operation modes of the counters A and B as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntADownUp or the bit
CntBDownUp). Also, the mapping of the interrupt sources IrqA and IrqB and the PWM output on PB(0) in these
different modes is shown.
© Semtech 2006
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20-5
XE8805/05A
CascadeAB
CountPWM0
CapFunc(1:0)
0
0
00
1
0
00
0
1
00
1
1
00
0
0
1
0
0
1
1x
or
x1
1x
or
x1
1x
or
x1
Counter A
mode
Counter B
mode
IrqA
source
IrqB
source
PB(0)
function
Counter 8b Counter 8b
Downup: A Downup: B
Counter 16b AB
Downup: A
PWM 8b
Counter 8b
Down
Down
PWM 10 – 16b AB
Down
Captured
Captured
counter 8b
counter 8b
Downup: A Downup: B
Counter
A
Counter
AB
Counter
B
PB(0)
-
PB(0)
-
Counter
B
PWM A
-
-
PWM AB
Capture
A
Capture
B
PB(0)
Captured counter 16b AB
Downup: A
Capture
AB
Capture
AB
PB(0)
Captured
counter 8b
Downup: B
Must not
be used
Capture
B
PWM A
PWM 8b
Down
Table 20-11: Operating modes of the counters A and B
Table 20-12 shows the different operation modes of the counters C and D as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntCDownUp or the bit
CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these
different modes is also shown.
The switching between different modes must be done while the concerned counters are stopped. While switching
capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode
change.
CascadeCD
CountPWM1
0
0
1
0
0
1
1
1
Counter C
mode
Counter D
mode
IrqC
Source
IrqD
source
PB(1)
function
Counter 8b
Counter 8b
Downup: C
Downup: D
Counter 16b CD
Downup: C
PWM 8b
Counter 8b
Down
Down
PWM 10 – 16b CD
Down
Counter
C
Counter
CD
-
Counter
D
-
PB(1)
Counter
D
-
PWM C
-
PB(1)
PWM CD
Table 20-12: Operating modes of the counters C and D
20.9 Counter / Timer mode
The counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock
periods applied on the counter clock input.
Each counter can be set individually either in upcount mode by setting CntXDownUp in the register
RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave as a 16
bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting
CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the
up/down count modes set for the counters A and C.
© Semtech 2006
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20-6
XE8805/05A
When in upcount mode, the counter will start incrementing from zero up to the target value which has been written
in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is
generated at the next falling edge of counter clock. Then the counter is loaded again with the zero value at the next
rising edge of counter clock (Figure 20-2).
When in downcount mode, the counter will start decrementing from the initial load value which has been written in
the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an
interrupt is generated at the next falling edge of counter clock. Then the counter is loaded again with the load value
at the next rising edge of counter clock (Figure 20-2).
Be careful to select the counter mode (no capture, not PWM, specify cascaded or not and up or down counting
mode) before writing any target or load value to the RegCntX register(s). This ensures that the counter will start
from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that
both cascaded counters will start from the correct initial values.
The stopping and consecutive starting of a counter in counter mode without a target or load value write operation in
between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it’s target
value (upcount). This interrupt is additional to the interrupt which has already been generated when the counter
reached the zero or the target value.
dow n counting
clock counter X
RegcntX_r
XX
RegCntX_w
XX
3
2
1
0
3
2
1
0
3
2
1
0
3
write RegCntX
CntXDownUp
IrqX
CntXEnable
up counting
clock counter X
RegCntX_r
RegCntX_w
XX
XX
0
1
2
3
0
1
2
3
0
1
2
3
3
write RegCntX
CntXDownUp
IrqX
CntXEnable
Figure 20-2. Up and down count interrupt generation.
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20.10 PWM mode
The counters can generate PWM signals (Pulse Width Modulation) on the Port B outputs PB(0) and PB(1).
The PWM mode is selected by setting CntPWM1 and CntPWM0 in the RegCntConfig1 register. See Table 20-11
and Table 20-12 for an exact description of how the setting of CntPWM1 and CntPWM0 affects the operating
mode of the counters A, B, C and D according to the other configuration settings.
When CntPWM0 is enabled, the PWMA or PWMAB output value overrides the value set in bit 0 of RegPBOut in
the Port B peripheral. When CntPWM1 is enabled, the PWMC or PWMCD output value overrides the value set in
bit 1 of RegPBOut. The corresponding ports (0 and/or 1) of Port B must be set in digital mode and as output and
either open drain or not and pull up or not through a proper setting of the control registers of the Port B.
Counters in PWM mode always count down, the CntXDownUp bit setting must be reset. No interrupts and events
are generated by the counters which are in PWM mode. Counters do count circularly: they restart at the maximal
value (either 0xFF when not cascaded or 0xFFFF when cascaded) when respectively an underflow condition
occurs in the counting.
The internal PWM signals are low as long as the counter contents are higher than the PWM code values written in
the RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values.
The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded.
PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the
counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in
cascaded mode are shown in Table 20-13. Choosing a 16 bit PWM code higher than the maximum value that can
be represented by the number of bits chosen for the resolution, results in a PWM output which is always tied to 1.
PwmXsize(1:0)
11
10
01
00
Resolution
16 bits
14 bits
12 bits
10 bits
Table 20-13: Resolution selection in cascaded PWM mode
Small PWM code
Tlsmall
Thsmall
Large PWM code
Tllarge
Thlarge
Tper
Figure 20-3: PWM modulation examples
The period of the PWM signal is given by the formula:
2 resolution
Tper =
f ckcnt
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20-8
XE8805/05A
The duty cycle ratio DCR of the PWM signal is defined as:
DCR =
DCR can be selected between 0 % and
Th
Tper
2 resolution − 1
* 100 %.
2 resolution
DCR in % in function of the RegCntX content(s) is given by the relation:
DCR =
100 * RegCntX
2 resolution
20.11 Capture function
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the external PA(2) or PA(3) ports. Both counters use the same capture condition.
When the capture function is active, the A and B counters must be written with the value 0xFF and can either
upcount or downcount. They do count circularly: they restart at zero or at the maximal value (either 0xFF when not
cascaded or 0xFFFF when cascaded) when respectively an overflow or an underflow condition occurs in the
counting.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 20-14 shows the capture condition as a function of the setting of these
configuration bits.
CapSel(1:0)
Selected capture signal
11
1K
10
32 K
01
PA3
00
PA2
CapFunc
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Selected condition
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture condition
1 K rising edge
1 K falling edge
1 K both edges
32 K rising edge
32 K falling edge
32 K both edges
PA3 rising edge
PA3 falling edge
PA3 both edges
PA2 rising edge
PA2 falling edge
PA2 both edges
Table 20-14: Capture condition selection
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the
effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the
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20-9
XE8805/05A
same clock, the interruptions on IrqA and IrqB which inform that the capture condition was met, may appear at
different moments. In this case, the processor should read the shadow register associated to a counter only if the
interruption related to this counter has been detected.
It must be noted that when counters A and B are cascaded, the capture might happen at different cycles for the A
and B registers. This is due to the asynchronous relationship between counter and capture clock and to the fact
that the capture condition detection is independent for A and B counters.
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XE8805/05A
21 VLD (Voltage Level Detector)
21.1
Features
21-2
21.2
Overview
21-2
21.3
Register map
21-2
21.4
Interrupt map
21-2
21.5
VLD operation
21-2
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XE8805/05A
21.1 Features
•
•
Can be switched off, on or simultaneously with CPU activities
Generates an interrupt if power supply is below a pre-determined level
21.2 Overview
The Voltage Level Detector monitors the state of the system battery. It returns a logical high value (an interrupt) in
the status register if the supplied voltage drops below the user defined level (Vsb).
21.3 Register map
There are two registers in the VLD, namely RegVldCtrl and RegVldStat. Table 221-1 shows the mapping of
control bits and functionality of RegVldCtrl while Table 221-2 describes that for RegVldStat.
pos.
7-4
3
RegVldCtrl
-VldRange
rw
r
rw
reset
0000
0 resetsystem
2-0
VldTune[2:0]
rw
000
resetsystem
function
reserved
VLD detection voltage range for VldTune = “011”:
0 : 1.3V
1 : 2.55V
VLD tuning:
000 : +19 %
111 : -18 %
Table 221-1: RegVldCtrl
pos.
7-3
2
RegVldStat
-VldResult
rw
r
r
reset
00000
0 resetsystem
1
0
VldValid
VldEn
r
rw
0 resetsystem
0 resetsystem
function
reserved
is 1 when battery voltage is below the detection
voltage
Indicates when VldResult can be read
VLD enable
Table 221-2: RegVldStat
21.4 Interrupt map
interrupt source
IrqVld
mapping in the interrupt manager
RegIrqMid(2)
Table 221-3: Interrupt map
21.5 VLD operation
The VLD is controlled by VldRange, VldTune and VldEn. VldRange selects the voltage range to be detected,
while VldTune is used to fine-tune this voltage level in 8 steps. VldEn is used to enable (disable) the VLD with a
1(0) value respectively.
Disabled, the block will dissipate no power.
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symbol
description
min
typ
max
unit
Note 1
Vth
TEOM
TPW
Threshold voltage
VldRange
0
VldTune
1.53
1.44
0
001
1.36
0
010
1.29
0
011
1.22
0
100
1.16
0
101
1.11
0
110
0
111
3.06
1
000
2.88
1
001
2.72
1
010
2.57
1
011
2.44
1
100
2.33
1
101
2.22
1
110
2.13
1
111
V
1.06
duration of
measurement
Minimum pulse width
detected
comments
trimming values:
2.0
2.5
ms
Note 2
875
1350
us
Note 2
000
Table 221-4: Voltage level detector operation
Note 1: absolute precision of the threshold voltage is ±10%.
Note 2: this timing is respected in case the internal RC or crystal oscillators are enabled
To start the voltage level detection, the user sets bit VldEn. The measurement is started.
After 2ms, the bit VldValid is set to indicate that the measurement results are valid. From that time on, as long as
the VLD is enabled, a maskable interrupt request is sent if the voltage level falls below the threshold. One can also
poll the VLD and monitor the actual measurement result by reading the VldResult bit of the RegVldStat. This
result is only valid as long as the VldValid bit is ‘1’.
An interrupt is generated on each rising edge of VldResult.
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XE8805/05A
22 Physical Dimensions
22.1
QFP type package
22-2
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XE8805/05A
22.1 QFP type package
The QFP package dimensions are given in Figure 22-1 and Table 22-1. The dimensions conform to JEDEC MS026 Rev. C.
Figure 22-1. QFP type package
package
LQFP-64
A
B
C
D
E
F
G
mm
10.0
mm
12.0
mm
1.4
mm
0.10
mm
0.22
mm
0.5
mm
Table 22-1. QFP package dimensions
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© Semtech 2005
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