FAN7389 3-Phase Half-Bridge Gate-Drive IC Features Description Floating Channel for Bootstrap Operation to +600 V The FAN7389 is a monolithic three-phase half-bridge gate-drive IC designed for high-voltage, high-speed driving MOSFETs and IGBTs operating up to +600 V. Extended Allowable Negative VS Swing to -9.8 V for Signal Propagation at VDD=VBS=15 V Output In-Phase with Input Signal Typically 350 mA/650 mA Sourcing/Sinking Current Driving Capability for All Channels Over-Current Shutdown Turns off All Six Drivers Matched Propagation Delay for All Channels 3.3 V and 5.0 V Input Logic Compatible Adjustable Fault-Clear Timing An advanced level-shift circuit allows high-side gate driver operation up to VS = -9.8 V (typical) for VBS =15 V. The protection functions include under-voltage lockout and inverter over-current trip with an automatic faultclear function. Over-current protection that terminates all six outputs can be derived from an external current-sense resistor. An open-drain fault signal is provided to indicate that an over-current or under-voltage shutdown has occurred. Built-in Advanced Input Filter Built-in Shoot-Through Prevention Logic Built-in Soft Turn-Off Function Common-Mode dv/dt Noise Canceling Circuit Built-in UVLO Functions for All Channels The UVLO circuits prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Output drivers typically source and sink 350 mA and 650 mA, respectively; which is suitable for three-phase half-bridge applications in motor drive systems. Applications Fairchild’s high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances. 3-Phase Motor Inverter Driver 28-SOIC Air Conditioners Washing Machines General-Purpose Three-Phase Inverters Ordering Information Part Number Package Operating Temperature Packing Method FAN7389MX1(1) 28-Lead, Small Outline Integrated Circuit Wide Body (SOIC) -40 to +125°C Tape & Reel Note: 1. These devices passed wave soldering test by JESD22A-111. © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com FAN7389 — 3-Phase Half-Bridge Gate-Drive IC January 2013 Figure 1. 3-Phase BLDC Motor Drive Application Internal Block Diagram FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Application Diagram Figure 2. Functional Block Diagram © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 2 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Pin Configuration Figure 3. Pin Configuration Pin Definitions Pin Name Description 1 VDD 2 HIN1 Logic Input 1 for high-side gate 1 driver 3 HIN2 Logic Input 2 for high-side gate 2 driver 4 HIN3 Logic Input 3 for high-side gate 3 driver 5 LIN1 Logic Input 1 for low-side gate 1 driver 6 LIN2 Logic Input 2 for low-side gate 2 driver 7 LIN3 Logic Input 3 for low-side gate 3 driver 8 FO Fault output with open drain (indicates over-current and low-side under-voltage) Logic and low-side gate driver power supply voltage 9 CS Analog input for over-current shutdown 10 EN Logic input for shutdown functionality 11 RCIN 12 VSS 13 COM Low-side driver return 14 LO3 Low-side gate driver 3 output 15 LO2 Low-side gate driver 2 output An external RC network input used to define the fault-clear delay Logic ground 16 LO1 Low-side gate driver 1 output 17, 21, 25 NC No connect 18 VS3 High-side driver 3 floating supply offset voltage 19 HO3 High-side driver 3 gate driver output 20 VB3 High-side driver 3 floating supply 22 VS2 High-side driver 2 floating supply offset voltage 23 HO2 High-side driver 2 gate driver output 24 VB2 High-side driver 2 floating supply 26 VS1 High-side driver 1 floating supply offset voltage 27 HO1 High-side driver 1 gate driver output 28 VB1 High-side driver 1 floating supply © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol Parameter Min. Max. Unit VS High-Side Floating Offset Voltage VB1,2,3-25.0 VB1,2,3+0.3 V VB High-Side Floating Supply Voltage -0.3 625.0 V VDD Low-Side and Logic-Fixed Supply Voltage -0.3 25.0 V VHO High-Side Floating Output Voltage VHO1,2,3 VS1,2,3-0.3 VB1,2,3+0.3 V VLO Low-Side Floating Output Voltage VLO1,2,3 -0.3 VDD+0.3 V VIN Input Voltage (HINx, LINx, CS, and EN) -0.3 5.5 V VFO Fault Output Voltage ( FO ) -0.3 VDD+0.3 V PWHIN High-Side Input Pulse Width 500 dVS/dt Allowable Offset Voltage Slew Rate (2,3,4) ns ±50 V/ns PD Power Dissipation 1.4 W θJA Thermal Resistance 70 °C/W TJ Junction Temperature 150 °C TSTG Storage Temperature 150 °C -55 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Absolute Maximum Ratings Notes: 2. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 4. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VB1,2,3 High-Side Floating Supply Voltage VS1,2,3 High-Side Floating Supply Offset Voltage VDD Low-Side and Logic Fixed Supply Voltage Min. Max. Unit VS1,2,3+10 VS1,2,3+20 V 6-VDD 600 V 10 20 V VHO1,2,3 High-Side Output Voltage VS1,2,3 VB1,2,3 V VLO1,2,3 Low-Side Output Voltage COM VDD V VFO Fault Output Voltage ( FO ) COM VDD V VCS Current-Sense Pin Input Voltage COM 5 V VIN Logic Input Voltage (HIN1,2,3 and LIN1,2,3) COM 5 V VSS Logic Ground -5 5 V TA Ambient Temperature -40 +125 °C © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 4 VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to COM and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to COM. The VBSUV parameters are referenced to VS1,2,3. Symbol Parameter Conditions Min. Typ. Max. Unit Low-Side Power Supply Section IQDD IPDD Quiescent VDD Supply Current VLIN1,2,3=0 V or 5 V, EN=0 V 200 μA 400 μA Operating VDD Supply Current fLIN1,2,3=20 kHz, rms Value VDDUV+ VDD Supply Under-Voltage Positive-Going Threshold VDD=Sweep 7.5 8.5 9.3 V VDDUV- VDD Supply Under-Voltage Negative-Going Threshold VDD=Sweep 7.0 8.0 8.7 V VDDHYS VDD Supply Under-Voltage Lockout Hysteresis VDD=Sweep 0.5 V Bootstrapped Power Supply Section VBSUV+ VBS Supply Under-Voltage Positive-Going Threshold VBS1,2,3=Sweep 7.5 8.5 9.3 V VBSUV- VBS Supply Under-Voltage Negative-Going Threshold VBS1,2,3=Sweep 7.0 8.0 8.7 V VBSHYS VBS Supply Under-Voltage Lockout Hysteresis VBS1,2,3=Sweep ILK Offset Supply Leakage Current VB1,2,3=VS1,2,3=600 V IQBS Quiescent VBS Supply Current VHIN1,2,3=0V or 5 V, EN=0V 10 IPBS Operating VBS Supply Current fHIN1,2,3=20 kHz, rms Value 200 0.5 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Electrical Characteristics V 10 μA 50 80 μA 420 480 μA IO=0 mA (No Load) 100 mV IO=0 mA (No Load) 100 mV Gate Driver Output Section VOH High-Level Output voltage, VBIAS-VO VOL Low-Level Output voltage, VO (5) IO+ Output HIGH Short-Circuit Pulse Current VO=0 V, VIN=5 V with PW≤10 µs 250 350 mA IO- Output LOW Short-Circuit Pulsed Current(5) VO=15 V, VIN=0 V with PW≤10 µs 500 650 mA VS Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO -9.8 -7.0 V Logic Input Section VIH Logic "1" Input Voltage HIN1,2,3, LIN1,2,3 2.5 VIL Logic "0" Input Voltage HIN1,2,3, LIN1,2,3 IIN+ Logic Input Bias Current (HO=LO=HIGH) VIN=5 V IIN- Logic Input Bias Current (HO=LO=LOW) VIN=0 V RIN Logic Input Pull-Down Resistance V 0.8 V μA 100 2 50 μA KΩ Enable Control Section (EN) VEN+ Enable Positive-Going Threshold Voltage VEN- Enable Negative-Going Threshold Voltage IEN+ Logic Enable “1” Input Bias Current VEN=5 V (Pull-Down=150KΩ) IEN- Logic Enable “0” Input Bias Current VEN=0 V 2.5 V 0.8 V 2 μA μA 33 Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 5 VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to COM and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to COM. The VBSUV parameters are referenced to VS1,2,3. Symbol Parameter Conditions Min. Typ. Max. Unit Over-Current Protection Section (5) VCSTH+ Over-Current Detect Positive Threshold VCSTH- Over-Current Detect Negative Threshold(5) VCSHYS 400 (5) Over-Current Detect Hysteresis ICSIN Short-Circuit Input Current ISOFT Soft Turn-Off Sink Current VCSIN=1 V 500 600 mV 440 mV 60 mV 5 10 15 μA 25 40 55 mA Fault Output Section VRCINTH+ RCIN Positive-Going Threshold Voltage 3.3 V VRCINTH- RCIN Negative-Going Threshold Voltage 2.6 V VRCINHYS RCIN Hysteresis Voltage 0.7 IRCIN RCIN Internal Current Source CRCIN=2 nF VFOL Fault Output Low Level Voltage VCS=1 V, IFO=1.5 mA RCIN On Resistance IRCIN=1.5 mA Fault Output On Resistance IFO=1.5 mA RDSRCIN RDSFO 3 V 5 7 µA 0.2 0.5 V 50 75 100 Ω 90 130 170 Ω FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Electrical Characteristics Note: 5. These parameters are guaranteed by design. Dynamic Electrical Characteristics TA=25°C, VBIAS (VDD, VBS1,2,3) = 15.0 V, VS1,2,3 = COM, CRCIN=2 nF, and CLoad = 1000 pF unless otherwise specified. Symbol Parameter tON Turn-On Propagation Delay tOFF Conditions Min. Typ. Max. Unit VLIN1,2,3=VHIN1,2,3=0 V, VS1,2,3=0 V 350 500 650 ns Turn-Off Propagation Delay VLIN1,2,3=VHIN1,2,3=5 V, VS1,2,3=0 V 350 500 650 ns tR Turn-On Rise Time VLIN1,2,3=VHIN1,2,3=0 V 20 50 100 ns tF Turn-Off Fall Time VLIN1,2,3=VHIN1,2,3=5 V 10 30 80 ns tEN Enable LOW to Output Shutdown Delay 400 500 600 ns 200 300 400 ns tCSBLT (6) CS Pin Leading-Edge Blanking Time (7) tCSFO Time from CS Triggering to FO tCSOFF Time from CS Triggering to All Gate Outputs Turn-Off(7) tFLTIN Input Filtering Time(8) (HINx, LINx, EN) tFLTCLR DT MDT From VCSC=1V to FO Turn-Off 630 ns From VCSC=1V to Starting Gate Turn-Off 640 ns 200 250 250 300 Fault-Clear Time 1.3 Dead Time Dead-Time Matching (All Six Channels) MT Delay Matching (All Six Channels) PM Output Pulse-Width Matching(6,9) 300 PWIN > 1µs 50 ns ms 350 ns 50 ns 50 ns 100 ns Notes: 6. These parameters are guaranteed by design. 7. These parameters are referenced to specified CRCIN(=2 nF), and proportional to value of CRCIN as shown in Figure 43. It is strongly recommended that the capacitor on RCIN pin should be less than 5 nF. 8. The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded. 9. PM is defined as PWIN-PWOUT. © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 6 650 600 600 550 550 tOFF [ns] tON [ns] 650 500 500 450 450 400 350 -40 400 High-Side Low-Side -20 0 20 40 60 80 100 350 -40 120 High-Side Low-Side -20 0 Temperature [°C] 100 80 90 70 80 60 70 50 60 50 80 100 120 40 20 High-Side Low-Side 30 -20 0 20 40 60 80 100 High-Side Low-Side 10 0 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 6. Turn-On Rise Time vs. Temperature Figure 7. Turn-Off Fall Time vs. Temperature 600 2.0 1.8 tFLTCLR [ms] 550 tEN [ns] 60 30 40 500 450 400 -40 40 Figure 5. Turn-Off Propagation Delay vs. Temperature tF [ns] tR [ns] Figure 4. Turn-On Propagation Delay vs. Temperature 20 -40 20 Temperature [°C] FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics 1.6 1.4 1.2 -20 0 20 40 60 80 100 1.0 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 8. Enable LOW to Output Shutdown Delay vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 -20 Figure 9. Fault-Clear Time vs. Temperature www.fairchildsemi.com 7 50 350 25 MDT [ns] DT [ns] 400 300 250 0 -25 DT1 DT2 200 -40 -20 0 20 40 60 80 100 -50 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 10. Dead Time vs. Temperature Figure 11.Dead-Time Matching vs. Temperature 50 -7 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) -8 30 20 -9 10 VS [V] Delay Matching [ns] 40 0 -10 -10 -11 -20 -30 -50 -40 -12 MTON MTOFF -40 -20 0 20 40 60 80 100 -13 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 12. Delay Matching vs. Temperature Figure 13.Allowable Negative VS Voltage vs. Temperature 400 100 350 80 IQBS [μA] IQDD [μA] 300 250 200 60 40 150 20 100 50 -40 -20 0 20 40 60 80 100 0 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 14. Quiescent VDD Supply Current vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 -20 Figure 15. Quiescent VBS Supply Current vs. Temperature www.fairchildsemi.com 8 700 600 600 500 500 IPBS [μA] IPDD [μA] 700 400 400 300 300 200 200 100 -40 -20 0 20 40 60 80 100 100 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 16. Operating VDD Supply Current vs. Temperature Figure 17.Operating VBS Supply Current vs. Temperature 9.5 9.5 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 9.0 VDDUV- [V] VDDUV+ [V] 9.0 8.5 8.5 8.0 7.5 8.0 7.0 7.5 -40 -20 0 20 40 60 80 100 6.5 -40 120 -20 0 Temperature [°C] 40 60 80 100 120 Figure 19.VDD UVLO- vs. Temperature 9.5 9.0 9.0 8.5 VBSUV- [V] VBSUV+ [V] Figure 18. VDD UVLO+ vs. Temperature 8.5 8.0 7.5 -40 20 Temperature [°C] 8.0 7.5 -20 0 20 40 60 80 100 7.0 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 20. VBS UVLO+ vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 -20 Figure 21.VBS UVLO- vs. Temperature www.fairchildsemi.com 9 100 100 High-Side Low-Side 60 40 60 40 20 20 0 -40 High-Side Low-Side 80 VOL [mV] VOH [mV] 80 -20 0 20 40 60 80 100 0 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 22. High-Level Output Voltage vs. Temperature Figure 23.Low-Level Output Voltage vs. Temperature 3.0 3.0 2.5 VIL [V] 2.5 VIH [V] FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 2.0 2.0 1.5 1.5 1.0 -40 1.0 -20 0 20 40 60 80 100 0.5 -40 120 -20 0 Temperature [°C] Figure 24. Logic HIGH Input Voltage vs. Temperature 40 60 80 100 120 Figure 25.Logic LOW Input Voltage vs. Temperature 160 2.0 140 1.5 IIN- [μA] IIN+ [μA] 20 Temperature [°C] 120 1.0 100 0.5 80 60 -40 -20 0 20 40 60 80 100 0.0 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 26. Logic Input HIGH Bias Current vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 -20 Figure 27.Logic Input LOW Bias Current vs. Temperature www.fairchildsemi.com 10 200 80 180 REN [KΩ] RIN [KΩ] 100 60 40 20 0 10 160 140 120 12 14 16 18 100 10 20 12 Supply Voltage [V] 14 16 18 20 Supply Voltage [V] Figure 28. Input Pull-Down Resistance vs. Supply Voltage Figure 29.Enable Pin Pull-Down Resistance vs. Supply Voltage 400 100 350 FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 80 IQBS [μA] IQDD [μA] 300 250 200 60 40 150 20 100 50 10 12 14 16 18 0 10 20 12 Supply Voltage [V] 16 18 20 Figure 31.Quiescent VBS Supply Current vs. Supply Voltage 700 700 600 600 500 500 IPBS [μA] IPDD [μA] Figure 30. Quiescent VDD Supply Current vs. Supply Voltage 400 300 200 100 10 14 Supply Voltage [V] 400 300 200 12 14 16 18 100 10 20 Supply Voltage [V] 14 16 18 20 Supply Voltage [V] Figure 32. Operating VDD Supply Current vs. Supply Voltage © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 12 Figure 33.Operating VBS Supply Current vs. Supply Voltage www.fairchildsemi.com 11 Figure 34. Switching Time Waveform Definitions FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Switching Time Definitions Figure 35. Input / Output Timing Diagram Figure 36. Detailed View of B and C Intervals During Over-Current Protection © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 12 2.2 Shoot-Through Protection The shoot-through protection circuitry prevents both high- and low-side switches from conducting at the same time, as shown Figure 39. 1. Dead Time Dead time is automatically inserted whenever the dead time of the external two input signals (between HINx and LINx signals) is shorter than internal fixed dead times (DT1 and DT2). Otherwise, external dead times larger than internal dead times are not modified by the gate driver and internal dead-time waveform definition is shown in Figure 37. Figure 37. Internal Dead-Time Definitions FAN7389 — 3-Phase Half-Bridge Gate-Drive IC Applications Information 2. Protection Function 2.1 Fault Out ( FO ) and Under-Voltage Lockout The high- and low-side drivers include under-voltage lockout (UVLO) protection circuitry that monitors the supply voltage for VDD and VBS independently. It can be designed to prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Also, the UVLO hysteresis prevents chattering during powersupply transitions. Moreover, the fault signal ( FO ) goes to LOW state to operate reliably during power-on events, when the power supply (VDD) is below the under-voltage lockout high threshold voltage for the circuit (during t1 ~ t2). The UVLO circuit is not otherwise activated; shown Figure 38. Figure 39. Shoot-Through Protection 2.3 Enable Input When the EN pin is in HIGH state, the gate driver operates normally. When a condition occurs that should shut down the gate driver, the EN pin should be LOW. The enable circuitry has an input filter; the minimum input duration is specified by tFLTIN (typically 250 ns). Figure 38. Waveforms for Under-Voltage Lockout Figure 40. Output Enable Timing Waveform © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 13 The fault-clear time (tFLTCLR) is determined by an internal current source (IRCIN=5 μA) and an external CRCIN at the RCIN pin, as shown in this equation: t FLTCLR = C RCIN × VRCIN ,TH I RCIN [s ] Figure 42. RCIN and Fault-Clear Waveform Definition 2.5 Recommended RCIN Figure 43 shows timing of tCSOFF and tCSFO versus CRCIN. (1) It is strongly recommended that the capacitor on RCIN pin should be less than 5 nF in order to properly protect power devices in over-current situations. The RDSRCIN of the MOSFET is a characteristic discharge curve with respect to the external capacitor CRCIN. The time constant is defined by the external capacitor CRCIN and the RDSRCIN of the MOSFET. FAN7389 — 3-Phase Half-Bridge Gate Driver IC 2.4 Fault-Out ( FO ) and Over-Current Protection FAN7389 provides an integrated fault output ( FO ) and an adjustable fault-clear timer (tFLTCLR). There are two situations that cause the gate driver to report a fault via the FO pin. The first is an under-voltage condition of low-side gate driver supply voltage (VDD) and the second is when the current-sense pin (CS) recognizes a fault. Once the fault condition occurs, the FO pin is internally pulled to COM, the fault-clear timer is activated, and all outputs (HO1,2,3 and LO1,2,3) of the gate driver are turned off. The fault output stays LOW until the fault condition has been removed and the faultclear timer expires. Once the fault-clear timer expires, the voltage on the FO pin returns to pull-up voltage. 1200 The output of current-sense comparator (CS_COMP) passes a noise filter, which inhibits an over-current shutdown caused by parasitic voltage spikes of VCS. 1100 This corresponds to a voltage level at the comparator of VCSTH+ - VCSHYS= 500 mV - 60 mV =440 mV, where VCSHYS=60 mV is the hysteresis of the current comparator (CS_COMP) as shown in Figure 41. 800 1000 Time [ns] 900 700 600 500 tCSOFF tCSFO 400 300 200 0 1 2 3 4 5 6 7 8 9 10 11 12 CRCIN [nF] Figure 43. Timing of tCSOFF and tCSFO vs. CRCIN 3. Noise Filter Figure 41. Over-Current Protection 3.1 Input Noise Filter Figure 44 shows the input noise filter method, which has symmetry duration between the input signal (tINPUT) and the output signal (tOUTPUT) and helps to reject noise spikes and short pulses. This input filter is applied to the HINx, LINx, and EN inputs. The upper pair of waveforms (Example A) shows an input signal duration (tINPUT) much longer than input filter time (tFLTIN); it is approximately the same duration between the input signal time (tINPUT) and the output signal time (tOUTPUT). The lower pair of waveforms (Example B) shows an input signal time (tINPUT) slightly longer than input filter time (tFLTIN); it is approximately the same duration between input signal time (tINPUT) and the output signal time (tOUTPUT). Figure 42 shows the waveform definitions of RCIN, FO and the low-side driver, which uses a soft turn-off method when an under-voltage condition of the low-side gate driver supply voltage (VDD) or the current-sense pin (CS) recognizes a fault. Once a fault condition occurs, the FO pin is internally pulled to COM and all outputs (HO1,2,3 and LO1,2,3) of the gate driver are turned off. Low-side outputs decline linearly by the internal sink current source (ISOFT=40 mA) for soft turn-off, as shown in Figure 42. © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 14 Figure 46 shows the characteristics of the input filters while receiving narrow ON and OFF pulses. If input signal pulse duration, PWIN, is less than input filter time, tFLTIN; the output pulse, PWOUT, is zero. The input signal is rejected by input filter. Once the input signal pulse duration, PWIN, exceeds input filter time, tFLTIN, the output pulse durations, PWOUT, matches the input pulse durations, PWIN. FAN7389 input filter time, tFLTIN, is about 250 ns for the high- and low-side outputs. tFLTIN tINPUT tOUTPUT OUTx Example B INx tFLTIN tINPUT tOUTPUT Output duration is same as input duration OUTx Figure 44. Input Noise Filter Definition 3.2. Short-Pulsed Input Noise Rejection Method The input filter circuitry provides protection against short-pulsed input signals (HINx, LINx, and EN) on the input signal lines by applied noise signal. FAN7389 — 3-Phase Half-Bridge Gate Driver IC Example A INx If the input signal duration is less than input filter time (tFLTIN), the output does not change states. Example A and B of the Figure 45 show the input and output waveforms with short-pulsed noise spikes with a duration less than input filter time; the output does not change states. Figure 46. Input Filter Characteristic of Narrow ON Figure 45. Noise Rejecting Input Filter Definition © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 15 FAN7389 — 3-Phase Half-Bridge Gate Driver IC Package Dimensions Figure 47. 28-Lead Small Outline Integrated Circuit (28-Wide Body SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 16 FAN7389 — 3-Phase Half-Bridge Gate Driver IC © 2010 Fairchild Semiconductor Corporation FAN7389 • Rev. 1.0.3 www.fairchildsemi.com 17