1. Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation • Medium-voltage and Standard-voltage Operation • • • • • • • • – 2.7 (VCC = 2.7V to 5.5V) Extended Temperature Range −40⋅C to +125⋅C 5.0 MHz Clock Rate 8-byte Page Mode Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years 8-lead JEDEC SOIC and 8-lead TSSOP Packages 2. Description The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 128/256/512 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT25010A/020A/040A is available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. SPI Automotive Temperature Serial EEPROMs 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) AT25010A AT25020A AT25040A Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 2-1. Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input 8-lead SOIC CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-lead TSSOP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 5087E–SEEPR–7/09 3. Absolute Maximum Ratings* Operating Temperature.......................................−55⋅C to +125⋅C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..........................................−65⋅C to +150⋅C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Figure 3-1. Block Diagram 128/256/ 512 x 8 Table 3-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25⋅C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions COUT CIN Note: 2 Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A Table 3-2. DC Characteristics Applicable over recommended operating range from: TA = −40⋅C to +125⋅C. VCC = +2.7V to +5.5V Symbol Parameter VCC1 Supply Voltage ICC1 Supply Current ICC2 Min Max Units 2.7 5.5 V VCC = 5.0V at 1 MHz, SO = Open, Read 3.0 mA Supply Current VCC = 5.0V at 2 MHz, SO = Open, Read, Write 6.0 mA ICC3 Supply Current VCC = 5.0V at 5 MHz, SO = Open, Read, Write 6.0 mA ISB1(1) Standby Current VCC = 2.7V CS = VCC 3.0 µA ISB2(1) Standby Current VCC = 5.0V CS = VCC 5.0 µA IIL Input Leakage VIN = 0V to VCC −0.6 3.0 µA IOL Output Leakage VIN = 0V to VCC −0.6 3.0 µA VIL(2) Input Low Voltage −0.6 VCC x 0.3 V VIH(2) Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage 0.4 V VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage Note: Test Condition 3.6V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.6V IOL = 2.0 mA IOH = −1.0 mA VCC – 0.8 IOL = 0.15 mA IOH = −100 µA V 0.2 VCC – 0.2 V V 1. Worst case measured at 125⋅C 2. VIL min and VIH max are reference only and are not tested. 3 5087E–SEEPR–7/09 Table 3-3. AC Characteristics Applicable over recommended operating range from TA = −40⋅C to +125⋅C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 2.7–5.5 0 5.0 MHz tRI Input Rise Time 2.7–5.5 2 µs tFI Input Fall Time 2.7–5.5 2 µs tWH SCK High Time 2.7–5.5 40 ns tWL SCK Low Time 2.7–5.5 40 ns tCS CS High Time 2.7–5.5 80 ns tCSS CS Setup Time 2.7–5.5 80 ns tCSH CS Hold Time 2.7–5.5 80 ns tSU Data In Setup Time 2.7–5.5 5 ns tH Data In Hold Time 2.7–5.5 20 ns tHD Hold Setup Time 2.7–5.5 40 tCD Hold Hold Time 2.7–5.5 40 tV Output Valid 2.7–5.5 0 tHO Output Hold Time 2.7–5.5 0 tLZ Hold to Output Low Z 2.7–5.5 0 tHZ Hold to Output High Z tDIS tWC Endurance(1) Note: ns 40 ns ns 40 ns 2.7–5.5 80 ns Output Disable Time 2.7–5.5 80 ns Write Cycle Time 2.7–5.5 5 ms 5.0V, 25°C, Page Mode 1M Write Cycles 1. This parameter is characterized and is not 100% tested. 4. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010A/020A/040A always operates as a slave. TRANSMITTER/RECEIVER: The AT25010A/020A/040A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. The opcode also contains address bit A8 in both the Read and Write instructions. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. 4 AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A CHIP SELECT: The AT25010A/020A/040A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010A/020A/040A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low, all write operations are inhibited. WP going low while CS is still low will interrupt a write to the AT25010A/020A/040A. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. Figure 4-1. SPI Serial Interface AT25010A/020A/040A 5 5087E–SEEPR–7/09 5. Functional Description The AT25010A/020A/040A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25010A/020A/040A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 5-1. Instruction Set for the AT25010A/020A/040A Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 A011 Read Data from Memory Array WRITE 0000 A010 Write Data to Memory Array Note: “A” represents MSB address bit A8. WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during a WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 5-2. 6 Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X BP1 BP0 WEN RDY AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A Table 5-3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 (WEN) Bit 1= “0” indicates the device is not write-enabled. Bit 1 = “1” indicates the device is write-enabled. Bit 2 (BP0) See Table 5-4 on page 7. Bit 3 (BP1) See Table 5-4 on page 7. Bits 4 − 6 are “0”s when device is not in an internal write cycle. Bits 0 − 7 are “1”s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25010A/020A/040A is divided into four array segments. Onequarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 5-4. Bits BP0 and BP1 are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR). Table 5-4. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP0 AT25010A AT25020A AT25040A 0 0 0 None None None 1 (1/4) 0 1 60-7F C0-FF 180-1FF 2 (1/2) 1 0 40-7F 80-FF 100-1FF 3 (All) 1 1 00-7F 00-FF 000-1FF READ SEQUENCE (READ): Reading the AT25010A/020A/040A via the serial output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the read opcode (including A8) is transmitted via the SI line followed by the byte address to be read (A7–A0). Upon completion, any data on the SI line will be ignored. The data (D7−D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address, allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25010A/020A/040A, the Write Protect (WP) pin must be held high and two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. 7 5087E–SEEPR–7/09 A write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code (including A8) is transmitted via the SI line followed by the byte address (A7−A0) and the data (D7–D0) to be programmed. Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a read status register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25010A/020A/040A is capable of an 8-byte page write operation. After each byte of data is received, the three low-order address bits are internally incremented by one; the six highorder bits of the address will remain constant. If more than eight bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25010A/020A/040A is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the WP pin is brought low or if the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. 6. Timing Diagrams Figure 6-1. Synchronous Data Timing (for Mode 0) t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL 8 AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A Figure 6-2. WREN Timing Figure 6-3. WRDI Timing Figure 6-4. RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 13 14 15 2 1 0 SCK INSTRUCTION SI SO HIGH IMPEDANCE DATA OUT 4 3 MSB 9 5087E–SEEPR–7/09 Figure 6-5. WRSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 7 6 5 4 12 13 14 15 2 1 0 SCK INSTRUCTION DATA IN SI SO 3 HIGH IMPEDANCE Figure 6-6. READ Timing Figure 6-7. WRITE Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK INSTRUCTION SI 8 BYTE ADDRESS 7 6 5 4 3 2 1 DATA IN 0 7 6 5 4 3 2 1 0 9TH BIT OF ADDRESS SO 10 HIGH IMPEDANCE AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A Figure 6-8. HOLD Timing CS t CD t CD SCK t HD t HD HOLD t HZ SO t LZ 11 5087E–SEEPR–7/09 7. AT25010A Ordering Information Ordering Code Package Operation Range 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) AT25010AN-10SQ-2.7 AT25010A-10TQ-2.7 Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170” Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 12 Low Voltage (2.7V to 5.5V) AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A 8. AT25020A Ordering Information Ordering Code AT25020AN-10SQ-2.7 AT25020A-10TQ-2.7 Package Operation Range 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V) 13 5087E–SEEPR–7/09 9. AT25040A Ordering Information Ordering Code Package Operation Range 8S1 8A2 Lead-free/Halogen-free Automotive Temperature (−40°C to 125°C) AT25040AN-10SQ-2.7 AT25040A-10TQ-2.7 Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 14 Low Voltage (2.7V to 5.5V) AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A 10. Packaging Information 10.1 8S1 – JEDEC SOIC C 1 E E1 L N ∅ Top View End View e B COMMON DIMENSIONS (Unit of Measure = mm) A A1 D Side View SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B 15 5087E–SEEPR–7/09 10.2 8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D A b MIN 2.90 E e A2 D 3.00 3.10 2, 5 3, 5 4.30 4.40 4.50 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 L 4 0.65 BSC 0.45 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 16 NOTE E1 L1 Notes: MAX 6.40 BSC e Side View NOM 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B AT25010A/020A/040A/080A 5087E–SEEPR–7/09 AT25010A/020A/040A/080A 11. Revision History Doc. Rev. Date Comments 5087E 06/2009 Correct type error in the Features listed on page 1. NO DEVICE CHARACTERISTICS HAVE CHANGED. The self-timed write cycle is 5 ms max (was 10 ms max only in the Features listed on pg 1). The tWC parameter entry (Write Cycle Time) in Table 4 AC Characteristics on page 4 has always been 5ms. 5087D 3/2007 Corrected package codes on pages 12 and 13 5087C 2/2007 Implemented revision history Removed PDIP package offering Removed PB’d parts 17 5087E–SEEPR–7/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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